summaryrefslogtreecommitdiff
path: root/target-arm/translate.c
AgeCommit message (Collapse)AuthorFilesLines
2011-02-04Set the right overflow bit for neon 32 and 64 bit saturating add/sub.Christophe Lyon1-10/+8
Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> (cherry picked from commit 72902672dc2ed6281cdb205259c1d52ecf01f6b2)
2011-02-04target-arm: Fix Neon vsra instructions.Christophe Lyon1-2/+2
This patch fixes the errors reported by my tests in VSRA. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> (cherry picked from commit 5371cb81405a35ca4c1f6ab23f93a4f7260ffa53)
2011-01-26target-arm: Fix loading of scalar value for Neon multiply-by-scalarPeter Maydell1-6/+6
Fix the register and part of register we get the scalar from in the various "multiply vector by scalar" ops (VMUL by scalar and friends). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-26target-arm: Fix garbage collection of temporaries in Neon emulation.Christophe Lyon1-5/+13
Fix garbage collection of temporaries in Neon emulation. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-26Support saturation with shift=0.Christophe Lyon1-16/+12
This patch fixes corner-case saturations, when the target range is zero. It merely removes the guard against (sh == 0), and makes: __ssat(0x87654321, 1) return 0xffffffff and set the saturation flag __usat(0x87654321, 0) return 0 and set the saturation flag Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-18target-arm: Log instruction start in TCG codePeter Maydell1-0/+4
Add support for logging the start of instructions in TCG code debug dumps for ARM targets. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-01-14target-arm: Restore IT bits when resuming after an exceptionPeter Maydell1-0/+36
We were not correctly restoring the IT bits when resuming execution after taking an unexpected exception in the middle of an IT block. Fix this by tracking them along with PC changes and restoring in gen_pc_load(). This fixes bug https://bugs.launchpad.net/qemu/+bug/581335 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Refactor translation of exception generating instructionsPeter Maydell1-28/+15
Create a new function which does the common sequence of gen_set_condexec, gen_set_pc_im, gen_exception, set is_jmp to DISAS_JUMP. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Remove redundant setting of IT bits before Thumb SWIPeter Maydell1-1/+0
Remove a redundant call to gen_set_condexec() in the translation of Thumb mode SWI. (SWI and WFI generate "exceptions" which happen after the execution of the instruction, ie when PC and IT bits have updated. So the condexec bits at this point are not correct. However, the code that handles finishing the translation of the TB will write the correct value of the condexec bits later, so the only effect was that a conditional Thumb SWI would generate slightly worse code than necessary.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Translate with user-state from TB flags, not CPUStatePeter Maydell1-5/+1
When translating, get the user/priv state from the TB flags, not the CPUState. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Translate with condexec bits from TB flags, not CPUStatePeter Maydell1-3/+3
When translating, the condexec bits for the TB are in the TB flags; the CPUState condexec bits may be different. This patch fixes https://bugs.launchpad.net/bugs/604872 where we might segfault if we took an exception in the middle of a TB with an IT block, because when we came to retranslate in cpu_restore_state() the CPUState condexec bits would have advanced compared to the start of the TB and we would generate different (wrong) code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Translate with Thumb state from TB flags, not CPUStatePeter Maydell1-3/+3
The Thumb/ARM state for the TB being translated should come from the TB flags, not the CPUState. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Translate with VFP len/stride from TB flags, not CPUStatePeter Maydell1-3/+7
When translating, the VFP vector length and stride for this TB are encoded in the TB flags; the CPUState copies may be different and must not be used. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Translate with VFP-enabled from TB flags, not CPUStatePeter Maydell1-9/+5
When translating code, whether the VFP unit is enabled for this TB is stored in a bit in the TB flags. Use this rather than incorrectly reading the FPEXC from the CPUState passed to translation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Don't generate code specific to current CPU mode for SRSPeter Maydell1-31/+15
When translating the SRS instruction, handle the "store registers to stack of current mode" case in the helper function rather than inline. This means the generated code does not make assumptions about the current CPU mode which might not be valid when the TB is executed later. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-12ARM: Fix decoding of VQSHL/VQSHLU immediate formsPeter Maydell1-15/+36
Fix errors in the decoding of ARM VQSHL/VQSHLU immediate forms, including using the new VQSHLU helper functions where appropriate. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-06target-arm: fix SMMLA/SMMLS instructionsAurelien Jarno1-45/+51
SMMLA and SMMLS are broken on both in normal and thumb mode, that is both (different) implementations are wrong. They try to avoid a 64-bit add for the rounding, which is not trivial if you want to support both SMMLA and SMMLS with the same code. The code below uses the same implementation for both modes, using the code from the ARM manual. It also fixes the thumb decoding that was a mix between normal and thumb mode. This fixes the issues reported in https://bugs.launchpad.net/qemu/+bug/629298 Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-31target-arm: fix UMAAL instructionAurelien Jarno1-10/+22
UMAAL should use unsigned multiply instead of signed. This patch fixes this issue by handling UMAAL separately from UMULL/UMLAL/SMULL/SMLAL as these instructions are different enough. It also explicitly list instructions in case and catch nonexistent instruction as illegal. Also fixes a few style issues. This fixes the issues reported in https://bugs.launchpad.net/qemu/+bug/696015 Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27target-arm: Fix arguments passed to VQSHL helpersJuha Riihimäki1-2/+2
Correct the arguments passed when generating neon qshl_{u,s}64() helpers so that we use the correct registers. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27target-arm: fix bug in translation of REVSHAurelien Jarno1-7/+3
The translation of REVSH shifted the low byte 8 steps left before performing an 8-bit sign extend, causing this part of the expression to alwas be 0. Reported-by: Johan Bengtsson <teofrastius@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-07ARM: Fix sense of to_integer bit in Neon VCVT float/int conversionPeter Maydell1-4/+4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07ARM: Fix decoding of Neon forms of VCVT between float and fixed pointPeter Maydell1-2/+6
Fix errors in the decoding of the Neon forms of fixed-point VCVT: * fixed-point VCVT is op 14 and 15, not 15 and 16 * the fbits immediate field was being misinterpreted * the sense of the to_fixed bit was inverted Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07ARM: Fix decoding of VFP forms of VCVT between float and int/fixedPeter Maydell1-7/+12
Correct the decoding of source and destination registers for the VFP forms of the VCVT instructions which convert between floating point and integer or fixed-point. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07ARM: fix ldrexd/strexdPeter Maydell1-3/+5
Correct ldrexd and strexd code to always read and write the high word of the 64-bit value from addr+4. Also make ldrexd and strexd agree that for a 64 bit value the address in env->exclusive_addr is that of the low word. This fixes the issues reported in https://bugs.launchpad.net/qemu/+bug/670883 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07target-arm: Handle 'smc' as an undefined instructionAdam Lackorzynski1-1/+8
Refine check on bkpt so that smc and undefined instruction encodings are handled as an undefined instruction and trap. Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07target-arm: Fix mixup in decoding of saturating add and subJohan Bengtsson1-2/+2
The thumb2 decoder contained a mixup between the bit controlling doubling and the bit controlling if the operation was an add or a sub. Signed-off-by: Johan Bengtsson <teofrastius@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07target-arm: Add support for PKHxx in thumb2Johan Bengtsson1-18/+45
The PKHxx instructions were not recognized by the thumb2 decoder. The solution provided in this changeset is identical to the arm-mode implementation. Signed-off-by: Johan Bengtsson <teofrastius@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-10-30target-xxx: Use fprintf_function (format checking)Stefan Weil1-2/+1
fprintf_function uses format checking with GCC_FMT_ATTR. Format errors were fixed in * target-i386/helper.c * target-mips/translate.c * target-ppc/translate.c Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-01target-arm : fix thumb2 parallel add/sub opcode decodingChih-Min Chao1-2/+2
Signed-off-by: Chih-Min Chao <cmchao@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-11NEON vldN optimizationPaul Brook1-2/+4
When combining multiple values as part of a NEON array load, do explcit shift/or rather than using gen_bfi. This voids redundant mask operations. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-04-25arm: remove dead assignments, spotted by clang analyzerBlue Swirl1-1/+0
Value stored is never read. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-04-08target-arm: fix neon vmon/vmvn with modified immediateJuha Riihimäki1-1/+1
Signed-Off-By: Riku Voipio <riku.voipio@nokia.com> Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08target-arm: resource leak fixes for iwmmxt disassembleLars Munch1-0/+2
This patch fixes few resource leaks in the iwmmxt disassemble. Signed-off-by: Lars Munch <lars@segv.dk> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-23target-arm: Fix handling of AL condition in IT instructionJohan Bengtsson1-3/+5
Do not try to insert a conditional jump over next instruction when the condition code is AL as this will trigger an internal error. Signed-off-by: Johan Bengtsson <teofrastius@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13target-arm: make RFE usable with any registerAdam Lackorzynski1-1/+1
The rfe instruction can be used with any register, not just sp. Adjust the condition check accordingly. Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-06target-arm: Fix missing 'return' in SRS handling.Adam Lackorzynski1-0/+1
There's a return missing in the srs handling which leads to srs always being treated an an invalid op. Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-28target-arm: neon vshll instruction fixJuha Riihimäki1-0/+1
implementation only widened the 32bit source vector elements into a 64bit destination vector but forgot to perform the actual shifting operation. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Signed-off-by: Riku Voipio <riku.voipio@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-28target-arm: neon - fix VRADDHN/VRSUBHN vs VADDHN/VSUBHNRiku Voipio1-2/+2
The rounding/truncating options were inverted. truncating was done when rounding was meant and vice verse. Signed-off-by: Riku Voipio <riku.voipio@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-23ARM CP15 tls fixPaul Brook1-9/+7
Fix temporary handling in cp15 tls register load/store. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-02-19target-arm: implement Thumb-2 exception returnRabin Vincent1-2/+10
Support the "subs pc, lr" Thumb-2 exception return instruction. Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-02-19target-arm: fix thumb CPSRabin Vincent1-1/+1
The Thumb CPS currently does not work correctly: CPSID touches more bits than the instruction wants to, and CPSIE does nothing. Fix it by passing the correct mask (the "affect" bits) and value. Signed-off-by: Rabin Vincent <rabin@rab.in>
2010-02-06target-arm: refactor cp15.c13 register accessRiku Voipio1-0/+55
Access the cp15.c13 TLS registers directly with TCG ops instead of with a slow helper. If the the cp15 read/write was not TLS register access, fall back to the cp15 helper. This makes accessing __thread variables in linux-user when apps are compiled with -mtp=cp15 possible. legal cp15 register to acces from linux-user are already checked in cp15_user_ok. While at it, make the cp15.c13 Thread ID registers available only on ARMv6K and newer. Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
2009-12-24target-arm: fix strexdAurelien Jarno1-1/+1
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-22ARM atomic ops rewritePaul Brook1-85/+165
Implement ARMv6 atomic ops (ldrex/strex) using the same trick as PPC. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-11-19ARM FP16 supportPaul Brook1-0/+85
Implement the ARM VFP half precision floating point extensions. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-10-27target-arm: use native tcg-ops for ror/bic/vornAurelien Jarno1-38/+14
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27target-arm: fix neon vsri, vshl and vsli opsJuha Riihimäki1-14/+18
Shift by immediate value is incorrectly overwritten by a temporary variable in the processing of NEON vsri, vshl and vsli instructions. This patch has been revised to also include a fix for the special case where the code would previously try to shift an integer value over 31 bits left/right. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27target-arm: allow modifying vfp fpexc en bit onlyJuha Riihimäki1-0/+3
All other bits except for the EN in the VFP FPEXC register are defined as subarchitecture specific and real functionality for any of the other bits has not been implemented in QEMU. However, current code allows modifying all bits in the VFP FPEXC register leading to problems when guest code is writing 1's to the subarchitecture specific bits and checking whether the bits stay up to verify the existence of functionality which in fact does not exist in QEMU. This patch has been revised to include the same behavior change in the gdb register write function. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27target-arm: add support for neon vld1.64/vst1.64 instructionsJuha Riihimäki1-52/+81
Add support for NEON vld1.64 and vst1.64 instructions. This patch is revised to follow more closely the specification and raises undefined exception if 64bit element size is used for vld2/vst2 or vld4/vst4 instructions. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27target-arm: fix neon vshrn/vrshrn opsJuha Riihimäki1-9/+3
In the existing code shift value is clobbered during the pass loop. This patch changes the code so that it stores the intermediate result in the target neon register directly and eliminates the need to use a temporary to hold the intermediate value thus leaving the shift value in the temporary variable intact. This is a new patch in this version of the patch series. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-29 21:34:43 +0000