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AgeCommit message (Expand)AuthorFilesLines
2015-11-02nir/lower_vec: handle different bit sizesi965-fp64-v3Connor Abbott1-0/+1
2015-11-02i965/vec4: divide width and exec_size by 2 for 64-bit typesConnor Abbott2-7/+28
2015-11-02i965/vec4: translate double immediates to hw regs correctlyConnor Abbott1-1/+4
2015-11-02i965/vec4: avoid dependency control around Align1 instructionsConnor Abbott1-5/+14
2015-11-02XXX vec4 fixup default dest typeConnor Abbott1-1/+1
2015-11-02fixup! i965/vec4/nir: allocate two registers for dvec3/dvec4Connor Abbott1-1/+1
2015-11-02i965: fixup uniform setup for doublesConnor Abbott1-1/+6
2015-11-02fixup! i965/fs: add a pass for lowering PACK opcodesConnor Abbott1-3/+3
2015-11-01fixup! i965/fs: add a pass for legalizing d2fConnor Abbott1-2/+2
2015-11-01XXX don't emit d2f speciallyConnor Abbott1-18/+1
2015-11-01i965/fs: add a pass for legalizing d2fConnor Abbott4-0/+80
2015-11-01fixup! i965/fs: add a pass for lowering PACK opcodesConnor Abbott1-1/+1
2015-11-01XXX use PACK for double packingConnor Abbott1-2/+1
2015-11-01i965/fs: add a pass for lowering PACK opcodesConnor Abbott4-0/+67
2015-11-01i965/fs: add PACK opcodeConnor Abbott5-1/+15
2015-11-01fixup! i965: fix 64-bit immediates in brw_inst(_set)_bitsConnor Abbott1-1/+1
2015-11-01nir/lower_tex: specify bit size in nir_ssa_dest_init()Connor Abbott1-1/+1
2015-11-01nir/two_sided_color: specify bit size in nir_ssa_dest_init()Connor Abbott1-1/+1
2015-11-01nir/lower_clip: specify bitsize in nir_ssa_dest_init()Connor Abbott1-2/+2
2015-11-01i965: add brw_vecn_grf()Connor Abbott1-0/+6
2015-11-01i965/vec4/nir: translate d2f/f2dConnor Abbott1-0/+32
2015-11-01i965/vec4: generate d2f/f2d pseudo-instructionsConnor Abbott1-0/+25
2015-11-01i965/vec4: teach DCE about d2f/f2dConnor Abbott1-0/+2
2015-11-01i965/vec4: teach opt_reduce_swizzle about d2f/f2dConnor Abbott1-0/+6
2015-11-01i965/vec4: add double/float conversion pseudo-opcodesConnor Abbott2-0/+6
2015-11-01i965/vec4/nir: implement double packing/unpackingConnor Abbott1-0/+56
2015-11-01i965/vec4/nir: implement double comparisonsConnor Abbott1-2/+22
2015-11-01i965/vec4/nir: fix emitting 64-bit immediatesConnor Abbott1-3/+19
2015-11-01i965/vec4: don't constant propagate 64-bit immediatesConnor Abbott1-0/+7
2015-11-01i965/vec4: add support for printing DF immediatesConnor Abbott1-0/+3
2015-11-01i965/vec4: add a constructor for DF immediatesConnor Abbott2-0/+10
2015-11-01i965/vec4: teach DCE about 64-bit typesConnor Abbott1-0/+10
2015-11-01i965/vec4/nir: duplicate swizzles and writemasks for doublesConnor Abbott1-7/+25
2015-11-01i965/vec4: set the right type for 64-bit registersConnor Abbott1-0/+3
2015-11-01i965/vec4/nir: allocate two registers for dvec3/dvec4Connor Abbott1-0/+11
2015-11-01i965/vec4: handle doubles in type_size()Connor Abbott1-3/+6
2015-11-01i965: add new BRW_SWIZZLE definesConnor Abbott1-0/+4
2015-11-01i965: add pass for splitting dvec3/dvec4 ALU operationsConnor Abbott4-0/+362
2015-11-01i965/fs: fix dst width calculation in CSEConnor Abbott1-1/+1
2015-11-01i965/fs: fix regs_written in LOAD_PAYLOAD for doublesConnor Abbott1-2/+5
2015-11-01i965/fs: fix is_copy_payload() for doublesConnor Abbott1-2/+2
2015-11-01i965: fix brw_glsl_base_type_for_nir_type() for doublesConnor Abbott1-3/+6
2015-11-01i965: fix brw_type_for_nir_type() for doublesConnor Abbott1-4/+12
2015-11-01i965: use pack/unpackDouble loweringConnor Abbott1-0/+2
2015-11-01i965/fs: fix regs_read() for uniformsConnor Abbott1-1/+1
2015-11-01nir/split_var_copies: handle doublesConnor Abbott1-0/+2
2015-11-01i965/fs: fix compares for doublesConnor Abbott1-3/+31
2015-11-01i965/fs: extend exec_size halving in the generatorConnor Abbott1-6/+10
2015-11-01XXX remove exec size hackConnor Abbott1-7/+0
2015-11-01nir/instr_set: handle 64-bit bit-sizesConnor Abbott2-6/+18
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