diff options
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_gtt.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem_gtt.h | 40 |
1 files changed, 30 insertions, 10 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 5d4bd3e83eec..7dddf4355a5c 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -88,7 +88,6 @@ typedef gen8_gtt_pte_t gen8_ppgtt_pde_t; #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ -#define GEN8_LEGACY_PDPES 4 #define GEN8_PTES_PER_PT (PAGE_SIZE / sizeof(gen8_gtt_pte_t)) /* GEN8 legacy style address is defined as a 3 level page table: @@ -97,8 +96,17 @@ typedef gen8_gtt_pte_t gen8_ppgtt_pde_t; * The difference as compared to normal x86 3 level page table is the PDPEs are * programmed via register. */ +#ifndef CONFIG_32BIT +# define I915_PDPES_PER_PDP(dev) (HAS_48B_PPGTT(dev) ? 512 : 4) +#else +# define I915_PDPES_PER_PDP 4 +#endif +#define GEN8_PML4ES_PER_PML4 512 +#define GEN8_PML4E_SHIFT 39 #define GEN8_PDPE_SHIFT 30 -#define GEN8_PDPE_MASK 0x3 +/* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page + * tables */ +#define GEN8_PDPE_MASK 0x1ff #define GEN8_PDE_SHIFT 21 #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) @@ -196,9 +204,17 @@ struct i915_pagedir { }; struct i915_pagedirpo { - /* struct page *page; */ - DECLARE_BITMAP(used_pdpes, GEN8_LEGACY_PDPES); - struct i915_pagedir *pagedirs[GEN8_LEGACY_PDPES]; + struct page *page; + dma_addr_t daddr; + unsigned long *used_pdpes; + struct i915_pagedir **pagedirs; +}; + +struct i915_pml4 { + struct page *page; + dma_addr_t daddr; + DECLARE_BITMAP(used_pml4es, GEN8_PML4ES_PER_PML4); + struct i915_pagedirpo *pdps[GEN8_PML4ES_PER_PML4]; }; struct i915_address_space { @@ -264,8 +280,9 @@ struct i915_hw_ppgtt { struct kref ref; struct drm_mm_node node; union { - struct i915_pagedirpo pdp; - struct i915_pagedir pd; + struct i915_pml4 pml4; /* GEN8+ & 64b PPGTT */ + struct i915_pagedirpo pdp; /* GEN8+ */ + struct i915_pagedir pd; /* GEN6-7 */ }; union { @@ -412,14 +429,17 @@ static inline size_t gen6_pde_count(uint32_t addr, uint32_t length) temp = min(temp, length), \ start += temp, length -= temp) -#define gen8_for_each_pdpe(pd, pdp, start, length, temp, iter) \ - for (iter = gen8_pdpe_index(start), pd = (pdp)->pagedirs[iter]; \ - length > 0 && iter < GEN8_LEGACY_PDPES; \ +#define gen8_for_each_pdpe_e(pd, pdp, start, length, temp, iter, b) \ + for (iter = gen8_pdpe_index(start), pd = (pdp)->pagedirs[iter]; \ + length > 0 && (iter < b); \ pd = (pdp)->pagedirs[++iter], \ temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT) - start, \ temp = min(temp, length), \ start += temp, length -= temp) +#define gen8_for_each_pdpe(pd, pdp, start, length, temp, iter) \ + gen8_for_each_pdpe_e(pd, pdp, start, length, temp, iter, I915_PDPES_PER_PDP(dev)) + /* Clamp length to the next pagetab boundary */ static inline uint64_t gen8_clamp_pt(uint64_t start, uint64_t length) { |