diff options
| author | Ben Widawsky <ben@bwidawsk.net> | 2016-04-11 12:21:40 -0700 |
|---|---|---|
| committer | Ben Widawsky <ben@bwidawsk.net> | 2016-04-13 10:54:59 -0700 |
| commit | f1cbcc51e6b3b94329252eb5cb68f23adcf4f355 (patch) | |
| tree | f6ca1a81eb1c3223c69d726701782c2967b80384 | |
| parent | 21c1ea4238128bd3b5f9fc1f2aa48f5df9c7f141 (diff) | |
drm/i915: Fix MOCS TC defines
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_mocs.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c index 7c7ac0aa192a..f4e63bd2abef 100644 --- a/drivers/gpu/drm/i915/intel_mocs.c +++ b/drivers/gpu/drm/i915/intel_mocs.c @@ -66,9 +66,9 @@ struct drm_i915_mocs_table { #define L3_WB 3 /* Target cache */ -#define ELLC 0 -#define LLC 1 -#define LLC_ELLC 2 +#define TC_PTE 0 +#define TC_LLC 1 +#define TC_LLC_ELLC 2 /* * MOCS tables @@ -97,15 +97,15 @@ struct drm_i915_mocs_table { */ static const struct drm_i915_mocs_entry skylake_mocs_table[] = { /* { 0x00000009, 0x0010 } */ - { (LE_CACHEABILITY(LE_UC) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(0) | + { (LE_CACHEABILITY(LE_UC) | LE_TGT_CACHE(TC_LLC_ELLC) | LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)), (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC)) }, /* { 0x00000038, 0x0030 } */ - { (LE_CACHEABILITY(LE_PAGETABLE) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) | + { (LE_CACHEABILITY(LE_PAGETABLE) | LE_TGT_CACHE(TC_LLC_ELLC) | LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)), (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) }, /* { 0x0000003b, 0x0030 } */ - { (LE_CACHEABILITY(LE_WB) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) | + { (LE_CACHEABILITY(LE_WB) | LE_TGT_CACHE(TC_LLC_ELLC) | LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)), (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) } }; @@ -113,15 +113,15 @@ static const struct drm_i915_mocs_entry skylake_mocs_table[] = { /* NOTE: the LE_TGT_CACHE is not used on Broxton */ static const struct drm_i915_mocs_entry broxton_mocs_table[] = { /* { 0x00000009, 0x0010 } */ - { (LE_CACHEABILITY(LE_UC) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(0) | + { (LE_CACHEABILITY(LE_UC) | LE_TGT_CACHE(TC_LLC_ELLC) | LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)), (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC)) }, /* { 0x00000038, 0x0030 } */ - { (LE_CACHEABILITY(LE_PAGETABLE) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) | + { (LE_CACHEABILITY(LE_PAGETABLE) | LE_TGT_CACHE(TC_LLC_ELLC) | LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)), (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) }, /* { 0x0000003b, 0x0030 } */ - { (LE_CACHEABILITY(LE_WB) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) | + { (LE_CACHEABILITY(LE_WB) | LE_TGT_CACHE(TC_LLC_ELLC) | LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)), (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) } }; |