|author||Ville Syrjälä <email@example.com>||2015-01-21 19:38:00 +0200|
|committer||Daniel Vetter <firstname.lastname@example.org>||2015-01-22 07:16:00 +0100|
drm/i915: Change CHV WIZ hashing mode to 16x4
I ran a few tests with xonotic and synmark2 trying out the different WIZ hashing modes on CHV. The results seem to match the results I got with IVB/HSW when I did the similar tests on them in the past. That is 16x4 is generally the fastest mode, 8x8 comes next and finally 8x4. On CHV the difference between the modes is at most ~1% in most tests. IIRC on IVB/HSW the difference was a little bigger, but as there doesn't seem to be any real downside to 16x4 let's use it by default. Signed-off-by: Ville Syrjälä <email@example.com> Reviewed-by: Arun Siluvery <firstname.lastname@example.org> Signed-off-by: Daniel Vetter <email@example.com>
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 2a1a178153e1..0bd3976d88e1 100644
@@ -858,6 +858,18 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
/* Improve HiZ throughput on CHV. */
+ * BSpec recommends 8x4 when MSAA is used,
+ * however in practice 16x4 seems fastest.
+ * Note that PS/WM thread counts depend on the WIZ hashing
+ * disable bit, which we don't touch here, but it's good
+ * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).