diff options
| author | Ben Widawsky <benjamin.widawsky@intel.com> | 2014-04-11 18:34:03 -0700 |
|---|---|---|
| committer | Ben Widawsky <benjamin.widawsky@linux.intel.com> | 2014-04-23 10:31:15 -0700 |
| commit | 0841940674871e3e1a6d0af620a0dabeb86f6c12 (patch) | |
| tree | b55ece7a4db786ed5efda060f9da03bae01291b4 | |
| parent | e4aaa5d20ec39e03077dd66e18de4aceedafcdb3 (diff) | |
drm/i915/bdw: cs-stall before state cache invld w/abroadwell-null-ctx
We do this already for previous GENs. I guess we must do it for BDW too
according to DOCS.
"Pipe_control with CS-stall bit set must be issued before a
pipe-control command that has the State Cache Invalidate bit set."
This does not solve the problem I have unfortunately.
I didn't check if this was in Ville's CHV series. If it was, I
apologize.
NOTE: I tried to use smaller lengths for the command, but nothing made
it happy except 6.
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Jordan Justen <jljusten@gmail.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 19 |
1 files changed, 16 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index a9b04d167032..092dea0306d9 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -266,17 +266,25 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring, static int gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring) { - int ret; + int ret, size = 4; - ret = intel_ring_begin(ring, 4); + if (IS_BROADWELL(ring->dev)) + size += 2; + + ret = intel_ring_begin(ring, size); if (ret) return ret; - intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); + intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(size)); intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD); intel_ring_emit(ring, 0); intel_ring_emit(ring, 0); + if (IS_BROADWELL(ring->dev)) { + intel_ring_emit(ring, 0); + intel_ring_emit(ring, 0); + } + intel_ring_advance(ring); return 0; @@ -389,6 +397,11 @@ gen8_render_ring_flush(struct intel_ring_buffer *ring, flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; flags |= PIPE_CONTROL_QW_WRITE; flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; + + /* Workaround: we must issue a pipe_control with CS-stall bit + * set before a pipe_control command that has the state cache + * invalidate bit set. */ + gen7_render_ring_cs_stall_wa(ring); } ret = intel_ring_begin(ring, 6); |