diff options
| author | Xiang, Haihao <haihao.xiang@intel.com> | 2011-06-09 13:13:24 +0800 |
|---|---|---|
| committer | Xiang, Haihao <haihao.xiang@intel.com> | 2011-06-10 11:08:42 +0800 |
| commit | 17be8ff554b8e708c2b7eda504a5060ee4bff2cc (patch) | |
| tree | 67bc95a59fe8c7c415ecb1ac58138fa175321491 /i965_drv_video/shaders/vme/inter_frame.asm | |
| parent | f7848e8ffeedd6901a789d6bc0431354397ea9ee (diff) | |
i965_drv_video: new shaders for VME on Ivybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Diffstat (limited to 'i965_drv_video/shaders/vme/inter_frame.asm')
| -rw-r--r-- | i965_drv_video/shaders/vme/inter_frame.asm | 45 |
1 files changed, 36 insertions, 9 deletions
diff --git a/i965_drv_video/shaders/vme/inter_frame.asm b/i965_drv_video/shaders/vme/inter_frame.asm index 4fa539a..4dd9401 100644 --- a/i965_drv_video/shaders/vme/inter_frame.asm +++ b/i965_drv_video/shaders/vme/inter_frame.asm @@ -15,8 +15,6 @@ // Now, begin source code.... // -include(`vme_header.inc') - /* * __START */ @@ -35,22 +33,37 @@ mov (1) tmp_reg0.12<1>:UD INTER_PART_MASK + INTER_SAD_HAAR + SUB_PEL_MODE_ mov (1) tmp_reg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mov (1) tmp_reg0.22<1>:UW REF_REGION_SIZE {align1}; /* Reference Width&Height, 32x32 */ -mov (8) msg_reg0.0<1>:UD tmp_reg0.0<8,8,1>:UD {align1}; +mov (8) vme_msg_0.0<1>:UD tmp_reg0.0<8,8,1>:UD {align1}; /* m1 */ mov (1) tmp_reg1.4<1>:UD MAX_NUM_MV:UD {align1}; /* Default value MAX 32 MVs */ mov (1) tmp_reg1.8<1>:UD SEARCH_PATH_LEN:UD {align1}; -mov (8) msg_reg1<1>:UD tmp_reg1.0<8,8,1>:UD {align1}; +mov (8) vme_msg_1<1>:UD tmp_reg1.0<8,8,1>:UD {align1}; /* m2 */ -mov (8) msg_reg2<1>:UD 0x0:UD {align1}; +mov (8) vme_msg_2<1>:UD 0x0:UD {align1}; /* m3 */ -mov (8) msg_reg3<1>:UD 0x0:UD {align1}; +mov (8) vme_msg_3<1>:UD 0x0:UD {align1}; -send (8) 0 vme_wb null vme(BIND_IDX_VME,0,0,VME_MESSAGE_TYPE_INTER) mlen 4 rlen 4 {align1}; +/* m4 */ +mov (8) vme_msg_4<1>:UD 0x0:UD {align1}; +send (8) + vme_msg_ind + vme_wb + null + vme( + BIND_IDX_VME, + 0, + 0, + VME_MESSAGE_TYPE_INTER + ) + mlen vme_msg_length + rlen 4 + {align1}; + /* * Oword Block Write message */ @@ -68,10 +81,24 @@ mov (8) msg_reg1.0<1>:UD tmp_reg3.0<8,8,0>:UD {align1}; mov (8) msg_reg2.0<1>:UD tmp_reg3.0<8,8,0>:UD {align1}; /* bind index 3, write 4 oword, msg type: 8(OWord Block Write) */ -send (16) 0 obw_wb null write(BIND_IDX_OUTPUT, 3, 8, 1) mlen 3 rlen 1 {align1}; +send (16) + msg_ind + obw_wb + null + data_port( + OBW_CACHE_TYPE, + OBW_MESSAGE_TYPE, + OBW_CONTROL_3, + OBW_BIND_IDX, + OBW_WRITE_COMMIT_CATEGORY, + OBW_HEADER_PRESENT + ) + mlen 3 + rlen obw_wb_length + {align1}; /* * kill thread */ mov (8) msg_reg0<1>:UD r0<8,8,1>:UD {align1}; -send (16) 0 acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; +send (16) msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; |