summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c')
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c12
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index 03ec1e59876b..997a777dd35b 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -172,11 +172,13 @@ static int polaris10_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
}
-static int
-polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr)
+static int polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr)
{
struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
+ if (!hwmgr->avfs_supported)
+ return 0;
+
PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(hwmgr),
"[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU",
return -EINVAL);
@@ -811,7 +813,7 @@ static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr,
struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
- ref_clk = smu7_get_xclk(hwmgr);
+ ref_clk = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
for (i = 0; i < NUM_SCLK_RANGE; i++) {
@@ -876,7 +878,7 @@ static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
return result;
}
- ref_clock = smu7_get_xclk(hwmgr);
+ ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
for (i = 0; i < NUM_SCLK_RANGE; i++) {
if (clock > smu_data->range_table[i].trans_lower_frequency
@@ -2132,7 +2134,7 @@ static int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
fan_table.TempRespLim = cpu_to_be16(5);
- reference_clock = smu7_get_xclk(hwmgr);
+ reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
fan_table.RefreshPeriod = cpu_to_be32((hwmgr->
thermal_controller.advanceFanControlParameters.ulCycleDelay *