diff options
| author | Ben Skeggs <bskeggs@redhat.com> | 2012-07-13 16:49:49 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2012-10-03 13:12:50 +1000 |
| commit | 70ee6f1cd6911098ddd4c11ee21b69dbe51fb3f9 (patch) | |
| tree | 3621a402910b4f73ef132263d5dbce59c6a1beb0 /drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c | |
| parent | 5787640db6ae722aeadb394d480c7ca21b603e34 (diff) | |
drm/nv04-nv40/fifo: remove use of nouveau_gpuobj_new_fake()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c | 31 |
1 files changed, 13 insertions, 18 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c index e42498fe8876..df53b9f27208 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c @@ -74,7 +74,7 @@ struct nv40_fifo_priv { struct nv40_fifo_chan { struct nouveau_fifo_chan base; - struct nouveau_gpuobj *ramfc; + u32 ramfc; }; static int @@ -91,6 +91,8 @@ nv40_fifo_context_new(struct nouveau_channel *chan, int engine) if (!fctx) return -ENOMEM; + fctx->ramfc = chan->id * 128; + /* map channel control registers */ chan->user = ioremap(pci_resource_start(dev->pdev, 0) + NV03_USER(chan->id), PAGE_SIZE); @@ -100,24 +102,17 @@ nv40_fifo_context_new(struct nouveau_channel *chan, int engine) } /* initialise default fifo context */ - ret = nouveau_gpuobj_new_fake(dev, priv->ramfc->pinst + - chan->id * 128, ~0, 128, - NVOBJ_FLAG_ZERO_ALLOC | - NVOBJ_FLAG_ZERO_FREE, &fctx->ramfc); - if (ret) - goto error; - - nv_wo32(fctx->ramfc, 0x00, chan->pushbuf_base); - nv_wo32(fctx->ramfc, 0x04, chan->pushbuf_base); - nv_wo32(fctx->ramfc, 0x0c, chan->pushbuf->pinst >> 4); - nv_wo32(fctx->ramfc, 0x18, 0x30000000 | - NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | - NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | + nv_wo32(priv->ramfc, fctx->ramfc + 0x00, chan->pushbuf_base); + nv_wo32(priv->ramfc, fctx->ramfc + 0x04, chan->pushbuf_base); + nv_wo32(priv->ramfc, fctx->ramfc + 0x0c, chan->pushbuf->pinst >> 4); + nv_wo32(priv->ramfc, fctx->ramfc + 0x18, 0x30000000 | + NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | + NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | #ifdef __BIG_ENDIAN - NV_PFIFO_CACHE1_BIG_ENDIAN | + NV_PFIFO_CACHE1_BIG_ENDIAN | #endif - NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); - nv_wo32(fctx->ramfc, 0x3c, 0x0001ffff); + NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); + nv_wo32(priv->ramfc, fctx->ramfc + 0x3c, 0x0001ffff); /* enable dma mode on the channel */ spin_lock_irqsave(&dev_priv->context_switch_lock, flags); @@ -125,7 +120,7 @@ nv40_fifo_context_new(struct nouveau_channel *chan, int engine) spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); /*XXX: remove this later, need fifo engine context commit hook */ - nouveau_gpuobj_ref(fctx->ramfc, &chan->ramfc); + nouveau_gpuobj_ref(priv->ramfc, &chan->ramfc); error: if (ret) |