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2019-11-01drm/amd/display: Add ENGINE_ID_DIGD condition check for Navi14amd-mainline-dkms-5.0Zhan liu1-0/+5
[Why] Navi10 has 6 PHY, but Navi14 only has 5 PHY, that is because there is no ENGINE_ID_DIGD in Navi14. Without this patch, many HDMI related issues (e.g. HDMI S3 resume failure, HDMI pink screen on boot) will be observed. [How] If "eng_id" is larger than ENGINE_ID_DIGD, then add "eng_id" by 1. Signed-off-by: Zhan Liu <zhan.liu@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
2019-10-25drm/amd/display: setting the DIG_MODE to the correct value.Zhan Liu1-0/+9
[Why] This patch is for fixing Navi14 HDMI display pink screen issue. [How] Call stream->link->link_enc->funcs->setup twice. This is setting the DIG_MODE to the correct value after having been overridden by the call to transmitter control. Signed-off-by: Zhan Liu <zhan.liu@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
2019-10-25drm/amd/display: Change Navi14's DWB flag to 1Zhan Liu1-1/+1
[Why] DWB (Display Writeback) flag needs to be enabled as 1, or system will throw out a few warnings when creating dcn20 resource pool. Also, Navi14's dwb setting needs to match Navi10's, which has already been set to 1. [How] Change value of num_dwb from 0 to 1. Signed-off-by: Zhan Liu <zhan.liu@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
2019-10-22Bump AMDGPU version to 5.0.89Rui Teng1-1/+1
Change-Id: I9b169e4bb610138023c8008bc1fc7c3708ee4b5a Signed-off-by: Rui Teng <rui.teng@amd.com>
2019-10-22Merge amd-staging-dkms-5.0 into amd-mainline-dkms-5.0Rui Teng92-296/+3030
Change-Id: I187750e2075462a2d36cf184a6757f4e6a819e91 Signed-off-by: Rui Teng <rui.teng@amd.com>
2019-10-21drm/amd/autoconf: Test whether drm_hdmi_vendor_infoframe_from_display_mode() ↵Rui Teng4-0/+22
wants 2 args Signed-off-by: Rui Teng <rui.teng@amd.com> Reviewed-by: Flora Cui <flora.cui@amd.com>
2019-10-21drm/amd/powerplay: update Arcturus driver smu interface XGMI link partEvan Quan2-9/+21
To fit the latest SMU firmware. Change-Id: Ie34e6930577b7a6fe993273f213732696628b264 Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
2019-10-21drm/amdgpu/psp11: fix typo in commentXiaojie Yuan1-1/+1
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
2019-10-21drm/amdgpu/psp11: wait for sOS ready for ring creationXiaojie Yuan1-0/+8
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
2019-10-20drm/amdgpu/psp11: fix typo in commentXiaojie Yuan1-1/+1
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
2019-10-20drm/amdgpu/psp11: wait for sOS ready for ring creationXiaojie Yuan1-0/+8
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
2019-10-19drm/amd/autoconf: narrow HAVE_DMA_FENCE_GET_STUB scopeYifan Zhang1-1/+3
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
2019-10-19drm/amd/autoconf: add drm-amdgpu-fence-to-handle.m4 backYifan Zhang2-1/+2
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
2019-10-18drm/amd/display: add NULL checks for clock manager pointerAhzo2-3/+4
This fixes kernel NULL pointer dereferences on shutdown: RIP: 0010:build_audio_output.isra.0+0x97/0x110 [amdgpu] RIP: 0010:enable_link_dp+0x186/0x300 [amdgpu] Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Ahzo <Ahzo@tutanota.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-18drm/amdgpu/powerplay: implement interface pp_power_profile_modePrike Liang1-0/+34
implement get_power_profile_mode for getting power profile mode status. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com>
2019-10-18drm/amdgpu/vcn: fix allocation size in enc ring testAlex Deucher1-12/+23
We need to allocate a large enough buffer for the session info, otherwise the IB test can overwrite other memory. - Session info is 128K according to mesa - Use the same session info for create and destroy Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204241 Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Tested-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-18drm/amdgpu/uvd7: fix allocation size in enc ring test (v2)Alex Deucher1-11/+22
We need to allocate a large enough buffer for the session info, otherwise the IB test can overwrite other memory. v2: - session info is 128K according to mesa - use the same session info for create and destroy Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204241 Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Tested-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-18drm/amdgpu/uvd6: fix allocation size in enc ring test (v2)Alex Deucher1-10/+21
We need to allocate a large enough buffer for the session info, otherwise the IB test can overwrite other memory. v2: - session info is 128K according to mesa - use the same session info for create and destroy Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204241 Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Tested-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-18drm/amdgpu: fix up for amdgpu_tmz.c and removal of drm/drmP.hStephen Rothwell1-1/+4
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-18drm/amdgpu/soc15: remove unused variablesAlex Deucher1-2/+0
Leftover when I rebased my last baco patches. Trivial. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-18Bump AMDGPU version to 5.0.88Rui Teng1-1/+1
Change-Id: I6e597a0fc656e54933e16b9470c4cb95a070bf2f Signed-off-by: Rui Teng <rui.teng@amd.com>
2019-10-18drm/amdgpu/display: fix build error casused by CONFIG_DRM_AMD_DC_DCN2_1Hersen Wu1-3/+0
when CONFIG_DRM_AMD_DC_DCN2_1 is not enable in .config, there is build error. struct dpm_clocks shoud not be guarded. Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
2019-10-18Merge amd-staging-dkms-5.0 into amd-mainline-dkms-5.0Rui Teng205-2114/+4236
Change-Id: Ia84590ea2eca9058cd1b9b5f73e12783ed8639ee Signed-off-by: Rui Teng <rui.teng@amd.com>
2019-10-18drm/amd/display: Make dc_link_detect_helper staticYueHaibing1-1/+2
Fix sparse warning: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:746:6: warning: symbol 'dc_link_detect_helper' was not declared. Should it be static? Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-18drm/amd/display: null check pp_smu clock table before using itBhawanpreet Lakha1-1/+1
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com>
2019-10-18drm/amd/display: handle dp is usb-cBhawanpreet Lakha3-1/+116
This patch adds handling of dp is usb-c, it is not tested but is needed to support dp over usb-c Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com>
2019-10-18drm/amd/display: use requested_dispclk_khz instead of clkBhawanpreet Lakha1-11/+2
Use requested_dispclk_khz / 1000 directly Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com>
2019-10-18drm/amd/display: enable smu set dcfclkLewis Huang1-2/+2
[Why] SMU fixed this issue after version 0x370c00 [How] enable smu send message to set dcfclk after smu version 0x370c00 Signed-off-by: Lewis Huang <Lewis.Huang@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com>
2019-10-18drm/amd/display: fix header for RN clk mgrjoseph gravenor1-1/+1
[why] Should always MP0_BASE for any register definition from MP per-IP header files. I belive the reason the linux version of MP1_BASE works is The 0th element of the 0th table of that is identical to the corrisponding value of MP0_BASE in the renoir offset header file. The reason we should only use MP0_BASE is There is only one set of per-IP headers MP that includes all register definitions related to SMU IP block. This IP includes MP0, MP1, MP2 and an ecryption engine that can be used only by MP0. As a result all register definitions from MP file should be based only on MP0_BASE data. [How] Change MP1_BASE to MP0_BASE Signed-off-by: joseph gravenor <joseph.gravenor@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com>
2019-10-18drm/amd/display: add sanity check for clk table from smuEric Yang1-0/+8
[Why] Handle the case where we don't get a valid table. Also fixes compiler warning for variable potentially used before assignment. [How] If the entire table has no valid fclk, reject the table and use our own hard code. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com>
2019-10-18drm/amd/display: Fix rn audio playback and video playback speedMichael Strauss1-8/+7
[WHY] dprefclk is improperly read due to incorrect units used. Causes an audio clock to be improperly set, making audio non-functional and videos play back too fast [HOW] Scale dprefclk value from MHz to KHz (multiply by 1000) to ensure that dprefclk_khz is in correct units Signed-off-by: Michael Strauss <michael.strauss@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com>
2019-10-18drm/amd/display: handle "18" case in TruncToValidBPPBhawanpreet Lakha1-0/+2
Handle 18 DecimalBPP like other cases Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com>
2019-10-18drm/amd/display: update odm mode validation to be in line with policyDmytro Laktyushkin1-1/+8
Previously 8k30 worked with dsc and odm combine due to a workaround that ran the formula a second time with dsc support enable should dsc validation fail. This worked when clocks were low enough for formula to enable odm to lower voltage, however now broke due to increased clocks. This change updates the ODM combine policy within the formula to properly reflect our current policy within DC, only enabling ODM when we have to, as well as adding a check for viewport width when dsc is enabled. As a side effect the redundant call to dml when odm is required is now unnecessary. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com>
2019-10-18drm/amd/display: add dummy functions to smu for Renoir Silicon DiagsSung Lee1-1/+1
[Why] Previously only dummy functions were added in Diags for FPGA. On silicon, this would lead to a segmentation fault on silicon diags. [How] Check if diags silicon and if so, add dummy functions. Signed-off-by: Sung Lee <sung.lee@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com>
2019-10-18drm/amd/display: change PP_SM defs to 8Bhawanpreet Lakha1-2/+2
DPM level is 8 these were incorrect before. Fix them Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com>
2019-10-18drm/amd/display: update renoir bounding box and res_capsBhawanpreet Lakha1-11/+13
The values for bounding box and res_caps were incorrect. So Fix them Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com>
2019-10-18drm/amd/display: update dcn21 hubbub registersBhawanpreet Lakha1-10/+7
use dcn20 common regs define to share some regs with dcn20 Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com>
2019-10-18drm/amd/display: add detile buffer size for renoirBhawanpreet Lakha1-0/+1
Detile buffer size affects dcc caps, it was already added for dcn2. Now add it for dcn21 Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com>
2019-10-18drm/amd/display: correct dcn21 NUM_VMID to 16Dmytro Laktyushkin1-1/+1
1 vmid limitation only exists for HOSTVM which is a custom use case anyway. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com>
2019-10-18drm/amd/display: use dcn10 version of program tiling on RenoirEric Yang1-1/+3
[Why] Renoir is gfx9, same as dcn10, not dcn20. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com>
2019-10-18drm/amd/display: initialize RN gpuvm context programming functionDmytro Laktyushkin1-1/+1
Renoir can use vm contexes as long as HOSTVM is off so this should be initialized. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com>
2019-10-18drm/amd/display: Temporary workaround to toggle watermark settingLewis Huang4-0/+15
[Why] Watermarks not propagated to DCHUBP after it is powered on [How] Add temoprary function apply_DEDCN21_147_wa to apply wm settings for Renoir Signed-off-by: Lewis Huang <Lewis.Huang@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com>
2019-10-18drm/amd/display: fix incorrect page table address for renoirBhawanpreet Lakha1-6/+17
Incorrect page table address and programming sys aperture for stutter gather, so fix it. Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com>
2019-10-18drm/amd/display: enable hostvm based on roimmu active for dcn2.1Dmytro Laktyushkin1-15/+25
Enabling hostvm when ROIMMU is not active seems to break GPUVM. This fixes the issue by not enabling hostvm if ROIMMU is not activated. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com>
2019-10-18drm/amd/display: move the bounding box patch before calculate wmLewis Huang1-0/+25
[why] driver updateis the dcn2_1_soc into dml before call update_bw_bounding_box [How] Move the patch function before calculate wm. Signed-off-by: Lewis Huang <Lewis.Huang@amd.com> Signed-off-by: joseph graveno <joseph.gravenor@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com>
2019-10-18drm/amd/display: add REFCYC_PER_TRIP_TO_MEMORY programmingBhawanpreet Lakha4-4/+69
it allows us to do urgent latency programming Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com>
2019-10-18drm/amd/display: create dcn21_link_encoder filesBhawanpreet Lakha6-4/+555
[Why] DCN20 and DCN21 have different phy programming sequences. [How] Create a separate dcn21_link_encoder for Renoir Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com>
2019-10-18drm/amd/display: Add renoir hw_seqBhawanpreet Lakha7-28/+255
This change adds renoir hw_seq, needed to do renoir specific hw programing Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com>
2019-10-18drm/amd/display: Add DCN_BASE regsBhawanpreet Lakha1-0/+34
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com>
2019-10-18drm/amd/display: Add DP_DPHY_INTERNAL_CTR regsBhawanpreet Lakha1-0/+10
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com>