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2020-06-12Bump AMDGPU version to 5.6.5.20.30amd-20.30Rui Teng1-1/+1
Signed-off-by: Rui Teng <rui.teng@amd.com>
2020-06-08Bump AMDGPU version to 5.6.5Rui Teng1-1/+1
Change-Id: I42760f7cc713010c589cb9fe9b8e2b0c053d6197 Signed-off-by: Rui Teng <rui.teng@amd.com>
2020-06-08Merge amd-staging-dkms-5.6 into amd-mainline-dkms-5.6Rui Teng88-1209/+7047
Change-Id: I7a18a78db009a37f45a4098a83400a77ad3a9dd2 Signed-off-by: Rui Teng <rui.teng@amd.com>
2020-06-05drm/amdkfd: fix debugged process vmid assignment during mappingJonathan Kim1-2/+3
Assign the debug VMID only to the debugged process when debugging is enabled. Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com> Reported-by: Tony Tye <Tony.Tye@amd.com> Tested-by: Kent Russell <Kent.Russell@amd.com>
2020-06-05drm/amdkfd: Redefine KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDEFelix Kuehling6-34/+103
Implement redefined KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE API as specified in SWDEV-237301 to support enabling the address watch trap on current GPUs and potentially other exceptions on future GPUs with a per-process trap-mask. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Tested-by: Laurent Morichetti <Laurent.Morichetti@amd.com>
2020-06-05drm/amdkfd: Simplify some functions that always return 0Felix Kuehling5-36/+20
Make them void, remove the return 0, remove unnecessary error checking in the caller. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
2020-06-05drm/amdkcl: drop individual tests for header filesSlava Grigorev28-411/+247
Change-Id: Ibf7a76190a7dd84dc6776573f62f7784793f2303 Signed-off-by: Slava Grigorev <slava.grigorev@amd.com> Reviewed-by: Flora Cui <flora.cui@amd.com>
2020-06-05drm/amdkcl: add test for drm/drm_backport.hSlava Grigorev2-0/+5
RHEL 7.x wraps some API in drm/drm_backport.h header file Change-Id: I414791a915d5f323d68cbaac8b64c84f62eac973 Signed-off-by: Flora Cui <flora.cui@amd.com> Signed-off-by: Slava Grigorev <slava.grigorev@amd.com>
2020-06-05drm/amdgpu: skip GPU scheduler setup for KIQ and MES ringLikun Gao1-1/+1
Fix the coding error to skip GPU scheduler setup for KIQ and MES ring. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amdgpu: no need to set up GPU scheduler for mes ringJack Xiao1-2/+3
As mes ring directly submits to hardwared, it's no need to set up GPU scheduler for mes ring. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amdgpu: bypass tmr when reserve c2p memoryLikun Gao1-29/+19
C2P memory reserved should not in tmr memory range. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amdgpu: remove unnecessary check for mem trainLikun Gao5-58/+7
a.Check whether mem train support when try to reserve related memory. b.Remove ASIC check and atom firmware table version check as the check of firmware capability is enough to achieve that purpose. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amdgpu: support memory training for sienna_cichlidLikun Gao1-1/+3
Add memory training support for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amdgpu: reserve fb according to return value from vbiosLikun Gao1-56/+71
Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc), otherwise, fallback to legacy approach to check and reserve tmr block for ip discovery data and G6 memory training data respectively Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amd/powerplay: let PMFW to handle the features disablement on BACO in V2Evan Quan1-6/+18
For Sienna_Cichlid, PMFW will handle the features disablement on BACO in. No need to have driver stepped in. V2: limit this for baco really Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amd/powerplay: drop sienna_cichlid hardcode of using pptableLikun Gao1-2/+1
Drop the hardcode of sienna_cichlid which will force to use softpptable, so that it can use pptable on vbios once the value of pp_table_id get from vbios is 0. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amd/powerplay: update smu function for sienna_cichlidLikun Gao1-56/+45
Add function to check whether baco is support for sienna cichlid. Remove fucntion of get clock by type with latency as it will not be called. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amdgpu: update golden setting for sienna_cichlidLikun Gao1-0/+2
Update golden setting for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amdgpu/psp: support for loading PSP SPL fwLikun Gao3-0/+46
Add support for loading SPL firmware. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amdgpu/psp: initialization PSP SPL fwLikun Gao2-0/+37
Support for psp firmware header version v1_3 initialization and information print. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amdgpu/psp: add structure to support PSP SPLLikun Gao2-0/+11
Add support for PSP SPL (Security patch level) table to support anti-rollback of FW loaded by Trusted OS. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amd/powerplay: show gfxclk=0 in gfxoff stateKenneth Feng1-3/+4
The instant retrieved gfxclk value should be 0 in gfxoff state. This can be fetched with gfxoff enabled. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amdgpu: enable gfxoff for sienna_cichlidLikun Gao3-3/+5
Enable GFXOFF for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amd/amdgpu: disable gfxoff to retrieve gfxclkLikun Gao1-11/+60
For Sienna_Cichlid, GFXOFF state puts gfx dpm into standby mode, then the gfxclk can't be retireved. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amd/powerplay: support mclk socclk limit value set for sienna_cichlid.Likun Gao1-0/+4
Add support to force and unforce MCLK or SOCCLK to dpm limit value. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amdgpu/sriov : Add sriov detection for sienna_cichlidshaoyunl1-0/+1
This is a regression due to the rebase , add sienna_cichlid sriov detection back Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amdgpu: only use one gfx pipe for Sienna_CichlidLikun Gao1-2/+2
Only enable one gfx pipe for sienna_cichlid currently. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amd/powerplay: drop jpeg instance1 dpm setupLikun Gao1-6/+0
VCN removed JPEG for instance 1, so drop jpeg instance1 dpm setup. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amdgpu: disable runtime pm for sienna_cichlid temporarilyLikun Gao1-0/+1
Disable runtime pm for sienna_cichlid temporarily as BACO regression issue. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amd/powerplay: enable fw ctfKenneth Feng1-0/+1
fw ctf can be triggered if the temperature can't be throttled below the limit. then the gpu will be powered off and the whole system will hang. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amd/powerplay: enable VDDCI and MVDD for sienna_cichlidLikun Gao1-1/+3
Enable VDDCI and MVDD if PP_MCLK_DPM_MASK was enable for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amd/powerplay: append pptable for sienna_cichlid (v2)Likun Gao1-0/+101
Add function to append powerplay table from vbios for sienna_cichlid. v2: squash in warning fix Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amd/powerplay: and smc dpm info struct for sienna_cichlidLikun Gao1-0/+123
And atom_smc_dpm_info_v4_9 struct for sienna_cichlid use. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amdgpu/sriov : Use kiq to do tlb invalidation for gfx10 on sriovshaoyunl2-0/+21
On SRIOV run time, driver shouldn't directly access invalidation registers through MMIO. Use kiq to submit wait_reg_mem package for the invalidation Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amd/powerplay: enable ULCK DS for sienna_cichlidLikun Gao1-0/+1
Enable uclk deep sleep for sienna_cichlid. Df cstate kicks in first, then df triggers uclk ds with the sideband. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amdgpu/vcn3.0: schedule instance 0 for decode and 1 for encodeAlex Deucher1-0/+4
VCN3 has 2 unsymmetrical instances, i.e there're less codecs on instance 1, we use 0 for decode and 1 for encode for now Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amdgpu/mes10.1: add no scheduler flag for mesAlex Deucher1-0/+1
We don't want a gpu scheduler for mes. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amdgpu: enable DPG mode for VCN3.0Boyuan Zhang2-2/+6
Enable DPG mode for VCN3.0 by updating related flag. V2: update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amdgpu: add workaround for issue in DPG for VCN3.0Boyuan Zhang1-0/+4
To workaround an issue in DPG V2: update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amdgpu: rename macro for VCN2.0 2.5 and 3.0Boyuan Zhang4-137/+137
Rename SOC15_DPG_MODE_OFFSET_2_0, RREG32_SOC15_DPG_MODE_2_0 and WREG32_SOC15_DPG_MODE_2_0 for VCN2.0, VCN2.5 and VCN3.0. These three macros are used VCN2.0, VCN2.5 and VCN3.0, therefore rename it to be a general name. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amdgpu: rename macro for VCN1.0Boyuan Zhang2-50/+50
Rename RREG32_SOC15_DPG_MODE and WREG32_SOC15_DPG_MODE for VCN1.0 These two macros are used specifically for VCN1.0, therefore rename it from general name to VCN1.0 specific name. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amdgpu: add internal reg offset translation for VCN inst 1Boyuan Zhang1-1/+13
Add range for vcn instance 1 for translation for internal register offset, which is needed for VCN3.0 V2: update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amdgpu: set indirect sram mode for VCN3.0Boyuan Zhang1-0/+3
Use indirect sram for secure DPG mode V2: update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amdgpu: add pause DPG mode for VCN3.0Boyuan Zhang1-0/+66
Add vcn_v3_0_pause_dpg_mode to pause/unpause DPG mode for VCN3.0 V2: update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amdgpu: add stop DPG mode for VCN3.0Boyuan Zhang1-0/+34
Add vcn_v3_0_stop_dpg_mode to power off in DPG mode for VCN3.0 V2: update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amdgpu: add start DPG mode for VCN3.0Boyuan Zhang1-0/+141
Add vcn_v3_0_start_dpg_mode to setup and start VCN block in DPG mode for VCN3.0 V2: Separate from previous patch-0002, and update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amdgpu: add mc resume DPG mode for VCN3.0Boyuan Zhang1-0/+89
Add vcn_v3_0_mc_resume_dpg_mode to resume memory controller in DPG mode for VCN3.0 V2: Separate from previous patch-0002, and update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amdgpu: add clock gating DPG mode for VCN3.0Boyuan Zhang1-0/+48
Add vcn_v3_0_clock_gating_dpg_mode to enabling clock gating in DPG mode for VCN3.0 V2: Separate from previous patch-0002, and update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/am/powerplay: enable OUT OF BAND MONITER for sienna_cichlidLikun Gao1-1/+2
Enable OUT OF BAND MONITER for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-05drm/amd/powerplay: enable RSMU SMN PG for sienna_cichlidLikun Gao1-0/+1
Enable RSMU SMN PG for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-25 15:31:06 +0000