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2019-12-03Revert "drm/amdgpu: Set GTT size to be bigger than 3/4 of RAM"amd-19.30Kevin Wang1-4/+5
This reverts commit fe775461ea80feed0ac2be7deb4ad1a6427002a6. Change-Id: I0f5f3f3de2da30ce518cb1327ca667c72a483229 Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Acked-by: Feifei Xu <feifei.xu@amd.com>
2019-11-28drm/amdgpu: put flush_delayed_work at firstYintian Tao1-3/+1
There is one regression from 042f3d7b745cd76aa To put flush_delayed_work after adev->shutdown = true which will make amdgpu_ih_process not response the irq At last, all ib ring tests will be failed just like below [drm] amdgpu: finishing device. [drm] Fence fallback timer expired on ring gfx [drm] Fence fallback timer expired on ring comp_1.0.0 [drm] Fence fallback timer expired on ring comp_1.1.0 [drm] Fence fallback timer expired on ring comp_1.2.0 [drm] Fence fallback timer expired on ring comp_1.3.0 [drm] Fence fallback timer expired on ring comp_1.0.1 amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on comp_1.1.1 (-110). amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on comp_1.2.1 (-110). amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on comp_1.3.1 (-110). amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on sdma0 (-110). amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on sdma1 (-110). amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on uvd_enc_0.0 (-110). amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on vce0 (-110). [drm:amdgpu_device_delayed_init_work_handler [amdgpu]] *ERROR* ib ring test failed (-110). v2: replace cancel_delayed_work_sync() with flush_delayed_work() Signed-off-by: Yintian Tao <yttao@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-13drm/amd/powerplay: maintain SMU FW backward compatibilityEvan Quan1-2/+9
Do not halt driver loading on if_version mismatch. As our driver and FWs are backward compatible. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-11SWDEV-208855 - drm/amd/amdgpu: finish delay works before release resourcesJesse Zhang3-0/+5
flush/cancel delayed works before doing finalization to avoid concurrently requests. Change-Id: I85b7ffbb34875af1c734cb4573a6ecc71d39d652 Signed-off-by: Jesse Zhang <zhexi.zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2019-11-07SWDEV-210749 drm/amdgpu: Need to disable msix when unloading driverEmily Deng1-0/+4
For driver reload test, it will report "can't enable MSI (MSI-X already enabled)". Change-Id: Id98a33e8404d8d803f20d9694f2f04a6e5251fb7 Signed-off-by: Emily Deng <Emily.Deng@amd.com>
2019-11-05drm/amdgpu/discovery: Need to free discovery memoryEmily Deng1-3/+3
When unloading driver, need to free discovery memory. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
2019-11-01drm/amd/display: Add ENGINE_ID_DIGD condition check for Navi14Zhan Liu1-0/+5
[Why] Navi10 has 6 PHY, but Navi14 only has 5 PHY, that is because there is no ENGINE_ID_DIGD in Navi14. Without this patch, many HDMI related issues (e.g. HDMI S3 resume failure, HDMI pink screen on boot) will be observed. [How] If "eng_id" is larger than ENGINE_ID_DIGD, then add "eng_id" by 1. Signed-off-by: Zhan Liu <zhan.liu@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
2019-11-01drm/amd/powerplay/smu11: disable uclk dpm feature on navi14Tianci.Yin1-0/+8
disable DPM UCLK on navi14 Change-Id: Id92555a4447a85200dea67250691352219897639 Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
2019-11-01drm/amdgpu/gmc10: properly set BANK_SELECT and FRAGMENT_SIZEAlex Deucher2-0/+18
These were not aligned for optimal performance for GPUVM. Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tianci Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-29drm/amdgpu: improve MSI-X handling (v3)Alex Deucher1-4/+13
Check the number of supported vectors and fall back to MSI if we return or error or 0 MSI-X vectors. v2: only allocate one vector. We can't currently use more than one anyway. v3: install the irq on vector 0. Tested-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Shaoyun liu <shaoyun.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-29drm/amdgpu : enable msix for amdgpu drivershaoyunl1-2/+3
We might used out of the msi resources in some cloud project which have a lot gpu devices(including PF and VF), msix can provide enough resources from system level view Change-Id: I9f03762074ac416c07f27b8f00c052ca93c7d6cb Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amdgpu/gfx10: update gfx golden settings for navi14Tianci.Yin1-1/+1
update registers: mmCGTT_SPI_CLK_CTRL Change-Id: Ib2539aae1fb0d001278b7f89c90ad6296f9fb85f Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
2019-10-25drm/amdgpu/gfx10: update gfx golden settingsTianci.Yin1-1/+1
update registers: mmCGTT_SPI_CLK_CTRL Change-Id: Ic64d532c61adfdeb681903f1133d9b353579ac55 Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
2019-10-22drm/amd/display: Change Navi14's DWB flag to 1Zhan Liu1-1/+1
[Why] DWB (Display Writeback) flag needs to be enabled as 1, or system will throw out a few warnings when creating dcn20 resource pool. Also, Navi14's dwb setting needs to match Navi10's, which has already been set to 1. [How] Change value of num_dwb from 0 to 1. Signed-off-by: Zhan Liu <zhan.liu@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
2019-10-17drm/amd/display: setting the DIG_MODE to the correct value.Zhan Liu1-0/+9
[Why] This patch is for fixing Navi14 HDMI display pink screen issue. [How] Call stream->link->link_enc->funcs->setup twice. This is setting the DIG_MODE to the correct value after having been overridden by the call to transmitter control. Signed-off-by: Zhan Liu <zhan.liu@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
2019-10-16drm/amd/powerplay: bug fix for memory clock request from displayKenneth Feng1-0/+2
In some cases, display fixes memory clock frequency to a high value rather than the natural memory clock switching. When we comes back from s3 resume, the request from display is not reset, this causes the bug which makes the memory clock goes into a low value. Then due to the insuffcient memory clock, the screen flicks. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
2019-10-16drm/amd/powerplay: fix deadlock around smu_handle_task V2Evan Quan1-3/+0
As the lock was already held on the entrance to smu_handle_task. - V2: lock in small granularity Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-14drm/amdgpu/discovery: reserve discovery data at the top of VRAMXiaojie Yuan5-3/+22
IP Discovery data is TMR fenced by the latest PSP BL, so we need to reserve this region. Tested on navi10/12/14 with VBIOS integrated with latest PSP BL. v2: use DISCOVERY_TMR_SIZE macro as bo size use amdgpu_bo_create_kernel_at() to allocate bo Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-14drm/amdgpu: once more fix amdgpu_bo_create_kernel_atChristian König1-3/+6
When CPU access is needed we should tell that to amdgpu_bo_create_reserved() or otherwise the access is denied later on. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com>
2019-10-14drm/amdgpu/ras: use GPU PAGE_SIZE/SHIFT for reserving pagesAlex Deucher1-1/+2
We are reserving vram pages so they should be aligned to the GPU page size. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2019-10-14drm/amdgpu: replace DRM_ERROR with DRM_WARN in ras_reserve_bad_pagesTao Zhou1-1/+6
There are two cases of reserve error should be ignored: 1) a ras bad page has been allocated (used by someone); 2) a ras bad page has been reserved (duplicate error injection for one page); DRM_ERROR is unnecessary for the failure of bad page reserve Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-14drm/amdgpu: cleanup creating BOs at fixed location (v2)Christian König4-150/+85
The placement is something TTM/BO internal and the RAS code should avoid touching that directly. Add a helper to create a BO at a fixed location and use that instead. v2: squash in fixes (Alex) Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-13Revert "drm/amdgpu/discovery: reserve discovery data at the top of VRAM"Rui Teng5-22/+3
This reverts commit e279331b9aa915b4092e8807fe2e84e377c0b105. It requires the patch about amdgpu_bo_create_kernel_at(). Signed-off-by: Rui Teng <rui.teng@amd.com>
2019-10-12drm/amdgpu/discovery: reserve discovery data at the top of VRAMXiaojie Yuan5-3/+22
IP Discovery data is TMR fenced by the latest PSP BL, so we need to reserve this region. Tested on navi10/12/14 with VBIOS integrated with latest PSP BL. v2: use DISCOVERY_TMR_SIZE macro as bo size use amdgpu_bo_create_kernel_at() to allocate bo Change-Id: I5a59b67d52464db7ea124468cab906793af61b72 Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-12drm/amdgpu/gfx10: add support for wks firmware loadingTianci.Yin1-6/+16
load different cp firmware according to the DID and RID Change-Id: I6bb4cee12c8c47be6d3ef1150df93d7e1fbbecc7 Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
2019-10-12drm/ttm: fix handling in ttm_bo_add_mem_to_lruChristian König1-2/+3
We should not add the BO to the swap LRU when the new mem is fixed and the TTM object about to be destroyed. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
2019-10-11drm/amdgpu/swSMU: custom UMD pstate peak clock for navi14Kevin Wang2-14/+45
add navi14 umd pstate peak clock support. NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK 1670 MHz NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK 1448 MHz NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK 1181 MHz NAVI14_UMD_PSTATE_PEAK_XTX_GFXCLK 1717 MHz NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK 1448 MHz Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
2019-10-10drm/amdgpu/sdma5: fix mask value of POLL_REGMEM packet for pipe syncXiaojie Yuan1-1/+1
sdma will hang once sequence number to be polled reaches 0x1000_0000 Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2019-09-29drm/amd/powerplay: some cosmetic fixesEvan Quan2-35/+28
Drop redundant check, duplicate check, duplicate setting and fix the return value. Change-Id: I04171bcac82f17152371d05e6958d4fc072c0f6b Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2019-09-27drm/amd/powerplay: add sensor lock support for smuKevin Wang4-0/+7
when multithreading access sysfs of amdgpu_pm_info at the sametime. the swsmu driver cause smu firmware hang. eg: single thread access: Message A + Param A ==> right Message B + Param B ==> right Message C + Param C ==> right multithreading access: Message A + Param B ==> error Message B + Param A ==> error Message C + Param C ==> right the patch will add sensor lock(mutex) to avoid this error. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
2019-09-27drm/amd/powerplay: change metrics update period from 1ms to 100msKevin Wang1-1/+1
v2: change period from 10ms to 100ms (typo error) too high frequence to update mertrics table will cause smu firmware error,so change mertrics table update period from 1ms to 100ms (navi10, 12, 14) Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
2019-09-27drm/amd/powerplay: change smu_read_sensor sequence in smuKenneth Feng5-8/+17
change the smu_read_sensor sequence to: asic specific sensor read -> smu v11 specific sensor read -> smu v11 common sensor read Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-09-27drm/amd/powerplay: honor hw limit on fetching metrics data for navi10Kevin Wang1-13/+33
too frequently to update mertrics table will cause smu internal error. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com>
2019-09-27drm/amdgpu: fix CPDMA hang in PRT mode for VEGA10Tianci.Yin1-9/+9
add and_mask since the programming logic of golden setting changed Change-Id: If3744beb779c56255c7e797eb115bd6e462237c5 Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
2019-09-23drm/amd/powerpaly: fix navi series custom peak level value errorKevin Wang1-0/+4
fix other navi asic set peak performance level error. because the navi10_ppt.c will handle navi12 14 asic, it will use navi10 peak value to set other asic, it is not correct. after patch: only navi10 use custom peak value, other asic will used default value. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-09-18drm/amdgpu/gfx10: update gfx golden settings for navi14Tianci.Yin1-1/+1
update registers: mmUTCL1_CTRL, Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
2019-09-18drm/amdgpu/gfx10: update gfx golden settingsTianci.Yin1-1/+1
update registers: mmUTCL1_CTRL, Change-Id: Icb50fb35a427a50a06138b8b3715651eebe92b95 Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
2019-09-12drm/amd/display: correct dc_link detect on eDP displayZhan Liu1-0/+4
[Why] Every time system resume from S3, link->local_sink needs to be checked, or eDP won't light up. [How] Add link->local_sink check for eDP. Signed-off-by: Zhan Liu <zhan.liu@amd.com> Reviewed-by: Roman Li <roman.li@amd.com>
2019-09-03drm/amd/powerplay: correct navi10 vcn powergateEvan Quan3-9/+19
vcn dpm on is a prerequisite for vcn power gate control. Change-Id: If89a81bc0709f1c26569e378507a873cfaf6e0ef Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
2019-09-03drm/amd/powerplay: correct UVD/VCE/VCN power status retrievalEvan Quan1-20/+36
VCN should be used for Vega20 later ASICs while UVD and VCE are for previous ASICs. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-09-03drm/amd/powerplay: correct Navi10 VCN powergate control (v2)Evan Quan1-18/+10
No VCN DPM bit check as that's different from VCN PG. Also no extra check for possible double enablement/disablement as that's already done by VCN. v2: check return value of smu_feature_set_enabled Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-09-03drm/amd/powerplay: support VCN powergate status retrieval for SW SMUEvan Quan1-0/+4
Commonly used for VCN powergate status retrieval for SW SMU. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-09-03drm/amd/powerplay: support VCN powergate status retrieval on RavenEvan Quan1-0/+9
Enable VCN powergate status report on Raven. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-09-03drm/amd/powerplay: add new sensor type for VCN powergate statusEvan Quan1-0/+1
VCN is widely used in new ASICs and different from tranditional UVD and VCE. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-20drm/amd/amdgpu: disable MMHUB PG for navi10Kenneth Feng1-1/+0
Disable MMHUB PG for navi10 according to the production requirement. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
2019-08-08drm/amd/powerplay: update smu11_driver_if_navi10.htiancyin2-6/+21
update the smu11_driver_if_navi10.h since navi14 smu fw update to 53.12 Change-Id: If0f729ec87c98f24e1794f0847eac5ba23671e34 Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: tiancyin <tianci.yin@amd.com>
2019-08-08drm/amd/powerplay: re-define smu interface version for smu v11tiancyin6-4/+26
[why] navi14 share same defination of smu interface version with navi10, anyone of them update the version may break the other one's version checking. [how] create different version defination, so that they can update their version separately. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: tiancyin <tianci.yin@amd.com>
2019-08-08drm/amdgpu: add navi14 PCI IDAlex Deucher1-0/+2
Add the navi14 PCI device id. Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-08drm/amdgpu/soc15: fix external_rev_id for navi14tiancyin1-1/+1
fix the hard code external_rev_id. Change-Id: I7b46f7b49b6d0586d1fa282d4961815fb124379b Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: tiancyin <tianci.yin@amd.com>
2019-08-08drm/amdgpu/psp11: simplify the ucode register logicAlex Deucher1-8/+4
Split it between navi10 and newer and everything before navi10. Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>