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| author | Tianci.Yin <tianci.yin@amd.com> | 2019-08-22 15:09:29 +0800 |
|---|---|---|
| committer | Tianci Yin <Tianci.Yin@amd.com> | 2019-09-18 21:58:27 -0400 |
| commit | 50f8c9b1c28a6f8d69fc2f5cb77a292d40f86aab (patch) | |
| tree | 0dcd93de27e07adf45772d3d177f71d672439c40 /drivers/gpu | |
| parent | b80d25e2339e49e5e1b79662bc035e2c585c6aa8 (diff) | |
drm/amdgpu/gfx10: update gfx golden settings for navi14
update registers: mmUTCL1_CTRL,
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 7901530d07f0..121824b47d02 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -161,7 +161,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), - SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), }; static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = |