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authorHarry Wentland <harry.wentland@amd.com>2015-12-17 14:01:53 -0500
committerAlex Deucher <alexander.deucher@amd.com>2016-03-09 14:36:57 -0500
commitf202ec0feb042726fc58d157059606086e857adf (patch)
tree80a4b3f34155314080193ffddaf1e6d3f992ef1e
parent50e35f9018478b99946111a808163b3244095fbe (diff)
drm/amd/dal: Asic Capabilities
Add a generic way to manage display HW capabilities for different ASICs and implement it for Carrizo. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile35
-rw-r--r--drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c190
-rw-r--r--drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c147
-rw-r--r--drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.h36
-rw-r--r--drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c146
-rw-r--r--drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.h36
6 files changed, 590 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile b/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
new file mode 100644
index 000000000000..8491b38ae726
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
@@ -0,0 +1,35 @@
+#
+# Makefile for the 'asic_capability' sub-component of DAL.
+#
+
+ASIC_CAPABILITY = asic_capability.o
+
+AMD_DAL_ASIC_CAPABILITY = \
+ $(addprefix $(AMDDALPATH)/dc/asic_capability/,$(ASIC_CAPABILITY))
+
+AMD_DAL_FILES += $(AMD_DAL_ASIC_CAPABILITY)
+
+###############################################################################
+# DCE 10x
+###############################################################################
+ifdef CONFIG_DRM_AMD_DAL_DCE10_0
+ASIC_CAPABILITY_DCE10 = tonga_asic_capability.o
+
+AMD_DAL_ASIC_CAPABILITY_DCE10 = \
+ $(addprefix $(AMDDALPATH)/dc/asic_capability/,$(ASIC_CAPABILITY_DCE10))
+
+AMD_DAL_FILES += $(AMD_DAL_ASIC_CAPABILITY_DCE10)
+endif
+
+
+###############################################################################
+# DCE 11x
+###############################################################################
+ifdef CONFIG_DRM_AMD_DAL_DCE11_0
+ASIC_CAPABILITY_DCE11 = carrizo_asic_capability.o
+
+AMD_DAL_ASIC_CAPABILITY_DCE11 = \
+ $(addprefix $(AMDDALPATH)/dc/asic_capability/,$(ASIC_CAPABILITY_DCE11))
+
+AMD_DAL_FILES += $(AMD_DAL_ASIC_CAPABILITY_DCE11)
+endif
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
new file mode 100644
index 000000000000..7a905f532040
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
@@ -0,0 +1,190 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+#include "include/logger_interface.h"
+
+#include "include/asic_capability_interface.h"
+#include "include/asic_capability_types.h"
+#include "include/dal_types.h"
+#include "include/dal_asic_id.h"
+
+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
+#include "tonga_asic_capability.h"
+#endif
+
+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
+#include "carrizo_asic_capability.h"
+#endif
+
+/*
+ * Initializes asic_capability instance.
+ */
+static bool construct(
+ struct asic_capability *cap,
+ struct hw_asic_id *init,
+ struct dc_context *ctx)
+{
+ bool asic_supported = false;
+
+ cap->ctx = ctx;
+ dm_memset(cap->data, 0, sizeof(cap->data));
+
+ /* ASIC data */
+ cap->data[ASIC_DATA_VRAM_TYPE] = init->vram_type;
+ cap->data[ASIC_DATA_VRAM_BITWIDTH] = init->vram_width;
+ cap->data[ASIC_DATA_FEATURE_FLAGS] = init->feature_flags;
+ cap->runtime_flags = init->runtime_flags;
+ cap->data[ASIC_DATA_REVISION_ID] = init->hw_internal_rev;
+ cap->data[ASIC_DATA_MAX_UNDERSCAN_PERCENTAGE] = 10;
+ cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 4;
+ cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM] = 1;
+ cap->data[ASIC_DATA_NUM_OF_VIDEO_PLANES] = 0;
+ cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ] = 25;
+
+ /* ASIC basic capability */
+ cap->caps.UNDERSCAN_FOR_HDMI_ONLY = true;
+ cap->caps.SUPPORT_CEA861E_FINAL = true;
+ cap->caps.MIRABILIS_SUPPORTED = false;
+ cap->caps.MIRABILIS_ENABLED_BY_DEFAULT = false;
+ cap->caps.WIRELESS_LIMIT_TO_720P = false;
+ cap->caps.WIRELESS_FULL_TIMING_ADJUSTMENT = false;
+ cap->caps.WIRELESS_TIMING_ADJUSTMENT = true;
+ cap->caps.WIRELESS_COMPRESSED_AUDIO = false;
+ cap->caps.VCE_SUPPORTED = false;
+ cap->caps.HPD_CHECK_FOR_EDID = false;
+ cap->caps.NO_VCC_OFF_HPD_POLLING = false;
+ cap->caps.NEED_MC_TUNING = false;
+ cap->caps.SUPPORT_8BPP = true;
+
+ /* ASIC stereo 3D capability */
+ cap->stereo_3d_caps.SUPPORTED = true;
+
+ switch (init->chip_family) {
+ case FAMILY_CI:
+ break;
+
+ case FAMILY_KV:
+ if (ASIC_REV_IS_KALINDI(init->hw_internal_rev) ||
+ ASIC_REV_IS_BHAVANI(init->hw_internal_rev)) {
+ } else {
+ }
+ break;
+
+ case FAMILY_CZ:
+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
+ carrizo_asic_capability_create(cap, init);
+ asic_supported = true;
+#endif
+ break;
+ case FAMILY_VI:
+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
+ if (ASIC_REV_IS_TONGA_P(init->hw_internal_rev) ||
+ ASIC_REV_IS_FIJI_P(init->hw_internal_rev)) {
+ tonga_asic_capability_create(cap, init);
+ asic_supported = true;
+ break;
+ }
+#endif
+ break;
+ default:
+ /* unsupported "chip_family" */
+ break;
+ }
+
+ if (false == asic_supported) {
+ dal_logger_write(ctx->logger,
+ LOG_MAJOR_ERROR,
+ LOG_MINOR_MASK_ALL,
+ "%s: ASIC not supported!\n", __func__);
+ }
+
+ return asic_supported;
+}
+
+static void destruct(
+ struct asic_capability *cap)
+{
+ /* nothing to do (yet?) */
+}
+
+/*
+ * dal_asic_capability_create
+ *
+ * Creates asic capability based on DCE version.
+ */
+struct asic_capability *dal_asic_capability_create(
+ struct hw_asic_id *init,
+ struct dc_context *ctx)
+{
+ struct asic_capability *cap;
+
+ if (!init) {
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
+
+ cap = dm_alloc(ctx, sizeof(struct asic_capability));
+
+ if (!cap) {
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
+
+ if (construct(cap, init, ctx))
+ return cap;
+
+ BREAK_TO_DEBUGGER();
+
+ dm_free(ctx, cap);
+
+ return NULL;
+}
+
+/*
+ * dal_asic_capability_destroy
+ *
+ * Destroy allocated memory.
+ */
+void dal_asic_capability_destroy(
+ struct asic_capability **cap)
+{
+ if (!cap) {
+ BREAK_TO_DEBUGGER();
+ return;
+ }
+
+ if (!*cap) {
+ BREAK_TO_DEBUGGER();
+ return;
+ }
+
+ destruct(*cap);
+
+ dm_free((*cap)->ctx, *cap);
+
+ *cap = NULL;
+}
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
new file mode 100644
index 000000000000..4aa8c305b08c
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+#include "include/asic_capability_interface.h"
+#include "include/asic_capability_types.h"
+
+#include "carrizo_asic_capability.h"
+
+#include "atom.h"
+#include "dce/dce_11_0_d.h"
+#include "smu/smu_8_0_d.h"
+#include "dce/dce_11_0_sh_mask.h"
+#include "dal_asic_id.h"
+
+#define ixVCE_HARVEST_FUSE_MACRO__ADDRESS 0xC0014074
+
+/*
+ * carrizo_asic_capability_create
+ *
+ * Create and initiate Carrizo capability.
+ */
+void carrizo_asic_capability_create(struct asic_capability *cap,
+ struct hw_asic_id *init)
+{
+ uint32_t e_fuse_setting;
+ /* ASIC data */
+ cap->data[ASIC_DATA_CONTROLLERS_NUM] = 3;
+ cap->data[ASIC_DATA_DIGFE_NUM] = 3;
+ cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM] = 3;
+ cap->data[ASIC_DATA_LINEBUFFER_NUM] = 3;
+ cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 4;
+ cap->data[ASIC_DATA_DCE_VERSION] = 0x110; /* DCE 11 */
+ cap->data[ASIC_DATA_LINEBUFFER_SIZE] = 1712 * 144;
+ cap->data[ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY] = 45;
+ cap->data[ASIC_DATA_CLOCKSOURCES_NUM] = 2;
+ cap->data[ASIC_DATA_MC_LATENCY] = 5000;
+ cap->data[ASIC_DATA_STUTTERMODE] = 0x200A;
+ cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 2;
+ cap->data[ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS] = 2;
+ cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 2;
+ cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ] = 100;
+ cap->data[ASIC_DATA_NUM_OF_VIDEO_PLANES] = 1;
+ cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM] = 3;
+
+ /* ASIC basic capability */
+ cap->caps.IS_FUSION = true;
+ cap->caps.DP_MST_SUPPORTED = true;
+ cap->caps.PANEL_SELF_REFRESH_SUPPORTED = true;
+ cap->caps.MIRABILIS_SUPPORTED = true;
+ cap->caps.NO_VCC_OFF_HPD_POLLING = true;
+ cap->caps.VCE_SUPPORTED = true;
+ cap->caps.HPD_CHECK_FOR_EDID = true;
+ cap->caps.DFSBYPASS_DYNAMIC_SUPPORT = true;
+ cap->caps.SUPPORT_8BPP = false;
+
+ /* ASIC stereo 3d capability */
+ cap->stereo_3d_caps.DISPLAY_BASED_ON_WS = true;
+ cap->stereo_3d_caps.HDMI_FRAME_PACK = true;
+ cap->stereo_3d_caps.INTERLACE_FRAME_PACK = true;
+ cap->stereo_3d_caps.DISPLAYPORT_FRAME_PACK = true;
+ cap->stereo_3d_caps.DISPLAYPORT_FRAME_ALT = true;
+ cap->stereo_3d_caps.INTERLEAVE = true;
+
+ e_fuse_setting = dm_read_index_reg(cap->ctx,CGS_IND_REG__SMC, ixVCE_HARVEST_FUSE_MACRO__ADDRESS);
+
+ /* Bits [28:27]*/
+ switch ((e_fuse_setting >> 27) & 0x3) {
+ case 0:
+ /*both VCE engine are working*/
+ cap->caps.VCE_SUPPORTED = true;
+ cap->caps.WIRELESS_TIMING_ADJUSTMENT = false;
+ /*TODO:
+ cap->caps.wirelessLowVCEPerformance = false;
+ m_AsicCaps.vceInstance0Enabled = true;
+ m_AsicCaps.vceInstance1Enabled = true;*/
+ cap->caps.NEED_MC_TUNING = true;
+ break;
+
+ case 1:
+ cap->caps.VCE_SUPPORTED = true;
+ cap->caps.WIRELESS_TIMING_ADJUSTMENT = true;
+ /*TODO:
+ m_AsicCaps.wirelessLowVCEPerformance = false;
+ m_AsicCaps.vceInstance1Enabled = true;*/
+ cap->caps.NEED_MC_TUNING = true;
+ break;
+
+ case 2:
+ cap->caps.VCE_SUPPORTED = true;
+ cap->caps.WIRELESS_TIMING_ADJUSTMENT = true;
+ /*TODO:
+ m_AsicCaps.wirelessLowVCEPerformance = false;
+ m_AsicCaps.vceInstance0Enabled = true;*/
+ cap->caps.NEED_MC_TUNING = true;
+ break;
+
+ case 3:
+ /* VCE_DISABLE = 0x3 - both VCE
+ * instances are in harvesting,
+ * no VCE supported any more.
+ */
+ cap->caps.VCE_SUPPORTED = false;
+ break;
+
+ default:
+ break;
+ }
+
+ if (ASIC_REV_IS_STONEY(init->hw_internal_rev))
+ {
+ /* Stoney is the same DCE11, but only two pipes, three digs.
+ * and HW added 64bit back for non SG */
+ cap->data[ASIC_DATA_CONTROLLERS_NUM] = 2;
+ cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM] = 2;
+ cap->data[ASIC_DATA_LINEBUFFER_NUM] = 2;
+ /*3 DP MST per connector, limited by number of pipe and number
+ * of Dig.*/
+ cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 2;
+
+ }
+
+
+}
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.h b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.h
new file mode 100644
index 000000000000..d1e9b8337d5b
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_CARRIZO_ASIC_CAPABILITY_H__
+#define __DAL_CARRIZO_ASIC_CAPABILITY_H__
+
+/* Forward declaration */
+struct asic_capability;
+
+/* Create and initialize Carrizo data */
+void carrizo_asic_capability_create(struct asic_capability *cap,
+ struct hw_asic_id *init);
+
+#endif /* __DAL_CARRIZO_ASIC_CAPABILITY_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
new file mode 100644
index 000000000000..af669c81085b
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+#include "include/asic_capability_interface.h"
+#include "include/asic_capability_types.h"
+
+#include "tonga_asic_capability.h"
+
+#include "atom.h"
+#include "dce/dce_10_0_d.h"
+#include "smu/smu_8_0_d.h"
+#include "dce/dce_10_0_sh_mask.h"
+#include "dal_asic_id.h"
+
+#define ixVCE_HARVEST_FUSE_MACRO__ADDRESS 0xC0014074
+
+/*
+ * carrizo_asic_capability_create
+ *
+ * Create and initiate Carrizo capability.
+ */
+void tonga_asic_capability_create(struct asic_capability *cap,
+ struct hw_asic_id *init)
+{
+ uint32_t e_fuse_setting;
+ /* ASIC data */
+ cap->data[ASIC_DATA_CONTROLLERS_NUM] = 6;
+ cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM] = 6;
+ cap->data[ASIC_DATA_DIGFE_NUM] = 6;
+ cap->data[ASIC_DATA_LINEBUFFER_NUM] = 6;
+
+ cap->data[ASIC_DATA_LINEBUFFER_SIZE] = 1712 * 144;
+ cap->data[ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY] = 70;
+ cap->data[ASIC_DATA_CLOCKSOURCES_NUM] = 3;
+ cap->data[ASIC_DATA_MC_LATENCY] = 5000;
+ cap->data[ASIC_DATA_STUTTERMODE] = 0x2002;
+ cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 4;
+ cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 2;
+ cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM] = 3;
+ cap->data[ASIC_DATA_MIN_DISPCLK_FOR_UNDERSCAN] = 300000;
+
+ cap->data[ASIC_DATA_DCE_VERSION] = 0x100; /* DCE 11 */
+
+ cap->data[ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS] = 2;
+ cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 4;
+ cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ] = 40;
+ cap->data[ASIC_DATA_NUM_OF_VIDEO_PLANES] = 1;
+
+
+ /* ASIC basic capability */
+ cap->caps.IS_FUSION = true;
+ cap->caps.DP_MST_SUPPORTED = true;
+ cap->caps.PANEL_SELF_REFRESH_SUPPORTED = true;
+ cap->caps.MIRABILIS_SUPPORTED = true;
+ cap->caps.NO_VCC_OFF_HPD_POLLING = true;
+ cap->caps.VCE_SUPPORTED = true;
+ cap->caps.HPD_CHECK_FOR_EDID = true;
+ cap->caps.DFSBYPASS_DYNAMIC_SUPPORT = true;
+ cap->caps.SUPPORT_8BPP = false;
+
+ /* ASIC stereo 3d capability */
+ cap->stereo_3d_caps.DISPLAY_BASED_ON_WS = true;
+ cap->stereo_3d_caps.HDMI_FRAME_PACK = true;
+ cap->stereo_3d_caps.INTERLACE_FRAME_PACK = true;
+ cap->stereo_3d_caps.DISPLAYPORT_FRAME_PACK = true;
+ cap->stereo_3d_caps.DISPLAYPORT_FRAME_ALT = true;
+ cap->stereo_3d_caps.INTERLEAVE = true;
+
+ e_fuse_setting = dm_read_index_reg(cap->ctx, CGS_IND_REG__SMC, ixVCE_HARVEST_FUSE_MACRO__ADDRESS);
+
+ /* Bits [28:27]*/
+ switch ((e_fuse_setting >> 27) & 0x3) {
+ case 0:
+ /* both VCE engine are working*/
+ cap->caps.VCE_SUPPORTED = true;
+ cap->caps.WIRELESS_TIMING_ADJUSTMENT = false;
+ /*
+ * TODO:
+ * cap->caps.wirelessLowVCEPerformance = false;
+ * m_AsicCaps.vceInstance0Enabled = true;
+ * m_AsicCaps.vceInstance1Enabled = true;
+ */
+ cap->caps.NEED_MC_TUNING = true;
+ break;
+
+ case 1:
+ cap->caps.VCE_SUPPORTED = true;
+ cap->caps.WIRELESS_TIMING_ADJUSTMENT = true;
+ /*
+ * TODO:
+ * m_AsicCaps.wirelessLowVCEPerformance = false;
+ * m_AsicCaps.vceInstance1Enabled = true;
+ */
+ cap->caps.NEED_MC_TUNING = true;
+ break;
+
+ case 2:
+ cap->caps.VCE_SUPPORTED = true;
+ cap->caps.WIRELESS_TIMING_ADJUSTMENT = true;
+ /*
+ * TODO:
+ * m_AsicCaps.wirelessLowVCEPerformance = false;
+ * m_AsicCaps.vceInstance0Enabled = true;
+ */
+ cap->caps.NEED_MC_TUNING = true;
+ break;
+
+ case 3:
+ /*
+ * VCE_DISABLE = 0x3 - both VCE
+ * instances are in harvesting,
+ * no VCE supported any more.
+ */
+ cap->caps.VCE_SUPPORTED = false;
+ break;
+
+ default:
+ break;
+ }
+
+
+}
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.h b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.h
new file mode 100644
index 000000000000..29d9760e6c94
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef TONGA_ASIC_CAPABILITY_H_
+#define TONGA_ASIC_CAPABILITY_H_
+
+/* Forward declaration */
+struct asic_capability;
+
+/* Create and initialize Carrizo data */
+void tonga_asic_capability_create(struct asic_capability *cap,
+ struct hw_asic_id *init);
+
+#endif /* TONGA_ASIC_CAPABILITY_H_ */