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authorBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>2019-10-03 13:49:30 -0400
committerStanley.Yang <Stanley.Yang@amd.com>2019-10-18 15:49:15 +0800
commitc5259bba1ff263afc4c398d8c76882cdcd90f1a4 (patch)
treeecd48998ca14240f469510c227d3861e402ebc9a
parent45cbe9518c48899ea715a56232c0cddd31deea2b (diff)
drm/amd/display: change PP_SM defs to 8
DPM level is 8 these were incorrect before. Fix them Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com>
-rw-r--r--drivers/gpu/drm/amd/display/dc/dm_pp_smu.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
index 30984ba33164..3170eae53080 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
@@ -249,8 +249,8 @@ struct pp_smu_funcs_nv {
#define PP_SMU_NUM_SOCCLK_DPM_LEVELS 8
#define PP_SMU_NUM_DCFCLK_DPM_LEVELS 8
-#define PP_SMU_NUM_FCLK_DPM_LEVELS 4
-#define PP_SMU_NUM_MEMCLK_DPM_LEVELS 4
+#define PP_SMU_NUM_FCLK_DPM_LEVELS 8
+#define PP_SMU_NUM_MEMCLK_DPM_LEVELS 8
struct dpm_clock {
uint32_t Freq; // In MHz