summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorXiaojie Yuan <xiaojie.yuan@amd.com>2019-10-18 18:46:38 +0800
committerLong Gang <gang.long@amd.com>2019-10-21 10:48:55 +0800
commitb92d4ef3725e705b8b854c74d8934d09ceeeafda (patch)
treefc2fa83714714ae9a60f2d76e87fba1d368a1c0a
parent82e50a648c214dace457c402214d6a61c1549f78 (diff)
drm/amdgpu/psp11: wait for sOS ready for ring creation
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/psp_v11_0.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index e8e70b74ea5b..dfe85a1d79a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -459,6 +459,14 @@ static int psp_v11_0_ring_create(struct psp_context *psp,
0x80000000, 0x8000FFFF, false);
} else {
+ /* Wait for sOS ready for ring creation */
+ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+ 0x80000000, 0x80000000, false);
+ if (ret) {
+ DRM_ERROR("Failed to wait for sOS ready for ring creation\n");
+ return ret;
+ }
+
/* Write low address of the ring to C2PMSG_69 */
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);