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authorHersen Wu <hersenxs.wu@amd.com>2019-10-15 12:47:31 -0400
committerRui Teng <rui.teng@amd.com>2019-10-18 16:19:09 +0800
commit51f035a0dcb9f82dbd4922c43e2dd86c63730abf (patch)
treec1f6efae2cf5fb08209383963bddbc41ad03e702
parentddb75ca062ee46d047d79bf8e8da3c81a6373aa4 (diff)
drm/amdgpu/display: fix build error casused by CONFIG_DRM_AMD_DC_DCN2_1
when CONFIG_DRM_AMD_DC_DCN2_1 is not enable in .config, there is build error. struct dpm_clocks shoud not be guarded. Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
-rw-r--r--drivers/gpu/drm/amd/display/dc/dm_pp_smu.h3
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
index 65763e558673..30984ba33164 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
@@ -247,8 +247,6 @@ struct pp_smu_funcs_nv {
};
#endif
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
-
#define PP_SMU_NUM_SOCCLK_DPM_LEVELS 8
#define PP_SMU_NUM_DCFCLK_DPM_LEVELS 8
#define PP_SMU_NUM_FCLK_DPM_LEVELS 4
@@ -286,7 +284,6 @@ struct pp_smu_funcs_rn {
enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp,
struct dpm_clocks *clock_table);
};
-#endif
struct pp_smu_funcs {
struct pp_smu ctx;