diff options
| author | Likun Gao <Likun.Gao@amd.com> | 2020-04-17 17:33:35 +0800 |
|---|---|---|
| committer | Yang Xiong <Yang.Xiong@amd.com> | 2020-06-05 17:23:13 +0800 |
| commit | c544c6992d30a45a56df5f9490d703de837e7d9c (patch) | |
| tree | 74ac7d0953a678db685a8077e47251788142a348 | |
| parent | d5614006438df7ce6bd61d2f91fb5ff7382f05b9 (diff) | |
drm/amdgpu: only use one gfx pipe for Sienna_Cichlid
Only enable one gfx pipe for sienna_cichlid currently.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 87ea3e44a36c..b83c6d704e5d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -55,7 +55,7 @@ * 2. Async ring */ #define GFX10_NUM_GFX_RINGS_NV1X 1 -#define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2 +#define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 1 #define GFX10_MEC_HPD_SIZE 2048 #define F32_CE_PROGRAM_RAM_SIZE 65536 @@ -4232,7 +4232,7 @@ static int gfx_v10_0_sw_init(void *handle) break; case CHIP_SIENNA_CICHLID: adev->gfx.me.num_me = 1; - adev->gfx.me.num_pipe_per_me = 2; + adev->gfx.me.num_pipe_per_me = 1; adev->gfx.me.num_queue_per_pipe = 1; adev->gfx.mec.num_mec = 2; adev->gfx.mec.num_pipe_per_mec = 4; |