diff options
| author | Xiaojie Yuan <xiaojie.yuan@amd.com> | 2019-02-12 02:27:34 +0000 |
|---|---|---|
| committer | tiancyin <tianci.yin@amd.com> | 2019-08-08 18:46:56 +0800 |
| commit | 8692af93be7fba829d8056d30d80224b9b3b0869 (patch) | |
| tree | 02fc7d5576f59f2ff4313450706335b83e34d0d2 | |
| parent | b38b7ca5eaee59bb593fa1b70e8686a38178c279 (diff) | |
drm/amdgpu/psp: add psp support for navi14
Same as navi10.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Snow Zhang <Snow.Zhang@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 8 |
2 files changed, 7 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 79adc192cf29..0c88837bb890 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -57,6 +57,7 @@ static int psp_early_init(void *handle) psp->autoload_supported = false; break; case CHIP_NAVI10: + case CHIP_NAVI14: psp_v11_0_set_psp_funcs(psp); psp->autoload_supported = true; break; diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c index eea4ec358334..3cb13722dc9e 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c @@ -41,6 +41,7 @@ MODULE_FIRMWARE("amdgpu/vega20_asd.bin"); MODULE_FIRMWARE("amdgpu/vega20_ta.bin"); MODULE_FIRMWARE("amdgpu/navi10_sos.bin"); MODULE_FIRMWARE("amdgpu/navi10_asd.bin"); +MODULE_FIRMWARE("amdgpu/navi14_sos.bin"); /* address block */ #define smnMP1_FIRMWARE_FLAGS 0x3010024 @@ -70,6 +71,9 @@ static int psp_v11_0_init_microcode(struct psp_context *psp) case CHIP_NAVI10: chip_name = "navi10"; break; + case CHIP_NAVI14: + chip_name = "navi14"; + break; default: BUG(); } @@ -577,7 +581,7 @@ psp_v11_0_sram_map(struct amdgpu_device *adev, case AMDGPU_UCODE_ID_RLC_G: *sram_offset = 0x2000; - if (adev->asic_type != CHIP_NAVI10) { + if (adev->asic_type != CHIP_NAVI10 || adev->asic_type != CHIP_NAVI14) { *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); } @@ -589,7 +593,7 @@ psp_v11_0_sram_map(struct amdgpu_device *adev, case AMDGPU_UCODE_ID_SDMA0: *sram_offset = 0x0; - if (adev->asic_type != CHIP_NAVI10) { + if (adev->asic_type != CHIP_NAVI10 || adev->asic_type != CHIP_NAVI14) { *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); } |