summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorKenneth Feng <kenneth.feng@amd.com>2019-10-16 16:20:38 +0800
committerKenneth Feng <kenneth.feng@amd.com>2019-10-16 18:27:07 +0800
commit65a1214784d24b65b863b0a618a6718dd1de21fd (patch)
tree4a3c07a90e2201e74747b5989080b289397ce82b
parent3dee81816abe33f5d740affe08250662702a1a27 (diff)
drm/amd/powerplay: bug fix for memory clock request from display
In some cases, display fixes memory clock frequency to a high value rather than the natural memory clock switching. When we comes back from s3 resume, the request from display is not reset, this causes the bug which makes the memory clock goes into a low value. Then due to the insuffcient memory clock, the screen flicks. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
-rw-r--r--drivers/gpu/drm/amd/powerplay/amdgpu_smu.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 6e785858cf70..72328dd8c989 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1138,6 +1138,8 @@ static int smu_resume(void *handle)
if (ret)
goto failed;
+ smu->disable_uclk_switch = 0;
+
mutex_unlock(&smu->mutex);
pr_info("SMU is resumed successfully!\n");