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authorKevin Wang <kevin1.wang@amd.com>2019-08-21 10:58:19 +0800
committerKevin Wang <kevin1.wang@amd.com>2019-09-23 12:58:49 +0800
commit1a401d670dba28b500683327dbbf81594983daa3 (patch)
treecc7efc60ec498fd1df2391bbcb1e37344d5a543b
parent50f8c9b1c28a6f8d69fc2f5cb77a292d40f86aab (diff)
drm/amd/powerpaly: fix navi series custom peak level value error
fix other navi asic set peak performance level error. because the navi10_ppt.c will handle navi12 14 asic, it will use navi10 peak value to set other asic, it is not correct. after patch: only navi10 use custom peak value, other asic will used default value. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/powerplay/navi10_ppt.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index e5ef8d00f581..b26156907add 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1549,6 +1549,10 @@ static int navi10_set_peak_clock_by_device(struct smu_context *smu)
static int navi10_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
{
int ret = 0;
+ struct amdgpu_device *adev = smu->adev;
+
+ if (adev->asic_type != CHIP_NAVI10)
+ return -EINVAL;
switch (level) {
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: