diff options
| author | Roman Li <Roman.Li@amd.com> | 2018-11-27 17:16:37 -0500 |
|---|---|---|
| committer | Evan Quan <evan.quan@amd.com> | 2018-12-03 17:07:30 +0800 |
| commit | bcf671e54d9e3b3231ceda884fe00c1870714a62 (patch) | |
| tree | 1fec3bed4e859272e3ff05d76552d448eeb93f7c | |
| parent | 1cdec2a6685f9854ba3e28a8cdb75d50b4710af0 (diff) | |
drm/amd/display: Fix 6x4K displays light-up on Vega20
[Why]
More than 4x4K didn't lightup on Vega20 due to low dcfclk value.
Powerplay expects valid min requirement for dcfclk from DC.
[How]
Update min_dcfclock_khz based on min_engine_clock value.
Change-Id: I123f5f98cb02fc8cb5e3c9ea619efc8aa5aa4463
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Roman Li <Roman.Li@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c index f1e71a862eab..493e2f4933aa 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c @@ -585,6 +585,8 @@ static void dce11_pplib_apply_display_requirements( dc, context->bw.dce.sclk_khz); + pp_display_cfg->min_dcfclock_khz = pp_display_cfg->min_engine_clock_khz; + pp_display_cfg->min_engine_clock_deep_sleep_khz = context->bw.dce.sclk_deep_sleep_khz; |