diff options
| author | Eric Yang <eric.yang2@amd.com> | 2015-10-28 17:24:07 -0400 |
|---|---|---|
| committer | Samuel Li <Samuel.Li@amd.com> | 2015-11-25 15:19:40 -0500 |
| commit | bd4455ebef46ac90959f876d4efdab45052cde54 (patch) | |
| tree | ccb7eb1b81512a3c17c053870ac70e0f6d50e05f | |
| parent | aab76a32bbb6568c77f80ee0fceb305a4be64773 (diff) | |
amd/dal: Add stoney capabilities in DAL
Signed-off-by: Eric Yang <eric.yang2@amd.com>
Review-by: Eagle Yeh <eagle.yeh@amd.com>
4 files changed, 21 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/dal/asic_capability/asic_capability.c b/drivers/gpu/drm/amd/dal/asic_capability/asic_capability.c index ecee5aa62afe..8cf6f11c29a1 100644 --- a/drivers/gpu/drm/amd/dal/asic_capability/asic_capability.c +++ b/drivers/gpu/drm/amd/dal/asic_capability/asic_capability.c @@ -89,7 +89,7 @@ static bool construct( case FAMILY_CZ: #if defined(CONFIG_DRM_AMD_DAL_DCE11_0) - carrizo_asic_capability_create(cap); + carrizo_asic_capability_create(cap, init); asic_supported = true; #endif break; diff --git a/drivers/gpu/drm/amd/dal/asic_capability/carrizo_asic_capability.c b/drivers/gpu/drm/amd/dal/asic_capability/carrizo_asic_capability.c index 1a96b9e0469e..ea371c93bcae 100644 --- a/drivers/gpu/drm/amd/dal/asic_capability/carrizo_asic_capability.c +++ b/drivers/gpu/drm/amd/dal/asic_capability/carrizo_asic_capability.c @@ -33,13 +33,15 @@ #include "dce/dce_11_0_d.h" #include "smu/smu_8_0_d.h" #include "dce/dce_11_0_sh_mask.h" +#include "dal_asic_id.h" /* * carrizo_asic_capability_create * * Create and initiate Carrizo capability. */ -void carrizo_asic_capability_create(struct asic_capability *cap) +void carrizo_asic_capability_create(struct asic_capability *cap, + struct hw_asic_id *init) { uint32_t e_fuse_setting; /* ASIC data */ @@ -125,4 +127,15 @@ void carrizo_asic_capability_create(struct asic_capability *cap) break; } + if (ASIC_REV_IS_STONEY(init->chip_id)) + { + // Stoney is the same DCE11, but only two pipes, three digs. and HW added 64bit back for non SG. + cap->data[ASIC_DATA_CONTROLLERS_NUM] = 2; + cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM] = 2; + cap->data[ASIC_DATA_LINEBUFFER_NUM] = 2; + + cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 2; //3 DP MST per connector, limited by number of pipe and number of Dig. + + } + } diff --git a/drivers/gpu/drm/amd/dal/asic_capability/carrizo_asic_capability.h b/drivers/gpu/drm/amd/dal/asic_capability/carrizo_asic_capability.h index 59d237f7040c..0bb81dbf4d1b 100644 --- a/drivers/gpu/drm/amd/dal/asic_capability/carrizo_asic_capability.h +++ b/drivers/gpu/drm/amd/dal/asic_capability/carrizo_asic_capability.h @@ -30,6 +30,7 @@ struct asic_capability; /* Create and initialize Carrizo data */ -void carrizo_asic_capability_create(struct asic_capability *cap); +void carrizo_asic_capability_create(struct asic_capability *cap, + struct hw_asic_id *init); #endif /* __DAL_CARRIZO_ASIC_CAPABILITY_H__ */ diff --git a/drivers/gpu/drm/amd/dal/include/dal_asic_id.h b/drivers/gpu/drm/amd/dal/include/dal_asic_id.h index da33f4dea666..c8dec0cedc67 100644 --- a/drivers/gpu/drm/amd/dal/include/dal_asic_id.h +++ b/drivers/gpu/drm/amd/dal/include/dal_asic_id.h @@ -77,8 +77,12 @@ /* DCE11 */ #define CZ_CARRIZO_A0 0x01 +#define STONEY_A0 0x61 #define CZ_UNKNOWN 0xFF +#define ASIC_REV_IS_STONEY(rev) \ + ((rev >= STONEY_A0) && (rev < CZ_UNKNOWN)) + /* * ASIC chip ID |