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2017-09-01Hybrid Version: 17.50.0.12amd-17.40-baseline1Junshan Fang1-2/+2
Change-Id: I068fbebf59b5046a0b52f86a7a6c1788edf4e650 Signed-off-by: Junshan Fang <Junshan.Fang@amd.com>
2017-08-21Merge branch 'amd-staging-hybrid-master20170517' into ↵amd-mainline-hybrid-master20170517Xiaojie Yuan6-213/+394
amd-mainline-hybrid-master20170517
2017-08-17Hybrid Version: 17.40.3.12Le.Ma1-1/+2
Change-Id: Ida81ed0a3dd4e084b359875fc81db66da89a08e0 Signed-off-by: Le.Ma <Le.Ma@amd.com> Reviewed-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com>
2017-08-15tests/amdgpu: update uvd enc test for new fwBoyuan Zhang2-158/+358
uvd hevc enc test failed due to firmware interface changes. re-write the test based on the new firmware interface. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher at amd.com>
2017-08-10amdgpu: merge and cleanup amdgpu_bo_freeMonk Liu2-56/+29
since bo_reference and bo_internal_free are all only used by bo_free, so we just merge them together Change-Id: I01355e7d450b075458b946717d5bddfa0a0c2d3c Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-10amdgpu: [HYBRID] change to use amdgpu_bo_freeQiang Yu2-3/+3
amdgpu_bo_reference is dropped in upstream, some hybrid spec code still use it. So change it to amdgpu_bo_free. This patch should be splited and merged to the coresponding hybrid patches which introduce the usage of amdgpu_bo_reference when next rebase. Change-Id: I79ca028270adfc8427cf3d3e6e18002c6c7590b4 Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
2017-08-10Revert "amdgpu:fix potential deadlock"Qiang Yu1-1/+1
This reverts commit eaea24b7acfb8d2cb1db8baa8f353d9fcc69a2b6. The reverted commit is submitted by mistaken. Signed-off-by: Qiang Yu <Qiang.Yu@amd.com>
2017-08-10amdgpu:fix potential deadlockMonk Liu1-1/+1
deadlock could occure between cpu mutex lock and bo table mutex lock, this patch avoid it. Change-Id: I083e402dde48f02a8ee196e59aa0cab80849fc18 Signed-off-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Qiang Yu <Qiang.Yu@amd.com>
2017-08-10drm:fix race issue between two bo functions(v2)Monk Liu2-6/+12
there is race issue between two threads on amdgpu_bo_reference and amdgpu_bo_import, this patch tends to fix it by moving the pthread_mutex_lock out of bo_free_internal and move to bo_reference to cover the update_reference part. The mutex_unlock in bo_import should also cover bo refcount increasement. Change-Id: I1f65eacf74cd28cc0d3a71ef2f7a19b890d63c29 Signed-off-by: Monk Liu <monk.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Qiang Yu <Qiang.Yu@amd.com>
2017-08-10drm: fix missing mutex unlock before returnMonk Liu1-0/+1
Change-Id: I377dde976648d53bc9a3a2d5ba294c284910b109 Signed-off-by: Monk Liu <monk.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Qiang Yu <Qiang.Yu@amd.com>
2017-08-08Merge branch 'amd-staging-hybrid-master20170517' into ↵Xiaojie Yuan22-155/+784
amd-mainline-hybrid-master20170517
2017-08-08Hybrid Version: 17.40.2Le.Ma1-1/+1
Change-Id: I1d223ce1c0b61d9dc11f3a2cbbbadb6d89f64909 Signed-off-by: Le.Ma <Le.Ma@amd.com> Reviewed-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com>
2017-08-01Hybrid Version: 17.40.1Junshan Fang1-1/+1
Change-Id: Ia2c16a3f2e33913f92090168baf5b9648a70a987 Signed-off-by: Junshan Fang <Junshan.Fang@amd.com>
2017-07-31configure.ac: bump version for releaseLucas Stach1-1/+1
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2017-07-31amdgpu: add new symbols to tests.Dave Airlie1-0/+7
2017-07-31drm/amdgpu: add new low overhead command submission API. (v2)Dave Airlie2-0/+77
This just sends chunks to the kernel API for a single command stream. This should provide a more future proof and extensible API for command submission. v2: use amdgpu_bo_list_handle, add two helper functions to access bo and context internals. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-07-31drm/amdgpu: add syncobj create/destroy/import/export apisDave Airlie2-1/+92
These are just wrappers using the amdgpu device handle. Acked-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-07-31Remove redundant memclearcoypu1-2/+0
drmMalloc will zero out the memory for us Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-07-31etnaviv: submit full struct drm_etnaviv_gem_submitChristian Gmeiner1-7/+1
It is safe to submit the full struct even on older kernels as such kernels do not process the full struct. Without this change it becomes quite challenging to extned the submit struct. Freedreno has no special treatment too. See git commits - freedreno: sync uapi header - freedreno: add fence fd support Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-07-31intel/intel_chipset: Move IS_9XX below IS_GEN10.Rodrigo Vivi1-9/+9
No functional change. Just organizing the code so it gets clear for future platforms. Paulo deserves credits becuase he was the one that just noticed this IS_9XX was in the wrong position after CNL patches got introduced. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-07-31intel: add GEN10 to IS_9XX.Paulo Zanoni1-1/+2
As far as I understand, IS_9XX should return true for it. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-07-31intel/gen10: Add missed gen10 stuffBen Widawsky2-1/+5
This got lost on rebase, I believe Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-07-31intel: Add Cannonlake PCI IDs for Y-skus.Rodrigo Vivi1-1/+15
By the Spec all CNL Y skus are 2+2, i.e. GT2. This is a copy of merged i915's commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.") v2: Add kernel commit id for reference. Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Clinton Taylor <clinton.a.taylor@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
2017-07-31intel: Add Cannonlake PCI IDs for U-skus.Rodrigo Vivi1-0/+13
Platform enabling and its power-on are organized in different skus (U x Y x S x H, etc). So instead of organizing it in GT1 x GT2 x GT3 let's also use the platform sku. This is a copy of merged i915's commit e918d79a5d0a ("drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.") v2: Remove PCI IDs for SKU not mentioned in spec. v3: Add kernel commit id for reference. Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Clinton Taylor <clinton.a.taylor@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
2017-07-31intel: PCI Ids for U SKU in CFLAnusha Srivatsa1-1/+11
Add the PCI IDs for U SKU IN CFL by following the spec. v2: Update IDs Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-07-31intel: PCI Ids for H SKU in CFLAnusha Srivatsa1-1/+7
Add the PCI IDs for H SKU IN CFL by following the spec. v2: Update IDs Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-07-31intel: PCI Ids for S SKU in CFLAnusha Srivatsa1-1/+16
Add the PCI IDs for S SKU IN CFL by following the spec. v2: Update IDs. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-07-31libdrm: add drm syncobj create/destroy/import/exportDave Airlie2-0/+89
These ioctls are now in drm next so add the first set of libdrm APIs. Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-07-31drm: update drm.h to latest in drm-next.Dave Airlie1-0/+26
This syncs the drm.h header with my drm-next branch as of 6d61e70ccc21606ffb8a0a03bd3aba24f659502b. It brings over the semaphore API changes. Generated using make headers_install. Generated from git://people.freedesktop.org/~airlied/linux drm-next commit 6d61e70ccc2. [airlied: I split patch in two, split reviewed by across both] Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-07-31headers: Update drm_fourcc and vc4_drm.h with new VC4 tiling UAPI.Eric Anholt2-4/+41
Taken from make headers_install of drm-misc-next (34c8ea400ff6383b028f63df2453914163afc07c) Reviewed-by: Daniel Stone <daniels@collabora.com>
2017-07-31amdgpu: Add .editorconfig file for amdgpu coding styleMichel Dänzer1-0/+9
The .editorconfig file in the toplevel directory doesn't match. Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2017-07-31tests/amdgpu: s/uvd_messages.h/decode_messages.h/ in Makefile.amMichel Dänzer1-1/+1
Fixes make distcheck with amdgpu enabled. Fixes: ec65d1980912 ("tests/amdgpu: rename uvd messages to decode messages") Trivial.
2017-07-31tests/amdgpu: Fix device_id optionTom St Denis1-9/+9
The device_id option [-d] was badly broken. This commit fixes the width (was 8 is now 16 bits) as well as enables searches without specifying a bus id. It was also comparing "dev" from the bus field which is not the PCI device id. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
2017-07-31headers: sync drm_sarea.h with airlied/drm-nextEric Engestrom1-0/+8
Adds the C++ extern guards from ebbb0e5cfd2ceb1150b1 drm: add extern C guard for the UAPI headers Generated using `make headers_install` from airlied/drm-next at commit 2a1720376adda5ecf8e636fbfb05339c7dad1c55 Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-07-31headers: sync drm_fourcc.h with airlied/drm-nextEric Engestrom1-0/+126
This adds a bunch of modifiers stuff, as well as a few new formats. Includes the following changes: ebbb0e5cfd2ceb1150b1 drm: add extern C guard for the UAPI headers b9fb2a21ac8058965a6b drm_fourcc: Document linear modifier af913418261d6d3e7a29 drm_fourcc: Fix DRM_FORMAT_MOD_LINEAR #define fd056f05b9fcba35b77e drm: add fourcc codes for 16bit R and RG 73f1a5858bf82f3bf232 drm/fourcc: add vivante tiled layout format modifiers ba2b5277dc52cc96944d drm: add RGB formats with separate alpha plane 5e91144dd702d068b22a drm/tegra: Add tiling FB modifiers Generated using `make headers_install` from airlied/drm-next at commit 2a1720376adda5ecf8e636fbfb05339c7dad1c55 Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-07-31Android: fix missing trailing \Rob Herring1-1/+1
In commit bbe998791d6c ("Android's major/minor/makedev live in <sys/sysmacros.h>"), it didn't apply cleanly and I missed the trailing \, so add it here. Signed-off-by: Rob Herring <robh@kernel.org>
2017-07-31Android's major/minor/makedev live in <sys/sysmacros.h>Elliott Hughes1-0/+1
Bug: https://github.com/android-ndk/ndk/issues/398 Signed-off-by: Rob Herring <robh@kernel.org>
2017-07-19test/amdgpu: fix test failure for SIFlora Cui3-126/+229
Change-Id: I646f1bf844bd92962b9f71aa287f90173ae233c6 Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2017-07-14Merge branch 'amd-staging-hybrid-master20170517' into ↵Xiaojie Yuan2-0/+110
amd-mainline-hybrid-master20170517
2017-07-07Hybrid Version: 17.40.0Junshan Fang1-0/+3
Change-Id: If2cd9b82d1979e4a22984195ce9910653a5dbb4c Signed-off-by: Junshan Fang <Junshan.Fang@amd.com>
2017-07-06Hybrid Version: 17.40.0Junshan Fang1-0/+3
Change-Id: Ie7ee85715e2e0e3df8e30727c3a03a93fcce772e Signed-off-by: Junshan Fang <Junshan.Fang@amd.com>
2017-06-29amdgpu: Add gpu always on cu bitmapFlora Cui1-0/+3
Change-Id: I8353678c3f74e71af4928dc863b41c92d4dff2ab Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2017-06-07tests/amdgpu: [HYBRID] add SSG unit testQiang Yu1-0/+107
Change-Id: I75c5a189a5046b0f56808a60da2f3b34f45e5dab Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
2017-06-06Bump version to 2.4.81Marek Olšák1-1/+1
Change-Id: I3cad7dd4bea1f16f6dd57514e1e5265340a51d19
2017-06-06tests/amdgpu: bypass VCE tests on ravenHawking Zhang1-0/+17
raven doesn't support VCE Change-Id: I5f511cd0ca4bcd8114eba16bc35892385453f98b Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com>
2017-06-06tests/amdgpu: bypass UVD ENC tests on ravenHawking Zhang1-8/+6
raven doesn't support UVD encode Change-Id: Ib880f767ead72b8c7f392c20c01b756600c5eee7 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com>
2017-06-06tests/amdgpu: bypass UVD CS tests on ravenHawking Zhang1-0/+17
raven doesn't support UVD decode Change-Id: Ibc3a3a1b1007aaf7cf8de8b6ccd2457167f11fcb Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com>
2017-06-06Bump version to 2.4.81Marek Olšák1-1/+1
Change-Id: I3cad7dd4bea1f16f6dd57514e1e5265340a51d19
2017-05-27tests/amdgpu: bypass VCE tests on ravenHawking Zhang1-0/+17
raven doesn't support VCE Change-Id: I5f511cd0ca4bcd8114eba16bc35892385453f98b Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com>
2017-05-27tests/amdgpu: bypass UVD ENC tests on ravenHawking Zhang1-8/+6
raven doesn't support UVD encode Change-Id: Ib880f767ead72b8c7f392c20c01b756600c5eee7 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com>