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authorJunwei Zhang <Jerry.Zhang@amd.com>2017-04-25 14:06:24 +0800
committerQiang Yu <Qiang.Yu@amd.com>2017-05-17 11:19:54 +0800
commitf4e28ff9bd21904ca0b5bc49923068f793f99203 (patch)
tree2b98e89b6535ef7caeb8ed16b387bbebba7a59f5
parent33f7fba1b3bc32bb65b00befb59827c5b93af6cd (diff)
amdgpu: export more gpu info for gfx9 (v2)
v2: 64-bit aligned Change-Id: If477c7f7499f8ac6766d0b7c29221616e93ff0e2 Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Qiang Yu <Qiang.Yu@amd.com>
-rw-r--r--include/drm/amdgpu_drm.h19
1 files changed, 19 insertions, 0 deletions
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 022e0037..faff3f1d 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -843,6 +843,25 @@ struct drm_amdgpu_info_device {
__u64 cntl_sb_buf_gpu_addr;
/* NGG Parameter Cache */
__u64 param_buf_gpu_addr;
+ __u32 prim_buf_size;
+ __u32 pos_buf_size;
+ __u32 cntl_sb_buf_size;
+ __u32 param_buf_size;
+ /* wavefront size*/
+ __u32 wave_front_size;
+ /* shader visible vgprs*/
+ __u32 num_shader_visible_vgprs;
+ /* CU per shader array*/
+ __u32 num_cu_per_sh;
+ /* number of tcc blocks*/
+ __u32 num_tcc_blocks;
+ /* gs vgt table depth*/
+ __u32 gs_vgt_table_depth;
+ /* gs primitive buffer depth*/
+ __u32 gs_prim_buffer_depth;
+ /* max gs wavefront per vgt*/
+ __u32 max_gs_waves_per_vgt;
+ __u32 _pad1;
};
struct drm_amdgpu_info_hw_ip {