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authorDavid Mao <david.mao@amd.com>2017-01-23 11:31:58 +0800
committerQiang Yu <Qiang.Yu@amd.com>2017-05-17 11:15:03 +0800
commitb9a7c402812a21be74ab76b19e38ee81d69c2d4c (patch)
tree32c3d0cfa2272172799e8d2dab767fc77cc9800f
parent4b1a756125a0cc53a084656a643d36547ead0c02 (diff)
test case for export/import sem
Test covers basic functionality includes create/destroy/import/export/wait/signal Change-Id: I8a8d767e5ef1889f8ac214fef98befba83969d8d Signed-off-by: David Mao <david.mao@amd.com> Signed-off-by: Flora Cui <Flora.Cui@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
-rw-r--r--tests/amdgpu/basic_tests.c60
1 files changed, 60 insertions, 0 deletions
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index 41a702db..18075383 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -504,6 +504,8 @@ static void amdgpu_semaphore_test(void)
uint32_t expired;
amdgpu_bo_list_handle bo_list[2];
amdgpu_va_handle va_handle[2];
+ amdgpu_sem_handle sem_handle, sem_handle_import;
+ int fd;
int r, i;
r = amdgpu_cs_create_semaphore(&sem);
@@ -604,6 +606,64 @@ static void amdgpu_semaphore_test(void)
500000000, 0, &expired);
CU_ASSERT_EQUAL(r, 0);
CU_ASSERT_EQUAL(expired, true);
+
+ /* 3. export/import sem test */
+ r = amdgpu_cs_create_sem(device_handle, &sem_handle);
+ CU_ASSERT_EQUAL(r, 0);
+
+ ptr = ib_result_cpu[0];
+ ptr[0] = SDMA_NOP;
+ ib_info[0].ib_mc_address = ib_result_mc_address[0];
+ ib_info[0].size = 1;
+
+ ibs_request[0].ip_type = AMDGPU_HW_IP_DMA;
+ ibs_request[0].number_of_ibs = 1;
+ ibs_request[0].ibs = &ib_info[0];
+ ibs_request[0].resources = bo_list[0];
+ ibs_request[0].fence_info.handle = NULL;
+ r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request[0], 1);
+ CU_ASSERT_EQUAL(r, 0);
+ r = amdgpu_cs_signal_sem(device_handle, context_handle[0], AMDGPU_HW_IP_DMA, 0, 0, sem_handle);
+ CU_ASSERT_EQUAL(r, 0);
+
+ // export the semaphore and import in different context to wait.
+ r = amdgpu_cs_export_sem(device_handle, sem_handle, &fd);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_cs_import_sem(device_handle, fd, &sem_handle_import);
+ CU_ASSERT_EQUAL(r, 0);
+ close(fd);
+ r = amdgpu_cs_destroy_sem(device_handle, sem_handle);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_cs_wait_sem(device_handle, context_handle[1], AMDGPU_HW_IP_GFX, 0, 0, sem_handle_import);
+ CU_ASSERT_EQUAL(r, 0);
+ ptr = ib_result_cpu[1];
+ ptr[0] = GFX_COMPUTE_NOP;
+ ib_info[1].ib_mc_address = ib_result_mc_address[1];
+ ib_info[1].size = 1;
+
+ ibs_request[1].ip_type = AMDGPU_HW_IP_GFX;
+ ibs_request[1].number_of_ibs = 1;
+ ibs_request[1].ibs = &ib_info[1];
+ ibs_request[1].resources = bo_list[1];
+ ibs_request[1].fence_info.handle = NULL;
+
+ r = amdgpu_cs_submit(context_handle[1], 0,&ibs_request[1], 1);
+ CU_ASSERT_EQUAL(r, 0);
+
+ fence_status.context = context_handle[1];
+ fence_status.ip_type = AMDGPU_HW_IP_GFX;
+ fence_status.ip_instance = 0;
+ fence_status.fence = ibs_request[1].seq_no;
+ r = amdgpu_cs_query_fence_status(&fence_status,
+ 500000000, 0, &expired);
+ CU_ASSERT_EQUAL(r, 0);
+ CU_ASSERT_EQUAL(expired, true);
+
+ r = amdgpu_cs_destroy_sem(device_handle, sem_handle_import);
+ CU_ASSERT_EQUAL(r, 0);
+
for (i = 0; i < 2; i++) {
r = amdgpu_bo_unmap_and_free(ib_result_handle[i], va_handle[i],
ib_result_mc_address[i], 4096);