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authorChunming Zhou <David1.Zhou@amd.com>2015-11-26 17:01:07 +0800
committerQiang Yu <Qiang.Yu@amd.com>2017-05-17 10:24:19 +0800
commit8ff2c9c5df265745518a43ffc46850ba7afe5b09 (patch)
tree08c9ec3c4fcdb9be2ad5de165f02b8e437cc0cbe
parent87be19955d9f536e59a3afe62641ae3143fb6622 (diff)
amdgpu: add amdgpu_find_bo_by_cpu_mapping interface
userspace needs to know if the user memory is from BO or malloc. Change-Id: I7fdb494c31f6d9f96b4d7238bf0998d0fe701608 Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Christian K├Ânig <christian.koenig@amd.com>
-rw-r--r--amdgpu/amdgpu.h24
-rw-r--r--amdgpu/amdgpu_bo.c37
-rw-r--r--include/drm/amdgpu_drm.h14
3 files changed, 75 insertions, 0 deletions
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 4d89c963..b125d06e 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -677,6 +677,30 @@ int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
amdgpu_bo_handle *buf_handle);
/**
+ * Validate if the user memory comes from BO
+ *
+ * \param dev - [in] Device handle. See #amdgpu_device_initialize()
+ * \param cpu - [in] CPU address of user allocated memory which we
+ * want to map to GPU address space (make GPU accessible)
+ * (This address must be correctly aligned).
+ * \param size - [in] Size of allocation (must be correctly aligned)
+ * \param buf_handle - [out] Buffer handle for the userptr memory
+ * if the user memory is not from BO, the buf_handle will be NULL.
+ * \param offset_in_bo - [out] offset in this BO for this user memory
+ *
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+*/
+int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev,
+ void *cpu,
+ uint64_t size,
+ amdgpu_bo_handle *buf_handle,
+ uint64_t *offset_in_bo);
+
+
+/**
* Free previosuly allocated memory
*
* \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index 5ac456be..9a110a00 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -529,6 +529,43 @@ int amdgpu_bo_wait_for_idle(amdgpu_bo_handle bo,
}
}
+int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev,
+ void *cpu,
+ uint64_t size,
+ amdgpu_bo_handle *buf_handle,
+ uint64_t *offset_in_bo)
+{
+ int r;
+ struct amdgpu_bo *bo;
+ struct drm_amdgpu_gem_find_bo args;
+
+ args.addr = (uintptr_t)cpu;
+ args.size = size;
+ r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_FIND_BO,
+ &args, sizeof(args));
+ if (r)
+ return r;
+ if (args.handle == 0)
+ return -EINVAL;
+ bo = util_hash_table_get(dev->bo_handles,
+ (void*)(uintptr_t)args.handle);
+ if (!bo) {
+ bo = calloc(1, sizeof(struct amdgpu_bo));
+ if (!bo)
+ return -ENOMEM;
+ atomic_set(&bo->refcount, 1);
+ bo->dev = dev;
+ bo->alloc_size = size;
+ bo->handle = args.handle;
+ } else
+ atomic_inc(&bo->refcount);
+
+ *buf_handle = bo;
+ *offset_in_bo = args.offset;
+ return r;
+}
+
+
int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
void *cpu,
uint64_t size,
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 035799c5..de2b0689 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -51,6 +51,8 @@ extern "C" {
#define DRM_AMDGPU_GEM_OP 0x10
#define DRM_AMDGPU_GEM_USERPTR 0x11
#define DRM_AMDGPU_WAIT_FENCES 0x12
+/* hybrid specific ioctls */
+#define DRM_AMDGPU_GEM_FIND_BO 0x5f
#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -65,6 +67,8 @@ extern "C" {
#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
+/* hybrid specific ioctls */
+#define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo)
#define AMDGPU_GEM_DOMAIN_CPU 0x1
#define AMDGPU_GEM_DOMAIN_GTT 0x2
@@ -215,6 +219,16 @@ struct drm_amdgpu_gem_userptr {
__u32 handle;
};
+struct drm_amdgpu_gem_find_bo {
+ uint64_t addr;
+ uint64_t size;
+ uint32_t flags;
+ /* Resulting GEM handle */
+ uint32_t handle;
+ /* offset in bo */
+ uint64_t offset;
+};
+
/* SI-CI-VI: */
/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0