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authorQiang Yu <Qiang.Yu@amd.com>2017-03-07 15:00:34 +0800
committerQiang Yu <Qiang.Yu@amd.com>2017-05-17 11:19:54 +0800
commit6fc42e3c901f6b126fff88a96b8e9f4209e24105 (patch)
tree189bceb678bb442d2fab8dd4e587a8472e9d362c
parent56c7f158475f6e4e594e3974c1f4cee714948126 (diff)
amdgpu:support 16 ibs per submit for PAL/SRIOV
to support SRIOV and MCBP, need 16 IBs per submit Change-Id: I1da908821e808c368a0c114a57445da682beb6f9 Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
-rw-r--r--amdgpu/amdgpu.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index eab20c65..048c2462 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -54,7 +54,7 @@ struct drm_amdgpu_capability;
*
* \sa amdgpu_cs_ib_info
*/
-#define AMDGPU_CS_MAX_IBS_PER_SUBMIT 4
+#define AMDGPU_CS_MAX_IBS_PER_SUBMIT 16
/**
* Special timeout value meaning that the timeout is infinite.