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authorChunming Zhou <David1.Zhou@amd.com>2017-04-28 10:37:41 +0800
committerQiang Yu <Qiang.Yu@amd.com>2017-05-17 11:19:54 +0800
commit6dd09c9911b8242d1e2b9bf9e1a5f31d90a4122e (patch)
tree2a82bf3e20c228cb0f42983e18786fdfcfd051c2
parentf4e28ff9bd21904ca0b5bc49923068f793f99203 (diff)
amdgpu: add vm ioctl support for reserved vmid
Change-Id: I3c1ea377dad8f6d64a992b071a6ec36a1143e416 Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
-rw-r--r--include/drm/amdgpu_drm.h22
1 files changed, 22 insertions, 0 deletions
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index faff3f1d..cccb91d7 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -51,6 +51,7 @@ extern "C" {
#define DRM_AMDGPU_GEM_OP 0x10
#define DRM_AMDGPU_GEM_USERPTR 0x11
#define DRM_AMDGPU_WAIT_FENCES 0x12
+#define DRM_AMDGPU_VM 0x13
/* hybrid specific ioctls */
#define DRM_AMDGPU_SEM 0x5b
@@ -71,6 +72,7 @@ extern "C" {
#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
+#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
/* hybrid specific ioctls */
#define DRM_IOCTL_AMDGPU_GEM_DGMA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_DGMA, struct drm_amdgpu_gem_dgma)
@@ -211,6 +213,26 @@ union drm_amdgpu_ctx {
union drm_amdgpu_ctx_out out;
};
+/* vm ioctl */
+#define AMDGPU_VM_OP_RESERVE_VMID 1
+#define AMDGPU_VM_OP_UNRESERVE_VMID 2
+
+struct drm_amdgpu_vm_in {
+ /** AMDGPU_VM_OP_* */
+ __u32 op;
+ __u32 flags;
+};
+
+struct drm_amdgpu_vm_out {
+ /** For future use, no flags defined so far */
+ __u64 flags;
+};
+
+union drm_amdgpu_vm {
+ struct drm_amdgpu_vm_in in;
+ struct drm_amdgpu_vm_out out;
+};
+
/* sync file related */
#define AMDGPU_SEM_OP_CREATE_SEM 1
#define AMDGPU_SEM_OP_WAIT_SEM 2