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authorChunming Zhou <David1.Zhou@amd.com>2016-09-22 14:50:16 +0800
committerQiang Yu <Qiang.Yu@amd.com>2017-05-17 11:15:03 +0800
commit4735df3e90422ad11316128b729c23850710e42d (patch)
treed05a6197581ee959b23f29926c40e19b046446d9
parent6107b89f0fdb216f9db28ee279311581d41c3c4f (diff)
amdgpu: add new semaphore support v2
v2: 612336476adaffdd715fcc74c5aabceee8d53add [Flora Cui] refine semaphore implementation to keep align with kmd 65f50d04e5083f9ed6f641a83b2b6d9190fc4cae [Monk Liu] fix SEM paramter issue for SEM ioctl, seq 0 means nothing to signal/wait and ~0ull means use the latest fence number to signal/wait Change-Id: I40ef6126efda61a4dcfff59531cd2a7b85ae8f01 Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Flora Cui <Flora.Cui@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
-rw-r--r--amdgpu/amdgpu.h74
-rw-r--r--amdgpu/amdgpu_cs.c91
-rw-r--r--include/drm/amdgpu_drm.h29
3 files changed, 194 insertions, 0 deletions
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 6ed67da2..6b8b3774 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -141,6 +141,12 @@ typedef struct amdgpu_va *amdgpu_va_handle;
*/
typedef struct amdgpu_semaphore *amdgpu_semaphore_handle;
+/**
+ * Define handle for sem file
+ */
+typedef uint32_t amdgpu_sem_handle;
+
+
/*--------------------------------------------------------------------------*/
/* -------------------------- Structures ---------------------------------- */
/*--------------------------------------------------------------------------*/
@@ -1578,6 +1584,74 @@ int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx,
int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem);
/**
+ * create sem
+ *
+ * \param dev - [in] Device handle. See #amdgpu_device_initialize()
+ * \param sem - \c [out] sem handle
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+*/
+int amdgpu_cs_create_sem(amdgpu_device_handle dev,
+ amdgpu_sem_handle *sem);
+
+/**
+ * signal sem
+ *
+ * \param dev - [in] Device handle. See #amdgpu_device_initialize()
+ * \param context - \c [in] GPU Context
+ * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_*
+ * \param ip_instance - \c [in] Index of the IP block of the same type
+ * \param ring - \c [in] Specify ring index of the IP
+ * \param sem - \c [out] sem handle
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+ */
+int amdgpu_cs_signal_sem(amdgpu_device_handle dev,
+ amdgpu_context_handle ctx,
+ uint32_t ip_type,
+ uint32_t ip_instance,
+ uint32_t ring,
+ amdgpu_sem_handle sem);
+
+/**
+ * wait sem
+ *
+ * \param dev - [in] Device handle. See #amdgpu_device_initialize()
+ * \param context - \c [in] GPU Context
+ * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_*
+ * \param ip_instance - \c [in] Index of the IP block of the same type
+ * \param ring - \c [in] Specify ring index of the IP
+ * \param sem - \c [out] sem handle
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+*/
+int amdgpu_cs_wait_sem(amdgpu_device_handle dev,
+ amdgpu_context_handle ctx,
+ uint32_t ip_type,
+ uint32_t ip_instance,
+ uint32_t ring,
+ amdgpu_sem_handle sem);
+
+/**
+ * destroy sem
+ *
+ * \param dev - [in] Device handle. See #amdgpu_device_initialize()
+ * \param sem - \c [out] sem handle
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+ */
+int amdgpu_cs_destroy_sem(amdgpu_device_handle dev,
+ amdgpu_sem_handle sem);
+
+/**
* Get the ASIC marketing name
*
* \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index 868eb7b0..e1160a47 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -25,6 +25,8 @@
#include "config.h"
#endif
+#include <sys/stat.h>
+#include <unistd.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
@@ -596,3 +598,92 @@ int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem)
{
return amdgpu_cs_unreference_sem(sem);
}
+
+int amdgpu_cs_create_sem(amdgpu_device_handle dev,
+ amdgpu_sem_handle *sem)
+{
+ union drm_amdgpu_sem args;
+ int r;
+
+ if (NULL == dev)
+ return -EINVAL;
+
+ /* Create the context */
+ memset(&args, 0, sizeof(args));
+ args.in.op = AMDGPU_SEM_OP_CREATE_SEM;
+ r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args));
+ if (r)
+ return r;
+
+ *sem = args.out.handle;
+
+ return 0;
+}
+
+int amdgpu_cs_signal_sem(amdgpu_device_handle dev,
+ amdgpu_context_handle ctx,
+ uint32_t ip_type,
+ uint32_t ip_instance,
+ uint32_t ring,
+ amdgpu_sem_handle sem)
+{
+ union drm_amdgpu_sem args;
+
+ if (NULL == dev)
+ return -EINVAL;
+
+ /* Create the context */
+ memset(&args, 0, sizeof(args));
+ args.in.op = AMDGPU_SEM_OP_SIGNAL_SEM;
+ args.in.ctx_id = ctx->id;
+ args.in.ip_type = ip_type;
+ args.in.ip_instance = ip_instance;
+ args.in.ring = ring;
+ args.in.handle = sem;
+ args.in.seq = ~0ull;
+ return drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args));
+}
+
+int amdgpu_cs_wait_sem(amdgpu_device_handle dev,
+ amdgpu_context_handle ctx,
+ uint32_t ip_type,
+ uint32_t ip_instance,
+ uint32_t ring,
+ amdgpu_sem_handle sem)
+{
+ union drm_amdgpu_sem args;
+
+ if (NULL == dev)
+ return -EINVAL;
+
+ /* Create the context */
+ memset(&args, 0, sizeof(args));
+ args.in.op = AMDGPU_SEM_OP_WAIT_SEM;
+ args.in.ctx_id = ctx->id;
+ args.in.ip_type = ip_type;
+ args.in.ip_instance = ip_instance;
+ args.in.ring = ring;
+ args.in.handle = sem;
+ args.in.seq = 0;
+ return drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args));
+}
+
+int amdgpu_cs_destroy_sem(amdgpu_device_handle dev,
+ amdgpu_sem_handle sem)
+{
+ union drm_amdgpu_sem args;
+ int r;
+
+ if (NULL == dev)
+ return -EINVAL;
+
+ /* Create the context */
+ memset(&args, 0, sizeof(args));
+ args.in.op = AMDGPU_SEM_OP_DESTROY_SEM;
+ args.in.handle = sem;
+ r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args));
+ if (r)
+ return r;
+
+ return 0;
+}
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 7a7ecb7f..a551ba7d 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -53,6 +53,7 @@ extern "C" {
#define DRM_AMDGPU_WAIT_FENCES 0x12
/* hybrid specific ioctls */
+#define DRM_AMDGPU_SEM 0x5b
#define DRM_AMDGPU_GEM_DGMA 0x5c
#define DRM_AMDGPU_FREESYNC 0x5d
#define DRM_AMDGPU_GEM_FIND_BO 0x5f
@@ -74,6 +75,7 @@ extern "C" {
/* hybrid specific ioctls */
#define DRM_IOCTL_AMDGPU_GEM_DGMA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_DGMA, struct drm_amdgpu_gem_dgma)
#define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo)
+#define DRM_IOCTL_AMDGPU_SEM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_SEM, union drm_amdgpu_sem)
#define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync)
#define AMDGPU_GEM_DOMAIN_CPU 0x1
@@ -207,6 +209,33 @@ union drm_amdgpu_ctx {
union drm_amdgpu_ctx_out out;
};
+/* sync file related */
+#define AMDGPU_SEM_OP_CREATE_SEM 1
+#define AMDGPU_SEM_OP_WAIT_SEM 2
+#define AMDGPU_SEM_OP_SIGNAL_SEM 3
+#define AMDGPU_SEM_OP_DESTROY_SEM 4
+
+struct drm_amdgpu_sem_in {
+ /** AMDGPU_SEM_OP_* */
+ uint32_t op;
+ uint32_t handle;
+ uint32_t ctx_id;
+ uint32_t ip_type;
+ uint32_t ip_instance;
+ uint32_t ring;
+ uint64_t seq;
+};
+
+union drm_amdgpu_sem_out {
+ int fd;
+ uint32_t handle;
+};
+
+union drm_amdgpu_sem {
+ struct drm_amdgpu_sem_in in;
+ union drm_amdgpu_sem_out out;
+};
+
/*
* This is not a reliable API and you should expect it to fail for any
* number of reasons and have fallback path that do not use userptr to