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authorHawking Zhang <Hawking.Zhang@amd.com>2017-05-27 13:40:45 +0800
committerHawking Zhang <Hawking.Zhang@amd.com>2017-05-27 16:32:33 +0800
commit44b1c4355965e9d8fb1a2fa7a17c8cbdfaad81d6 (patch)
tree57f74b460bc7f56ac854509d5ae8a1bcbe11a8c3
parent476150860fd759a228bef2eeaa2eb2e51f21c6c5 (diff)
tests/amdgpu: bypass UVD CS tests on raven
raven doesn't support UVD decode Change-Id: Ibc3a3a1b1007aaf7cf8de8b6ccd2457167f11fcb Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com>
-rw-r--r--tests/amdgpu/cs_tests.c17
1 files changed, 17 insertions, 0 deletions
diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c
index 081ec9c2..df55c70d 100644
--- a/tests/amdgpu/cs_tests.c
+++ b/tests/amdgpu/cs_tests.c
@@ -90,6 +90,11 @@ int suite_cs_tests_init(void)
chip_rev = device_handle->info.chip_rev;
chip_id = device_handle->info.chip_external_rev;
+ if (family_id >= AMDGPU_FAMILY_RV) {
+ printf("\n\nThe ASIC NOT support UVD, all sub-tests will pass\n");
+ return CUE_SUCCESS;
+ }
+
r = amdgpu_cs_ctx_create(device_handle, &context_handle);
if (r)
return CUE_SINIT_FAILED;
@@ -114,6 +119,9 @@ int suite_cs_tests_clean(void)
{
int r;
+ if (family_id >= AMDGPU_FAMILY_RV)
+ return CUE_SUCCESS;
+
r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
ib_mc_address, IB_SIZE);
if (r)
@@ -192,6 +200,9 @@ static void amdgpu_cs_uvd_create(void)
void *msg;
int i, r;
+ if (family_id >= AMDGPU_FAMILY_RV)
+ return;
+
req.alloc_size = 4*1024;
req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
@@ -263,6 +274,9 @@ static void amdgpu_cs_uvd_decode(void)
uint8_t *ptr;
int i, r;
+ if (family_id >= AMDGPU_FAMILY_RV)
+ return;
+
req.alloc_size = 4*1024; /* msg */
req.alloc_size += 4*1024; /* fb */
if (family_id >= AMDGPU_FAMILY_VI)
@@ -402,6 +416,9 @@ static void amdgpu_cs_uvd_destroy(void)
void *msg;
int i, r;
+ if (family_id >= AMDGPU_FAMILY_RV)
+ return;
+
req.alloc_size = 4*1024;
req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;