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authorQiang Yu <Qiang.Yu@amd.com>2017-04-18 09:50:23 +0800
committerQiang Yu <Qiang.Yu@amd.com>2017-05-17 11:19:54 +0800
commit33f7fba1b3bc32bb65b00befb59827c5b93af6cd (patch)
treea589b905499267f3d3bc66aab5cdab3274106505
parente98f90a7b095abd07679eef9044fd73065808971 (diff)
[HYBRID] amdgpu: unify dk drm header changes
This is needed by close source components only (OGL). Change-Id: I069da74ed41c40561cd95ef28bb8810fe4d64353 Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
-rw-r--r--amdgpu/amdgpu.h17
1 files changed, 12 insertions, 5 deletions
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 048c2462..38a1f540 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -193,11 +193,18 @@ struct amdgpu_bo_metadata {
/** Special flag associated with surface */
uint64_t flags;
- /**
- * ASIC-specific tiling information (also used by DCE).
- * The encoding is defined by the AMDGPU_TILING_* definitions.
- */
- uint64_t tiling_info;
+ union {
+ /**
+ * ASIC-specific tiling information (also used by DCE).
+ * The encoding is defined by the AMDGPU_TILING_* definitions.
+ */
+ uint64_t tiling_info;
+ /**
+ * ASIC-specific swizzle information.
+ * The encoding is defined by the AMDGPU_SWIZZLE_* definitions.
+ */
+ uint64_t swizzle_info;
+ };
/** Size of metadata associated with the buffer, in bytes. */
uint32_t size_metadata;