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authorHawking Zhang <Hawking.Zhang@amd.com>2016-08-04 14:26:51 +0800
committerQiang Yu <Qiang.Yu@amd.com>2017-05-17 11:10:47 +0800
commit2c46a79696dd5b8a3981b85c8929c945e775b148 (patch)
tree6fb579fee42fe336899ba3912b797b99ef52f2bd
parenta76591320ae15e695086290e86ee8851871a9720 (diff)
drm/amdgpu: add freesync ioctl defines
Change-Id: Id5d607fee4ae119015ca685a508a2ee140a8e331 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Flora Cui <Flora.Cui@amd.com>
-rw-r--r--include/drm/amdgpu_drm.h17
1 files changed, 17 insertions, 0 deletions
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index de2b0689..85addfde 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -51,7 +51,9 @@ extern "C" {
#define DRM_AMDGPU_GEM_OP 0x10
#define DRM_AMDGPU_GEM_USERPTR 0x11
#define DRM_AMDGPU_WAIT_FENCES 0x12
+
/* hybrid specific ioctls */
+#define DRM_AMDGPU_FREESYNC 0x5d
#define DRM_AMDGPU_GEM_FIND_BO 0x5f
#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
@@ -67,8 +69,10 @@ extern "C" {
#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
+
/* hybrid specific ioctls */
#define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo)
+#define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync)
#define AMDGPU_GEM_DOMAIN_CPU 0x1
#define AMDGPU_GEM_DOMAIN_GTT 0x2
@@ -867,6 +871,19 @@ struct drm_amdgpu_capability {
uint32_t direct_gma_size;
};
+/*
+ * Definition of free sync enter and exit signals
+ * We may have more options in the future
+ */
+#define AMDGPU_FREESYNC_FULLSCREEN_ENTER 1
+#define AMDGPU_FREESYNC_FULLSCREEN_EXIT 2
+
+struct drm_amdgpu_freesync {
+ __u32 op; /* AMDGPU_FREESYNC_FULLSCREEN_ENTER or */
+ /* AMDGPU_FREESYNC_FULLSCREEN_ENTER */
+ __u32 spare[7];
+};
+
#if defined(__cplusplus)
}
#endif