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authorFlora Cui <flora.cui@amd.com>2015-10-10 17:25:06 +0800
committerQiang Yu <Qiang.Yu@amd.com>2017-05-17 10:24:19 +0800
commit1df72708b4762e795ba5382318b8cd6db55eb7a3 (patch)
treedd02a3ec2556c0912ad963aa7b343bb77e9d923a
parenta126c245306ba47190e60007bc1c41602b9c6e61 (diff)
amdgpu: add query for aperture va range
Change-Id: I65814c6f8db2fa51f8267ae202c1d9999e9fe82b Signed-off-by: Flora Cui <flora.cui@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--amdgpu/amdgpu.h30
-rw-r--r--amdgpu/amdgpu_gpu_info.c45
-rw-r--r--include/drm/amdgpu_drm.h18
3 files changed, 93 insertions, 0 deletions
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 1cec608f..e9eef188 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1106,6 +1106,36 @@ int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type,
unsigned size, void *value);
/**
+ * Query private aperture range
+ *
+ * \param dev - [in] Device handle. See #amdgpu_device_initialize()
+ * \param start - \c [out] Start of private aperture
+ * \param end - \c [out] End of private aperture
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+*/
+int amdgpu_query_private_aperture(amdgpu_device_handle dev,
+ uint64_t *start,
+ uint64_t *end);
+
+/**
+ * Query shared aperture range
+ *
+ * \param dev - [in] Device handle. See #amdgpu_device_initialize()
+ * \param start - \c [out] Start of shared aperture
+ * \param end - \c [out] End of shared aperture
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+*/
+int amdgpu_query_shared_aperture(amdgpu_device_handle dev,
+ uint64_t *start,
+ uint64_t *end);
+
+/**
* Read a set of consecutive memory-mapped registers.
* Not all registers are allowed to be read by userspace.
*
diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c
index 1efffc6f..697360b2 100644
--- a/amdgpu/amdgpu_gpu_info.c
+++ b/amdgpu/amdgpu_gpu_info.c
@@ -334,3 +334,48 @@ int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type,
return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
sizeof(struct drm_amdgpu_info));
}
+
+static int amdgpu_query_virtual_range_info(amdgpu_device_handle dev,
+ uint32_t aperture,
+ uint64_t *start,
+ uint64_t *end)
+{
+ struct drm_amdgpu_virtual_range range_info;
+ struct drm_amdgpu_info request;
+ int r;
+
+ memset(&range_info, 0, sizeof(range_info));
+ request.return_pointer = (uintptr_t)&range_info;
+ request.return_size = sizeof(range_info);
+ request.query = AMDGPU_INFO_VIRTUAL_RANGE;
+ request.virtual_range.aperture = aperture;
+
+ r = drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
+ sizeof(struct drm_amdgpu_info));
+ if (r)
+ return r;
+
+ *start = range_info.start;
+ *end = range_info.end;
+ return 0;
+}
+
+int amdgpu_query_private_aperture(amdgpu_device_handle dev,
+ uint64_t *start,
+ uint64_t *end)
+{
+ return amdgpu_query_virtual_range_info(dev,
+ AMDGPU_SUA_APERTURE_PRIVATE,
+ start,
+ end);
+}
+
+int amdgpu_query_shared_aperture(amdgpu_device_handle dev,
+ uint64_t *start,
+ uint64_t *end)
+{
+ return amdgpu_query_virtual_range_info(dev,
+ AMDGPU_SUA_APERTURE_SHARED,
+ start,
+ end);
+}
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 516a9f28..6e5544ef 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -577,6 +577,9 @@ struct drm_amdgpu_cs_chunk_data {
/* Subquery id: Query graphics voltage */
#define AMDGPU_INFO_SENSOR_VDDGFX 0x7
+/* virtual range */
+#define AMDGPU_INFO_VIRTUAL_RANGE 0x51
+
#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
@@ -633,6 +636,11 @@ struct drm_amdgpu_info {
__u32 flags;
} read_mmr_reg;
+ struct {
+ uint32_t aperture;
+ uint32_t _pad;
+ } virtual_range;
+
struct drm_amdgpu_query_fw query_fw;
struct {
@@ -817,6 +825,16 @@ struct drm_amdgpu_info_vce_clock_table {
#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */
#define AMDGPU_FAMILY_AI 141 /* Vega10 */
+/**
+ * Definition of System Unified Address (SUA) apertures
+ */
+#define AMDGPU_SUA_APERTURE_PRIVATE 1
+#define AMDGPU_SUA_APERTURE_SHARED 2
+struct drm_amdgpu_virtual_range {
+ uint64_t start;
+ uint64_t end;
+};
+
#if defined(__cplusplus)
}
#endif