diff options
Diffstat (limited to 'hw/xfree86/scanpci/xf86PciStdIds.h')
| -rw-r--r-- | hw/xfree86/scanpci/xf86PciStdIds.h | 80800 |
1 files changed, 80800 insertions, 0 deletions
diff --git a/hw/xfree86/scanpci/xf86PciStdIds.h b/hw/xfree86/scanpci/xf86PciStdIds.h new file mode 100644 index 000000000..58403ccf7 --- /dev/null +++ b/hw/xfree86/scanpci/xf86PciStdIds.h @@ -0,0 +1,80800 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/scanpci/xf86PciStdIds.h,v 1.10 2003/02/26 16:33:03 dawes Exp $ */ + +/* + * THIS FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + * + * It is generated by pciid2c.pl using data from the following files: + * + * ../etc/pci.ids + * ../etc/extrapci.ids + * ../common/xf86PciInfo.h + */ + +/* + * Copyright © 2002 by the XFree86 Project, Inc. + * + * The pci.ids file and the data it contains are from the Linux PCI ID's + * Project (http://pciids.sf.net/). It is maintained by Martin Mares + * <mj@ucw.cz> and other volunteers. The pci.ids file contains no + * copyright notice. + */ + +#include "xf86PciInfo.h" +#ifndef NULL +#define NULL (void *)0 +#endif + +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0000[] = "Gammagraphx, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_001a[] = "Ascend Communications, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0033[] = "Paradyne corp."; +#endif +static const char pci_vendor_003d[] = "Lockheed Martin-Marietta Corp"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0059[] = "Tiger Jet Network Inc. (Wrong ID)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0070[] = "Hauppauge computer works Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0100[] = "Ncipher Corp Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0675[] = "Dynalink"; +static const char pci_device_0675_1700[] = "IS64PH ISDN Adapter"; +static const char pci_device_0675_1702[] = "IS64PH ISDN Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0925[] = "VIA Technologies, Inc. (Wrong ID)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_09c1[] = "Arris"; +static const char pci_device_09c1_0704[] = "CM 200E Cable Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0a89[] = "BREA Technologies Inc"; +#endif +static const char pci_vendor_0e11[] = "Compaq Computer Corporation"; +static const char pci_device_0e11_0001[] = "PCI to EISA Bridge"; +static const char pci_device_0e11_0002[] = "PCI to ISA Bridge"; +static const char pci_device_0e11_0049[] = "NC7132 Gigabit Upgrade Module"; +static const char pci_device_0e11_004a[] = "NC6136 Gigabit Server Adapter"; +static const char pci_device_0e11_0508[] = "Netelligent 4/16 Token Ring"; +static const char pci_device_0e11_1000[] = "Triflex/Pentium Bridge, Model 1000"; +static const char pci_device_0e11_2000[] = "Triflex/Pentium Bridge, Model 2000"; +static const char pci_device_0e11_3032[] = "QVision 1280/p"; +static const char pci_device_0e11_3033[] = "QVision 1280/p"; +static const char pci_device_0e11_3034[] = "QVision 1280/p"; +static const char pci_device_0e11_4000[] = "4000 [Triflex]"; +static const char pci_device_0e11_6010[] = "HotPlug PCI Bridge 6010"; +static const char pci_device_0e11_7020[] = "USB Controller"; +static const char pci_device_0e11_a0ec[] = "Fibre Channel Host Controller"; +static const char pci_device_0e11_a0f0[] = "Advanced System Management Controller"; +static const char pci_device_0e11_a0f3[] = "Triflex PCI to ISA Bridge"; +static const char pci_device_0e11_a0f7[] = "PCI Hotplug Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_a0f7_8086_002a[] = "PCI Hotplug Controller A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_a0f7_8086_002b[] = "PCI Hotplug Controller B"; +#endif +static const char pci_device_0e11_a0f8[] = "ZFMicro Chipset USB"; +static const char pci_device_0e11_a0fc[] = "Fibre Channel Host Controller"; +static const char pci_device_0e11_ae10[] = "Smart-2/P RAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_ae10_0e11_4030[] = "Smart-2/P Array Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_ae10_0e11_4031[] = "Smart-2SL Array Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_ae10_0e11_4032[] = "Smart Array Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_ae10_0e11_4033[] = "Smart 3100ES Array Controller"; +#endif +static const char pci_device_0e11_ae29[] = "MIS-L"; +static const char pci_device_0e11_ae2a[] = "MPC"; +static const char pci_device_0e11_ae2b[] = "MIS-E"; +static const char pci_device_0e11_ae31[] = "System Management Controller"; +static const char pci_device_0e11_ae32[] = "Netelligent 10/100"; +static const char pci_device_0e11_ae33[] = "Triflex Dual EIDE Controller"; +static const char pci_device_0e11_ae34[] = "Netelligent 10"; +static const char pci_device_0e11_ae35[] = "Integrated NetFlex-3/P"; +static const char pci_device_0e11_ae40[] = "Netelligent 10/100 Dual"; +static const char pci_device_0e11_ae43[] = "ProLiant Integrated Netelligent 10/100"; +static const char pci_device_0e11_ae69[] = "CETUS-L"; +static const char pci_device_0e11_ae6c[] = "Northstar"; +static const char pci_device_0e11_ae6d[] = "NorthStar CPU to PCI Bridge"; +static const char pci_device_0e11_b011[] = "Integrated Netelligent 10/100"; +static const char pci_device_0e11_b012[] = "Netelligent 10 T/2"; +static const char pci_device_0e11_b01e[] = "NC3120 Fast Ethernet NIC"; +static const char pci_device_0e11_b01f[] = "NC3122 Fast Ethernet NIC"; +static const char pci_device_0e11_b02f[] = "NC1120 Ethernet NIC"; +static const char pci_device_0e11_b030[] = "Netelligent WS 5100"; +static const char pci_device_0e11_b04a[] = "10/100 TX PCI Intel WOL UTP Controller"; +static const char pci_device_0e11_b060[] = "Smart Array 5300 Controller"; +static const char pci_device_0e11_b0c6[] = "NC3161 Fast Ethernet NIC"; +static const char pci_device_0e11_b0c7[] = "NC3160 Fast Ethernet NIC"; +static const char pci_device_0e11_b0d7[] = "NC3121 Fast Ethernet NIC"; +static const char pci_device_0e11_b0dd[] = "NC3131 Fast Ethernet NIC"; +static const char pci_device_0e11_b0de[] = "NC3132 Fast Ethernet Module"; +static const char pci_device_0e11_b0df[] = "NC6132 Gigabit Module"; +static const char pci_device_0e11_b0e0[] = "NC6133 Gigabit Module"; +static const char pci_device_0e11_b0e1[] = "NC3133 Fast Ethernet Module"; +static const char pci_device_0e11_b123[] = "NC6134 Gigabit NIC"; +static const char pci_device_0e11_b134[] = "NC3163 Fast Ethernet NIC"; +static const char pci_device_0e11_b13c[] = "NC3162 Fast Ethernet NIC"; +static const char pci_device_0e11_b144[] = "NC3123 Fast Ethernet NIC"; +static const char pci_device_0e11_b163[] = "NC3134 Fast Ethernet NIC"; +static const char pci_device_0e11_b164[] = "NC3165 Fast Ethernet Upgrade Module"; +static const char pci_device_0e11_b178[] = "Smart Array 5i/532"; +static const char pci_device_0e11_b1a4[] = "NC7131 Gigabit Server Adapter"; +static const char pci_device_0e11_f130[] = "NetFlex-3/P ThunderLAN 1.0"; +static const char pci_device_0e11_f150[] = "NetFlex-3/P ThunderLAN 2.3"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0e55[] = "HaSoTec GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1000[] = "LSI Logic / Symbios Logic"; +static const char pci_device_1000_0001[] = "53c810"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0001_1000_1000[] = "8100S"; +#endif +static const char pci_device_1000_0002[] = "53c820"; +static const char pci_device_1000_0003[] = "53c825"; +static const char pci_device_1000_0004[] = "53c815"; +static const char pci_device_1000_0005[] = "53c810AP"; +static const char pci_device_1000_0006[] = "53c860"; +static const char pci_device_1000_000a[] = "53c1510"; +static const char pci_device_1000_000b[] = "53c896"; +static const char pci_device_1000_000c[] = "53c895"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000c_1de1_3907[] = "DC-390U2W"; +#endif +static const char pci_device_1000_000d[] = "53c885"; +static const char pci_device_1000_000f[] = "53c875"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_0e11_7004[] = "Embedded Ultra Wide SCSI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1092_8760[] = "FirePort 40 Dual SCSI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1de1_3904[] = "DC390F Ultra Wide SCSI Controller"; +#endif +static const char pci_device_1000_0010[] = "53c895"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0010_0e11_4040[] = "Integrated Array Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0010_0e11_4048[] = "Integrated Array Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1000_0012[] = "53c895a"; +static const char pci_device_1000_0013[] = "53c875a"; +static const char pci_device_1000_0020[] = "53c1010 Ultra3 SCSI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0020_1de1_1020[] = "DC-390U3W"; +#endif +static const char pci_device_1000_0021[] = "53c1010 66MHz Ultra3 SCSI Adapter"; +static const char pci_device_1000_0030[] = "53c1030"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1028_1010[] = "LSI U320 SCSI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1000_0040[] = "53c1035"; +static const char pci_device_1000_008f[] = "53c875J"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_008f_1092_8000[] = "FirePort 40 SCSI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_008f_1092_8760[] = "FirePort 40 Dual SCSI Host Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1000_0621[] = "FC909"; +static const char pci_device_1000_0622[] = "FC929"; +static const char pci_device_1000_0623[] = "FC929 LAN"; +static const char pci_device_1000_0624[] = "FC919"; +static const char pci_device_1000_0625[] = "FC919 LAN"; +static const char pci_device_1000_0626[] = "FC929X"; +static const char pci_device_1000_0627[] = "FC929X LAN"; +static const char pci_device_1000_0628[] = "FC919X"; +static const char pci_device_1000_0629[] = "FC919X LAN"; +static const char pci_device_1000_0701[] = "83C885 NT50 DigitalScape Fast Ethernet"; +static const char pci_device_1000_0702[] = "Yellowfin G-NIC gigabit ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0702_1318_0000[] = "PEI100X"; +#endif +static const char pci_device_1000_0901[] = "61C102"; +static const char pci_device_1000_1000[] = "63C815"; +static const char pci_device_1000_1960[] = "PowerEdge Expandable RAID Controller 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1028_0518[] = "PowerEdge Expandable RAID Controller 4/DC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1028_0520[] = "PowerEdge Expandable RAID Controller 4/SC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1028_0531[] = "PowerEdge Expandable RAID Controller 4/QC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1001[] = "Kolter Electronic"; +static const char pci_device_1001_0010[] = "PCI 1616 Measurement card with 32 digital I/O lines"; +static const char pci_device_1001_0011[] = "OPTO-PCI Opto-Isolated digital I/O board"; +static const char pci_device_1001_0012[] = "PCI-AD/DA Analogue I/O board"; +static const char pci_device_1001_0013[] = "PCI-OPTO-RELAIS Digital I/O board with relay outputs"; +static const char pci_device_1001_0014[] = "PCI-Counter/Timer Counter Timer board"; +static const char pci_device_1001_0015[] = "PCI-DAC416 Analogue output board"; +static const char pci_device_1001_0016[] = "PCI-MFB Analogue I/O board"; +static const char pci_device_1001_0017[] = "PROTO-3 PCI Prototyping board"; +static const char pci_device_1001_9100[] = "INI-9100/9100W SCSI Host"; +#endif +static const char pci_vendor_1002[] = "ATI Technologies Inc"; +static const char pci_device_1002_4144[] = "Radeon R300 AD [Radeon 9500 Pro]"; +static const char pci_device_1002_4145[] = "Radeon R300 AE [Radeon 9500 Pro]"; +static const char pci_device_1002_4146[] = "Radeon R300 AF [Radeon 9500 Pro]"; +static const char pci_device_1002_4147[] = "Radeon R300 AG [FireGL Z1/X1]"; +static const char pci_device_1002_4158[] = "68800AX [Mach32]"; +static const char pci_device_1002_4242[] = "Radeon R200 BB [Radeon All in Wonder 8500DV]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4242_1002_02aa[] = "Radeon 8500 AIW DV Edition"; +#endif +static const char pci_device_1002_4336[] = "Radeon Mobility U1"; +static const char pci_device_1002_4337[] = "Radeon IGP 340M"; +static const char pci_device_1002_4354[] = "215CT [Mach64 CT]"; +static const char pci_device_1002_4358[] = "210888CX [Mach64 CX]"; +static const char pci_device_1002_4554[] = "210888ET [Mach64 ET]"; +static const char pci_device_1002_4654[] = "Mach64 VT"; +static const char pci_device_1002_4742[] = "3D Rage Pro AGP 1X/2X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0040[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0044[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0061[] = "Rage Pro AIW AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0062[] = "Rage Pro AIW AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0063[] = "Rage Pro AIW AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0080[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0084[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_4742[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_8001[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1028_0082[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1028_4082[] = "Optiplex GX1 Onboard Display Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1028_8082[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1028_c082[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_8086_4152[] = "Xpert 98D AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_8086_464a[] = "Rage Pro Turbo AGP 2X"; +#endif +static const char pci_device_1002_4744[] = "3D Rage Pro AGP 1X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4744_1002_4744[] = "Rage Pro Turbo AGP"; +#endif +static const char pci_device_1002_4747[] = "3D Rage Pro"; +static const char pci_device_1002_4749[] = "3D Rage Pro"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4749_1002_0061[] = "Rage Pro AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4749_1002_0062[] = "Rage Pro AIW"; +#endif +static const char pci_device_1002_474c[] = "Rage XC"; +static const char pci_device_1002_474d[] = "Rage XL AGP 2X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_0004[] = "Xpert 98 RXL AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_0008[] = "Xpert 98 RXL AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_0080[] = "Rage XL AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_0084[] = "Xpert 98 AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_474d[] = "Rage XL AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1033_806a[] = "Rage XL AGP"; +#endif +static const char pci_device_1002_474e[] = "Rage XC AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474e_1002_474e[] = "Rage XC AGP"; +#endif +static const char pci_device_1002_474f[] = "Rage XL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474f_1002_0008[] = "Rage XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474f_1002_474f[] = "Rage XL"; +#endif +static const char pci_device_1002_4750[] = "3D Rage Pro 215GP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_0040[] = "Rage Pro Turbo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_0044[] = "Rage Pro Turbo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_0080[] = "Rage Pro Turbo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_0084[] = "Rage Pro Turbo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_4750[] = "Rage Pro Turbo"; +#endif +static const char pci_device_1002_4751[] = "3D Rage Pro 215GQ"; +static const char pci_device_1002_4752[] = "Rage XL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1002_0008[] = "Rage XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1002_4752[] = "Rage XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1002_8008[] = "Rage XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1028_00d1[] = "PowerEdge 2550"; +#endif +static const char pci_device_1002_4753[] = "Rage XC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4753_1002_4753[] = "Rage XC"; +#endif +static const char pci_device_1002_4754[] = "3D Rage I/II 215GT [Mach64 GT]"; +static const char pci_device_1002_4755[] = "3D Rage II+ 215GTB [Mach64 GTB]"; +static const char pci_device_1002_4756[] = "3D Rage IIC 215IIC [Mach64 GT IIC]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4756_1002_4756[] = "Rage IIC"; +#endif +static const char pci_device_1002_4757[] = "3D Rage IIC AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1002_4757[] = "Rage IIC AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1028_0089[] = "Rage 3D IIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1028_4082[] = "Rage 3D IIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1028_8082[] = "Rage 3D IIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1028_c082[] = "Rage 3D IIC"; +#endif +static const char pci_device_1002_4758[] = "210888GX [Mach64 GX]"; +static const char pci_device_1002_4759[] = "3D Rage IIC"; +static const char pci_device_1002_475a[] = "3D Rage IIC AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_475a_1002_0087[] = "Rage 3D IIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_475a_1002_475a[] = "Rage IIC AGP"; +#endif +static const char pci_device_1002_4964[] = "Radeon R250 Id [Radeon 9000]"; +static const char pci_device_1002_4965[] = "Radeon R250 Ie [Radeon 9000]"; +static const char pci_device_1002_4966[] = "Radeon R250 If [Radeon 9000]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_10f1_0002[] = "R250 If [Tachyon G9000 PRO]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_148c_2039[] = "R250 If [Radeon 9000 Pro Evil Commando]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_1509_9a00[] = "R250 If [Radeon 9000 AT009]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_1681_0040[] = "R250 If [3D prophet 9000]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_174b_7176[] = "R250 If [Sapphire Radeon 9000 Pro]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_174b_7192[] = "R250 If [Radeon 9000 Atlantis]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_17af_2005[] = "R250 If [Excalibur Radeon 9000 Pro]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_17af_2006[] = "R250 If [Excalibur Radeon 9000]"; +#endif +static const char pci_device_1002_4967[] = "Radeon R250 Ig [Radeon 9000]"; +static const char pci_device_1002_496e[] = "Radeon R250 [Radeon 9000] (Secondary)"; +static const char pci_device_1002_4c42[] = "3D Rage LT Pro AGP-133"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_0e11_b0e8[] = "Rage 3D LT Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_0e11_b10e[] = "3D Rage LT Pro (Compaq Armada 1750)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1002_0040[] = "Rage LT Pro AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1002_0044[] = "Rage LT Pro AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1002_4c42[] = "Rage LT Pro AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1002_8001[] = "Rage LT Pro AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1028_0085[] = "Rage 3D LT Pro"; +#endif +static const char pci_device_1002_4c44[] = "3D Rage LT Pro AGP-66"; +static const char pci_device_1002_4c45[] = "Rage Mobility M3 AGP"; +static const char pci_device_1002_4c46[] = "Rage Mobility M3 AGP 2x"; +static const char pci_device_1002_4c47[] = "3D Rage LT-G 215LG"; +static const char pci_device_1002_4c49[] = "3D Rage LT Pro"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c49_1002_0004[] = "Rage LT Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c49_1002_0040[] = "Rage LT Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c49_1002_0044[] = "Rage LT Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c49_1002_4c49[] = "Rage LT Pro"; +#endif +static const char pci_device_1002_4c4d[] = "Rage Mobility P/M AGP 2x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_0e11_b111[] = "Armada M700"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_1002_0084[] = "Xpert 98 AGP 2X (Mobility)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_1014_0154[] = "ThinkPad A20m"; +#endif +static const char pci_device_1002_4c4e[] = "Rage Mobility L AGP 2x"; +static const char pci_device_1002_4c50[] = "3D Rage LT Pro"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c50_1002_4c50[] = "Rage LT Pro"; +#endif +static const char pci_device_1002_4c51[] = "3D Rage LT Pro"; +static const char pci_device_1002_4c52[] = "Rage Mobility P/M"; +static const char pci_device_1002_4c53[] = "Rage Mobility L"; +static const char pci_device_1002_4c54[] = "264LT [Mach64 LT]"; +static const char pci_device_1002_4c57[] = "Radeon Mobility M7 LW [Radeon Mobility 7500]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c57_1014_0517[] = "ThinkPad T30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c57_1028_00e6[] = "Radeon Mobility M7 LW (Dell Inspiron 8100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c57_144d_c006[] = "Radeon Mobility M7 LW in vpr Matrix 170B4"; +#endif +static const char pci_device_1002_4c58[] = "Radeon RV200 LX [Mobility FireGL 7800 M7]"; +static const char pci_device_1002_4c59[] = "Radeon Mobility M6 LY"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_1014_0235[] = "ThinkPad A30p (2653-64G)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_1014_0239[] = "ThinkPad X22/X23/X24"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +static const char pci_device_1002_4c5a[] = "Radeon Mobility M6 LZ"; +static const char pci_device_1002_4c64[] = "Radeon R250 Ld [Radeon Mobility 9000 M9]"; +static const char pci_device_1002_4c65[] = "Radeon R250 Le [Radeon Mobility 9000 M9]"; +static const char pci_device_1002_4c66[] = "Radeon R250 Lf [Radeon Mobility 9000 M9]"; +static const char pci_device_1002_4c67[] = "Radeon R250 Lg [Radeon Mobility 9000 M9]"; +static const char pci_device_1002_4d46[] = "Rage Mobility M4 AGP"; +static const char pci_device_1002_4d4c[] = "Rage Mobility M4 AGP"; +static const char pci_device_1002_4e44[] = "Radeon R300 ND [Radeon 9700]"; +static const char pci_device_1002_4e45[] = "Radeon R300 NE [Radeon 9700]"; +static const char pci_device_1002_4e46[] = "Radeon R300 NF [Radeon 9700]"; +static const char pci_device_1002_4e47[] = "Radeon R300 NG [FireGL X1]"; +static const char pci_device_1002_4e64[] = "Radeon R300 [Radeon 9700 Pro] (Secondary)"; +static const char pci_device_1002_4e65[] = "Radeon R300 [Radeon 9700] (Secondary)"; +static const char pci_device_1002_4e66[] = "Radeon R300 [Radeon 9700] (Secondary)"; +static const char pci_device_1002_4e67[] = "Radeon R300 [FireGL X1] (Secondary)"; +static const char pci_device_1002_5041[] = "Rage 128 PA/PRO"; +static const char pci_device_1002_5042[] = "Rage 128 PB/PRO AGP 2x"; +static const char pci_device_1002_5043[] = "Rage 128 PC/PRO AGP 4x"; +static const char pci_device_1002_5044[] = "Rage 128 PD/PRO TMDS"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5044_1002_0028[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5044_1002_0029[] = "Rage 128 AIW"; +#endif +static const char pci_device_1002_5045[] = "Rage 128 PE/PRO AGP 2x TMDS"; +static const char pci_device_1002_5046[] = "Rage 128 PF/PRO AGP 4x TMDS"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0004[] = "Rage Fury Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0008[] = "Rage Fury Pro/Xpert 2000 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0014[] = "Rage Fury Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0018[] = "Rage Fury Pro/Xpert 2000 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0028[] = "Rage 128 Pro AIW AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_002a[] = "Rage 128 Pro AIW AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0048[] = "Rage Fury Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_2000[] = "Rage Fury MAXX AGP 4x (TMDS) (VGA device)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_2001[] = "Rage Fury MAXX AGP 4x (TMDS) (Extra device?!)"; +#endif +static const char pci_device_1002_5047[] = "Rage 128 PG/PRO"; +static const char pci_device_1002_5048[] = "Rage 128 PH/PRO AGP 2x"; +static const char pci_device_1002_5049[] = "Rage 128 PI/PRO AGP 4x"; +static const char pci_device_1002_504a[] = "Rage 128 PJ/PRO TMDS"; +static const char pci_device_1002_504b[] = "Rage 128 PK/PRO AGP 2x TMDS"; +static const char pci_device_1002_504c[] = "Rage 128 PL/PRO AGP 4x TMDS"; +static const char pci_device_1002_504d[] = "Rage 128 PM/PRO"; +static const char pci_device_1002_504e[] = "Rage 128 PN/PRO AGP 2x"; +static const char pci_device_1002_504f[] = "Rage 128 PO/PRO AGP 4x"; +static const char pci_device_1002_5050[] = "Rage 128 PP/PRO TMDS [Xpert 128]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5050_1002_0008[] = "Xpert 128"; +#endif +static const char pci_device_1002_5051[] = "Rage 128 PQ/PRO AGP 2x TMDS"; +static const char pci_device_1002_5052[] = "Rage 128 PR/PRO AGP 4x TMDS"; +static const char pci_device_1002_5053[] = "Rage 128 PS/PRO"; +static const char pci_device_1002_5054[] = "Rage 128 PT/PRO AGP 2x"; +static const char pci_device_1002_5055[] = "Rage 128 PU/PRO AGP 4x"; +static const char pci_device_1002_5056[] = "Rage 128 PV/PRO TMDS"; +static const char pci_device_1002_5057[] = "Rage 128 PW/PRO AGP 2x TMDS"; +static const char pci_device_1002_5058[] = "Rage 128 PX/PRO AGP 4x TMDS"; +static const char pci_device_1002_5144[] = "Radeon R100 QD [Radeon 7200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0008[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0009[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_000a[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_001a[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0029[] = "Radeon AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0038[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0039[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_008a[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_00ba[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0139[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_028a[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_02aa[] = "Radeon AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_053a[] = "Radeon 7000/Radeon"; +#endif +static const char pci_device_1002_5145[] = "Radeon R100 QE"; +static const char pci_device_1002_5146[] = "Radeon R100 QF"; +static const char pci_device_1002_5147[] = "Radeon R100 QG"; +static const char pci_device_1002_5148[] = "Radeon R200 QH [Radeon 8500]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5148_1002_010a[] = "FireGL 8800 64Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5148_1002_0152[] = "FireGL 8800 128Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5148_1002_0162[] = "FireGL 8700 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5148_1002_0172[] = "FireGL 8700 64Mb"; +#endif +static const char pci_device_1002_5149[] = "Radeon R200 QI"; +static const char pci_device_1002_514a[] = "Radeon R200 QJ"; +static const char pci_device_1002_514b[] = "Radeon R200 QK"; +static const char pci_device_1002_514c[] = "Radeon R200 QL [Radeon 8500 LE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_1002_003a[] = "Radeon R200 QL [Radeon 8500 LE]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_1002_013a[] = "Radeon 8500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_148c_2026[] = "R200 QL [Radeon 8500 Evil Master II Multi Display Edition]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_174b_7149[] = "Radeon R200 QL [Sapphire Radeon 8500 LE]"; +#endif +static const char pci_device_1002_514d[] = "Radeon R200 QM [Radeon 9100]"; +static const char pci_device_1002_514e[] = "Radeon R200 QN [Radeon 8500LE]"; +static const char pci_device_1002_514f[] = "Radeon R200 QO [Radeon 8500LE]"; +static const char pci_device_1002_5157[] = "Radeon RV200 QW [Radeon 7500]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_1002_013a[] = "Radeon 7500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_1458_4000[] = "RV200 QW [RADEON 7500 PRO MAYA AR]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_148c_2024[] = "RV200 QW [Radeon 7500LE Dual Display]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_148c_2025[] = "RV200 QW [Radeon 7500 Evil Master Multi Display Edition]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_148c_2036[] = "RV200 QW [Radeon 7500 PCI Dual Display]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_174b_7147[] = "RV200 QW [Sapphire Radeon 7500LE]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_174b_7161[] = "Radeon RV200 QW [Radeon 7500 LE]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_17af_0202[] = "RV200 QW [Excalibur Radeon 7500LE]"; +#endif +static const char pci_device_1002_5158[] = "Radeon RV200 QX [Radeon 7500]"; +static const char pci_device_1002_5159[] = "Radeon RV100 QY [Radeon 7000/VE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_000a[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_000b[] = "Radeon 7000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_0038[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_003a[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_00ba[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_013a[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1458_4002[] = "RV100 QY [RADEON 7000 PRO MAYA AV Series]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_148c_2003[] = "RV100 QY [Radeon 7000 Multi-Display Edition]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_148c_2023[] = "RV100 QY [Radeon 7000 Evil Master Multi-Display]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_174b_7112[] = "RV100 QY [Sapphire Radeon VE 7000]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1787_0202[] = "RV100 QY [Excalibur Radeon 7000]"; +#endif +static const char pci_device_1002_515a[] = "Radeon RV100 QZ [Radeon 7000/VE]"; +static const char pci_device_1002_5168[] = "Radeon R200 Qh"; +static const char pci_device_1002_5169[] = "Radeon R200 Qi"; +static const char pci_device_1002_516a[] = "Radeon R200 Qj"; +static const char pci_device_1002_516b[] = "Radeon R200 Qk"; +static const char pci_device_1002_516c[] = "Radeon R200 Ql"; +static const char pci_device_1002_5245[] = "Rage 128 RE/SG"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5245_1002_0008[] = "Xpert 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5245_1002_0028[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5245_1002_0029[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5245_1002_0068[] = "Rage 128 AIW"; +#endif +static const char pci_device_1002_5246[] = "Rage 128 RF/SG AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0004[] = "Magnum/Xpert 128/Xpert 99"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0008[] = "Magnum/Xpert128/X99/Xpert2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0028[] = "Rage 128 AIW AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0044[] = "Rage Fury/Xpert 128/Xpert 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0068[] = "Rage 128 AIW AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0448[] = "Rage Fury"; +#endif +static const char pci_device_1002_5247[] = "Rage 128 RG"; +static const char pci_device_1002_524b[] = "Rage 128 RK/VR"; +static const char pci_device_1002_524c[] = "Rage 128 RL/VR AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_524c_1002_0008[] = "Xpert 99/Xpert 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_524c_1002_0088[] = "Xpert 99"; +#endif +static const char pci_device_1002_5345[] = "Rage 128 SE/4x"; +static const char pci_device_1002_5346[] = "Rage 128 SF/4x AGP 2x"; +static const char pci_device_1002_5347[] = "Rage 128 SG/4x AGP 4x"; +static const char pci_device_1002_5348[] = "Rage 128 SH"; +static const char pci_device_1002_534b[] = "Rage 128 SK/4x"; +static const char pci_device_1002_534c[] = "Rage 128 SL/4x AGP 2x"; +static const char pci_device_1002_534d[] = "Rage 128 SM/4x AGP 4x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_534d_1002_0008[] = "Xpert 99/Xpert 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_534d_1002_0018[] = "Xpert 2000"; +#endif +static const char pci_device_1002_534e[] = "Rage 128 4x"; +static const char pci_device_1002_5354[] = "Mach 64 VT"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5354_1002_5654[] = "Mach 64 reference"; +#endif +static const char pci_device_1002_5446[] = "Rage 128 Pro Ultra TF"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0004[] = "Rage Fury Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0008[] = "Rage Fury Pro/Xpert 2000 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0018[] = "Rage Fury Pro/Xpert 2000 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0028[] = "Rage 128 AIW Pro AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0029[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_002a[] = "Rage 128 AIW Pro AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_002b[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0048[] = "Xpert 2000 Pro"; +#endif +static const char pci_device_1002_544c[] = "Rage 128 Pro Ultra TL"; +static const char pci_device_1002_5452[] = "Rage 128 Pro Ultra TR"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5452_1002_001c[] = "Rage 128 Pro 4XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5452_103c_1279[] = "Rage 128 Pro 4XL"; +#endif +static const char pci_device_1002_5453[] = "Rage 128 Pro Ultra TS"; +static const char pci_device_1002_5454[] = "Rage 128 Pro Ultra TT"; +static const char pci_device_1002_5455[] = "Rage 128 Pro Ultra TU"; +static const char pci_device_1002_5654[] = "264VT [Mach64 VT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5654_1002_5654[] = "Mach64VT Reference"; +#endif +static const char pci_device_1002_5655[] = "264VT3 [Mach64 VT3]"; +static const char pci_device_1002_5656[] = "264VT4 [Mach64 VT4]"; +static const char pci_device_1002_700f[] = "U1/A3 AGP Bridge [IGP 320M]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1003[] = "ULSI Systems"; +static const char pci_device_1003_0201[] = "US201"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1004[] = "VLSI Technology Inc"; +static const char pci_device_1004_0005[] = "82C592-FC1"; +static const char pci_device_1004_0006[] = "82C593-FC1"; +static const char pci_device_1004_0007[] = "82C594-AFC2"; +static const char pci_device_1004_0008[] = "82C596/7 [Wildcat]"; +static const char pci_device_1004_0009[] = "82C597-AFC2"; +static const char pci_device_1004_000c[] = "82C541 [Lynx]"; +static const char pci_device_1004_000d[] = "82C543 [Lynx]"; +static const char pci_device_1004_0101[] = "82C532"; +static const char pci_device_1004_0102[] = "82C534 [Eagle]"; +static const char pci_device_1004_0103[] = "82C538"; +static const char pci_device_1004_0104[] = "82C535"; +static const char pci_device_1004_0105[] = "82C147"; +static const char pci_device_1004_0200[] = "82C975"; +static const char pci_device_1004_0280[] = "82C925"; +static const char pci_device_1004_0304[] = "QSound ThunderBird PCI Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0304_1004_0304[] = "QSound ThunderBird PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0304_122d_1206[] = "DSP368 Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0304_1483_5020[] = "XWave Thunder 3D Audio"; +#endif +static const char pci_device_1004_0305[] = "QSound ThunderBird PCI Audio Gameport"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0305_1004_0305[] = "QSound ThunderBird PCI Audio Gameport"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0305_122d_1207[] = "DSP368 Audio Gameport"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0305_1483_5021[] = "XWave Thunder 3D Audio Gameport"; +#endif +static const char pci_device_1004_0306[] = "QSound ThunderBird PCI Audio Support Registers"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0306_1004_0306[] = "QSound ThunderBird PCI Audio Support Registers"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0306_122d_1208[] = "DSP368 Audio Support Registers"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0306_1483_5022[] = "XWave Thunder 3D Audio Support Registers"; +#endif +static const char pci_device_1004_0307[] = "Thunderbird"; +static const char pci_device_1004_0308[] = "Thunderbird"; +static const char pci_device_1004_0702[] = "VAS96011 [Golden Gate II]"; +static const char pci_device_1004_0703[] = "Tollgate"; +#endif +static const char pci_vendor_1005[] = "Avance Logic Inc. [ALI]"; +static const char pci_device_1005_2064[] = "ALG2032/2064"; +static const char pci_device_1005_2128[] = "ALG2364A"; +static const char pci_device_1005_2301[] = "ALG2301"; +static const char pci_device_1005_2302[] = "ALG2302"; +static const char pci_device_1005_2364[] = "ALG2364"; +static const char pci_device_1005_2464[] = "ALG2364A"; +static const char pci_device_1005_2501[] = "ALG2564A/25128A"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1006[] = "Reply Group"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1007[] = "NetFrame Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1008[] = "Epson"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_100a[] = "Phoenix Technologies"; +#endif +static const char pci_vendor_100b[] = "National Semiconductor Corporation"; +static const char pci_device_100b_0001[] = "DP83810"; +static const char pci_device_100b_0002[] = "87415/87560 IDE"; +static const char pci_device_100b_000e[] = "87560 Legacy I/O"; +static const char pci_device_100b_000f[] = "FireWire Controller"; +static const char pci_device_100b_0011[] = "NS87560 National PCI System I/O"; +static const char pci_device_100b_0012[] = "USB Controller"; +static const char pci_device_100b_0020[] = "DP83815 (MacPhyter) Ethernet Controller"; +static const char pci_device_100b_0022[] = "DP83820 10/100/1000 Ethernet Controller"; +static const char pci_device_100b_0500[] = "SCx200 Bridge"; +static const char pci_device_100b_0501[] = "SCx200 SMI"; +static const char pci_device_100b_0502[] = "SCx200 IDE"; +static const char pci_device_100b_0503[] = "SCx200 Audio"; +static const char pci_device_100b_0504[] = "SCx200 Video"; +static const char pci_device_100b_0505[] = "SCx200 XBus"; +static const char pci_device_100b_d001[] = "87410 IDE"; +static const char pci_vendor_100c[] = "Tseng Labs Inc"; +static const char pci_device_100c_3202[] = "ET4000/W32p rev A"; +static const char pci_device_100c_3205[] = "ET4000/W32p rev B"; +static const char pci_device_100c_3206[] = "ET4000/W32p rev C"; +static const char pci_device_100c_3207[] = "ET4000/W32p rev D"; +static const char pci_device_100c_3208[] = "ET6000"; +static const char pci_device_100c_4702[] = "ET6300"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_100d[] = "AST Research Inc"; +#endif +static const char pci_vendor_100e[] = "Weitek"; +static const char pci_device_100e_9000[] = "P9000 Viper"; +static const char pci_device_100e_9001[] = "P9000 Viper"; +static const char pci_device_100e_9002[] = "P9000 Viper"; +static const char pci_device_100e_9100[] = "P9100 Viper Pro/SE"; +static const char pci_vendor_1010[] = "Video Logic, Ltd."; +static const char pci_vendor_1011[] = "Digital Equipment Corporation"; +static const char pci_device_1011_0001[] = "DECchip 21050"; +static const char pci_device_1011_0002[] = "DECchip 21040 [Tulip]"; +static const char pci_device_1011_0004[] = "DECchip 21030 [TGA]"; +static const char pci_device_1011_0007[] = "NVRAM [Zephyr NVRAM]"; +static const char pci_device_1011_0008[] = "KZPSA [KZPSA]"; +static const char pci_device_1011_0009[] = "DECchip 21140 [FasterNet]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1025_0310[] = "21140 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_10b8_2001[] = "SMC9332BDT EtherPower 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_10b8_2002[] = "SMC9332BVT EtherPower T4 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_10b8_2003[] = "SMC9334BDT EtherPower 10/100 (1-port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1109_2400[] = "ANA-6944A/TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1112_2300[] = "RNS2300 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1112_2320[] = "RNS2320 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1112_2340[] = "RNS2340 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1113_1207[] = "EN-1207-TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1186_1100[] = "DFE-500TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1186_1112[] = "DFE-570TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1186_1140[] = "DFE-660 Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1186_1142[] = "DFE-660 Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_11f6_0503[] = "Freedomline Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1282_9100[] = "AEF-380TXD Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1385_1100[] = "FA310TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_2646_0001[] = "KNE100TX Fast Ethernet"; +#endif +static const char pci_device_1011_000a[] = "21230 Video Codec"; +static const char pci_device_1011_000d[] = "PBXGB [TGA2]"; +static const char pci_device_1011_000f[] = "DEFPA"; +static const char pci_device_1011_0014[] = "DECchip 21041 [Tulip Pass 3]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0014_1186_0100[] = "DE-530+"; +#endif +static const char pci_device_1011_0016[] = "DGLPB [OPPO]"; +static const char pci_device_1011_0019[] = "DECchip 21142/43"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1011_500a[] = "DE500A Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1011_500b[] = "DE500B Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1014_0001[] = "10/100 EtherJet Cardbus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1025_0315[] = "ALN315 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1033_800c[] = "PC-9821-CS01 100BASE-TX Interface Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1033_800d[] = "PC-9821NR-B06 100BASE-TX Interface Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_108d_0016[] = "Rapidfire 2327 10/100 Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_108d_0017[] = "GoCard 2250 Ethernet 10/100 Cardbus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_10b8_2005[] = "SMC8032DT Extreme Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_10b8_8034[] = "SMC8034 Extreme Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_10ef_8169[] = "Cardbus Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1109_2a00[] = "ANA-6911A/TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1109_2b00[] = "ANA-6911A/TXC Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1109_3000[] = "ANA-6922/TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1113_1207[] = "Cheetah Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1113_2220[] = "Cardbus Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_115d_0002[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1179_0203[] = "Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1179_0204[] = "Cardbus Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1186_1100[] = "DFE-500TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1186_1101[] = "DFE-500TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1186_1102[] = "DFE-500TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1259_2800[] = "AT-2800Tx Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1266_0004[] = "Eagle Fast EtherMAX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_12af_0019[] = "NetFlyer Cardbus Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1374_0001[] = "Cardbus Ethernet Card 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1374_0002[] = "Cardbus Ethernet Card 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1374_0007[] = "Cardbus Ethernet Card 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1374_0008[] = "Cardbus Ethernet Card 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1385_2100[] = "FA510"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1395_0001[] = "10/100 Ethernet CardBus PC Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_13d1_ab01[] = "EtherFast 10/100 Cardbus (PCMPC200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_8086_0001[] = "EtherExpress PRO/100 Mobile CardBus 32"; +#endif +static const char pci_device_1011_001a[] = "Farallon PN9000SX"; +static const char pci_device_1011_0021[] = "DECchip 21052"; +static const char pci_device_1011_0022[] = "DECchip 21150"; +static const char pci_device_1011_0023[] = "DECchip 21150"; +static const char pci_device_1011_0024[] = "DECchip 21152"; +static const char pci_device_1011_0025[] = "DECchip 21153"; +static const char pci_device_1011_0026[] = "DECchip 21154"; +static const char pci_device_1011_0034[] = "56k Modem Cardbus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0034_1374_0003[] = "56k Modem Cardbus"; +#endif +static const char pci_device_1011_0045[] = "DECchip 21553"; +static const char pci_device_1011_0046[] = "DECchip 21554"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_0e11_4050[] = "Integrated Smart Array"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_0e11_4051[] = "Integrated Smart Array"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_0e11_4058[] = "Integrated Smart Array"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_103c_10c2[] = "Hewlett-Packard NetRAID-4M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_12d9_000a[] = "VoIP PCI Gateway"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_9005_0365[] = "Adaptec 5400S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_9005_1364[] = "Dell PowerEdge RAID Controller 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_9005_1365[] = "Dell PowerEdge RAID Controller 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_e4bf_1000[] = "CC8-1-BLUES"; +#endif +static const char pci_device_1011_1065[] = "StrongARM DC21285"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_1065_1069_0020[] = "DAC960P / DAC1164P"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1012[] = "Micronics Computers Inc"; +#endif +static const char pci_vendor_1013[] = "Cirrus Logic"; +static const char pci_device_1013_0038[] = "GD 7548"; +static const char pci_device_1013_0040[] = "GD 7555 Flat Panel GUI Accelerator"; +static const char pci_device_1013_004c[] = "GD 7556 Video/Graphics LCD/CRT Ctrlr"; +static const char pci_device_1013_00a0[] = "GD 5430/40 [Alpine]"; +static const char pci_device_1013_00a2[] = "GD 5432 [Alpine]"; +static const char pci_device_1013_00a4[] = "GD 5434-4 [Alpine]"; +static const char pci_device_1013_00a8[] = "GD 5434-8 [Alpine]"; +static const char pci_device_1013_00ac[] = "GD 5436 [Alpine]"; +static const char pci_device_1013_00b0[] = "GD 5440"; +static const char pci_device_1013_00b8[] = "GD 5446"; +static const char pci_device_1013_00bc[] = "GD 5480"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_00bc_1013_00bc[] = "CL-GD5480"; +#endif +static const char pci_device_1013_00d0[] = "GD 5462"; +static const char pci_device_1013_00d2[] = "GD 5462 [Laguna I]"; +static const char pci_device_1013_00d4[] = "GD 5464 [Laguna]"; +static const char pci_device_1013_00d5[] = "GD 5464 BD [Laguna]"; +static const char pci_device_1013_00d6[] = "GD 5465 [Laguna]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_00d6_13ce_8031[] = "Barco Metheus 2 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_00d6_13cf_8031[] = "Barco Metheus 2 Megapixel, Dual Head"; +#endif +static const char pci_device_1013_00e8[] = "GD 5436U"; +static const char pci_device_1013_1100[] = "CL 6729"; +static const char pci_device_1013_1110[] = "PD 6832 PCMCIA/CardBus Ctrlr"; +static const char pci_device_1013_1112[] = "PD 6834 PCMCIA/CardBus Ctrlr"; +static const char pci_device_1013_1113[] = "PD 6833 PCMCIA/CardBus Ctrlr"; +static const char pci_device_1013_1200[] = "GD 7542 [Nordic]"; +static const char pci_device_1013_1202[] = "GD 7543 [Viking]"; +static const char pci_device_1013_1204[] = "GD 7541 [Nordic Light]"; +static const char pci_device_1013_4400[] = "CD 4400"; +static const char pci_device_1013_6001[] = "CS 4610/11 [CrystalClear SoundFusion Audio Accelerator]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6001_1014_1010[] = "CS4610 SoundFusion Audio Accelerator"; +#endif +static const char pci_device_1013_6003[] = "CS 4614/22/24 [CrystalClear SoundFusion Audio Accelerator]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6003_1013_4280[] = "Crystal SoundFusion PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6003_1681_0050[] = "Game Theater XP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6003_1681_a011[] = "Fortissimo III 7.1"; +#endif +static const char pci_device_1013_6004[] = "CS 4614/22/24 [CrystalClear SoundFusion Audio Accelerator]"; +static const char pci_device_1013_6005[] = "Crystal CS4281 PCI Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_1013_4281[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10a8[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10a9[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10aa[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10ab[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10ac[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10ad[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10b4[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_1179_0001[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_14c0_000c[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1014[] = "IBM"; +static const char pci_device_1014_0002[] = "PCI to MCA Bridge"; +static const char pci_device_1014_0005[] = "Alta Lite"; +static const char pci_device_1014_0007[] = "Alta MP"; +static const char pci_device_1014_000a[] = "Fire Coral"; +static const char pci_device_1014_0017[] = "CPU to PCI Bridge"; +static const char pci_device_1014_0018[] = "TR Auto LANstreamer"; +static const char pci_device_1014_001b[] = "GXT-150P"; +static const char pci_device_1014_001c[] = "Carrera"; +static const char pci_device_1014_001d[] = "82G2675"; +static const char pci_device_1014_0020[] = "MCA"; +static const char pci_device_1014_0022[] = "IBM27-82351"; +static const char pci_device_1014_002d[] = "Python"; +static const char pci_device_1014_002e[] = "ServeRAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_002e_1014_002e[] = "ServeRAID-3x"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_002e_1014_022e[] = "ServeRAID-4H"; +#endif +static const char pci_device_1014_0036[] = "Miami"; +static const char pci_device_1014_003a[] = "CPU to PCI Bridge"; +static const char pci_device_1014_003e[] = "16/4 Token ring UTP/STP controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_003e[] = "Token-Ring Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00cd[] = "Token-Ring Adapter + Wake-On-LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00ce[] = "16/4 Token-Ring Adapter 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00cf[] = "16/4 Token-Ring Adapter Special"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00e4[] = "High-Speed 100/16/4 Token-Ring Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00e5[] = "16/4 Token-Ring Adapter 2 + Wake-On-LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_016d[] = "iSeries 2744 Card"; +#endif +static const char pci_device_1014_0045[] = "SSA Adapter"; +static const char pci_device_1014_0046[] = "MPIC interrupt controller"; +static const char pci_device_1014_0047[] = "PCI to PCI Bridge"; +static const char pci_device_1014_0048[] = "PCI to PCI Bridge"; +static const char pci_device_1014_0049[] = "Warhead SCSI Controller"; +static const char pci_device_1014_004e[] = "ATM Controller (14104e00)"; +static const char pci_device_1014_004f[] = "ATM Controller (14104f00)"; +static const char pci_device_1014_0050[] = "ATM Controller (14105000)"; +static const char pci_device_1014_0053[] = "25 MBit ATM Controller"; +static const char pci_device_1014_0057[] = "MPEG PCI Bridge"; +static const char pci_device_1014_005c[] = "i82557B 10/100"; +static const char pci_device_1014_007c[] = "ATM Controller (14107c00)"; +static const char pci_device_1014_007d[] = "3780IDSP [MWave]"; +static const char pci_device_1014_0090[] = "GXT 3000P"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0090_1014_008e[] = "GXT-3000P"; +#endif +static const char pci_device_1014_0095[] = "20H2999 PCI Docking Bridge"; +static const char pci_device_1014_0096[] = "Chukar chipset SCSI controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0096_1014_0097[] = "iSeries 2778 DASD IOA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0096_1014_0098[] = "iSeries 2763 DASD IOA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0096_1014_0099[] = "iSeries 2748 DASD IOA"; +#endif +static const char pci_device_1014_00a5[] = "ATM Controller (1410a500)"; +static const char pci_device_1014_00a6[] = "ATM 155MBPS MM Controller (1410a600)"; +static const char pci_device_1014_00b7[] = "256-bit Graphics Rasterizer [Fire GL1]"; +static const char pci_device_1014_00be[] = "ATM 622MBPS Controller (1410be00)"; +static const char pci_device_1014_00dc[] = "Advanced Systems Management Adapter (ASMA)"; +static const char pci_device_1014_00fc[] = "CPC710 Dual Bridge and Memory Controller (PCI-64)"; +static const char pci_device_1014_0105[] = "CPC710 Dual Bridge and Memory Controller (PCI-32)"; +static const char pci_device_1014_010f[] = "Remote Supervisor Adapter (RSA)"; +static const char pci_device_1014_0142[] = "Yotta Video Compositor Input"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0142_1014_0143[] = "Yotta Input Controller (ytin)"; +#endif +static const char pci_device_1014_0144[] = "Yotta Video Compositor Output"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0144_1014_0145[] = "Yotta Output Controller (ytout)"; +#endif +static const char pci_device_1014_0156[] = "405GP PLB to PCI Bridge"; +static const char pci_device_1014_01a7[] = "PCI-X to PCI-X Bridge"; +static const char pci_device_1014_01bd[] = "ServeRAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_01be[] = "ServeRAID-4M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_01bf[] = "ServeRAID-4L"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_0208[] = "ServeRAID-4Mx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_020e[] = "ServeRAID-4Lx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_022e[] = "ServeRAID-4H"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_0258[] = "ServeRAID-5i"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_0259[] = "ServeRAID-5i"; +#endif +static const char pci_device_1014_0302[] = "XA-32 chipset [Summit]"; +static const char pci_device_1014_ffff[] = "MPIC-2 interrupt controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1015[] = "LSI Logic Corp of Canada"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1016[] = "ICL Personal Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1017[] = "SPEA Software AG"; +static const char pci_device_1017_5343[] = "SPEA 3D Accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1018[] = "Unisys Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1019[] = "Elitegroup Computer Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101a[] = "AT&T GIS (NCR)"; +static const char pci_device_101a_0005[] = "100VG ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101b[] = "Vitesse Semiconductor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101c[] = "Western Digital"; +static const char pci_device_101c_0193[] = "33C193A"; +static const char pci_device_101c_0196[] = "33C196A"; +static const char pci_device_101c_0197[] = "33C197A"; +static const char pci_device_101c_0296[] = "33C296A"; +static const char pci_device_101c_3193[] = "7193"; +static const char pci_device_101c_3197[] = "7197"; +static const char pci_device_101c_3296[] = "33C296A"; +static const char pci_device_101c_4296[] = "34C296"; +static const char pci_device_101c_9710[] = "Pipeline 9710"; +static const char pci_device_101c_9712[] = "Pipeline 9712"; +static const char pci_device_101c_c24a[] = "90C"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101e[] = "American Megatrends Inc."; +static const char pci_device_101e_1960[] = "MegaRAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0471[] = "MegaRAID 471 Enterprise 1600 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0475[] = "MegaRAID 475 Express 500 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0493[] = "MegaRAID 493 Elite 1600 RAID Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_1028_0471[] = "PowerEdge RAID Controller 3/QC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_1028_0475[] = "PowerEdge RAID Controller 3/SC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_1028_0493[] = "PowerEdge RAID Controller 3/DC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_1028_0511[] = "PowerEdge Cost Effective RAID Controller ATA100/4Ch"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_101e_9010[] = "MegaRAID 428 Ultra RAID Controller"; +static const char pci_device_101e_9030[] = "EIDE Controller"; +static const char pci_device_101e_9031[] = "EIDE Controller"; +static const char pci_device_101e_9032[] = "EIDE & SCSI Controller"; +static const char pci_device_101e_9033[] = "SCSI Controller"; +static const char pci_device_101e_9040[] = "Multimedia card"; +static const char pci_device_101e_9060[] = "MegaRAID 434 Ultra GT RAID Controller"; +static const char pci_device_101e_9063[] = "MegaRAC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_9063_101e_0767[] = "Dell Remote Assistant Card 2"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101f[] = "PictureTel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1020[] = "Hitachi Computer Products"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1021[] = "OKI Electric Industry Co. Ltd."; +#endif +static const char pci_vendor_1022[] = "Advanced Micro Devices [AMD]"; +static const char pci_device_1022_1100[] = "K8 NorthBridge"; +static const char pci_device_1022_1101[] = "K8 NorthBridge"; +static const char pci_device_1022_1102[] = "K8 NorthBridge"; +static const char pci_device_1022_1103[] = "K8 NorthBridge"; +static const char pci_device_1022_2000[] = "79c970 [PCnet32 LANCE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1014_2000[] = "NetFinity 10/100 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_104c[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_1064[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_1065[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_106c[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_106e[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_10ea[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1113_1220[] = "EN1220 10/100 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2450[] = "AT-2450 10/100 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2454[] = "AT-2450v4 10Mb Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2700[] = "AT-2700TX 10/100 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2701[] = "AT-2700FX 100Mb Ethernet"; +#endif +static const char pci_device_1022_2001[] = "79c978 [HomePNA]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2001_1092_0a78[] = "Multimedia Home Network Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2001_1668_0299[] = "ActionLink Home Network Adapter"; +#endif +static const char pci_device_1022_2020[] = "53c974 [PCscsi]"; +static const char pci_device_1022_2040[] = "79c974"; +static const char pci_device_1022_3000[] = "ELanSC520 Microcontroller"; +static const char pci_device_1022_7006[] = "AMD-751 [Irongate] System Controller"; +static const char pci_device_1022_7007[] = "AMD-751 [Irongate] AGP Bridge"; +static const char pci_device_1022_700c[] = "AMD-760 MP [IGD4-2P] System Controller"; +static const char pci_device_1022_700d[] = "AMD-760 MP [IGD4-2P] AGP Bridge"; +static const char pci_device_1022_700e[] = "AMD-760 [IGD4-1P] System Controller"; +static const char pci_device_1022_700f[] = "AMD-760 [IGD4-1P] AGP Bridge"; +static const char pci_device_1022_7400[] = "AMD-755 [Cobra] ISA"; +static const char pci_device_1022_7401[] = "AMD-755 [Cobra] IDE"; +static const char pci_device_1022_7403[] = "AMD-755 [Cobra] ACPI"; +static const char pci_device_1022_7404[] = "AMD-755 [Cobra] USB"; +static const char pci_device_1022_7408[] = "AMD-756 [Viper] ISA"; +static const char pci_device_1022_7409[] = "AMD-756 [Viper] IDE"; +static const char pci_device_1022_740b[] = "AMD-756 [Viper] ACPI"; +static const char pci_device_1022_740c[] = "AMD-756 [Viper] USB"; +static const char pci_device_1022_7410[] = "AMD-766 [ViperPlus] ISA"; +static const char pci_device_1022_7411[] = "AMD-766 [ViperPlus] IDE"; +static const char pci_device_1022_7413[] = "AMD-766 [ViperPlus] ACPI"; +static const char pci_device_1022_7414[] = "AMD-766 [ViperPlus] USB"; +static const char pci_device_1022_7440[] = "AMD-768 [Opus] ISA"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7440_1043_8044[] = "A7M-D Mainboard"; +#endif +static const char pci_device_1022_7441[] = "AMD-768 [Opus] IDE"; +static const char pci_device_1022_7443[] = "AMD-768 [Opus] ACPI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7443_1043_8044[] = "A7M-D Mainboard"; +#endif +static const char pci_device_1022_7445[] = "AMD-768 [Opus] Audio"; +static const char pci_device_1022_7446[] = "AMD-768 [Opus] MC97 Modem (Smart Link HAMR5600 compatible)"; +static const char pci_device_1022_7448[] = "AMD-768 [Opus] PCI"; +static const char pci_device_1022_7449[] = "AMD-768 [Opus] USB"; +static const char pci_device_1022_7450[] = "AMD-8131 PCI-X Bridge"; +static const char pci_device_1022_7451[] = "AMD-8131 PCI-X APIC"; +static const char pci_device_1022_7454[] = "AMD-8151 System Controller"; +static const char pci_device_1022_7455[] = "AMD-8151 AGP Bridge"; +static const char pci_device_1022_7460[] = "AMD-8111 PCI"; +static const char pci_device_1022_7461[] = "AMD-8111 USB"; +static const char pci_device_1022_7462[] = "AMD-8111 Ethernet"; +static const char pci_device_1022_7464[] = "AMD-8111 USB"; +static const char pci_device_1022_7468[] = "AMD-8111 LPC"; +static const char pci_device_1022_7469[] = "AMD-8111 IDE"; +static const char pci_device_1022_746a[] = "AMD-8111 SMBus 2.0"; +static const char pci_device_1022_746b[] = "AMD-8111 ACPI"; +static const char pci_device_1022_746d[] = "AMD-8111 AC97 Audio"; +static const char pci_device_1022_746e[] = "AMD-8111 MC97 Modem"; +static const char pci_vendor_1023[] = "Trident Microsystems"; +static const char pci_device_1023_0194[] = "82C194"; +static const char pci_device_1023_2000[] = "4DWave DX"; +static const char pci_device_1023_2001[] = "4DWave NX"; +static const char pci_device_1023_8400[] = "CyberBlade/i7"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8400_1023_8400[] = "CyberBlade i7 AGP"; +#endif +static const char pci_device_1023_8420[] = "CyberBlade/i7d"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8420_0e11_b15a[] = "CyberBlade i7 AGP"; +#endif +static const char pci_device_1023_8500[] = "CyberBlade/i1"; +static const char pci_device_1023_8520[] = "CyberBlade i1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8520_0e11_b16e[] = "CyberBlade i1 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8520_1023_8520[] = "CyberBlade i1 AGP"; +#endif +static const char pci_device_1023_8620[] = "CyberBlade/i1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8620_1014_0502[] = "ThinkPad T30"; +#endif +static const char pci_device_1023_8820[] = "CyberBlade XPAi1"; +static const char pci_device_1023_9320[] = "TGUI 9320"; +static const char pci_device_1023_9350[] = "GUI Accelerator"; +static const char pci_device_1023_9360[] = "Flat panel GUI Accelerator"; +static const char pci_device_1023_9382[] = "Cyber 9382 [Reference design]"; +static const char pci_device_1023_9383[] = "Cyber 9383 [Reference design]"; +static const char pci_device_1023_9385[] = "Cyber 9385 [Reference design]"; +static const char pci_device_1023_9386[] = "Cyber 9386"; +static const char pci_device_1023_9388[] = "Cyber 9388"; +static const char pci_device_1023_9397[] = "Cyber 9397"; +static const char pci_device_1023_939a[] = "Cyber 9397DVD"; +static const char pci_device_1023_9420[] = "TGUI 9420"; +static const char pci_device_1023_9430[] = "TGUI 9430"; +static const char pci_device_1023_9440[] = "TGUI 9440"; +static const char pci_device_1023_9460[] = "TGUI 9460"; +static const char pci_device_1023_9470[] = "TGUI 9470"; +static const char pci_device_1023_9520[] = "Cyber 9520"; +static const char pci_device_1023_9525[] = "Cyber 9525"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_9525_10cf_1094[] = "Lifebook C6155"; +#endif +static const char pci_device_1023_9540[] = "Cyber 9540"; +static const char pci_device_1023_9660[] = "TGUI 9660/938x/968x"; +static const char pci_device_1023_9680[] = "TGUI 9680"; +static const char pci_device_1023_9682[] = "TGUI 9682"; +static const char pci_device_1023_9683[] = "TGUI 9683"; +static const char pci_device_1023_9685[] = "ProVIDIA 9685"; +static const char pci_device_1023_9750[] = "3DImage 9750"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_9750_1014_9750[] = "3DImage 9750"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_9750_1023_9750[] = "3DImage 9750"; +#endif +static const char pci_device_1023_9753[] = "TGUI 9753"; +static const char pci_device_1023_9754[] = "TGUI 9754"; +static const char pci_device_1023_9759[] = "TGUI 975"; +static const char pci_device_1023_9783[] = "TGUI 9783"; +static const char pci_device_1023_9785[] = "TGUI 9785"; +static const char pci_device_1023_9850[] = "3DImage 9850"; +static const char pci_device_1023_9880[] = "Blade 3D PCI/AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_9880_1023_9880[] = "Blade 3D"; +#endif +static const char pci_device_1023_9910[] = "CyberBlade/XP"; +static const char pci_device_1023_9930[] = "CyberBlade/XPm"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1024[] = "Zenith Data Systems"; +#endif +static const char pci_vendor_1025[] = "Acer Incorporated [ALI]"; +static const char pci_device_1025_1435[] = "M1435"; +static const char pci_device_1025_1445[] = "M1445"; +static const char pci_device_1025_1449[] = "M1449"; +static const char pci_device_1025_1451[] = "M1451"; +static const char pci_device_1025_1461[] = "M1461"; +static const char pci_device_1025_1489[] = "M1489"; +static const char pci_device_1025_1511[] = "M1511"; +static const char pci_device_1025_1512[] = "ALI M1512 Aladdin"; +static const char pci_device_1025_1513[] = "M1513"; +static const char pci_device_1025_1521[] = "ALI M1521 Aladdin III CPU Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_1521_10b9_1521[] = "ALI M1521 Aladdin III CPU Bridge"; +#endif +static const char pci_device_1025_1523[] = "ALI M1523 ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_1523_10b9_1523[] = "ALI M1523 ISA Bridge"; +#endif +static const char pci_device_1025_1531[] = "M1531 Northbridge [Aladdin IV/IV+]"; +static const char pci_device_1025_1533[] = "M1533 PCI-to-ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_1533_10b9_1533[] = "ALI M1533 Aladdin IV/V ISA South Bridge"; +#endif +static const char pci_device_1025_1535[] = "M1535 PCI Bridge + Super I/O + FIR"; +static const char pci_device_1025_1541[] = "M1541 Northbridge [Aladdin V]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_1541_10b9_1541[] = "ALI M1541 Aladdin V/V+ AGP+PCI North Bridge"; +#endif +static const char pci_device_1025_1542[] = "M1542 Northbridge [Aladdin V]"; +static const char pci_device_1025_1543[] = "M1543 PCI-to-ISA Bridge + Super I/O + FIR"; +static const char pci_device_1025_1561[] = "M1561 Northbridge [Aladdin 7]"; +static const char pci_device_1025_1621[] = "M1621 Northbridge [Aladdin-Pro II]"; +static const char pci_device_1025_1631[] = "M1631 Northbridge+3D Graphics [Aladdin TNT2]"; +static const char pci_device_1025_1641[] = "M1641 Northbridge [Aladdin-Pro IV]"; +static const char pci_device_1025_1647[] = "M1647 [MaGiK1] PCI North Bridge"; +static const char pci_device_1025_3141[] = "M3141"; +static const char pci_device_1025_3143[] = "M3143"; +static const char pci_device_1025_3145[] = "M3145"; +static const char pci_device_1025_3147[] = "M3147"; +static const char pci_device_1025_3149[] = "M3149"; +static const char pci_device_1025_3151[] = "M3151"; +static const char pci_device_1025_3307[] = "M3307 MPEG-I Video Controller"; +static const char pci_device_1025_3309[] = "M3309 MPEG-II Video w/ Software Audio Decoder"; +static const char pci_device_1025_3321[] = "M3321 MPEG-II Audio/Video Decoder"; +static const char pci_device_1025_5212[] = "M4803"; +static const char pci_device_1025_5215[] = "ALI PCI EIDE Controller"; +static const char pci_device_1025_5217[] = "M5217H"; +static const char pci_device_1025_5219[] = "M5219"; +static const char pci_device_1025_5225[] = "M5225"; +static const char pci_device_1025_5229[] = "M5229"; +static const char pci_device_1025_5235[] = "M5235"; +static const char pci_device_1025_5237[] = "M5237 PCI USB Host Controller"; +static const char pci_device_1025_5240[] = "EIDE Controller"; +static const char pci_device_1025_5241[] = "PCMCIA Bridge"; +static const char pci_device_1025_5242[] = "General Purpose Controller"; +static const char pci_device_1025_5243[] = "PCI to PCI Bridge Controller"; +static const char pci_device_1025_5244[] = "Floppy Disk Controller"; +static const char pci_device_1025_5247[] = "M1541 PCI to PCI Bridge"; +static const char pci_device_1025_5251[] = "M5251 P1394 Controller"; +static const char pci_device_1025_5427[] = "PCI to AGP Bridge"; +static const char pci_device_1025_5451[] = "M5451 PCI AC-Link Controller Audio Device"; +static const char pci_device_1025_5453[] = "M5453 PCI AC-Link Controller Modem Device"; +static const char pci_device_1025_7101[] = "M7101 PCI PMU Power Management Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_7101_10b9_7101[] = "M7101 PCI PMU Power Management Controller"; +#endif +static const char pci_vendor_1028[] = "Dell Computer Corporation"; +static const char pci_device_1028_0001[] = "PowerEdge Expandable RAID Controller 2/Si"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0001_1028_0001[] = "PowerEdge Expandable RAID Controller 2/Si"; +#endif +static const char pci_device_1028_0002[] = "PowerEdge Expandable RAID Controller 3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0002_1028_0002[] = "PowerEdge Expandable RAID Controller 3/Di"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0002_1028_00d1[] = "PowerEdge Expandable RAID Controller 3/Di"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0002_1028_00d9[] = "PowerEdge Expandable RAID Controller 3/Di"; +#endif +static const char pci_device_1028_0003[] = "PowerEdge Expandable RAID Controller 3/Si"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0003_1028_0003[] = "PowerEdge Expandable RAID Controller 3/Si"; +#endif +static const char pci_device_1028_0004[] = "PowerEdge Expandable RAID Controller 3/Si"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0004_1028_00d0[] = "PowerEdge Expandable RAID Controller 3/Si"; +#endif +static const char pci_device_1028_0005[] = "PowerEdge Expandable RAID Controller 3/Di"; +static const char pci_device_1028_0006[] = "PowerEdge Expandable RAID Controller 3/Di"; +static const char pci_device_1028_0007[] = "Remote Assistant Card 3"; +static const char pci_device_1028_0008[] = "PowerEdge Expandable RAID Controller 3/Di"; +static const char pci_device_1028_000a[] = "PowerEdge Expandable RAID Controller 3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_000a_1028_0106[] = "PowerEdge Expandable RAID Controller 3/Di"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_000a_1028_011b[] = "PowerEdge Expandable RAID Controller 3/Di"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_000a_1028_0121[] = "PowerEdge Expandable RAID Controller 3/Di"; +#endif +static const char pci_device_1028_000c[] = "Embedded Systems Management Device 4"; +static const char pci_device_1028_000e[] = "PowerEdge Expandable RAID Controller"; +static const char pci_device_1028_000f[] = "PowerEdge Expandable RAID Controller 4/Di"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1029[] = "Siemens Nixdorf IS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_102a[] = "LSI Logic"; +static const char pci_device_102a_0000[] = "HYDRA"; +static const char pci_device_102a_0010[] = "ASPEN"; +#endif +static const char pci_vendor_102b[] = "Matrox Graphics, Inc."; +static const char pci_device_102b_0010[] = "MGA-I [Impression?]"; +static const char pci_device_102b_0518[] = "MGA-II [Athena]"; +static const char pci_device_102b_0519[] = "MGA 2064W [Millennium]"; +static const char pci_device_102b_051a[] = "MGA 1064SG [Mystique]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_102b_0100[] = "MGA-1064SG Mystique"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_102b_1100[] = "MGA-1084SG Mystique"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_102b_1200[] = "MGA-1084SG Mystique"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_1100_102b[] = "MGA-1084SG Mystique"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_110a_0018[] = "Scenic Pro C5 (D1025)"; +#endif +static const char pci_device_102b_051b[] = "MGA 2164W [Millennium II]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051b_102b_051b[] = "MGA-2164W Millennium II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051b_102b_1100[] = "MGA-2164W Millennium II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051b_102b_1200[] = "MGA-2164W Millennium II"; +#endif +static const char pci_device_102b_051e[] = "MGA 1064SG [Mystique] AGP"; +static const char pci_device_102b_051f[] = "MGA 2164W [Millennium II] AGP"; +static const char pci_device_102b_0520[] = "MGA G200"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_dbc2[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_dbc8[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_dbe2[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_dbe8[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_ff03[] = "Millennium G200 SD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_ff04[] = "Marvel G200"; +#endif +static const char pci_device_102b_0521[] = "MGA G200 AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_1014_ff03[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_48e9[] = "Mystique G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_48f8[] = "Millennium G200 SD AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_4a60[] = "Millennium G200 LE AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_4a64[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_c93c[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_c9b0[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_c9bc[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ca60[] = "Millennium G250 LE AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ca6c[] = "Millennium G250 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbbc[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbc2[] = "Millennium G200 MMS (Dual G200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbc3[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbc8[] = "Millennium G200 MMS (Dual G200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd2[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd3[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd4[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd5[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd8[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd9[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbe2[] = "Millennium G200 MMS (Quad G200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbe3[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbe8[] = "Millennium G200 MMS (Quad G200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf2[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf3[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf4[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf5[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf8[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf9[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_f806[] = "Mystique G200 Video AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ff00[] = "MGA-G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ff02[] = "Mystique G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ff03[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ff04[] = "Marvel G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_110a_0032[] = "MGA-G200 AGP"; +#endif +static const char pci_device_102b_0525[] = "MGA G400 AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_0e11_b16f[] = "MGA-G400 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0328[] = "Millennium G400 16Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0338[] = "Millennium G400 16Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0378[] = "Millennium G400 32Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0541[] = "Millennium G450 Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0542[] = "Millennium G450 Dual Head LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0543[] = "Millennium G450 Single Head LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0641[] = "Millennium G450 32Mb SDRAM Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0642[] = "Millennium G450 32Mb SDRAM Dual Head LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0643[] = "Millennium G450 32Mb SDRAM Single Head LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_07c0[] = "Millennium G450 Dual Head LE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_07c1[] = "Millennium G450 SDR Dual Head LE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0d41[] = "Millennium G450 Dual Head PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0d42[] = "Millennium G450 Dual Head LX PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0e00[] = "Marvel G450 eTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0e01[] = "Marvel G450 eTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0e02[] = "Marvel G450 eTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0e03[] = "Marvel G450 eTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0f80[] = "Millennium G450 Low Profile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0f81[] = "Millennium G450 Low Profile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0f82[] = "Millennium G450 Low Profile DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0f83[] = "Millennium G450 Low Profile DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_19d8[] = "Millennium G400 16Mb SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_19f8[] = "Millennium G400 32Mb SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_2159[] = "Millennium G400 Dual Head 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_2179[] = "Millennium G400 MAX/Dual Head 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_217d[] = "Millennium G400 Dual Head Max"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_23c0[] = "Millennium G450"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_23c1[] = "Millennium G450"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_23c2[] = "Millennium G450 DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_23c3[] = "Millennium G450 DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_2f58[] = "Millennium G400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_2f78[] = "Millennium G400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_3693[] = "Marvel G400 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_5dd0[] = "4Sight II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_5f50[] = "4Sight II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_5f51[] = "4Sight II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_5f52[] = "4Sight II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_9010[] = "Millennium G400 Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1458_0400[] = "GA-G400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1705_0001[] = "Millennium G450 32MB SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1705_0002[] = "Millennium G450 16MB SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1705_0003[] = "Millennium G450 32MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1705_0004[] = "Millennium G450 16MB"; +#endif +static const char pci_device_102b_0527[] = "MGA Parhelia AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0527_102b_0840[] = "Parhelia 128Mb"; +#endif +static const char pci_device_102b_0d10[] = "MGA Ultima/Impression"; +static const char pci_device_102b_1000[] = "MGA G100 [Productiva]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1000_102b_ff01[] = "Productiva G100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1000_102b_ff05[] = "Productiva G100 Multi-Monitor"; +#endif +static const char pci_device_102b_1001[] = "MGA G100 [Productiva] AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_1001[] = "MGA-G100 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff00[] = "MGA-G100 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff01[] = "MGA-G100 Productiva AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff03[] = "Millennium G100 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff04[] = "MGA-G100 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff05[] = "MGA-G100 Productiva AGP Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_110a_001e[] = "MGA-G100 AGP"; +#endif +static const char pci_device_102b_2007[] = "MGA Mistral"; +static const char pci_device_102b_2527[] = "MGA G550 AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2527_102b_0f83[] = "Millennium G550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2527_102b_0f84[] = "Millennium G550 Dual Head DDR 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2527_102b_1e41[] = "Millennium G550"; +#endif +static const char pci_device_102b_4536[] = "VIA Framegrabber"; +static const char pci_device_102b_6573[] = "Shark 10/100 Multiport SwitchNIC"; +static const char pci_vendor_102c[] = "Chips and Technologies"; +static const char pci_device_102c_00b8[] = "F64310"; +static const char pci_device_102c_00c0[] = "F69000 HiQVideo"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_102c_00c0[] = "F69000 HiQVideo"; +#endif +static const char pci_device_102c_00d0[] = "F65545"; +static const char pci_device_102c_00d8[] = "F65545"; +static const char pci_device_102c_00dc[] = "F65548"; +static const char pci_device_102c_00e0[] = "F65550"; +static const char pci_device_102c_00e4[] = "F65554"; +static const char pci_device_102c_00e5[] = "F65555 HiQVPro"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00e5_0e11_b049[] = "Armada 1700 Laptop Display Controller"; +#endif +static const char pci_device_102c_00f0[] = "F68554"; +static const char pci_device_102c_00f4[] = "F68554 HiQVision"; +static const char pci_device_102c_00f5[] = "F68555"; +static const char pci_device_102c_0c30[] = "F69030"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_102d[] = "Wyse Technology Inc."; +static const char pci_device_102d_50dc[] = "3328 Audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_102e[] = "Olivetti Advanced Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_102f[] = "Toshiba America"; +static const char pci_device_102f_0009[] = "r4x00"; +static const char pci_device_102f_0020[] = "ATM Meteor 155"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102f_0020_102f_00f8[] = "ATM Meteor 155"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1030[] = "TMC Research"; +#endif +static const char pci_vendor_1031[] = "Miro Computer Products AG"; +static const char pci_device_1031_5601[] = "DC20 ASIC"; +static const char pci_device_1031_5607[] = "Video I/O & motion JPEG compressor"; +static const char pci_device_1031_5631[] = "Media 3D"; +static const char pci_device_1031_6057[] = "MiroVideo DC10/DC30+"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1032[] = "Compaq"; +#endif +static const char pci_vendor_1033[] = "NEC Corporation"; +static const char pci_device_1033_0001[] = "PCI to 486-like bus Bridge"; +static const char pci_device_1033_0002[] = "PCI to VL98 Bridge"; +static const char pci_device_1033_0003[] = "ATM Controller"; +static const char pci_device_1033_0004[] = "R4000 PCI Bridge"; +static const char pci_device_1033_0005[] = "PCI to 486-like bus Bridge"; +static const char pci_device_1033_0006[] = "PC-9800 Graphic Accelerator"; +static const char pci_device_1033_0007[] = "PCI to UX-Bus Bridge"; +static const char pci_device_1033_0008[] = "PC-9800 Graphic Accelerator"; +static const char pci_device_1033_0009[] = "PCI to PC9800 Core-Graph Bridge"; +static const char pci_device_1033_0016[] = "PCI to VL Bridge"; +static const char pci_device_1033_001a[] = "[Nile II]"; +static const char pci_device_1033_0021[] = "Vrc4373 [Nile I]"; +static const char pci_device_1033_0029[] = "PowerVR PCX1"; +static const char pci_device_1033_002a[] = "PowerVR 3D"; +static const char pci_device_1033_002c[] = "Star Alpha 2"; +static const char pci_device_1033_002d[] = "PCI to C-bus Bridge"; +static const char pci_device_1033_0035[] = "USB"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_1179_0001[] = "USB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_12ee_7000[] = "Root Hub"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_1799_0001[] = "Root Hub"; +#endif +static const char pci_device_1033_003b[] = "PCI to C-bus Bridge"; +static const char pci_device_1033_003e[] = "NAPCCARD Cardbus Controller"; +static const char pci_device_1033_0046[] = "PowerVR PCX2 [midas]"; +static const char pci_device_1033_005a[] = "Vrc5074 [Nile 4]"; +static const char pci_device_1033_0063[] = "Firewarden"; +static const char pci_device_1033_0067[] = "PowerVR Neon 250 Chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0020[] = "PowerVR Neon 250 AGP 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0080[] = "PowerVR Neon 250 AGP 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0088[] = "PowerVR Neon 250 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0090[] = "PowerVR Neon 250 AGP 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0098[] = "PowerVR Neon 250 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_00a0[] = "PowerVR Neon 250 AGP 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_00a8[] = "PowerVR Neon 250 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0120[] = "PowerVR Neon 250 AGP 32Mb"; +#endif +static const char pci_device_1033_0074[] = "56k Voice Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0074_1033_8014[] = "RCV56ACF 56k Voice Modem"; +#endif +static const char pci_device_1033_009b[] = "Vrc5476"; +static const char pci_device_1033_00a6[] = "VRC5477 AC97"; +static const char pci_device_1033_00cd[] = "IEEE 1394 [OrangeLink] Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00cd_12ee_8011[] = "Root hub"; +#endif +static const char pci_device_1033_00e0[] = "USB 2.0"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00e0_12ee_7001[] = "Root hub"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00e0_1799_0002[] = "Root Hub"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1034[] = "Framatome Connectors USA Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1035[] = "Comp. & Comm. Research Lab"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1036[] = "Future Domain Corp."; +static const char pci_device_1036_0000[] = "TMC-18C30 [36C70]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1037[] = "Hitachi Micro Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1038[] = "AMP, Inc"; +#endif +static const char pci_vendor_1039[] = "Silicon Integrated Systems [SiS]"; +static const char pci_device_1039_0001[] = "SiS 530 Virtual PCI-to-PCI bridge (AGP)"; +static const char pci_device_1039_0002[] = "SG86C202"; +static const char pci_device_1039_0006[] = "85C501/2/3"; +static const char pci_device_1039_0008[] = "85C503/5513"; +static const char pci_device_1039_0009[] = "ACPI"; +static const char pci_device_1039_0018[] = "SiS85C503/5513 (LPC Bridge)"; +static const char pci_device_1039_0200[] = "5597/5598/6326 VGA"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0200_1039_0000[] = "SiS5597 SVGA (Shared RAM)"; +#endif +static const char pci_device_1039_0204[] = "82C204"; +static const char pci_device_1039_0205[] = "SG86C205"; +static const char pci_device_1039_0300[] = "SiS300/305 PCI/AGP VGA Display Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0300_107d_2720[] = "Leadtek WinFast VR300"; +#endif +static const char pci_device_1039_0310[] = "SiS315H PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_0315[] = "SiS315 PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_0325[] = "SiS315PRO PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_0330[] = "SiS330 [Xabre] PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_0406[] = "85C501/2"; +static const char pci_device_1039_0496[] = "85C496"; +static const char pci_device_1039_0530[] = "530 Host"; +static const char pci_device_1039_0540[] = "540 Host"; +static const char pci_device_1039_0597[] = "5513C"; +static const char pci_device_1039_0601[] = "85C601"; +static const char pci_device_1039_0620[] = "620 Host"; +static const char pci_device_1039_0630[] = "630 Host"; +static const char pci_device_1039_0633[] = "633 Host"; +static const char pci_device_1039_0635[] = "635 Host"; +static const char pci_device_1039_0645[] = "SiS645 Host & Memory & AGP Controller"; +static const char pci_device_1039_0646[] = "SiS645DX Host & Memory & AGP Controller"; +static const char pci_device_1039_0650[] = "650 Host"; +static const char pci_device_1039_0651[] = "SiS651 Host"; +static const char pci_device_1039_0730[] = "730 Host"; +static const char pci_device_1039_0733[] = "733 Host"; +static const char pci_device_1039_0735[] = "735 Host"; +static const char pci_device_1039_0740[] = "740 Host"; +static const char pci_device_1039_0745[] = "745 Host"; +static const char pci_device_1039_0900[] = "SiS900 10/100 Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0900_1039_0900[] = "SiS900 10/100 Ethernet Adapter"; +#endif +static const char pci_device_1039_0961[] = "SiS961 [MuTIOL Media IO]"; +static const char pci_device_1039_0962[] = "SiS962 [MuTIOL Media IO]"; +static const char pci_device_1039_3602[] = "83C602"; +static const char pci_device_1039_5107[] = "5107"; +static const char pci_device_1039_5300[] = "SiS540 PCI Display Adapter"; +static const char pci_device_1039_5315[] = "SiS550 AGP/VGA VGA Display Adapter"; +static const char pci_device_1039_5401[] = "486 PCI Chipset"; +static const char pci_device_1039_5511[] = "5511/5512"; +static const char pci_device_1039_5513[] = "5513 [IDE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_5513_1019_0970[] = "P6STP-FL motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_5513_1039_5513[] = "SiS5513 EIDE Controller (A,B step)"; +#endif +static const char pci_device_1039_5517[] = "5517"; +static const char pci_device_1039_5571[] = "5571"; +static const char pci_device_1039_5581[] = "5581 Pentium Chipset"; +static const char pci_device_1039_5582[] = "5582"; +static const char pci_device_1039_5591[] = "5591/5592 Host"; +static const char pci_device_1039_5596[] = "5596 Pentium Chipset"; +static const char pci_device_1039_5597[] = "5597 [SiS5582]"; +static const char pci_device_1039_5600[] = "5600 Host"; +static const char pci_device_1039_6204[] = "Video decoder & MPEG interface"; +static const char pci_device_1039_6205[] = "VGA Controller"; +static const char pci_device_1039_6236[] = "6236 3D-AGP"; +static const char pci_device_1039_6300[] = "SiS630 GUI Accelerator+3D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6300_1019_0970[] = "P6STP-FL motherboard"; +#endif +static const char pci_device_1039_6306[] = "SiS530 3D PCI/AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6306_1039_6306[] = "SiS530,620 GUI Accelerator+3D"; +#endif +static const char pci_device_1039_6325[] = "SiS650/651/M650/740 PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_6326[] = "86C326 5598/6326"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1039_6326[] = "SiS6326 GUI Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1092_0a50[] = "SpeedStar A50"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1092_0a70[] = "SpeedStar A70"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1092_4910[] = "SpeedStar A70"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1092_4920[] = "SpeedStar A70"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1569_6326[] = "SiS6326 GUI Accelerator"; +#endif +static const char pci_device_1039_7001[] = "SiS7001 USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7001_1039_7000[] = "Onboard USB Controller"; +#endif +static const char pci_device_1039_7002[] = "SiS7002 USB 2.0"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7002_1509_7002[] = "Onboard USB Controller"; +#endif +static const char pci_device_1039_7007[] = "FireWire Controller"; +static const char pci_device_1039_7012[] = "SiS7012 PCI Audio Accelerator"; +static const char pci_device_1039_7013[] = "Intel 537 [56k Winmodem]"; +static const char pci_device_1039_7016[] = "SiS7016 10/100 Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7016_1039_7016[] = "SiS7016 10/100 Ethernet Adapter"; +#endif +static const char pci_device_1039_7018[] = "SiS PCI Audio Accelerator"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1014_01b6[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1014_01b7[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1019_7018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1025_000e[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1025_0018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1039_7018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1043_800b[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1054_7018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_107d_5330[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_107d_5350[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1170_3209[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1462_400a[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_14a4_2089[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_14cd_2194[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_14ff_1100[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_152d_8808[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1558_1103[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1558_2200[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1563_7018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_15c5_0111[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_270f_a171[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_a0a0_0022[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_103a[] = "Seiko Epson Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_103b[] = "Tatung Co. of America"; +#endif +static const char pci_vendor_103c[] = "Hewlett-Packard Company"; +static const char pci_device_103c_1005[] = "A4977A Visualize EG"; +static const char pci_device_103c_1006[] = "Visualize FX6"; +static const char pci_device_103c_1008[] = "Visualize FX4"; +static const char pci_device_103c_100a[] = "Visualize FX2"; +static const char pci_device_103c_1028[] = "Tach TL Fibre Channel Host Adapter"; +static const char pci_device_103c_1029[] = "Tach XL2 Fibre Channel Host Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1029_107e_000f[] = "Interphase 5560 Fibre Channel Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1029_9004_9210[] = "1Gb/2Gb Family Fibre Channel Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1029_9004_9211[] = "1Gb/2Gb Family Fibre Channel Controller"; +#endif +static const char pci_device_103c_102a[] = "Tach TS Fibre Channel Host Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_102a_107e_000e[] = "Interphase 5540/5541 Fibre Channel Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_102a_9004_9110[] = "1Gb/2Gb Family Fibre Channel Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_102a_9004_9111[] = "1Gb/2Gb Family Fibre Channel Controller"; +#endif +static const char pci_device_103c_1030[] = "J2585A DeskDirect 10/100VG NIC"; +static const char pci_device_103c_1031[] = "J2585B HP 10/100VG PCI LAN Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1031_103c_1040[] = "J2973A DeskDirect 10BaseT NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1031_103c_1041[] = "J2585B DeskDirect 10/100VG NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1031_103c_1042[] = "J2970A DeskDirect 10BaseT/2 NIC"; +#endif +static const char pci_device_103c_1040[] = "J2973A DeskDirect 10BaseT NIC"; +static const char pci_device_103c_1041[] = "J2585B DeskDirect 10/100 NIC"; +static const char pci_device_103c_1042[] = "J2970A DeskDirect 10BaseT/2 NIC"; +static const char pci_device_103c_1048[] = "Diva Serial [GSP] Multiport UART"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1049[] = "Tosca Console"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_104a[] = "Tosca Secondary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_104b[] = "Maestro SP2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1223[] = "Halfdome Console"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1226[] = "Keystone SP2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1227[] = "Powerbar SP2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1282[] = "Everest SP2"; +#endif +static const char pci_device_103c_1064[] = "79C970 PCnet Ethernet Controller"; +static const char pci_device_103c_108b[] = "Visualize FXe"; +static const char pci_device_103c_10c1[] = "NetServer Smart IRQ Router"; +static const char pci_device_103c_10ed[] = "TopTools Remote Control"; +static const char pci_device_103c_1200[] = "82557B 10/100 NIC"; +static const char pci_device_103c_1219[] = "NetServer PCI Hot-Plug Controller"; +static const char pci_device_103c_121a[] = "NetServer SMIC Controller"; +static const char pci_device_103c_121b[] = "NetServer Legacy COM Port Decoder"; +static const char pci_device_103c_121c[] = "NetServer PCI COM Port Decoder"; +static const char pci_device_103c_1229[] = "zx1 System Bus Adapter"; +static const char pci_device_103c_122a[] = "zx1 I/O Controller"; +static const char pci_device_103c_122e[] = "zx1 Local Bus Adapter"; +static const char pci_device_103c_1290[] = "Auxiliary Diva Serial Port"; +static const char pci_device_103c_2910[] = "E2910A PCIBus Exerciser"; +static const char pci_device_103c_2925[] = "E2925A 32 Bit, 33 MHzPCI Exerciser & Analyzer"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_103e[] = "Solliday Engineering"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_103f[] = "Synopsys/Logic Modeling Group"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1040[] = "Accelgraphics Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1041[] = "Computrend"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1042[] = "Micron"; +static const char pci_device_1042_1000[] = "FDC 37C665"; +static const char pci_device_1042_1001[] = "37C922"; +static const char pci_device_1042_3000[] = "Samurai_0"; +static const char pci_device_1042_3010[] = "Samurai_1"; +static const char pci_device_1042_3020[] = "Samurai_IDE"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1043[] = "Asustek Computer, Inc."; +static const char pci_device_1043_0675[] = "ISDNLink P-IN100-ST-D"; +static const char pci_device_1043_4021[] = "v7100 Combo Deluxe [GeForce2 MX + TV tuner]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1044[] = "Distributed Processing Technology"; +static const char pci_device_1044_1012[] = "Domino RAID Engine"; +static const char pci_device_1044_a400[] = "SmartCache/Raid I-IV Controller"; +static const char pci_device_1044_a500[] = "PCI Bridge"; +static const char pci_device_1044_a501[] = "SmartRAID V Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c001[] = "PM1554U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c002[] = "PM1654U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c003[] = "PM1564U3 Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c004[] = "PM1564U3 Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c005[] = "PM1554U2 Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00a[] = "PM2554U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00b[] = "PM2654U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00c[] = "PM2664U3 Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00d[] = "PM2664U3 Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00e[] = "PM2554U2 Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00f[] = "PM2654U2 Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c014[] = "PM3754U2 Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c015[] = "PM3755U2B Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c016[] = "PM3755F Fibre Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c01e[] = "PM3757U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c01f[] = "PM3757U2 Ultra2 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c020[] = "PM3767U3 Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c021[] = "PM3767U3 Ultra3 Quad Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c028[] = "PM2865U3 Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c029[] = "PM2865U3 Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c02a[] = "PM2865F Fibre Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c03c[] = "2000S Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c03d[] = "2000S Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c03e[] = "2000F Fibre Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c046[] = "3000S Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c047[] = "3000S Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c048[] = "3000F Fibre Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c050[] = "5000S Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c051[] = "5000S Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c052[] = "5000F Fibre Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c05a[] = "2400A UDMA Four Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c05b[] = "2400A UDMA Four Channel DAC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c064[] = "3010S Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c065[] = "3010S Ultra3 Four Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c066[] = "3010S Fibre Channel"; +#endif +static const char pci_device_1044_a511[] = "SmartRAID V Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1045[] = "OPTi Inc."; +static const char pci_device_1045_a0f8[] = "82C750 [Vendetta] USB Controller"; +static const char pci_device_1045_c101[] = "92C264"; +static const char pci_device_1045_c178[] = "92C178"; +static const char pci_device_1045_c556[] = "82X556 [Viper]"; +static const char pci_device_1045_c557[] = "82C557 [Viper-M]"; +static const char pci_device_1045_c558[] = "82C558 [Viper-M ISA+IDE]"; +static const char pci_device_1045_c567[] = "82C750 [Vendetta], device 0"; +static const char pci_device_1045_c568[] = "82C750 [Vendetta], device 1"; +static const char pci_device_1045_c569[] = "82C579 [Viper XPress+ Chipset]"; +static const char pci_device_1045_c621[] = "82C621 [Viper-M/N+]"; +static const char pci_device_1045_c700[] = "82C700 [FireStar]"; +static const char pci_device_1045_c701[] = "82C701 [FireStar Plus]"; +static const char pci_device_1045_c814[] = "82C814 [Firebridge 1]"; +static const char pci_device_1045_c822[] = "82C822"; +static const char pci_device_1045_c824[] = "82C824"; +static const char pci_device_1045_c825[] = "82C825 [Firebridge 2]"; +static const char pci_device_1045_c832[] = "82C832"; +static const char pci_device_1045_c861[] = "82C861"; +static const char pci_device_1045_c895[] = "82C895"; +static const char pci_device_1045_c935[] = "EV1935 ECTIVA MachOne PCI Audio"; +static const char pci_device_1045_d568[] = "82C825 [Firebridge 2]"; +static const char pci_device_1045_d721[] = "IDE [FireStar]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1046[] = "IPC Corporation, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1047[] = "Genoa Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1048[] = "Elsa AG"; +static const char pci_device_1048_0d22[] = "Quadro4 900XGL [ELSA GLoria4 900XGL]"; +static const char pci_device_1048_1000[] = "QuickStep 1000"; +static const char pci_device_1048_3000[] = "QuickStep 3000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1049[] = "Fountain Technologies, Inc."; +#endif +static const char pci_vendor_104a[] = "SGS Thomson Microelectronics"; +static const char pci_device_104a_0008[] = "STG 2000X"; +static const char pci_device_104a_0009[] = "STG 1764X"; +static const char pci_device_104a_0010[] = "STG4000 [3D Prophet Kyro Series]"; +static const char pci_device_104a_0210[] = "STPC Atlas ISA Bridge"; +static const char pci_device_104a_0981[] = "DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_104a_1746[] = "STG 1764X"; +static const char pci_device_104a_2774[] = "DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_104a_3520[] = "MPEG-II decoder card"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_104b[] = "BusLogic"; +static const char pci_device_104b_0140[] = "BT-946C (old) [multimaster 01]"; +static const char pci_device_104b_1040[] = "BT-946C (BA80C30) [MultiMaster 10]"; +static const char pci_device_104b_8130[] = "Flashpoint LT"; +#endif +static const char pci_vendor_104c[] = "Texas Instruments"; +static const char pci_device_104c_0500[] = "100 MBit LAN Controller"; +static const char pci_device_104c_0508[] = "TMS380C2X Compressor Interface"; +static const char pci_device_104c_1000[] = "Eagle i/f AS"; +static const char pci_device_104c_104c[] = "PCI1510 PC card Cardbus Controller"; +static const char pci_device_104c_3d04[] = "TVP4010 [Permedia]"; +static const char pci_device_104c_3d07[] = "TVP4020 [Permedia 2]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1011_4d10[] = "Comet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1040_000f[] = "AccelStar II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1040_0011[] = "AccelStar II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a31[] = "WINNER 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a32[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a35[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_107d_2633[] = "WinFast 3D L2300"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0127[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0136[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0141[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0146[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0148[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0149[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0152[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0154[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0155[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0156[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0157[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1097_3d01[] = "Jeronimo Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1102_100f[] = "Graphics Blaster Extreme"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_3d3d_0100[] = "Reference Permedia 2 3D"; +#endif +static const char pci_device_104c_8000[] = "PCILynx/PCILynx2 IEEE 1394 Link Layer Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8000_e4bf_1010[] = "CF1-1-SNARE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8000_e4bf_1020[] = "CF1-2-SNARE"; +#endif +static const char pci_device_104c_8009[] = "FireWire Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8009_104d_8032[] = "8032 OHCI i.LINK (IEEE 1394) Controller"; +#endif +static const char pci_device_104c_8017[] = "PCI4410 FireWire Controller"; +static const char pci_device_104c_8019[] = "TSB12LV23 IEEE-1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8019_11bd_000a[] = "Studio DV500-1394"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8019_11bd_000e[] = "Studio DV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8019_e4bf_1010[] = "CF2-1-CYMBAL"; +#endif +static const char pci_device_104c_8020[] = "TSB12LV26 IEEE-1394 Controller (Link)"; +static const char pci_device_104c_8021[] = "TSB43AA22 IEEE-1394 Controller (PHY/Link Integrated)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8021_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8021_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +static const char pci_device_104c_8022[] = "TSB43AB22 IEEE-1394a-2000 Controller (PHY/Link)"; +static const char pci_device_104c_8023[] = "TSB43AB22/A IEEE-1394a-2000 Controller (PHY/Link)"; +static const char pci_device_104c_8024[] = "TSB43AB23 IEEE-1394a-2000 Controller (PHY/Link)"; +static const char pci_device_104c_8026[] = "TSB43AB21 IEEE-1394a-2000 Controller (PHY/Link)"; +static const char pci_device_104c_8027[] = "PCI4451 IEEE-1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8027_1028_00e6[] = "PCI4451 IEEE-1394 Controller (Dell Inspiron 8100)"; +#endif +static const char pci_device_104c_8400[] = "ACX 100 22Mbps Wireless Interface"; +static const char pci_device_104c_a001[] = "TDC1570"; +static const char pci_device_104c_a100[] = "TDC1561"; +static const char pci_device_104c_a102[] = "TNETA1575 HyperSAR Plus w/PCI Host i/f & UTOPIA i/f"; +static const char pci_device_104c_a106[] = "TMS320C6205"; +static const char pci_device_104c_ac10[] = "PCI1050"; +static const char pci_device_104c_ac11[] = "PCI1053"; +static const char pci_device_104c_ac12[] = "PCI1130"; +static const char pci_device_104c_ac13[] = "PCI1031"; +static const char pci_device_104c_ac15[] = "PCI1131"; +static const char pci_device_104c_ac16[] = "PCI1250"; +static const char pci_device_104c_ac17[] = "PCI1220"; +static const char pci_device_104c_ac18[] = "PCI1260"; +static const char pci_device_104c_ac19[] = "PCI1221"; +static const char pci_device_104c_ac1a[] = "PCI1210"; +static const char pci_device_104c_ac1b[] = "PCI1450"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac1b_0e11_b113[] = "Armada M700"; +#endif +static const char pci_device_104c_ac1c[] = "PCI1225"; +static const char pci_device_104c_ac1d[] = "PCI1251A"; +static const char pci_device_104c_ac1e[] = "PCI1211"; +static const char pci_device_104c_ac1f[] = "PCI1251B"; +static const char pci_device_104c_ac20[] = "TI 2030"; +static const char pci_device_104c_ac21[] = "PCI2031"; +static const char pci_device_104c_ac22[] = "PCI2032 PCI Docking Bridge"; +static const char pci_device_104c_ac23[] = "PCI2250 PCI-to-PCI Bridge"; +static const char pci_device_104c_ac28[] = "PCI2050 PCI-to-PCI Bridge"; +static const char pci_device_104c_ac30[] = "PCI1260 PC card Cardbus Controller"; +static const char pci_device_104c_ac40[] = "PCI4450 PC card Cardbus Controller"; +static const char pci_device_104c_ac41[] = "PCI4410 PC card Cardbus Controller"; +static const char pci_device_104c_ac42[] = "PCI4451 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac42_1028_00e6[] = "PCI4451 PC card CardBus Controller (Dell Inspiron 8100)"; +#endif +static const char pci_device_104c_ac50[] = "PCI1410 PC card Cardbus Controller"; +static const char pci_device_104c_ac51[] = "PCI1420"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_1014_023b[] = "ThinkPad T23 (2647-4MG)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_10cf_1095[] = "Lifebook C6155"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_e4bf_1000[] = "CP2-2-HIPHOP"; +#endif +static const char pci_device_104c_ac52[] = "PCI1451 PC card Cardbus Controller"; +static const char pci_device_104c_ac53[] = "PCI1421 PC card Cardbus Controller"; +static const char pci_device_104c_ac55[] = "PCI1250 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac55_1014_0512[] = "ThinkPad T30"; +#endif +static const char pci_device_104c_ac56[] = "PCI1510 PC card Cardbus Controller"; +static const char pci_device_104c_ac60[] = "PCI2040 PCI to DSP Bridge Controller"; +static const char pci_device_104c_fe00[] = "FireWire Host Controller"; +static const char pci_device_104c_fe03[] = "12C01A FireWire Host Controller"; +static const char pci_vendor_104d[] = "Sony Corporation"; +static const char pci_device_104d_8009[] = "CXD1947Q i.LINK Controller"; +static const char pci_device_104d_8039[] = "CXD3222 i.LINK Controller"; +static const char pci_device_104d_8056[] = "Rockwell HCF 56K modem"; +static const char pci_device_104d_808a[] = "Memory Stick Controller"; +static const char pci_vendor_104e[] = "Oak Technology, Inc"; +static const char pci_device_104e_0017[] = "OTI-64017"; +static const char pci_device_104e_0107[] = "OTI-107 [Spitfire]"; +static const char pci_device_104e_0109[] = "Video Adapter"; +static const char pci_device_104e_0111[] = "OTI-64111 [Spitfire]"; +static const char pci_device_104e_0217[] = "OTI-64217"; +static const char pci_device_104e_0317[] = "OTI-64317"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_104f[] = "Co-time Computer Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1050[] = "Winbond Electronics Corp"; +static const char pci_device_1050_0000[] = "NE2000"; +static const char pci_device_1050_0001[] = "W83769F"; +static const char pci_device_1050_0105[] = "W82C105"; +static const char pci_device_1050_0840[] = "W89C840"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_0840_1050_0001[] = "W89C840 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_0840_1050_0840[] = "W89C840 Ethernet Adapter"; +#endif +static const char pci_device_1050_0940[] = "W89C940"; +static const char pci_device_1050_5a5a[] = "W89C940F"; +static const char pci_device_1050_6692[] = "W6692"; +static const char pci_device_1050_9970[] = "W9970CF"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1051[] = "Anigma, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1052[] = "?Young Micro Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1053[] = "Young Micro Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1054[] = "Hitachi, Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1055[] = "Efar Microsystems"; +static const char pci_device_1055_9130[] = "SLC90E66 [Victory66] IDE"; +static const char pci_device_1055_9460[] = "SLC90E66 [Victory66] ISA"; +static const char pci_device_1055_9462[] = "SLC90E66 [Victory66] USB"; +static const char pci_device_1055_9463[] = "SLC90E66 [Victory66] ACPI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1056[] = "ICL"; +#endif +static const char pci_vendor_1057[] = "Motorola"; +static const char pci_device_1057_0001[] = "MPC105 [Eagle]"; +static const char pci_device_1057_0002[] = "MPC106 [Grackle]"; +static const char pci_device_1057_0003[] = "MPC8240 [Kahlua]"; +static const char pci_device_1057_0004[] = "MPC107"; +static const char pci_device_1057_0006[] = "MPC8245 [Unity]"; +static const char pci_device_1057_0100[] = "MC145575 [HFC-PCI]"; +static const char pci_device_1057_0431[] = "KTI829c 100VG"; +static const char pci_device_1057_1801[] = "Audio I/O Controller (MIDI)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0030[] = "Layla"; +#endif +static const char pci_device_1057_18c0[] = "MPC8265A/MPC8266"; +static const char pci_device_1057_4801[] = "Raven"; +static const char pci_device_1057_4802[] = "Falcon"; +static const char pci_device_1057_4803[] = "Hawk"; +static const char pci_device_1057_4806[] = "CPX8216"; +static const char pci_device_1057_4d68[] = "20268"; +static const char pci_device_1057_5600[] = "SM56 PCI Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1057_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1057_0301[] = "SM56 PCI Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1057_0302[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1057_5600[] = "SM56 PCI Voice modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_13d2_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_13d2_0301[] = "SM56 PCI Voice modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_13d2_0302[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1436_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1436_0301[] = "SM56 PCI Voice modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1436_0302[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_144f_100c[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1494_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1494_0301[] = "SM56 PCI Voice modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_14c8_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_14c8_0302[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1668_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1668_0302[] = "SM56 PCI Fax Modem"; +#endif +static const char pci_device_1057_6400[] = "MPC190 Security Processor (S1 family, encryption)"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1058[] = "Electronics & Telecommunications RSH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1059[] = "Teknor Industrial Computers Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105a[] = "Promise Technology, Inc."; +static const char pci_device_105a_0d30[] = "20265"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_0d30_105a_4d33[] = "Ultra100"; +#endif +static const char pci_device_105a_0d38[] = "20263"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_0d38_105a_4d39[] = "Fasttrak66"; +#endif +static const char pci_device_105a_1275[] = "20275"; +static const char pci_device_105a_3376[] = "PDC20376"; +static const char pci_device_105a_4d30[] = "20267"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d30_105a_4d33[] = "Ultra100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d30_105a_4d39[] = "Fasttrak100"; +#endif +static const char pci_device_105a_4d33[] = "20246"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d33_105a_4d33[] = "20246 IDE Controller"; +#endif +static const char pci_device_105a_4d38[] = "20262"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d38_105a_4d30[] = "Ultra Device on SuperTrak"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d38_105a_4d33[] = "Ultra66"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d38_105a_4d39[] = "Fasttrak66"; +#endif +static const char pci_device_105a_4d68[] = "20268"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d68_105a_4d68[] = "Ultra100TX2"; +#endif +static const char pci_device_105a_4d69[] = "20269"; +static const char pci_device_105a_5275[] = "PDC20276 IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_5275_105a_0275[] = "SuperTrak SX6000 IDE"; +#endif +static const char pci_device_105a_5300[] = "DC5300"; +static const char pci_device_105a_6268[] = "20268R"; +static const char pci_device_105a_6269[] = "PDC20271"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_6269_105a_6269[] = "FastTrak TX2/TX2000"; +#endif +static const char pci_device_105a_6621[] = "PDC20621 [SX4000] 4 Channel IDE RAID Controller"; +static const char pci_device_105a_7275[] = "PDC20277"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105b[] = "Foxconn International, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105c[] = "Wipro Infotech Limited"; +#endif +static const char pci_vendor_105d[] = "Number 9 Computer Company"; +static const char pci_device_105d_2309[] = "Imagine 128"; +static const char pci_device_105d_2339[] = "Imagine 128-II"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0000[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0001[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0002[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0003[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0004[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0005[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0006[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0007[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0008[] = "Imagine 128 series 2e 4Mb DRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0009[] = "Imagine 128 series 2e 4Mb DRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_000a[] = "Imagine 128 series 2 8Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_000b[] = "Imagine 128 series 2 8Mb H-VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_11a4_000a[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0000[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0004[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0005[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0006[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0008[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0009[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_000a[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_000c[] = "Barco Metheus 5 Megapixel"; +#endif +static const char pci_device_105d_493d[] = "Imagine 128 T2R [Ticket to Ride]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_11a4_000a[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_11a4_000b[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0002[] = "Barco Metheus 4 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0003[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0007[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0008[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0009[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_000a[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +static const char pci_device_105d_5348[] = "Revolution 4"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105e[] = "Vtech Computers Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105f[] = "Infotronic America Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1060[] = "United Microelectronics [UMC]"; +static const char pci_device_1060_0001[] = "UM82C881"; +static const char pci_device_1060_0002[] = "UM82C886"; +static const char pci_device_1060_0101[] = "UM8673F"; +static const char pci_device_1060_0881[] = "UM8881"; +static const char pci_device_1060_0886[] = "UM8886F"; +static const char pci_device_1060_0891[] = "UM8891A"; +static const char pci_device_1060_1001[] = "UM886A"; +static const char pci_device_1060_673a[] = "UM8886BF"; +static const char pci_device_1060_673b[] = "EIDE Master/DMA"; +static const char pci_device_1060_8710[] = "UM8710"; +static const char pci_device_1060_886a[] = "UM8886A"; +static const char pci_device_1060_8881[] = "UM8881F"; +static const char pci_device_1060_8886[] = "UM8886F"; +static const char pci_device_1060_888a[] = "UM8886A"; +static const char pci_device_1060_8891[] = "UM8891A"; +static const char pci_device_1060_9017[] = "UM9017F"; +static const char pci_device_1060_9018[] = "UM9018"; +static const char pci_device_1060_9026[] = "UM9026"; +static const char pci_device_1060_e881[] = "UM8881N"; +static const char pci_device_1060_e886[] = "UM8886N"; +static const char pci_device_1060_e88a[] = "UM8886N"; +static const char pci_device_1060_e891[] = "UM8891N"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1061[] = "I.I.T."; +static const char pci_device_1061_0001[] = "AGX016"; +static const char pci_device_1061_0002[] = "IIT3204/3501"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1062[] = "Maspar Computer Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1063[] = "Ocean Office Automation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1064[] = "Alcatel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1065[] = "Texas Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1066[] = "PicoPower Technology"; +static const char pci_device_1066_0000[] = "PT80C826"; +static const char pci_device_1066_0001[] = "PT86C521 [Vesuvius v1] Host Bridge"; +static const char pci_device_1066_0002[] = "PT86C523 [Vesuvius v3] PCI-ISA Bridge Master"; +static const char pci_device_1066_0003[] = "PT86C524 [Nile] PCI-to-PCI Bridge"; +static const char pci_device_1066_0004[] = "PT86C525 [Nile-II] PCI-to-PCI Bridge"; +static const char pci_device_1066_0005[] = "National PC87550 System Controller"; +static const char pci_device_1066_8002[] = "PT86C523 [Vesuvius v3] PCI-ISA Bridge Slave"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1067[] = "Mitsubishi Electric"; +static const char pci_device_1067_1002[] = "VG500 [VolumePro Volume Rendering Accelerator]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1068[] = "Diversified Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1069[] = "Mylex Corporation"; +static const char pci_device_1069_0001[] = "DAC960P"; +static const char pci_device_1069_0002[] = "DAC960PD"; +static const char pci_device_1069_0010[] = "DAC960PX"; +static const char pci_device_1069_0050[] = "AcceleRAID 352/170/160 support Device"; +static const char pci_device_1069_ba55[] = "eXtremeRAID 1100 support Device"; +static const char pci_device_1069_ba56[] = "eXtremeRAID 2000/3000 support Device"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106a[] = "Aten Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106b[] = "Apple Computer Inc."; +static const char pci_device_106b_0001[] = "Bandit PowerPC host bridge"; +static const char pci_device_106b_0002[] = "Grand Central I/O"; +static const char pci_device_106b_0003[] = "Control Video"; +static const char pci_device_106b_0004[] = "PlanB Video-In"; +static const char pci_device_106b_0007[] = "O'Hare I/O"; +static const char pci_device_106b_000e[] = "Hydra Mac I/O"; +static const char pci_device_106b_0010[] = "Heathrow Mac I/O"; +static const char pci_device_106b_0017[] = "Paddington Mac I/O"; +static const char pci_device_106b_0018[] = "UniNorth FireWire"; +static const char pci_device_106b_0019[] = "KeyLargo USB"; +static const char pci_device_106b_001e[] = "UniNorth Internal PCI"; +static const char pci_device_106b_001f[] = "UniNorth PCI"; +static const char pci_device_106b_0020[] = "UniNorth AGP"; +static const char pci_device_106b_0021[] = "UniNorth GMAC (Sun GEM)"; +static const char pci_device_106b_0022[] = "KeyLargo Mac I/O"; +static const char pci_device_106b_0024[] = "UniNorth/Pangea GMAC (Sun GEM)"; +static const char pci_device_106b_0025[] = "KeyLargo/Pangea Mac I/O"; +static const char pci_device_106b_0026[] = "KeyLargo/Pangea USB"; +static const char pci_device_106b_0027[] = "UniNorth/Pangea AGP"; +static const char pci_device_106b_0028[] = "UniNorth/Pangea PCI"; +static const char pci_device_106b_0029[] = "UniNorth/Pangea Internal PCI"; +static const char pci_device_106b_002d[] = "UniNorth 1.5 AGP"; +static const char pci_device_106b_002e[] = "UniNorth 1.5 PCI"; +static const char pci_device_106b_002f[] = "UniNorth 1.5 Internal PCI"; +static const char pci_device_106b_0030[] = "UniNorth/Pangea FireWire"; +static const char pci_device_106b_0031[] = "UniNorth 2 FireWire"; +static const char pci_device_106b_0032[] = "UniNorth 2 GMAC (Sun GEM)"; +static const char pci_device_106b_0033[] = "UniNorth 2 ATA/100"; +static const char pci_device_106b_0034[] = "UniNorth 2 AGP"; +static const char pci_device_106b_1645[] = "Tigon3 Gigabit Ethernet NIC (BCM5701)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106c[] = "Hyundai Electronics America"; +static const char pci_device_106c_8801[] = "Dual Pentium ISA/PCI Motherboard"; +static const char pci_device_106c_8802[] = "PowerPC ISA/PCI Motherboard"; +static const char pci_device_106c_8803[] = "Dual Window Graphics Accelerator"; +static const char pci_device_106c_8804[] = "LAN Controller"; +static const char pci_device_106c_8805[] = "100-BaseT LAN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106d[] = "Sequent Computer Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106e[] = "DFI, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106f[] = "City Gate Development Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1070[] = "Daewoo Telecom Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1071[] = "Mitac"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1072[] = "GIT Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1073[] = "Yamaha Corporation"; +static const char pci_device_1073_0001[] = "3D GUI Accelerator"; +static const char pci_device_1073_0002[] = "YGV615 [RPA3 3D-Graphics Controller]"; +static const char pci_device_1073_0003[] = "YMF-740"; +static const char pci_device_1073_0004[] = "YMF-724"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0004_1073_0004[] = "YMF724-Based PCI Audio Adapter"; +#endif +static const char pci_device_1073_0005[] = "DS1 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0005_1073_0005[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_0006[] = "DS1 Audio"; +static const char pci_device_1073_0008[] = "DS1 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0008_1073_0008[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_000a[] = "DS1L Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_000a_1073_0004[] = "DS-XG PCI Audio CODEC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_000a_1073_000a[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_000c[] = "YMF-740C [DS-1L Audio Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_000c_107a_000c[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_000d[] = "YMF-724F [DS-1 Audio Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_000d_1073_000d[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_0010[] = "YMF-744B [DS-1S Audio Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0010_1073_0006[] = "DS-XG PCI Audio CODEC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0010_1073_0010[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_0012[] = "YMF-754 [DS-1E Audio Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0012_1073_0012[] = "DS-XG PCI Audio Codec"; +#endif +static const char pci_device_1073_0020[] = "DS-1 Audio"; +static const char pci_device_1073_2000[] = "DS2416 Digital Mixing Card"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_2000_1073_2000[] = "DS2416 Digital Mixing Card"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1074[] = "NexGen Microsystems"; +static const char pci_device_1074_4e78[] = "82c500/1"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1075[] = "Advanced Integrations Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1076[] = "Chaintech Computer Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1077[] = "QLogic Corp."; +static const char pci_device_1077_1016[] = "ISP10160 Single Channel Ultra3 SCSI Processor"; +static const char pci_device_1077_1020[] = "ISP1020 Fast-wide SCSI"; +static const char pci_device_1077_1022[] = "ISP1022 Fast-wide SCSI"; +static const char pci_device_1077_1080[] = "ISP1080 SCSI Host Adapter"; +static const char pci_device_1077_1216[] = "ISP12160 Dual Channel Ultra3 SCSI Processor"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1077_1216_101e_8471[] = "QLA12160 on AMI MegaRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1077_1216_101e_8493[] = "QLA12160 on AMI MegaRAID"; +#endif +static const char pci_device_1077_1240[] = "ISP1240 SCSI Host Adapter"; +static const char pci_device_1077_1280[] = "ISP1280"; +static const char pci_device_1077_2020[] = "ISP2020A Fast!SCSI Basic Adapter"; +static const char pci_device_1077_2100[] = "QLA2100 64-bit Fibre Channel Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1077_2100_1077_0001[] = "QLA2100 64-bit Fibre Channel Adapter"; +#endif +static const char pci_device_1077_2200[] = "QLA2200"; +static const char pci_device_1077_2300[] = "QLA2300 64-bit FC-AL Adapter"; +static const char pci_device_1077_2312[] = "QLA2312 Fibre Channel Adapter"; +#endif +static const char pci_vendor_1078[] = "Cyrix Corporation"; +static const char pci_device_1078_0000[] = "5510 [Grappa]"; +static const char pci_device_1078_0001[] = "PCI Master"; +static const char pci_device_1078_0002[] = "5520 [Cognac]"; +static const char pci_device_1078_0100[] = "5530 Legacy [Kahlua]"; +static const char pci_device_1078_0101[] = "5530 SMI [Kahlua]"; +static const char pci_device_1078_0102[] = "5530 IDE [Kahlua]"; +static const char pci_device_1078_0103[] = "5530 Audio [Kahlua]"; +static const char pci_device_1078_0104[] = "5530 Video [Kahlua]"; +static const char pci_device_1078_0400[] = "ZFMicro PCI Bridge"; +static const char pci_device_1078_0401[] = "ZFMicro Chipset SMI"; +static const char pci_device_1078_0402[] = "ZFMicro Chipset IDE"; +static const char pci_device_1078_0403[] = "ZFMicro Expansion Bus"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1079[] = "I-Bus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107a[] = "NetWorth"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107b[] = "Gateway 2000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107c[] = "LG Electronics [Lucky Goldstar Co. Ltd]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107d[] = "LeadTek Research Inc."; +static const char pci_device_107d_0000[] = "P86C850"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107e[] = "Interphase Corporation"; +static const char pci_device_107e_0001[] = "5515 ATM Adapter [Flipper]"; +static const char pci_device_107e_0002[] = "100 VG AnyLan Controller"; +static const char pci_device_107e_0004[] = "5526 Fibre Channel Host Adapter"; +static const char pci_device_107e_0005[] = "x526 Fibre Channel Host Adapter"; +static const char pci_device_107e_0008[] = "5525/5575 ATM Adapter (155 Mbit) [Atlantic]"; +static const char pci_device_107e_9003[] = "5535-4P-BRI-ST"; +static const char pci_device_107e_9007[] = "5535-4P-BRI-U"; +static const char pci_device_107e_9008[] = "5535-1P-SR"; +static const char pci_device_107e_900c[] = "5535-1P-SR-ST"; +static const char pci_device_107e_900e[] = "5535-1P-SR-U"; +static const char pci_device_107e_9011[] = "5535-1P-PRI"; +static const char pci_device_107e_9013[] = "5535-2P-PRI"; +static const char pci_device_107e_9023[] = "5536-4P-BRI-ST"; +static const char pci_device_107e_9027[] = "5536-4P-BRI-U"; +static const char pci_device_107e_9031[] = "5536-1P-PRI"; +static const char pci_device_107e_9033[] = "5536-2P-PRI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107f[] = "Data Technology Corporation"; +static const char pci_device_107f_0802[] = "SL82C105"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1080[] = "Contaq Microsystems"; +static const char pci_device_1080_0600[] = "82C599"; +static const char pci_device_1080_c691[] = "Cypress CY82C691"; +static const char pci_device_1080_c693[] = "82c693"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1081[] = "Supermac Technology"; +static const char pci_device_1081_0d47[] = "Radius PCI to NuBUS Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1082[] = "EFA Corporation of America"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1083[] = "Forex Computer Corporation"; +static const char pci_device_1083_0001[] = "FR710"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1084[] = "Parador"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1085[] = "Tulip Computers Int.B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1086[] = "J. Bond Computer Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1087[] = "Cache Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1088[] = "Microcomputer Systems (M) Son"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1089[] = "Data General Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_108a[] = "SBS Technologies"; +static const char pci_device_108a_0001[] = "VME Bridge Model 617"; +static const char pci_device_108a_0010[] = "VME Bridge Model 618"; +static const char pci_device_108a_0040[] = "dataBLIZZARD"; +static const char pci_device_108a_3000[] = "VME Bridge Model 2706"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_108c[] = "Oakleigh Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_108d[] = "Olicom"; +static const char pci_device_108d_0001[] = "Token-Ring 16/4 PCI Adapter (3136/3137)"; +static const char pci_device_108d_0002[] = "16/4 Token Ring"; +static const char pci_device_108d_0004[] = "RapidFire 3139 Token-Ring 16/4 PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0004_108d_0004[] = "OC-3139/3140 RapidFire Token-Ring 16/4 Adapter"; +#endif +static const char pci_device_108d_0005[] = "GoCard 3250 Token-Ring 16/4 CardBus PC Card"; +static const char pci_device_108d_0006[] = "OC-3530 RapidFire Token-Ring 100"; +static const char pci_device_108d_0007[] = "RapidFire 3141 Token-Ring 16/4 PCI Fiber Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0007_108d_0007[] = "OC-3141 RapidFire Token-Ring 16/4 Adapter"; +#endif +static const char pci_device_108d_0008[] = "RapidFire 3540 HSTR 100/16/4 PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0008_108d_0008[] = "OC-3540 RapidFire HSTR 100/16/4 Adapter"; +#endif +static const char pci_device_108d_0011[] = "OC-2315"; +static const char pci_device_108d_0012[] = "OC-2325"; +static const char pci_device_108d_0013[] = "OC-2183/2185"; +static const char pci_device_108d_0014[] = "OC-2326"; +static const char pci_device_108d_0019[] = "OC-2327/2250 10/100 Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0019_108d_0016[] = "OC-2327 Rapidfire 10/100 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0019_108d_0017[] = "OC-2250 GoCard 10/100 Ethernet Adapter"; +#endif +static const char pci_device_108d_0021[] = "OC-6151/6152 [RapidFire ATM 155]"; +static const char pci_device_108d_0022[] = "ATM Adapter"; +#endif +static const char pci_vendor_108e[] = "Sun Microsystems Computer Corp."; +static const char pci_device_108e_0001[] = "EBUS"; +static const char pci_device_108e_1000[] = "EBUS"; +static const char pci_device_108e_1001[] = "Happy Meal"; +static const char pci_device_108e_1100[] = "RIO EBUS"; +static const char pci_device_108e_1101[] = "RIO GEM"; +static const char pci_device_108e_1102[] = "RIO 1394"; +static const char pci_device_108e_1103[] = "RIO USB"; +static const char pci_device_108e_2bad[] = "GEM"; +static const char pci_device_108e_5000[] = "Simba Advanced PCI Bridge"; +static const char pci_device_108e_5043[] = "SunPCI Co-processor"; +static const char pci_device_108e_8000[] = "Psycho PCI Bus Module"; +static const char pci_device_108e_8001[] = "Schizo PCI Bus Module"; +static const char pci_device_108e_a000[] = "Ultra IIi"; +static const char pci_device_108e_a001[] = "Ultra IIe"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_108f[] = "Systemsoft"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1090[] = "Encore Computer Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1091[] = "Intergraph Corporation"; +static const char pci_device_1091_0020[] = "3D graphics processor"; +static const char pci_device_1091_0021[] = "3D graphics processor w/Texturing"; +static const char pci_device_1091_0040[] = "3D graphics frame buffer"; +static const char pci_device_1091_0041[] = "3D graphics frame buffer"; +static const char pci_device_1091_0060[] = "Proprietary bus bridge"; +static const char pci_device_1091_00e4[] = "Powerstorm 4D50T"; +static const char pci_device_1091_0720[] = "Motion JPEG codec"; +#endif +static const char pci_vendor_1092[] = "Diamond Multimedia Systems"; +static const char pci_device_1092_00a0[] = "Speedstar Pro SE"; +static const char pci_device_1092_00a8[] = "Speedstar 64"; +static const char pci_device_1092_0550[] = "Viper V550"; +static const char pci_device_1092_08d4[] = "Supra 2260 Modem"; +static const char pci_device_1092_094c[] = "SupraExpress 56i Pro"; +static const char pci_device_1092_1092[] = "Viper V330"; +static const char pci_device_1092_6120[] = "Maximum DVD"; +static const char pci_device_1092_8810[] = "Stealth SE"; +static const char pci_device_1092_8811[] = "Stealth 64/SE"; +static const char pci_device_1092_8880[] = "Stealth"; +static const char pci_device_1092_8881[] = "Stealth"; +static const char pci_device_1092_88b0[] = "Stealth 64"; +static const char pci_device_1092_88b1[] = "Stealth 64"; +static const char pci_device_1092_88c0[] = "Stealth 64"; +static const char pci_device_1092_88c1[] = "Stealth 64"; +static const char pci_device_1092_88d0[] = "Stealth 64"; +static const char pci_device_1092_88d1[] = "Stealth 64"; +static const char pci_device_1092_88f0[] = "Stealth 64"; +static const char pci_device_1092_88f1[] = "Stealth 64"; +static const char pci_device_1092_9999[] = "DMD-I0928-1 Monster sound sound chip"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1093[] = "National Instruments"; +static const char pci_device_1093_0160[] = "PCI-DIO-96"; +static const char pci_device_1093_0162[] = "PCI-MIO-16XE-50"; +static const char pci_device_1093_1170[] = "PCI-MIO-16XE-10"; +static const char pci_device_1093_1180[] = "PCI-MIO-16E-1"; +static const char pci_device_1093_1190[] = "PCI-MIO-16E-4"; +static const char pci_device_1093_1330[] = "PCI-6031E"; +static const char pci_device_1093_1350[] = "PCI-6071E"; +static const char pci_device_1093_2a60[] = "PCI-6023E"; +static const char pci_device_1093_b001[] = "IMAQ-PCI-1408"; +static const char pci_device_1093_b011[] = "IMAQ-PXI-1408"; +static const char pci_device_1093_b021[] = "IMAQ-PCI-1424"; +static const char pci_device_1093_b031[] = "IMAQ-PCI-1413"; +static const char pci_device_1093_b041[] = "IMAQ-PCI-1407"; +static const char pci_device_1093_b051[] = "IMAQ-PXI-1407"; +static const char pci_device_1093_b061[] = "IMAQ-PCI-1411"; +static const char pci_device_1093_b071[] = "IMAQ-PCI-1422"; +static const char pci_device_1093_b081[] = "IMAQ-PXI-1422"; +static const char pci_device_1093_b091[] = "IMAQ-PXI-1411"; +static const char pci_device_1093_c801[] = "PCI-GPIB"; +static const char pci_device_1093_c831[] = "PCI-GPIB bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1094[] = "First International Computers [FIC]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1095[] = "CMD Technology Inc"; +static const char pci_device_1095_0640[] = "PCI0640"; +static const char pci_device_1095_0643[] = "PCI0643"; +static const char pci_device_1095_0646[] = "PCI0646"; +static const char pci_device_1095_0647[] = "PCI0647"; +static const char pci_device_1095_0648[] = "PCI0648"; +static const char pci_device_1095_0649[] = "PCI0649"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0649_0e11_005d[] = "Integrated Ultra ATA-100 Dual Channel Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0649_0e11_007e[] = "Integrated Ultra ATA-100 IDE RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0649_101e_0649[] = "AMI MegaRAID IDE 100 Controller"; +#endif +static const char pci_device_1095_0650[] = "PBC0650A"; +static const char pci_device_1095_0670[] = "USB0670"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0670_1095_0670[] = "USB0670"; +#endif +static const char pci_device_1095_0673[] = "USB0673"; +static const char pci_device_1095_0680[] = "PCI0680"; +static const char pci_device_1095_3112[] = "Silicon Image SiI 3112 SATARaid Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1096[] = "Alacron"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1097[] = "Appian Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1098[] = "Quantum Designs (H.K.) Ltd"; +static const char pci_device_1098_0001[] = "QD-8500"; +static const char pci_device_1098_0002[] = "QD-8580"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1099[] = "Samsung Electronics Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109a[] = "Packard Bell"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109b[] = "Gemlight Computer Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109c[] = "Megachips Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109d[] = "Zida Technologies Ltd."; +#endif +static const char pci_vendor_109e[] = "Brooktree Corporation"; +static const char pci_device_109e_0350[] = "Bt848 Video Capture"; +static const char pci_device_109e_0351[] = "Bt849A Video capture"; +static const char pci_device_109e_0369[] = "Bt878 Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0369_1002_0001[] = "TV-Wonder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0369_1002_0003[] = "TV-Wonder/VE"; +#endif +static const char pci_device_109e_036c[] = "Bt879(?) Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036c_13e9_0070[] = "Win/TV (Video Section)"; +#endif +static const char pci_device_109e_036e[] = "Bt878 Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_0070_13eb[] = "WinTV Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_0070_ff01[] = "Viewcast Osprey 200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_107d_6606[] = "WinFast TV 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_11bd_0012[] = "PCTV pro (TV + FM stereo receiver)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_11bd_001c[] = "PCTV Sat (DBC receiver)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_127a_0001[] = "Bt878 Mediastream Controller NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_127a_0002[] = "Bt878 Mediastream Controller PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_127a_0003[] = "Bt878a Mediastream Controller PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_127a_0048[] = "Bt878/832 Mediastream Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_144f_3000[] = "MagicTView CPH060 - Video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1461_0004[] = "AVerTV WDM Video Capture"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_14f1_0001[] = "Bt878 Mediastream Controller NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_14f1_0002[] = "Bt878 Mediastream Controller PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_14f1_0003[] = "Bt878a Mediastream Controller PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_14f1_0048[] = "Bt878/832 Mediastream Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1851_1850[] = "FlyVideo'98 - Video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1851_1851[] = "FlyVideo II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1852_1852[] = "FlyVideo'98 - Video (with FM Tuner)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_bd11_1200[] = "PCTV pro (TV + FM stereo receiver)"; +#endif +static const char pci_device_109e_036f[] = "Bt879 Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0044[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0122[] = "Bt879 Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0144[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0222[] = "Bt879 Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0244[] = "Bt879a Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0322[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0422[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1122[] = "Bt879 Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1222[] = "Bt879 Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1322[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1522[] = "Bt879a Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1622[] = "Bt879a Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1722[] = "Bt879a Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0044[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0122[] = "Bt879 Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0144[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0222[] = "Bt879 Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0244[] = "Bt879a Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0322[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0422[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1122[] = "Bt879 Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1222[] = "Bt879 Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1322[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1522[] = "Bt879a Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1622[] = "Bt879a Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1722[] = "Bt879a Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_1851_1850[] = "FlyVideo'98 - Video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_1851_1851[] = "FlyVideo II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_1852_1852[] = "FlyVideo'98 - Video (with FM Tuner)"; +#endif +static const char pci_device_109e_0370[] = "Bt880 Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0370_1851_1850[] = "FlyVideo'98"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0370_1851_1851[] = "FlyVideo'98 EZ - video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0370_1852_1852[] = "FlyVideo'98 (with FM Tuner)"; +#endif +static const char pci_device_109e_0878[] = "Bt878 Audio Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_0070_13eb[] = "WinTV Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_0070_ff01[] = "Viewcast Osprey 200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1002_0001[] = "TV-Wonder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1002_0003[] = "TV-Wonder/VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_11bd_0012[] = "PCTV pro (TV + FM stereo receiver, audio section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_11bd_001c[] = "PCTV Sat (DBC receiver)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_127a_0001[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_127a_0002[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_127a_0003[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_127a_0048[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_13e9_0070[] = "Win/TV (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_144f_3000[] = "MagicTView CPH060 - Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1461_0004[] = "AVerTV WDM Audio Capture"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_14f1_0001[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_14f1_0002[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_14f1_0003[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_14f1_0048[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_bd11_1200[] = "PCTV pro (TV + FM stereo receiver, audio section)"; +#endif +static const char pci_device_109e_0879[] = "Bt879 Audio Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0044[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0122[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0144[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0222[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0244[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0322[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0422[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1122[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1222[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1322[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1522[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1622[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1722[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0044[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0122[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0144[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0222[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0244[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0322[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0422[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1122[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1222[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1322[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1522[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1622[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1722[] = "Bt879 Video Capture (Audio Section)"; +#endif +static const char pci_device_109e_0880[] = "Bt880 Audio Capture"; +static const char pci_device_109e_2115[] = "BtV 2115 Mediastream controller"; +static const char pci_device_109e_2125[] = "BtV 2125 Mediastream controller"; +static const char pci_device_109e_2164[] = "BtV 2164"; +static const char pci_device_109e_2165[] = "BtV 2165"; +static const char pci_device_109e_8230[] = "Bt8230 ATM Segment/Reassembly Ctrlr (SRC)"; +static const char pci_device_109e_8472[] = "Bt8472"; +static const char pci_device_109e_8474[] = "Bt8474"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109f[] = "Trigem Computer Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a0[] = "Meidensha Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a1[] = "Juko Electronics Ind. Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a2[] = "Quantum Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a3[] = "Everex Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a4[] = "Globe Manufacturing Sales"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a5[] = "Smart Link Ltd."; +static const char pci_device_10a5_5449[] = "SmartPCI561 modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a6[] = "Informtech Industrial Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a7[] = "Benchmarq Microelectronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a8[] = "Sierra Semiconductor"; +static const char pci_device_10a8_0000[] = "STB Horizon 64"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a9[] = "Silicon Graphics, Inc."; +static const char pci_device_10a9_0001[] = "Crosstalk to PCI Bridge"; +static const char pci_device_10a9_0002[] = "Linc I/O controller"; +static const char pci_device_10a9_0003[] = "IOC3 I/O controller"; +static const char pci_device_10a9_0004[] = "O2 MACE"; +static const char pci_device_10a9_0005[] = "RAD Audio"; +static const char pci_device_10a9_0006[] = "HPCEX"; +static const char pci_device_10a9_0007[] = "RPCEX"; +static const char pci_device_10a9_0008[] = "DiVO VIP"; +static const char pci_device_10a9_0009[] = "Alteon Gigabit Ethernet"; +static const char pci_device_10a9_0010[] = "AMP Video I/O"; +static const char pci_device_10a9_0011[] = "GRIP"; +static const char pci_device_10a9_0012[] = "SGH PSHAC GSN"; +static const char pci_device_10a9_1001[] = "Magic Carpet"; +static const char pci_device_10a9_1002[] = "Lithium"; +static const char pci_device_10a9_1003[] = "Dual JPEG 1"; +static const char pci_device_10a9_1004[] = "Dual JPEG 2"; +static const char pci_device_10a9_1005[] = "Dual JPEG 3"; +static const char pci_device_10a9_1006[] = "Dual JPEG 4"; +static const char pci_device_10a9_1007[] = "Dual JPEG 5"; +static const char pci_device_10a9_1008[] = "Cesium"; +static const char pci_device_10a9_2001[] = "Fibre Channel"; +static const char pci_device_10a9_2002[] = "ASDE"; +static const char pci_device_10a9_8001[] = "O2 1394"; +static const char pci_device_10a9_8002[] = "G-net NT"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10aa[] = "ACC Microelectronics"; +static const char pci_device_10aa_0000[] = "ACCM 2188"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ab[] = "Digicom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ac[] = "Honeywell IAC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ad[] = "Symphony Labs"; +static const char pci_device_10ad_0001[] = "W83769F"; +static const char pci_device_10ad_0003[] = "SL82C103"; +static const char pci_device_10ad_0005[] = "SL82C105"; +static const char pci_device_10ad_0103[] = "SL82c103"; +static const char pci_device_10ad_0105[] = "SL82c105"; +static const char pci_device_10ad_0565[] = "W83C553"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ae[] = "Cornerstone Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10af[] = "Micro Computer Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b0[] = "CardExpert Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b1[] = "Cabletron Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b2[] = "Raytheon Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b3[] = "Databook Inc"; +static const char pci_device_10b3_3106[] = "DB87144"; +static const char pci_device_10b3_b106[] = "DB87144"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b4[] = "STB Systems Inc"; +static const char pci_device_10b4_1b1d[] = "Velocity 128 3D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b4_1b1d_10b4_237e[] = "Velocity 4400"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b5[] = "PLX Technology, Inc."; +static const char pci_device_10b5_0001[] = "i960 PCI bus interface"; +static const char pci_device_10b5_1076[] = "VScom 800 8 port serial adaptor"; +static const char pci_device_10b5_1077[] = "VScom 400 4 port serial adaptor"; +static const char pci_device_10b5_1078[] = "VScom 210 2 port serial and 1 port parallel adaptor"; +static const char pci_device_10b5_1103[] = "VScom 200 2 port serial adaptor"; +static const char pci_device_10b5_1146[] = "VScom 010 1 port parallel adaptor"; +static const char pci_device_10b5_1147[] = "VScom 020 2 port parallel adaptor"; +static const char pci_device_10b5_2724[] = "Thales PCSM Security Card"; +static const char pci_device_10b5_9030[] = "PCI <-> IOBus Bridge Hot Swap"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_15ed_1002[] = "MCCS 8-port Serial Hot Swap"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_15ed_1003[] = "MCCS 16-port Serial Hot Swap"; +#endif +static const char pci_device_10b5_9036[] = "9036"; +static const char pci_device_10b5_9050[] = "PCI <-> IOBus Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_2036[] = "SatPak GPS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_2273[] = "SH-ARC SoHard ARCnet card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_9050[] = "MP9050"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0001[] = "RockForce 4 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0002[] = "RockForce 2 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0003[] = "RockForce 6 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0004[] = "RockForce 8 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0010[] = "RockForce2000 4 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0020[] = "RockForce2000 2 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_15ed_1000[] = "Macrolink MCCS 8-port Serial"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_15ed_1001[] = "Macrolink MCCS 16-port Serial"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_15ed_1002[] = "Macrolink MCCS 8-port Serial Hot Swap"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_15ed_1003[] = "Macrolink MCCS 16-port Serial Hot Swap"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_5654_5634[] = "OpenLine4 Telephony Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d531_c002[] = "PCIntelliCAN 2xSJA1000 CAN bus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4006[] = "EX-4006 1P"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4008[] = "EX-4008 1P EPP/ECP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4014[] = "EX-4014 2P"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4018[] = "EX-4018 3P EPP/ECP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4025[] = "EX-4025 1S(16C550) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4027[] = "EX-4027 1S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4028[] = "EX-4028 1S(16C850) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4036[] = "EX-4036 2S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4037[] = "EX-4037 2S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4038[] = "EX-4038 2S(16C850) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4052[] = "EX-4052 1S(16C550) RS-422/485"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4053[] = "EX-4053 2S(16C550) RS-422/485"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4055[] = "EX-4055 4S(16C550) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4058[] = "EX-4055 4S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4065[] = "EX-4065 8S(16C550) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4068[] = "EX-4068 8S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4078[] = "EX-4078 2S(16C552) RS-232+1P"; +#endif +static const char pci_device_10b5_9054[] = "PCI <-> IOBus Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_10b5_2455[] = "Wessex Techology PHIL-PCI"; +#endif +static const char pci_device_10b5_9060[] = "9060"; +static const char pci_device_10b5_906d[] = "9060SD"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_906d_125c_0640[] = "Aries 16000P"; +#endif +static const char pci_device_10b5_906e[] = "9060ES"; +static const char pci_device_10b5_9080[] = "9080"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_10b5_9080[] = "9080 [real subsystem ID not set]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_129d_0002[] = "Aculab PCI Prosidy card"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b6[] = "Madge Networks"; +static const char pci_device_10b6_0001[] = "Smart 16/4 PCI Ringnode"; +static const char pci_device_10b6_0002[] = "Smart 16/4 PCI Ringnode Mk2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0002_10b6_0002[] = "Smart 16/4 PCI Ringnode Mk2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0002_10b6_0006[] = "16/4 CardBus Adapter"; +#endif +static const char pci_device_10b6_0003[] = "Smart 16/4 PCI Ringnode Mk3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0003_0e11_b0fd[] = "Compaq NC4621 PCI, 4/16, WOL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0003_10b6_0003[] = "Smart 16/4 PCI Ringnode Mk3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0003_10b6_0007[] = "Presto PCI Plus Adapter"; +#endif +static const char pci_device_10b6_0004[] = "Smart 16/4 PCI Ringnode Mk1"; +static const char pci_device_10b6_0006[] = "16/4 Cardbus Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0006_10b6_0006[] = "16/4 CardBus Adapter"; +#endif +static const char pci_device_10b6_0007[] = "Presto PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0007_10b6_0007[] = "Presto PCI"; +#endif +static const char pci_device_10b6_0009[] = "Smart 100/16/4 PCI-HS Ringnode"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0009_10b6_0009[] = "Smart 100/16/4 PCI-HS Ringnode"; +#endif +static const char pci_device_10b6_000a[] = "Smart 100/16/4 PCI Ringnode"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_000a_10b6_000a[] = "Smart 100/16/4 PCI Ringnode"; +#endif +static const char pci_device_10b6_000b[] = "16/4 CardBus Adapter Mk2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_000b_10b6_0008[] = "16/4 CardBus Adapter Mk2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_000b_10b6_000b[] = "16/4 Cardbus Adapter Mk2"; +#endif +static const char pci_device_10b6_000c[] = "RapidFire 3140V2 16/4 TR Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_000c_10b6_000c[] = "RapidFire 3140V2 16/4 TR Adapter"; +#endif +static const char pci_device_10b6_1000[] = "Collage 25/155 ATM Client Adapter"; +static const char pci_device_10b6_1001[] = "Collage 155 ATM Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b7[] = "3Com Corporation"; +static const char pci_device_10b7_0001[] = "3c985 1000BaseSX (SX/TX)"; +static const char pci_device_10b7_1006[] = "MINI PCI type 3B Data Fax Modem"; +static const char pci_device_10b7_1007[] = "Mini PCI 56k Winmodem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_1007_10b7_615c[] = "Mini PCI 56K Modem"; +#endif +static const char pci_device_10b7_3390[] = "3c339 TokenLink Velocity"; +static const char pci_device_10b7_3590[] = "3c359 TokenLink Velocity XL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_3590_10b7_3590[] = "TokenLink Velocity XL Adapter (3C359/359B)"; +#endif +static const char pci_device_10b7_4500[] = "3c450 Cyclone/unknown"; +static const char pci_device_10b7_5055[] = "3c555 Laptop Hurricane"; +static const char pci_device_10b7_5057[] = "3c575 [Megahertz] 10/100 LAN CardBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_5057_10b7_5a57[] = "3C575 Megahertz 10/100 LAN Cardbus PC Card"; +#endif +static const char pci_device_10b7_5157[] = "3c575 [Megahertz] 10/100 LAN CardBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_5157_10b7_5b57[] = "3C575 Megahertz 10/100 LAN Cardbus PC Card"; +#endif +static const char pci_device_10b7_5257[] = "3CCFE575CT Cyclone CardBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_5257_10b7_5c57[] = "FE575C-3Com 10/100 LAN CardBus-Fast Ethernet"; +#endif +static const char pci_device_10b7_5900[] = "3c590 10BaseT [Vortex]"; +static const char pci_device_10b7_5920[] = "3c592 EISA 10mbps Demon/Vortex"; +static const char pci_device_10b7_5950[] = "3c595 100BaseTX [Vortex]"; +static const char pci_device_10b7_5951[] = "3c595 100BaseT4 [Vortex]"; +static const char pci_device_10b7_5952[] = "3c595 100Base-MII [Vortex]"; +static const char pci_device_10b7_5970[] = "3c597 EISA Fast Demon/Vortex"; +static const char pci_device_10b7_5b57[] = "3c595 [Megahertz] 10/100 LAN CardBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_5b57_10b7_5b57[] = "3C575 Megahertz 10/100 LAN Cardbus PC Card"; +#endif +static const char pci_device_10b7_6055[] = "3c556 Hurricane CardBus"; +static const char pci_device_10b7_6056[] = "3c556B Hurricane CardBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6056_10b7_6556[] = "10/100 Mini PCI Ethernet Adapter"; +#endif +static const char pci_device_10b7_6560[] = "3CCFE656 Cyclone CardBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6560_10b7_656a[] = "3CCFEM656 10/100 LAN+56K Modem CardBus"; +#endif +static const char pci_device_10b7_6561[] = "3CCFEM656 10/100 LAN+56K Modem CardBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6561_10b7_656b[] = "3CCFEM656 10/100 LAN+56K Modem CardBus"; +#endif +static const char pci_device_10b7_6562[] = "3CCFEM656 [id 6562] Cyclone CardBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6562_10b7_656b[] = "3CCFEM656B 10/100 LAN+56K Modem CardBus"; +#endif +static const char pci_device_10b7_6563[] = "3CCFEM656B 10/100 LAN+56K Modem CardBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6563_10b7_656b[] = "3CCFEM656 10/100 LAN+56K Modem CardBus"; +#endif +static const char pci_device_10b7_6564[] = "3CCFEM656 [id 6564] Cyclone CardBus"; +static const char pci_device_10b7_7646[] = "3cSOHO100-TX Hurricane"; +static const char pci_device_10b7_7940[] = "3c803 FDDILink UTP Controller"; +static const char pci_device_10b7_7980[] = "3c804 FDDILink SAS Controller"; +static const char pci_device_10b7_7990[] = "3c805 FDDILink DAS Controller"; +static const char pci_device_10b7_8811[] = "Token ring"; +static const char pci_device_10b7_9000[] = "3c900 10BaseT [Boomerang]"; +static const char pci_device_10b7_9001[] = "3c900 Combo [Boomerang]"; +static const char pci_device_10b7_9004[] = "3c900B-TPO [Etherlink XL TPO]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9004_10b7_9004[] = "3C900B-TPO Etherlink XL TPO 10Mb"; +#endif +static const char pci_device_10b7_9005[] = "3c900B-Combo [Etherlink XL Combo]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9005_10b7_9005[] = "3C900B-Combo Etherlink XL Combo"; +#endif +static const char pci_device_10b7_9006[] = "3c900B-TPC [Etherlink XL TPC]"; +static const char pci_device_10b7_900a[] = "3c900B-FL [Etherlink XL FL]"; +static const char pci_device_10b7_9050[] = "3c905 100BaseTX [Boomerang]"; +static const char pci_device_10b7_9051[] = "3c905 100BaseT4 [Boomerang]"; +static const char pci_device_10b7_9055[] = "3c905B 100BaseTX [Cyclone]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0080[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0081[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0082[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0083[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0084[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0085[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0086[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0087[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0088[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0089[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0090[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0091[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0092[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0093[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0094[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0095[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0096[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0097[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0098[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0099[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_10b7_9055[] = "3C905B Fast Etherlink XL 10/100"; +#endif +static const char pci_device_10b7_9056[] = "3c905B-T4 [Fast EtherLink XL 10/100]"; +static const char pci_device_10b7_9058[] = "3c905B-Combo [Deluxe Etherlink XL 10/100]"; +static const char pci_device_10b7_905a[] = "3c905B-FX [Fast Etherlink XL FX 10/100]"; +static const char pci_device_10b7_9200[] = "3c905C-TX/TX-M [Tornado]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_1028_0095[] = "Integrated 3C905C-TX Fast Etherlink for PC Management NIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_10b7_1000[] = "3C905C-TX Fast Etherlink for PC Management NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_10b7_7000[] = "10/100 Mini PCI Ethernet Adapter"; +#endif +static const char pci_device_10b7_9201[] = "3C920B-EMB Integrated Fast Ethernet Controller"; +static const char pci_device_10b7_9300[] = "3CSOHO100B-TX [910-A01]"; +static const char pci_device_10b7_9800[] = "3c980-TX [Fast Etherlink XL Server Adapter]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9800_10b7_9800[] = "3c980-TX Fast Etherlink XL Server Adapter"; +#endif +static const char pci_device_10b7_9805[] = "3c980-TX 10/100baseTX NIC [Python-T]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9805_10b7_1201[] = "3c982-TXM 10/100baseTX Dual Port A [Hydra]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9805_10b7_1202[] = "3c982-TXM 10/100baseTX Dual Port B [Hydra]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9805_10b7_9805[] = "3c980 10/100baseTX NIC [Python-T]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9805_10f1_2462[] = "Thunder K7 S2462"; +#endif +static const char pci_device_10b7_9900[] = "3C990-TX [Typhoon]"; +static const char pci_device_10b7_9902[] = "3CR990-TX-95 [Typhoon 56-bit]"; +static const char pci_device_10b7_9903[] = "3CR990-TX-97 [Typhoon 168-bit]"; +static const char pci_device_10b7_9904[] = "3C990B-TX-M/3C990BSVR [Typhoon2]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9904_10b7_1000[] = "3CR990B-TX-M [Typhoon2]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9904_10b7_2000[] = "3CR990BSVR [Typhoon2 Server]"; +#endif +static const char pci_device_10b7_9905[] = "3CR990-FX-95/97/95 [Typhon Fiber]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9905_10b7_1101[] = "3CR990-FX-95 [Typhoon Fiber 56-bit]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9905_10b7_1102[] = "3CR990-FX-97 [Typhoon Fiber 168-bit]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9905_10b7_2101[] = "3CR990-FX-95 Server [Typhoon Fiber 56-bit]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9905_10b7_2102[] = "3CR990-FX-97 Server [Typhoon Fiber 168-bit]"; +#endif +static const char pci_device_10b7_9908[] = "3CR990SVR95 [Typhoon Server 56-bit]"; +static const char pci_device_10b7_9909[] = "3CR990SVR97 [Typhoon Server 168-bit]"; +static const char pci_device_10b7_990b[] = "3C990SVR [Typhoon Server]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b8[] = "Standard Microsystems Corp [SMC]"; +static const char pci_device_10b8_0005[] = "83C170QF"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_1055_e000[] = "LANEPIC 10/100 [EVB171Q-PCI]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_1055_e002[] = "LANEPIC 10/100 [EVB171G-PCI]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a011[] = "EtherPower II 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a014[] = "EtherPower II 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a015[] = "EtherPower II 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a016[] = "EtherPower II 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a017[] = "EtherPower II 10/100"; +#endif +static const char pci_device_10b8_0006[] = "LANEPIC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_1055_e100[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_1055_e102[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_1055_e300[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_1055_e302[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_10b8_a012[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_13a2_8002[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_13a2_8006[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +static const char pci_device_10b8_1000[] = "FDC 37c665"; +static const char pci_device_10b8_1001[] = "FDC 37C922"; +static const char pci_device_10b8_a011[] = "83C170QF"; +static const char pci_device_10b8_b106[] = "SMC34C90"; +#endif +static const char pci_vendor_10b9[] = "ALi Corporation"; +static const char pci_device_10b9_0111[] = "C-Media CMI8738/C3DX Audio Device (OEM)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_0111_10b9_0111[] = "C-Media CMI8738/C3DX Audio Device (OEM)"; +#endif +static const char pci_device_10b9_1435[] = "M1435"; +static const char pci_device_10b9_1445[] = "M1445"; +static const char pci_device_10b9_1449[] = "M1449"; +static const char pci_device_10b9_1451[] = "M1451"; +static const char pci_device_10b9_1461[] = "M1461"; +static const char pci_device_10b9_1489[] = "M1489"; +static const char pci_device_10b9_1511[] = "M1511 [Aladdin]"; +static const char pci_device_10b9_1512[] = "M1512 [Aladdin]"; +static const char pci_device_10b9_1513[] = "M1513 [Aladdin]"; +static const char pci_device_10b9_1521[] = "M1521 [Aladdin III]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1521_10b9_1521[] = "ALI M1521 Aladdin III CPU Bridge"; +#endif +static const char pci_device_10b9_1523[] = "M1523"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1523_10b9_1523[] = "ALI M1523 ISA Bridge"; +#endif +static const char pci_device_10b9_1531[] = "M1531 [Aladdin IV]"; +static const char pci_device_10b9_1533[] = "M1533 PCI to ISA Bridge [Aladdin IV]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1533_10b9_1533[] = "ALI M1533 Aladdin IV ISA Bridge"; +#endif +static const char pci_device_10b9_1541[] = "M1541"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1541_10b9_1541[] = "ALI M1541 Aladdin V/V+ AGP System Controller"; +#endif +static const char pci_device_10b9_1543[] = "M1543"; +static const char pci_device_10b9_1563[] = "M1563 HyperTransport South Bridge"; +static const char pci_device_10b9_1621[] = "M1621"; +static const char pci_device_10b9_1631[] = "ALI M1631 PCI North Bridge Aladdin Pro III"; +static const char pci_device_10b9_1632[] = "M1632M Northbridge+Trident"; +static const char pci_device_10b9_1641[] = "ALI M1641 PCI North Bridge Aladdin Pro IV"; +static const char pci_device_10b9_1644[] = "M1644/M1644T Northbridge+Trident"; +static const char pci_device_10b9_1646[] = "M1646 Northbridge+Trident"; +static const char pci_device_10b9_1647[] = "M1647 Northbridge [MAGiK 1 / MobileMAGiK 1]"; +static const char pci_device_10b9_1651[] = "M1651/M1651T Northbridge [Aladdin-Pro 5/5M,Aladdin-Pro 5T/5TM]"; +static const char pci_device_10b9_1671[] = "M1671 Super P4 Northbridge [AGP4X,PCI and SDR/DDR]"; +static const char pci_device_10b9_1681[] = "M1681 P4 Northbridge [AGP8X,HyperTransport and SDR/DDR]"; +static const char pci_device_10b9_1687[] = "M1687 K8 Northbridge [AGP8X and HyperTransport]"; +static const char pci_device_10b9_3141[] = "M3141"; +static const char pci_device_10b9_3143[] = "M3143"; +static const char pci_device_10b9_3145[] = "M3145"; +static const char pci_device_10b9_3147[] = "M3147"; +static const char pci_device_10b9_3149[] = "M3149"; +static const char pci_device_10b9_3151[] = "M3151"; +static const char pci_device_10b9_3307[] = "M3307"; +static const char pci_device_10b9_3309[] = "M3309"; +static const char pci_device_10b9_5212[] = "M4803"; +static const char pci_device_10b9_5215[] = "MS4803"; +static const char pci_device_10b9_5217[] = "M5217H"; +static const char pci_device_10b9_5219[] = "M5219"; +static const char pci_device_10b9_5225[] = "M5225"; +static const char pci_device_10b9_5229[] = "M5229 IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5229_1043_8053[] = "A7A266 Motherboard IDE"; +#endif +static const char pci_device_10b9_5235[] = "M5225"; +static const char pci_device_10b9_5237[] = "USB 1.1 Controller"; +static const char pci_device_10b9_5239[] = "USB 2.0 Controller"; +static const char pci_device_10b9_5243[] = "M1541 PCI to AGP Controller"; +static const char pci_device_10b9_5247[] = "PCI to AGP Controller"; +static const char pci_device_10b9_5249[] = "M5249 HTT to PCI Bridge"; +static const char pci_device_10b9_5251[] = "M5251 P1394 OHCI 1.0 Controller"; +static const char pci_device_10b9_5253[] = "M5253 P1394 OHCI 1.1 Controller"; +static const char pci_device_10b9_5261[] = "M5261 Ethernet Controller"; +static const char pci_device_10b9_5451[] = "M5451 PCI AC-Link Controller Audio Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5451_1014_0506[] = "ThinkPad R30"; +#endif +static const char pci_device_10b9_5453[] = "M5453 PCI AC-Link Controller Modem Device"; +static const char pci_device_10b9_5455[] = "M5455 PCI AC-Link Controller Audio Device"; +static const char pci_device_10b9_5457[] = "Intel 537 [M5457 AC-Link Modem]"; +static const char pci_device_10b9_5459[] = "SmartLink SmartPCI561 56K Modem"; +static const char pci_device_10b9_545a[] = "SmartLink SmartPCI563 56K Modem"; +static const char pci_device_10b9_5471[] = "M5471 Memory Stick Controller"; +static const char pci_device_10b9_5473[] = "M5473 SD-MMC Controller"; +static const char pci_device_10b9_7101[] = "M7101 PMU"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_7101_10b9_7101[] = "ALI M7101 Power Management Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ba[] = "Mitsubishi Electric Corp."; +static const char pci_device_10ba_0301[] = "AccelGraphics AccelECLIPSE"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10bb[] = "Dapha Electronics Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10bc[] = "Advanced Logic Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10bd[] = "Surecom Technology"; +static const char pci_device_10bd_0e34[] = "NE-34"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10be[] = "Tseng Labs International Co."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10bf[] = "Most Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c0[] = "Boca Research Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c1[] = "ICM Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c2[] = "Auspex Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c3[] = "Samsung Semiconductors, Inc."; +static const char pci_device_10c3_1100[] = "Smartether100 SC1100 LAN Adapter (i82557B)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c4[] = "Award Software International Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c5[] = "Xerox Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c6[] = "Rambus Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c7[] = "Media Vision"; +#endif +static const char pci_vendor_10c8[] = "Neomagic Corporation"; +static const char pci_device_10c8_0001[] = "NM2070 [MagicGraph 128]"; +static const char pci_device_10c8_0002[] = "NM2090 [MagicGraph 128V]"; +static const char pci_device_10c8_0003[] = "NM2093 [MagicGraph 128ZV]"; +static const char pci_device_10c8_0004[] = "NM2160 [MagicGraph 128XD]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1014_00ba[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1025_1007[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1028_0074[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1028_0075[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1028_007d[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1028_007e[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1033_802f[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_104d_801b[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_104d_802f[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_104d_830b[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10ba_0e00[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10c8_0004[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10cf_1029[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_8308[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_8309[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_830b[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_830d[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_8312[] = "MagicGraph 128XD"; +#endif +static const char pci_device_10c8_0005[] = "NM2200 [MagicGraph 256AV]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0005_1014_00dd[] = "ThinkPad 570"; +#endif +static const char pci_device_10c8_0006[] = "NM2360 [MagicMedia 256ZX]"; +static const char pci_device_10c8_0016[] = "NM2380 [MagicMedia 256XL+]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0016_10c8_0016[] = "MagicMedia 256XL+"; +#endif +static const char pci_device_10c8_0025[] = "NM2230 [MagicGraph 256AV+]"; +static const char pci_device_10c8_0083[] = "NM2093 [MagicGraph 128ZV+]"; +static const char pci_device_10c8_8005[] = "NM2200 [MagicMedia 256AV Audio]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_0e11_b0d1[] = "MagicMedia 256AV Audio Device on Discovery"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_0e11_b126[] = "MagicMedia 256AV Audio Device on Durango"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_1014_00dd[] = "MagicMedia 256AV Audio Device on BlackTip Thinkpad"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_1025_1003[] = "MagicMedia 256AV Audio Device on TravelMate 720"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_1028_008f[] = "MagicMedia 256AV Audio Device on Colorado Inspiron"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_103c_0007[] = "MagicMedia 256AV Audio Device on Voyager II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_103c_0008[] = "MagicMedia 256AV Audio Device on Voyager III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_103c_000d[] = "MagicMedia 256AV Audio Device on Omnibook 900"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_10c8_8005[] = "MagicMedia 256AV Audio Device on FireAnt"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_110a_8005[] = "MagicMedia 256AV Audio Device"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_14c0_0004[] = "MagicMedia 256AV Audio Device"; +#endif +static const char pci_device_10c8_8006[] = "NM2360 [MagicMedia 256ZX Audio]"; +static const char pci_device_10c8_8016[] = "NM2380 [MagicMedia 256XL+ Audio]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c9[] = "Dataexpert Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ca[] = "Fujitsu Microelectr., Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10cb[] = "Omron Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10cc[] = "Mentor ARC Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10cd[] = "Advanced System Products, Inc"; +static const char pci_device_10cd_1100[] = "ASC1100"; +static const char pci_device_10cd_1200[] = "ASC1200 [(abp940) Fast SCSI-II]"; +static const char pci_device_10cd_1300[] = "ABP940-U / ABP960-U"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10cd_1300_10cd_1310[] = "ASC1300 SCSI Adapter"; +#endif +static const char pci_device_10cd_2300[] = "ABP940-UW"; +static const char pci_device_10cd_2500[] = "ABP940-U2W"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ce[] = "Radius"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10cf[] = "Citicorp TTI"; +static const char pci_device_10cf_2001[] = "mb86605"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d0[] = "Fujitsu Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d1[] = "FuturePlus Systems Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d2[] = "Molex Incorporated"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d3[] = "Jabil Circuit Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d4[] = "Hualon Microelectronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d5[] = "Autologic Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d6[] = "Cetia"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d7[] = "BCM Advanced Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d8[] = "Advanced Peripherals Labs"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d9[] = "Macronix, Inc. [MXIC]"; +static const char pci_device_10d9_0512[] = "MX98713"; +static const char pci_device_10d9_0531[] = "MX987x5"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10d9_0531_1186_1200[] = "DFE-540TX ProFAST 10/100 Adapter"; +#endif +static const char pci_device_10d9_8625[] = "MX86250"; +static const char pci_device_10d9_8888[] = "MX86200"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10da[] = "Compaq IPG-Austin"; +static const char pci_device_10da_0508[] = "TC4048 Token Ring 4/16"; +static const char pci_device_10da_3390[] = "Tl3c3x9"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10db[] = "Rohm LSI Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10dc[] = "CERN/ECP/EDU"; +static const char pci_device_10dc_0001[] = "STAR/RD24 SCI-PCI (PMC)"; +static const char pci_device_10dc_0002[] = "TAR/RD24 SCI-PCI (PMC)"; +static const char pci_device_10dc_0021[] = "HIPPI destination"; +static const char pci_device_10dc_0022[] = "HIPPI source"; +static const char pci_device_10dc_10dc[] = "ATT2C15-3 FPGA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10dd[] = "Evans & Sutherland"; +#endif +static const char pci_vendor_10de[] = "nVidia Corporation"; +static const char pci_device_10de_0008[] = "NV1 [EDGE 3D]"; +static const char pci_device_10de_0009[] = "NV1 [EDGE 3D]"; +static const char pci_device_10de_0010[] = "NV2 [Mutara V08]"; +static const char pci_device_10de_0020[] = "NV4 [RIVA TNT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1043_0200[] = "V3400 TNT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1048_0c18[] = "Erazor II SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1048_0c1b[] = "Erazor II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_0550[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_0552[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4804[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4808[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4810[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4812[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4815[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4820[] = "Viper V550 with TV out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4822[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4904[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4914[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_8225[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_10b4_273d[] = "Velocity 4400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_10b4_273e[] = "Velocity 4400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_10b4_2740[] = "Velocity 4400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_10de_0020[] = "Riva TNT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1102_1015[] = "Graphics Blaster CT6710"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1102_1016[] = "Graphics Blaster RIVA TNT"; +#endif +static const char pci_device_10de_0028[] = "NV5 [RIVA TNT2/TNT2 Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1043_0200[] = "AGP-V3800 SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1043_0201[] = "AGP-V3800 SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1043_0205[] = "PCI-V3800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1043_4000[] = "AGP-V3800PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_4804[] = "Viper V770"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_4a00[] = "Viper V770"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_4a02[] = "Viper V770 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_5a00[] = "RIVA TNT2/TNT2 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_6a02[] = "Viper V770 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_7a02[] = "Viper V770 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_10de_0005[] = "RIVA TNT2 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_10de_000f[] = "Compaq NVIDIA TNT2 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1102_1020[] = "3D Blaster RIVA TNT2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1102_1026[] = "3D Blaster RIVA TNT2 Digital"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_14af_5810[] = "Maxi Gamer Xentor"; +#endif +static const char pci_device_10de_0029[] = "NV5 [RIVA TNT2 Ultra]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1043_0200[] = "AGP-V3800 Deluxe"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1043_0201[] = "AGP-V3800 Ultra SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1043_0205[] = "PCI-V3800 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1102_1021[] = "3D Blaster RIVA TNT2 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1102_1029[] = "3D Blaster RIVA TNT2 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1102_102f[] = "3D Blaster RIVA TNT2 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_14af_5820[] = "Maxi Gamer Xentor 32"; +#endif +static const char pci_device_10de_002a[] = "NV5 [Riva TnT2]"; +static const char pci_device_10de_002b[] = "NV5 [Riva TnT2]"; +static const char pci_device_10de_002c[] = "NV6 [Vanta/Vanta LT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1043_0200[] = "AGP-V3800 Combat SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1043_0201[] = "AGP-V3800 Combat"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1092_6820[] = "Viper V730"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1102_1031[] = "CT6938 VANTA 8MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1102_1034[] = "CT6894 VANTA 16MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_14af_5008[] = "Maxi Gamer Phoenix 2"; +#endif +static const char pci_device_10de_002d[] = "NV5M64 [RIVA TNT2 Model 64/Model 64 Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1043_0200[] = "AGP-V3800M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1043_0201[] = "AGP-V3800M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1048_0c3a[] = "Erazor III LT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_10de_001e[] = "M64 AGP4x"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1102_1023[] = "CT6892 RIVA TNT2 Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1102_1024[] = "CT6932 RIVA TNT2 Value 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1102_102c[] = "CT6931 RIVA TNT2 Value [Jumper]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1462_8808[] = "MSI-8808"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1554_1041[] = "PixelView RIVA TNT2 M64 32MB"; +#endif +static const char pci_device_10de_002e[] = "NV6 [Vanta]"; +static const char pci_device_10de_002f[] = "NV6 [Vanta]"; +static const char pci_device_10de_0060[] = "nForce2 ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0060_1043_80ad[] = "A7N8X Mainboard"; +#endif +static const char pci_device_10de_0064[] = "nForce2 SMBus (MCP)"; +static const char pci_device_10de_0065[] = "nForce2 IDE"; +static const char pci_device_10de_0066[] = "nForce2 Ethernet Controller"; +static const char pci_device_10de_0067[] = "nForce2 USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0067_1043_0c11[] = "A7N8X Mainboard"; +#endif +static const char pci_device_10de_0068[] = "nForce2 USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0068_1043_0c11[] = "A7N8X Mainboard"; +#endif +static const char pci_device_10de_006a[] = "nForce2 AC97 Audio Controler (MCP)"; +static const char pci_device_10de_006b[] = "nForce MultiMedia audio [Via VT82C686B]"; +static const char pci_device_10de_006e[] = "nForce2 FireWire (IEEE 1394) Controller"; +static const char pci_device_10de_00a0[] = "NV5 [Aladdin TNT2]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00a0_14af_5810[] = "Maxi Gamer Xentor"; +#endif +static const char pci_device_10de_0100[] = "NV10 [GeForce 256 SDR]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1043_0200[] = "AGP-V6600 SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1043_0201[] = "AGP-V6600 SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1043_4008[] = "AGP-V6600 SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1043_4009[] = "AGP-V6600 SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1102_102d[] = "CT6941 GeForce 256"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_14af_5022[] = "3D Prophet SE"; +#endif +static const char pci_device_10de_0101[] = "NV10DDR [GeForce 256 DDR]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1043_0202[] = "AGP-V6800 DDR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1043_400a[] = "AGP-V6800 DDR SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1043_400b[] = "AGP-V6800 DDR SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1102_102e[] = "CT6971 GeForce 256 DDR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_14af_5021[] = "3D Prophet DDR-DVI"; +#endif +static const char pci_device_10de_0103[] = "NV10GL [Quadro]"; +static const char pci_device_10de_0110[] = "NV11 [GeForce2 MX/MX 400]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1043_4015[] = "AGP-V7100 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1043_4031[] = "V7100 Pro with TV output"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1462_8817[] = "MSI GeForce2 MX400 Pro32S [MS-8817]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_14af_7102[] = "3D Prophet II MX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_14af_7103[] = "3D Prophet II MX Dual-Display"; +#endif +static const char pci_device_10de_0111[] = "NV11DDR [GeForce2 MX 100 DDR/200 DDR]"; +static const char pci_device_10de_0112[] = "NV11 [GeForce2 Go]"; +static const char pci_device_10de_0113[] = "NV11GL [Quadro2 MXR/EX]"; +static const char pci_device_10de_0150[] = "NV15 [GeForce2 GTS/Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_1043_4016[] = "V7700 AGP Video Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_107d_2840[] = "WinFast GeForce2 GTS with TV output"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_1462_8831[] = "Creative GeForce2 Pro"; +#endif +static const char pci_device_10de_0151[] = "NV15DDR [GeForce2 Ti]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0151_1043_405f[] = "V7700Ti"; +#endif +static const char pci_device_10de_0152[] = "NV15BR [GeForce2 Ultra, Bladerunner]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0152_1048_0c56[] = "GLADIAC Ultra"; +#endif +static const char pci_device_10de_0153[] = "NV15GL [Quadro2 Pro]"; +static const char pci_device_10de_0170[] = "NV17 [GeForce4 MX 460]"; +static const char pci_device_10de_0171[] = "NV17 [GeForce4 MX 440]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_1462_8661[] = "G4MX440-VTP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_1462_8730[] = "MX440SES-T (MS-8873)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_147b_8f00[] = "Abit Siluro GeForce4MX440"; +#endif +static const char pci_device_10de_0172[] = "NV17 [GeForce4 MX 420]"; +static const char pci_device_10de_0173[] = "NV17 [GeForce4 MX 440-SE]"; +static const char pci_device_10de_0174[] = "NV17 [GeForce4 440 Go]"; +static const char pci_device_10de_0175[] = "NV17 [GeForce4 420 Go]"; +static const char pci_device_10de_0176[] = "NV17 [GeForce4 420 Go 32M]"; +static const char pci_device_10de_0178[] = "NV17GL [Quadro4 550 XGL]"; +static const char pci_device_10de_0179[] = "NV17 [GeForce4 440 Go 64M]"; +static const char pci_device_10de_017a[] = "NV17GL [Quadro4 200/400 NVS]"; +static const char pci_device_10de_017b[] = "NV17GL [Quadro4 550 XGL]"; +static const char pci_device_10de_017c[] = "NV17GL [Quadro4 550 GoGL]"; +static const char pci_device_10de_0181[] = "NV18 [GeForce4 MX 440 AGP 8x]"; +static const char pci_device_10de_0182[] = "NV18 [GeForce4 MX 440SE AGP 8x]"; +static const char pci_device_10de_0183[] = "NV18 [GeForce4 MX 420 AGP 8x]"; +static const char pci_device_10de_0188[] = "NV18GL [Quadro4 580 XGL]"; +static const char pci_device_10de_018a[] = "NV18GL [Quadro4 NVS]"; +static const char pci_device_10de_018b[] = "NV18GL [Quadro4 380 XGL]"; +static const char pci_device_10de_01a0[] = "NV15 [GeForce2 - nForce GPU]"; +static const char pci_device_10de_01a4[] = "nForce CPU bridge"; +static const char pci_device_10de_01ab[] = "nForce 420 Memory Controller (DDR)"; +static const char pci_device_10de_01ac[] = "nForce 220/420 Memory Controller"; +static const char pci_device_10de_01ad[] = "nForce 220/420 Memory Controller"; +static const char pci_device_10de_01b1[] = "nForce Audio"; +static const char pci_device_10de_01b2[] = "nForce ISA Bridge"; +static const char pci_device_10de_01b4[] = "nForce PCI System Management"; +static const char pci_device_10de_01b7[] = "nForce AGP to PCI Bridge"; +static const char pci_device_10de_01b8[] = "nForce PCI-to-PCI bridge"; +static const char pci_device_10de_01bc[] = "nForce IDE"; +static const char pci_device_10de_01c1[] = "Intel 537 [nForce MC97 Modem]"; +static const char pci_device_10de_01c2[] = "nForce USB Controller"; +static const char pci_device_10de_01c3[] = "nForce Ethernet Controller"; +static const char pci_device_10de_01e8[] = "nForce2 AGP"; +static const char pci_device_10de_01f0[] = "NV18 [GeForce4 MX - nForce GPU]"; +static const char pci_device_10de_0200[] = "NV20 [GeForce3]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0200_1043_402f[] = "AGP-V8200 DDR"; +#endif +static const char pci_device_10de_0201[] = "NV20 [GeForce3 Ti 200]"; +static const char pci_device_10de_0202[] = "NV20 [GeForce3 Ti 500]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0202_1043_405b[] = "V8200 T5"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0202_1545_002f[] = "Xtasy 6964"; +#endif +static const char pci_device_10de_0203[] = "NV20DCC [Quadro DCC]"; +static const char pci_device_10de_0250[] = "NV25 [GeForce4 Ti 4600]"; +static const char pci_device_10de_0251[] = "NV25 [GeForce4 Ti 4400]"; +static const char pci_device_10de_0252[] = "NV25 [GeForce4 Ti]"; +static const char pci_device_10de_0253[] = "NV25 [GeForce4 Ti 4200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0253_107d_2896[] = "WinFast A250 LE TD (Dual VGA/TV-out/DVI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0253_147b_8f09[] = "Siluro (Dual VGA/TV-out/DVI)"; +#endif +static const char pci_device_10de_0258[] = "NV25GL [Quadro4 900 XGL]"; +static const char pci_device_10de_0259[] = "NV25GL [Quadro4 750 XGL]"; +static const char pci_device_10de_025b[] = "NV25GL [Quadro4 700 XGL]"; +static const char pci_device_10de_0280[] = "NV28 [GeForce4 Ti 4800]"; +static const char pci_device_10de_0281[] = "NV28 [GeForce4 Ti 4200 AGP 8x]"; +static const char pci_device_10de_0282[] = "NV28 [GeForce4 Ti 4800 SE]"; +static const char pci_device_10de_0288[] = "NV28GL [Quadro4 980 XGL]"; +static const char pci_device_10de_0289[] = "NV28GL [Quadro4 780 XGL]"; +static const char pci_device_10de_0300[] = "NV30 [GeForce FX]"; +static const char pci_device_10de_0301[] = "NV30 [GeForce FX 5800 Ultra]"; +static const char pci_device_10de_0302[] = "NV30 [GeForce FX 5800]"; +static const char pci_device_10de_0308[] = "NV30GL [Quadro FX 2000]"; +static const char pci_device_10de_0309[] = "NV30GL [Quadro FX 1000]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10df[] = "Emulex Corporation"; +static const char pci_device_10df_1ae5[] = "LP6000 Fibre Channel Host Adapter"; +static const char pci_device_10df_f085[] = "LP850 Fibre Channel Adapter"; +static const char pci_device_10df_f095[] = "LP952 Fibre Channel Adapter"; +static const char pci_device_10df_f098[] = "LP982 Fibre Channel Adapter"; +static const char pci_device_10df_f700[] = "LP7000 Fibre Channel Host Adapter"; +static const char pci_device_10df_f800[] = "LP8000 Fibre Channel Host Adapter"; +static const char pci_device_10df_f900[] = "LP9000 Fibre Channel Host Adapter"; +static const char pci_device_10df_f980[] = "LP9802 Fibre Channel Adapter"; +#endif +static const char pci_vendor_10e0[] = "Integrated Micro Solutions Inc."; +static const char pci_device_10e0_5026[] = "IMS5026/27/28"; +static const char pci_device_10e0_5027[] = "IMS5027"; +static const char pci_device_10e0_5028[] = "IMS5028"; +static const char pci_device_10e0_8849[] = "IMS8849"; +static const char pci_device_10e0_8853[] = "IMS8853"; +static const char pci_device_10e0_9128[] = "IMS9128 [Twin turbo 128]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e1[] = "Tekram Technology Co.,Ltd."; +static const char pci_device_10e1_0391[] = "TRM-S1040"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10e1_0391_10e1_0391[] = "DC-315U SCSI-3 Host Adapter"; +#endif +static const char pci_device_10e1_690c[] = "DC-690c"; +static const char pci_device_10e1_dc29[] = "DC-290"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e2[] = "Aptix Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e3[] = "Tundra Semiconductor Corp."; +static const char pci_device_10e3_0000[] = "CA91C042 [Universe]"; +static const char pci_device_10e3_0860[] = "CA91C860 [QSpan]"; +static const char pci_device_10e3_0862[] = "CA91C862A [QSpan-II]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e4[] = "Tandem Computers"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e5[] = "Micro Industries Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e6[] = "Gainbery Computer Products Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e7[] = "Vadem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e8[] = "Applied Micro Circuits Corp."; +static const char pci_device_10e8_2011[] = "Q-Motion Video Capture/Edit board"; +static const char pci_device_10e8_4750[] = "S5930 [Matchmaker]"; +static const char pci_device_10e8_5920[] = "S5920"; +static const char pci_device_10e8_8043[] = "LANai4.x [Myrinet LANai interface chip]"; +static const char pci_device_10e8_8062[] = "S5933_PARASTATION"; +static const char pci_device_10e8_807d[] = "S5933 [Matchmaker]"; +static const char pci_device_10e8_8088[] = "Kongsberg Spacetec Format Synchronizer"; +static const char pci_device_10e8_8089[] = "Kongsberg Spacetec Serial Output Board"; +static const char pci_device_10e8_809c[] = "S5933_HEPC3"; +static const char pci_device_10e8_80d7[] = "PCI-9112"; +static const char pci_device_10e8_80d9[] = "PCI-9118"; +static const char pci_device_10e8_80da[] = "PCI-9812"; +static const char pci_device_10e8_811a[] = "PCI-IEEE1355-DS-DE Interface"; +static const char pci_device_10e8_8170[] = "S5933 [Matchmaker] (Chipset Development Tool)"; +static const char pci_device_10e8_82db[] = "AJA HDNTV HD SDI Framestore"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e9[] = "Alps Electric Co., Ltd."; +#endif +static const char pci_vendor_10ea[] = "Intergraphics Systems"; +static const char pci_device_10ea_1680[] = "IGA-1680"; +static const char pci_device_10ea_1682[] = "IGA-1682"; +static const char pci_device_10ea_1683[] = "IGA-1683"; +static const char pci_device_10ea_2000[] = "CyberPro 2000"; +static const char pci_device_10ea_2010[] = "CyberPro 2000A"; +static const char pci_device_10ea_5000[] = "CyberPro 5000"; +static const char pci_device_10ea_5050[] = "CyberPro 5050"; +static const char pci_device_10ea_5202[] = "CyberPro 5202"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10eb[] = "Artists Graphics"; +static const char pci_device_10eb_0101[] = "3GA"; +static const char pci_device_10eb_8111[] = "Twist3 Frame Grabber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ec[] = "Realtek Semiconductor Co., Ltd."; +static const char pci_device_10ec_8029[] = "RTL-8029(AS)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_10b8_2011[] = "EZ-Card (SMC1208)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_10ec_8029[] = "RTL-8029(AS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_1113_1208[] = "EN1208"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_1186_0300[] = "DE-528"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_1259_2400[] = "AT-2400"; +#endif +static const char pci_device_10ec_8129[] = "RTL-8129"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8129_10ec_8129[] = "RT8129 Fast Ethernet Adapter"; +#endif +static const char pci_device_10ec_8138[] = "RT8139 (B/C) Cardbus Fast Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8138_10ec_8138[] = "RT8139 (B/C) Fast Ethernet Adapter"; +#endif +static const char pci_device_10ec_8139[] = "RTL-8139/8139C/8139C+"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1025_8920[] = "ALN-325"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1025_8921[] = "ALN-325"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_10bd_0320[] = "EP-320X-R"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_10ec_8139[] = "RT8139"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1186_1300[] = "DFE-538TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1186_1320[] = "SN5200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1186_8139[] = "DRN-32TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_11f6_8139[] = "FN22-3(A) LinxPRO Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1259_2500[] = "AT-2500TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1259_2503[] = "AT-2500TX/ACPI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1429_d010[] = "ND010"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1432_9130[] = "EN-9130TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1436_8139[] = "RT8139"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_146c_1439[] = "FE-1439TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1489_6001[] = "GF100TXRII"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1489_6002[] = "GF100TXRA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_149c_139a[] = "LFE-8139ATX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_149c_8139[] = "LFE-8139TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_2646_0001[] = "EtheRx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_8e2e_7000[] = "KF-230TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_8e2e_7100[] = "KF-230TX/2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_a0a0_0007[] = "ALN-325C"; +#endif +static const char pci_device_10ec_8169[] = "RTL-8169"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8169_1371_434e[] = "ProG-2000L"; +#endif +static const char pci_device_10ec_8197[] = "SmartLAN56 56K Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ed[] = "Ascii Corporation"; +static const char pci_device_10ed_7310[] = "V7310"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ee[] = "Xilinx Corporation"; +static const char pci_device_10ee_3fc0[] = "RME Digi96"; +static const char pci_device_10ee_3fc1[] = "RME Digi96/8"; +static const char pci_device_10ee_3fc2[] = "RME Digi96/8 Pro"; +static const char pci_device_10ee_3fc3[] = "RME Digi96/8 Pad"; +static const char pci_device_10ee_3fc4[] = "RME Digi9652 (Hammerfall)"; +static const char pci_device_10ee_3fc5[] = "RME Hammerfall DSP"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ef[] = "Racore Computer Products, Inc."; +static const char pci_device_10ef_8154[] = "M815x Token Ring Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f0[] = "Peritek Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f1[] = "Tyan Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f2[] = "Achme Computer, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f3[] = "Alaris, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f4[] = "S-MOS Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f5[] = "NKK Corporation"; +static const char pci_device_10f5_a001[] = "NDR4000 [NR4600 Bridge]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f6[] = "Creative Electronic Systems SA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f7[] = "Matsushita Electric Industrial Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f8[] = "Altos India Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f9[] = "PC Direct"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fa[] = "Truevision"; +static const char pci_device_10fa_000c[] = "TARGA 1000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fb[] = "Thesys Gesellschaft für Mikroelektronik mbH"; +static const char pci_device_10fb_186f[] = "TH 6255"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fc[] = "I-O Data Device, Inc."; +static const char pci_device_10fc_0003[] = "Cardbus IDE Controller"; +static const char pci_device_10fc_0005[] = "Cardbus SCSI CBSC II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fd[] = "Soyo Computer, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fe[] = "Fast Multimedia AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ff[] = "NCube"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1100[] = "Jazz Multimedia"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1101[] = "Initio Corporation"; +static const char pci_device_1101_1060[] = "INI-A100U2W"; +static const char pci_device_1101_9100[] = "INI-9100/9100W"; +static const char pci_device_1101_9400[] = "INI-940"; +static const char pci_device_1101_9401[] = "INI-950"; +static const char pci_device_1101_9500[] = "360P"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1102[] = "Creative Labs"; +static const char pci_device_1102_0002[] = "SB Live! EMU10k1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_0020[] = "CT4850 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_0021[] = "CT4620 SBLive!"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_002f[] = "SBLive! mainboard implementation"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_4001[] = "E-mu APS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8022[] = "CT4780 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8023[] = "CT4790 SoundBlaster PCI512"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8024[] = "CT4760 SBLive!"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8025[] = "SBLive! Mainboard Implementation"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8026[] = "CT4830 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8027[] = "CT4832 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8028[] = "CT4760 SBLive! OEM version"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8031[] = "CT4831 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8040[] = "CT4760 SBLive!"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8051[] = "CT4850 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8061[] = "SBLive! Player 5.1"; +#endif +static const char pci_device_1102_0004[] = "SB Audigy"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0004_1102_0051[] = "SB0090 Audigy Player"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0004_1102_0053[] = "SB0090 Audigy Player/OEM"; +#endif +static const char pci_device_1102_0006[] = "[SB Live! Value] EMU10k1X"; +static const char pci_device_1102_4001[] = "SB Audigy FireWire Port"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_4001_1102_0010[] = "SB Audigy FireWire Port"; +#endif +static const char pci_device_1102_7002[] = "SB Live! MIDI/Game Port"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_7002_1102_0020[] = "Gameport Joystick"; +#endif +static const char pci_device_1102_7003[] = "SB Audigy MIDI/Game port"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_7003_1102_0040[] = "SB Audigy MIDI/Game Port"; +#endif +static const char pci_device_1102_7004[] = "[SB Live! Value] Input device controller"; +static const char pci_device_1102_8064[] = "SB0100 [SBLive! 5.1 OEM]"; +static const char pci_device_1102_8938[] = "ES1371"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1103[] = "Triones Technologies, Inc."; +static const char pci_device_1103_0003[] = "HPT343"; +static const char pci_device_1103_0004[] = "HPT366/368/370/370A/372"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0001[] = "HPT370A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0005[] = "HPT370 UDMA100"; +#endif +static const char pci_device_1103_0005[] = "HPT372A"; +static const char pci_device_1103_0006[] = "HPT302"; +static const char pci_device_1103_0007[] = "HPT371"; +static const char pci_device_1103_0008[] = "HPT374"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1104[] = "RasterOps Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1105[] = "Sigma Designs, Inc."; +static const char pci_device_1105_1105[] = "REALmagic Xcard MPEG 1/2/3/4 DVD Decoder"; +static const char pci_device_1105_8300[] = "REALmagic Hollywood Plus DVD Decoder"; +static const char pci_device_1105_8400[] = "EM840x REALmagic DVD/MPEG-2 Audio/Video Decoder"; +#endif +static const char pci_vendor_1106[] = "VIA Technologies, Inc."; +static const char pci_device_1106_0102[] = "Embedded VIA Ethernet Controller"; +static const char pci_device_1106_0130[] = "VT6305 1394.A Controller"; +static const char pci_device_1106_0305[] = "VT8363/8365 [KT133/KM133]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_1043_8033[] = "A7V Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_1043_803e[] = "A7V-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_1043_8042[] = "A7V133/A7V133-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_147b_a401[] = "KT7/KT7-RAID/KT7A/KT7A-RAID Mainboard"; +#endif +static const char pci_device_1106_0391[] = "VT8371 [KX133]"; +static const char pci_device_1106_0501[] = "VT8501 [Apollo MVP4]"; +static const char pci_device_1106_0505[] = "VT82C505"; +static const char pci_device_1106_0561[] = "VT82C561"; +static const char pci_device_1106_0571[] = "VT82C586/B/686A/B PIPC Bus Master IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1043_8052[] = "VT8233A Bus Master ATA100/66/33 IDE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1106_0571[] = "VT8235 Bus Master ATA133/100/66/33 IDE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1179_0001[] = "Magnia Z310"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1458_5002[] = "GA-7VAX Mainboard"; +#endif +static const char pci_device_1106_0576[] = "VT82C576 3V [Apollo Master]"; +static const char pci_device_1106_0585[] = "VT82C585VP [Apollo VP1/VPX]"; +static const char pci_device_1106_0586[] = "VT82C586/A/B PCI-to-ISA [Apollo VP]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0586_1106_0000[] = "MVP3 ISA Bridge"; +#endif +static const char pci_device_1106_0595[] = "VT82C595 [Apollo VP2]"; +static const char pci_device_1106_0596[] = "VT82C596 ISA [Mobile South]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0596_1106_0000[] = "VT82C596/A/B PCI to ISA Bridge"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0596_1458_0596[] = "VT82C596/A/B PCI to ISA Bridge"; +#endif +static const char pci_device_1106_0597[] = "VT82C597 [Apollo VP3]"; +static const char pci_device_1106_0598[] = "VT82C598 [Apollo MVP3]"; +static const char pci_device_1106_0601[] = "VT8601 [Apollo ProMedia]"; +static const char pci_device_1106_0605[] = "VT8605 [ProSavage PM133]"; +static const char pci_device_1106_0680[] = "VT82C680 [Apollo P6]"; +static const char pci_device_1106_0686[] = "VT82C686 [Apollo Super South]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_8033[] = "A7V Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_803e[] = "A7V-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_8040[] = "A7M266 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_8042[] = "A7V133/A7V133-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1106_0000[] = "VT82C686/A PCI to ISA Bridge"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1106_0686[] = "VT82C686/A PCI to ISA Bridge"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1179_0001[] = "Magnia Z310"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_147b_a702[] = "KG7-Lite Mainboard"; +#endif +static const char pci_device_1106_0691[] = "VT82C693A/694x [Apollo PRO133x]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0691_1179_0001[] = "Magnia Z310"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0691_1458_0691[] = "VT82C691 Apollo Pro System Controller"; +#endif +static const char pci_device_1106_0693[] = "VT82C693 [Apollo Pro Plus]"; +static const char pci_device_1106_0698[] = "VT82C693A [Apollo Pro133 AGP]"; +static const char pci_device_1106_0926[] = "VT82C926 [Amazon]"; +static const char pci_device_1106_1000[] = "VT82C570MV"; +static const char pci_device_1106_1106[] = "VT82C570MV"; +static const char pci_device_1106_1571[] = "VT82C416MV"; +static const char pci_device_1106_1595[] = "VT82C595/97 [Apollo VP2/97]"; +static const char pci_device_1106_3038[] = "USB"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_0925_1234[] = "USB Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1179_0001[] = "Magnia Z310"; +#endif +static const char pci_device_1106_3040[] = "VT82C586B ACPI"; +static const char pci_device_1106_3043[] = "VT86C100A [Rhine]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3043_10bd_0000[] = "VT86C100A Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3043_1106_0100[] = "VT86C100A Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3043_1186_1400[] = "DFE-530TX rev A"; +#endif +static const char pci_device_1106_3044[] = "IEEE 1394 Host Controller"; +static const char pci_device_1106_3050[] = "VT82C596 Power Management"; +static const char pci_device_1106_3051[] = "VT82C596 Power Management"; +static const char pci_device_1106_3057[] = "VT82C686 [Apollo Super ACPI]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1043_8033[] = "A7V Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1043_803e[] = "A7V-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1043_8040[] = "A7M266 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1043_8042[] = "A7V133/A7V133-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1179_0001[] = "Magnia Z310"; +#endif +static const char pci_device_1106_3058[] = "VT82C686 AC97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_0e11_b194[] = "Soundmax integrated digital audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1106_4511[] = "Onboard Audio on EP7KXA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1458_7600[] = "Onboard Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1462_3091[] = "MS-6309 Onboard Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_15dd_7609[] = "Onboard Audio"; +#endif +static const char pci_device_1106_3059[] = "VT8233 AC97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1458_a002[] = "GA-7VAX Onboard Audio (Realtek ALC650)"; +#endif +static const char pci_device_1106_3065[] = "VT6102 [Rhine-II]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1106_0102[] = "VT6102 [Rhine II] Embeded Ethernet Controller on VT8235"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1186_1400[] = "DFE-530TX rev A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1186_1401[] = "DFE-530TX rev B"; +#endif +static const char pci_device_1106_3068[] = "Intel 537 [AC97 Modem]"; +static const char pci_device_1106_3074[] = "VT8233 PCI to ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3074_1043_8052[] = "VT8233A"; +#endif +static const char pci_device_1106_3091[] = "VT8633 [Apollo Pro266]"; +static const char pci_device_1106_3099[] = "VT8366/A/7 [Apollo KT266/A/333]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3099_1043_8064[] = "A7V266-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3099_1043_807f[] = "A7V333 Mainboard"; +#endif +static const char pci_device_1106_3101[] = "VT8653 Host Bridge"; +static const char pci_device_1106_3102[] = "VT8662 Host Bridge"; +static const char pci_device_1106_3103[] = "VT8615 Host Bridge"; +static const char pci_device_1106_3104[] = "USB 2.0"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1458_5004[] = "GA-7VAX Mainboard"; +#endif +static const char pci_device_1106_3106[] = "VT6105 [Rhine-III]"; +static const char pci_device_1106_3109[] = "VT8233C PCI to ISA Bridge"; +static const char pci_device_1106_3112[] = "VT8361 [KLE133] Host Bridge"; +static const char pci_device_1106_3116[] = "VT8375 [KM266] Host Bridge"; +static const char pci_device_1106_3122[] = "VT8623 [Apollo CLE266] integrated CastleRock graphics"; +static const char pci_device_1106_3123[] = "VT8623 [Apollo CLE266]"; +static const char pci_device_1106_3128[] = "VT8753 [P4X266 AGP]"; +static const char pci_device_1106_3133[] = "VT3133 Host Bridge"; +static const char pci_device_1106_3147[] = "VT8233A ISA Bridge"; +static const char pci_device_1106_3148[] = "P4M266 Host Bridge"; +static const char pci_device_1106_3156[] = "P/KN266 Host Bridge"; +static const char pci_device_1106_3168[] = "VT8374 P4X400 Host Controller/AGP Bridge"; +static const char pci_device_1106_3177[] = "VT8235 ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1458_5001[] = "GA-7VAX Mainboard"; +#endif +static const char pci_device_1106_3189[] = "VT8377 [KT400 AGP] Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3189_1458_5000[] = "GA-7VAX Mainboard"; +#endif +static const char pci_device_1106_5030[] = "VT82C596 ACPI [Apollo PRO]"; +static const char pci_device_1106_6100[] = "VT85C100A [Rhine II]"; +static const char pci_device_1106_8231[] = "VT8231 [PCI-to-ISA Bridge]"; +static const char pci_device_1106_8235[] = "VT8235 ACPI"; +static const char pci_device_1106_8305[] = "VT8363/8365 [KT133/KM133 AGP]"; +static const char pci_device_1106_8391[] = "VT8371 [KX133 AGP]"; +static const char pci_device_1106_8501[] = "VT8501 [Apollo MVP4 AGP]"; +static const char pci_device_1106_8596[] = "VT82C596 [Apollo PRO AGP]"; +static const char pci_device_1106_8597[] = "VT82C597 [Apollo VP3 AGP]"; +static const char pci_device_1106_8598[] = "VT82C598/694x [Apollo MVP3/Pro133x AGP]"; +static const char pci_device_1106_8601[] = "VT8601 [Apollo ProMedia AGP]"; +static const char pci_device_1106_8605[] = "VT8605 [PM133 AGP]"; +static const char pci_device_1106_8691[] = "VT82C691 [Apollo Pro]"; +static const char pci_device_1106_8693[] = "VT82C693 [Apollo Pro Plus] PCI Bridge"; +static const char pci_device_1106_b091[] = "VT8633 [Apollo Pro266 AGP]"; +static const char pci_device_1106_b099[] = "VT8366/A/7 [Apollo KT266/A/333 AGP]"; +static const char pci_device_1106_b101[] = "VT8653 AGP Bridge"; +static const char pci_device_1106_b102[] = "VT8362 AGP Bridge"; +static const char pci_device_1106_b103[] = "VT8615 AGP Bridge"; +static const char pci_device_1106_b112[] = "VT8361 [KLE133] AGP Bridge"; +static const char pci_device_1106_b168[] = "VT8235 PCI Bridge"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1107[] = "Stratus Computers"; +static const char pci_device_1107_0576[] = "VIA VT82C570MV [Apollo] (Wrong vendor ID!)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1108[] = "Proteon, Inc."; +static const char pci_device_1108_0100[] = "p1690plus_AA"; +static const char pci_device_1108_0101[] = "p1690plus_AB"; +static const char pci_device_1108_0105[] = "P1690Plus"; +static const char pci_device_1108_0108[] = "P1690Plus"; +static const char pci_device_1108_0138[] = "P1690Plus"; +static const char pci_device_1108_0139[] = "P1690Plus"; +static const char pci_device_1108_013c[] = "P1690Plus"; +static const char pci_device_1108_013d[] = "P1690Plus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1109[] = "Cogent Data Technologies, Inc."; +static const char pci_device_1109_1400[] = "EM110TX [EX110TX]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110a[] = "Siemens Nixdorf AG"; +static const char pci_device_110a_0002[] = "Pirahna 2-port"; +static const char pci_device_110a_0005[] = "Tulip controller, power management, switch extender"; +static const char pci_device_110a_2102[] = "DSCC4 WAN adapter"; +static const char pci_device_110a_4942[] = "FPGA I-Bus Tracer for MBD"; +static const char pci_device_110a_6120[] = "SZB6120"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110b[] = "Chromatic Research Inc."; +static const char pci_device_110b_0001[] = "Mpact Media Processor"; +static const char pci_device_110b_0004[] = "Mpact 2"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110c[] = "Mini-Max Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110d[] = "Znyx Advanced Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110e[] = "CPU Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110f[] = "Ross Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1110[] = "Powerhouse Systems"; +static const char pci_device_1110_6037[] = "Firepower Powerized SMP I/O ASIC"; +static const char pci_device_1110_6073[] = "Firepower Powerized SMP I/O ASIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1111[] = "Santa Cruz Operation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1112[] = "Osicom Technologies Inc"; +static const char pci_device_1112_2200[] = "FDDI Adapter"; +static const char pci_device_1112_2300[] = "Fast Ethernet Adapter"; +static const char pci_device_1112_2340[] = "4 Port Fast Ethernet Adapter"; +static const char pci_device_1112_2400[] = "ATM Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1113[] = "Accton Technology Corporation"; +static const char pci_device_1113_1211[] = "SMC2-1211TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_1211_103c_1207[] = "EN-1207D Fast Ethernet Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_1211_1113_1211[] = "EN-1207D Fast Ethernet Adapter"; +#endif +static const char pci_device_1113_1216[] = "EN-1216 Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_1216_111a_1020[] = "SpeedStream 1020 PCI 10/100 Ethernet Adaptor [EN-1207F-TX ?]"; +#endif +static const char pci_device_1113_1217[] = "EN-1217 Ethernet Adapter"; +static const char pci_device_1113_5105[] = "10Mbps Network card"; +static const char pci_device_1113_9211[] = "EN-1207D Fast Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_9211_1113_9211[] = "EN-1207D Fast Ethernet Adapter"; +#endif +static const char pci_device_1113_9511[] = "Fast Ethernet Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1114[] = "Atmel Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1115[] = "3D Labs"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1116[] = "Data Translation"; +static const char pci_device_1116_0022[] = "DT3001"; +static const char pci_device_1116_0023[] = "DT3002"; +static const char pci_device_1116_0024[] = "DT3003"; +static const char pci_device_1116_0025[] = "DT3004"; +static const char pci_device_1116_0026[] = "DT3005"; +static const char pci_device_1116_0027[] = "DT3001-PGL"; +static const char pci_device_1116_0028[] = "DT3003-PGL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1117[] = "Datacube, Inc"; +static const char pci_device_1117_9500[] = "Max-1C SVGA card"; +static const char pci_device_1117_9501[] = "Max-1C image processing"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1118[] = "Berg Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1119[] = "ICP Vortex Computersysteme GmbH"; +static const char pci_device_1119_0000[] = "GDT 6000/6020/6050"; +static const char pci_device_1119_0001[] = "GDT 6000B/6010"; +static const char pci_device_1119_0002[] = "GDT 6110/6510"; +static const char pci_device_1119_0003[] = "GDT 6120/6520"; +static const char pci_device_1119_0004[] = "GDT 6530"; +static const char pci_device_1119_0005[] = "GDT 6550"; +static const char pci_device_1119_0006[] = "GDT 6x17"; +static const char pci_device_1119_0007[] = "GDT 6x27"; +static const char pci_device_1119_0008[] = "GDT 6537"; +static const char pci_device_1119_0009[] = "GDT 6557"; +static const char pci_device_1119_000a[] = "GDT 6115/6515"; +static const char pci_device_1119_000b[] = "GDT 6125/6525"; +static const char pci_device_1119_000c[] = "GDT 6535"; +static const char pci_device_1119_000d[] = "GDT 6555"; +static const char pci_device_1119_0100[] = "GDT 6117RP/6517RP"; +static const char pci_device_1119_0101[] = "GDT 6127RP/6527RP"; +static const char pci_device_1119_0102[] = "GDT 6537RP"; +static const char pci_device_1119_0103[] = "GDT 6557RP"; +static const char pci_device_1119_0104[] = "GDT 6111RP/6511RP"; +static const char pci_device_1119_0105[] = "GDT 6121RP/6521RP"; +static const char pci_device_1119_0110[] = "GDT 6117RD/6517RD"; +static const char pci_device_1119_0111[] = "GDT 6127RD/6527RD"; +static const char pci_device_1119_0112[] = "GDT 6537RD"; +static const char pci_device_1119_0113[] = "GDT 6557RD"; +static const char pci_device_1119_0114[] = "GDT 6111RD/6511RD"; +static const char pci_device_1119_0115[] = "GDT 6121RD/6521RD"; +static const char pci_device_1119_0118[] = "GDT 6118RD/6518RD/6618RD"; +static const char pci_device_1119_0119[] = "GDT 6128RD/6528RD/6628RD"; +static const char pci_device_1119_011a[] = "GDT 6538RD/6638RD"; +static const char pci_device_1119_011b[] = "GDT 6558RD/6658RD"; +static const char pci_device_1119_0120[] = "GDT 6117RP2/6517RP2"; +static const char pci_device_1119_0121[] = "GDT 6127RP2/6527RP2"; +static const char pci_device_1119_0122[] = "GDT 6537RP2"; +static const char pci_device_1119_0123[] = "GDT 6557RP2"; +static const char pci_device_1119_0124[] = "GDT 6111RP2/6511RP2"; +static const char pci_device_1119_0125[] = "GDT 6121RP2/6521RP2"; +static const char pci_device_1119_0136[] = "GDT 6113RS/6513RS"; +static const char pci_device_1119_0137[] = "GDT 6123RS/6523RS"; +static const char pci_device_1119_0138[] = "GDT 6118RS/6518RS/6618RS"; +static const char pci_device_1119_0139[] = "GDT 6128RS/6528RS/6628RS"; +static const char pci_device_1119_013a[] = "GDT 6538RS/6638RS"; +static const char pci_device_1119_013b[] = "GDT 6558RS/6658RS"; +static const char pci_device_1119_013c[] = "GDT 6533RS/6633RS"; +static const char pci_device_1119_013d[] = "GDT 6543RS/6643RS"; +static const char pci_device_1119_013e[] = "GDT 6553RS/6653RS"; +static const char pci_device_1119_013f[] = "GDT 6563RS/6663RS"; +static const char pci_device_1119_0166[] = "GDT 7113RN/7513RN/7613RN"; +static const char pci_device_1119_0167[] = "GDT 7123RN/7523RN/7623RN"; +static const char pci_device_1119_0168[] = "GDT 7118RN/7518RN/7518RN"; +static const char pci_device_1119_0169[] = "GDT 7128RN/7528RN/7628RN"; +static const char pci_device_1119_016a[] = "GDT 7538RN/7638RN"; +static const char pci_device_1119_016b[] = "GDT 7558RN/7658RN"; +static const char pci_device_1119_016c[] = "GDT 7533RN/7633RN"; +static const char pci_device_1119_016d[] = "GDT 7543RN/7643RN"; +static const char pci_device_1119_016e[] = "GDT 7553RN/7653RN"; +static const char pci_device_1119_016f[] = "GDT 7563RN/7663RN"; +static const char pci_device_1119_01d6[] = "GDT 4x13RZ"; +static const char pci_device_1119_01d7[] = "GDT 4x23RZ"; +static const char pci_device_1119_01f6[] = "GDT 8x13RZ"; +static const char pci_device_1119_01f7[] = "GDT 8x23RZ"; +static const char pci_device_1119_01fc[] = "GDT 8x33RZ"; +static const char pci_device_1119_01fd[] = "GDT 8x43RZ"; +static const char pci_device_1119_01fe[] = "GDT 8x53RZ"; +static const char pci_device_1119_01ff[] = "GDT 8x63RZ"; +static const char pci_device_1119_0210[] = "GDT 6519RD/6619RD"; +static const char pci_device_1119_0211[] = "GDT 6529RD/6629RD"; +static const char pci_device_1119_0260[] = "GDT 7519RN/7619RN"; +static const char pci_device_1119_0261[] = "GDT 7529RN/7629RN"; +static const char pci_device_1119_0300[] = "GDT Raid Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111a[] = "Efficient Networks, Inc"; +static const char pci_device_111a_0000[] = "155P-MF1 (FPGA)"; +static const char pci_device_111a_0002[] = "155P-MF1 (ASIC)"; +static const char pci_device_111a_0003[] = "ENI-25P ATM"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0003_111a_0000[] = "ENI-25p Miniport ATM Adapter"; +#endif +static const char pci_device_111a_0005[] = "SpeedStream (LANAI)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0001[] = "ENI-3010 ATM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0009[] = "ENI-3060 ADSL (VPI=0)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0101[] = "ENI-3010 ATM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0109[] = "ENI-3060CO ADSL (VPI=0)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0809[] = "ENI-3060 ADSL (VPI=0 or 8)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0909[] = "ENI-3060CO ADSL (VPI=0 or 8)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0a09[] = "ENI-3060 ADSL (VPI=<0..15>)"; +#endif +static const char pci_device_111a_0007[] = "SpeedStream ADSL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0007_111a_1001[] = "ENI-3061 ADSL [ASIC]"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111b[] = "Teledyne Electronic Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111c[] = "Tricord Systems Inc."; +static const char pci_device_111c_0001[] = "Powerbis Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111d[] = "Integrated Device Tech"; +static const char pci_device_111d_0001[] = "IDT77211 ATM Adapter"; +static const char pci_device_111d_0003[] = "IDT77252 ATM network controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111e[] = "Eldec"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111f[] = "Precision Digital Images"; +static const char pci_device_111f_4a47[] = "Precision MX Video engine interface"; +static const char pci_device_111f_5243[] = "Frame capture bus interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1120[] = "EMC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1121[] = "Zilog"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1122[] = "Multi-tech Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1123[] = "Excellent Design, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1124[] = "Leutron Vision AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1125[] = "Eurocore"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1126[] = "Vigra"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1127[] = "FORE Systems Inc"; +static const char pci_device_1127_0200[] = "ForeRunner PCA-200 ATM"; +static const char pci_device_1127_0210[] = "PCA-200PC"; +static const char pci_device_1127_0250[] = "ATM"; +static const char pci_device_1127_0300[] = "ForeRunner PCA-200EPC ATM"; +static const char pci_device_1127_0310[] = "ATM"; +static const char pci_device_1127_0400[] = "ForeRunnerHE ATM Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1127_0400_1127_0400[] = "ForeRunnerHE ATM"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1129[] = "Firmworks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112a[] = "Hermes Electronics Company, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112b[] = "Linotype - Hell AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112c[] = "Zenith Data Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112d[] = "Ravicad"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112e[] = "Infomedia Microelectronics Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112f[] = "Imaging Technology Inc"; +static const char pci_device_112f_0000[] = "MVC IC-PCI"; +static const char pci_device_112f_0001[] = "MVC IM-PCI Video frame grabber/processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1130[] = "Computervision"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1131[] = "Philips Semiconductors"; +static const char pci_device_1131_1561[] = "USB 1.1 Host Controller"; +static const char pci_device_1131_1562[] = "USB 2.0 Host Controller"; +static const char pci_device_1131_3400[] = "SmartPCI56(UCB1500) 56K Modem"; +static const char pci_device_1131_7130[] = "SAA7130 Video Broadcast Decoder"; +static const char pci_device_1131_7133[] = "SAA7133 Audio+video broadcast decoder"; +static const char pci_device_1131_7134[] = "SAA7134"; +static const char pci_device_1131_7135[] = "SAA7135 Audio+video broadcast decoder"; +static const char pci_device_1131_7145[] = "SAA7145"; +static const char pci_device_1131_7146[] = "SAA7146"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_114b_2003[] = "DVRaptor Video Edit/Capture Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_11bd_0006[] = "DV500 Overlay"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_11bd_000a[] = "DV500 Overlay"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1132[] = "Mitel Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1133[] = "Eicon Technology Corporation"; +static const char pci_device_1133_7901[] = "EiconCard S90"; +static const char pci_device_1133_7902[] = "EiconCard S90"; +static const char pci_device_1133_7911[] = "EiconCard S91"; +static const char pci_device_1133_7912[] = "EiconCard S91"; +static const char pci_device_1133_7941[] = "EiconCard S94"; +static const char pci_device_1133_7942[] = "EiconCard S94"; +static const char pci_device_1133_7943[] = "EiconCard S94"; +static const char pci_device_1133_7944[] = "EiconCard S94"; +static const char pci_device_1133_b921[] = "EiconCard P92"; +static const char pci_device_1133_b922[] = "EiconCard P92"; +static const char pci_device_1133_b923[] = "EiconCard P92"; +static const char pci_device_1133_e001[] = "DIVA 20PRO"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e001_1133_e001[] = "DIVA Pro 2.0 S/T"; +#endif +static const char pci_device_1133_e002[] = "DIVA 20"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e002_1133_e002[] = "DIVA 2.0 S/T"; +#endif +static const char pci_device_1133_e003[] = "DIVA 20PRO_U"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e003_1133_e003[] = "DIVA Pro 2.0 U"; +#endif +static const char pci_device_1133_e004[] = "DIVA 20_U"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e004_1133_e004[] = "DIVA 2.0 U"; +#endif +static const char pci_device_1133_e005[] = "DIVA LOW"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e005_1133_e005[] = "DIVA 2.01 S/T"; +#endif +static const char pci_device_1133_e00b[] = "DIVA 2.02"; +static const char pci_device_1133_e010[] = "DIVA Server BRI-2M"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e010_1133_e010[] = "DIVA Server BRI-2M"; +#endif +static const char pci_device_1133_e012[] = "DIVA Server BRI-8M"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e012_1133_e012[] = "DIVA Server BRI-8M"; +#endif +static const char pci_device_1133_e014[] = "DIVA Server PRI-30M"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e014_1133_e014[] = "DIVA Server PRI-30M"; +#endif +static const char pci_device_1133_e018[] = "DIVA Server BRI-2M/-2F"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1134[] = "Mercury Computer Systems"; +static const char pci_device_1134_0001[] = "Raceway Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1135[] = "Fuji Xerox Co Ltd"; +static const char pci_device_1135_0001[] = "Printer controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1136[] = "Momentum Data Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1137[] = "Cisco Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1138[] = "Ziatech Corporation"; +static const char pci_device_1138_8905[] = "8905 [STD 32 Bridge]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1139[] = "Dynamic Pictures, Inc"; +static const char pci_device_1139_0001[] = "VGA Compatable 3D Graphics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113a[] = "FWB Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113b[] = "Network Computing Devices"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113c[] = "Cyclone Microsystems, Inc."; +static const char pci_device_113c_0000[] = "PCI-9060 i960 Bridge"; +static const char pci_device_113c_0001[] = "PCI-SDK [PCI i960 Evaluation Platform]"; +static const char pci_device_113c_0911[] = "PCI-911 [i960Jx-based Intelligent I/O Controller]"; +static const char pci_device_113c_0912[] = "PCI-912 [i960CF-based Intelligent I/O Controller]"; +static const char pci_device_113c_0913[] = "PCI-913"; +static const char pci_device_113c_0914[] = "PCI-914 [I/O Controller w/ secondary PCI bus]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113d[] = "Leading Edge Products Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113e[] = "Sanyo Electric Co - Computer Engineering Dept"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113f[] = "Equinox Systems, Inc."; +static const char pci_device_113f_0808[] = "SST-64P Adapter"; +static const char pci_device_113f_1010[] = "SST-128P Adapter"; +static const char pci_device_113f_80c0[] = "SST-16P DB Adapter"; +static const char pci_device_113f_80c4[] = "SST-16P RJ Adapter"; +static const char pci_device_113f_80c8[] = "SST-16P Adapter"; +static const char pci_device_113f_8888[] = "SST-4P Adapter"; +static const char pci_device_113f_9090[] = "SST-8P Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1140[] = "Intervoice Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1141[] = "Crest Microsystem Inc"; +#endif +static const char pci_vendor_1142[] = "Alliance Semiconductor Corporation"; +static const char pci_device_1142_3210[] = "AP6410"; +static const char pci_device_1142_6422[] = "ProVideo 6422"; +static const char pci_device_1142_6424[] = "ProVideo 6424"; +static const char pci_device_1142_6425[] = "ProMotion AT25"; +static const char pci_device_1142_643d[] = "ProMotion AT3D"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1143[] = "NetPower, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1144[] = "Cincinnati Milacron"; +static const char pci_device_1144_0001[] = "Noservo controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1145[] = "Workbit Corporation"; +static const char pci_device_1145_8007[] = "NinjaSCSI-32 Workbit"; +static const char pci_device_1145_f007[] = "NinjaSCSI-32 KME"; +static const char pci_device_1145_f010[] = "NinjaSCSI-32 Workbit"; +static const char pci_device_1145_f012[] = "NinjaSCSI-32 Logitec"; +static const char pci_device_1145_f013[] = "NinjaSCSI-32 Logitec"; +static const char pci_device_1145_f015[] = "NinjaSCSI-32 Melco"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1146[] = "Force Computers"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1147[] = "Interface Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1148[] = "Syskonnect (Schneider & Koch)"; +static const char pci_device_1148_4000[] = "FDDI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03b[] = "Netelligent 100 FDDI DAS Fibre SC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03c[] = "Netelligent 100 FDDI SAS Fibre SC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03d[] = "Netelligent 100 FDDI DAS UTP"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03e[] = "Netelligent 100 FDDI SAS UTP"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03f[] = "Netelligent 100 FDDI SAS Fibre MIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5521[] = "FDDI SK-5521 (SK-NET FDDI-UP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5522[] = "FDDI SK-5522 (SK-NET FDDI-UP DAS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5541[] = "FDDI SK-5541 (SK-NET FDDI-FP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5543[] = "FDDI SK-5543 (SK-NET FDDI-LP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5544[] = "FDDI SK-5544 (SK-NET FDDI-LP DAS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5821[] = "FDDI SK-5821 (SK-NET FDDI-UP64)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5822[] = "FDDI SK-5822 (SK-NET FDDI-UP64 DAS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5841[] = "FDDI SK-5841 (SK-NET FDDI-FP64)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5843[] = "FDDI SK-5843 (SK-NET FDDI-LP64)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5844[] = "FDDI SK-5844 (SK-NET FDDI-LP64 DAS)"; +#endif +static const char pci_device_1148_4200[] = "Token Ring adapter"; +static const char pci_device_1148_4300[] = "Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9821[] = "SK-9821 (1000Base-T single link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9822[] = "SK-9822 (1000Base-T dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9841[] = "SK-9841 (1000Base-LX single link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9842[] = "SK-9842 (1000Base-LX dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9843[] = "SK-9843 (1000Base-SX single link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9844[] = "SK-9844 (1000Base-SX dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9861[] = "SK-9861 (1000Base-SX VF45 single link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9862[] = "SK-9862 (1000Base-SX VF45 dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9871[] = "SK-9871 (1000Base-ZX single link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9872[] = "SK-9872 (1000Base-ZX dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2970[] = "AT-2970SX [Allied Telesyn]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2972[] = "AT-2970T [Allied Telesyn]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2975[] = "AT-2970SX [Allied Telesyn]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2977[] = "AT-2970T [Allied Telesyn]"; +#endif +static const char pci_device_1148_4320[] = "SK-98xx Gigabit Ethernet Server Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5021[] = "SK-9821 V2.0 Gigabit Ethernet 10/100/1000Base-T Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5041[] = "SK-9841 V2.0 Gigabit Ethernet 1000Base-LX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5043[] = "SK-9843 V2.0 Gigabit Ethernet 1000Base-SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5051[] = "SK-9851 V2.0 Gigabit Ethernet 1000Base-SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5061[] = "SK-9861 V2.0 Gigabit Ethernet 1000Base-SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5071[] = "SK-9871 V2.0 Gigabit Ethernet 1000Base-ZX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_9521[] = "SK-9521 10/100/1000Base-T Adapter"; +#endif +static const char pci_device_1148_4400[] = "Gigabit Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1149[] = "Win System Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114a[] = "VMIC"; +static const char pci_device_114a_5579[] = "VMIPCI-5579 (Reflective Memory Card)"; +static const char pci_device_114a_5587[] = "VMIPCI-5587 (Reflective Memory Card)"; +static const char pci_device_114a_6504[] = "VMIC PCI 7755 FPGA"; +static const char pci_device_114a_7587[] = "VMIVME-7587"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114b[] = "Canopus Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114c[] = "Annabooks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114d[] = "IC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114e[] = "Nikon Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114f[] = "Digi International"; +static const char pci_device_114f_0002[] = "AccelePort EPC"; +static const char pci_device_114f_0003[] = "RightSwitch SE-6"; +static const char pci_device_114f_0004[] = "AccelePort Xem"; +static const char pci_device_114f_0005[] = "AccelePort Xr"; +static const char pci_device_114f_0006[] = "AccelePort Xr,C/X"; +static const char pci_device_114f_0009[] = "AccelePort Xr/J"; +static const char pci_device_114f_000a[] = "AccelePort EPC/J"; +static const char pci_device_114f_000c[] = "DataFirePRIme T1 (1-port)"; +static const char pci_device_114f_000d[] = "SyncPort 2-Port (x.25/FR)"; +static const char pci_device_114f_0011[] = "AccelePort 8r EIA-232 (IBM)"; +static const char pci_device_114f_0012[] = "AccelePort 8r EIA-422"; +static const char pci_device_114f_0013[] = "AccelePort Xr"; +static const char pci_device_114f_0014[] = "AccelePort 8r EIA-422"; +static const char pci_device_114f_0015[] = "AccelePort Xem"; +static const char pci_device_114f_0016[] = "AccelePort EPC/X"; +static const char pci_device_114f_0017[] = "AccelePort C/X"; +static const char pci_device_114f_001a[] = "DataFirePRIme E1 (1-port)"; +static const char pci_device_114f_001b[] = "AccelePort C/X (IBM)"; +static const char pci_device_114f_001d[] = "DataFire RAS T1/E1/PRI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_001d_114f_0050[] = "DataFire RAS E1 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_001d_114f_0051[] = "DataFire RAS Dual E1 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_001d_114f_0052[] = "DataFire RAS T1 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_001d_114f_0053[] = "DataFire RAS Dual T1 Adapter"; +#endif +static const char pci_device_114f_0023[] = "AccelePort RAS"; +static const char pci_device_114f_0024[] = "DataFire RAS B4 ST/U"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_0024_114f_0030[] = "DataFire RAS BRI U Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_0024_114f_0031[] = "DataFire RAS BRI S/T Adapter"; +#endif +static const char pci_device_114f_0026[] = "AccelePort 4r 920"; +static const char pci_device_114f_0027[] = "AccelePort Xr 920"; +static const char pci_device_114f_0034[] = "AccelePort 2r 920"; +static const char pci_device_114f_0035[] = "DataFire DSP T1/E1/PRI cPCI"; +static const char pci_device_114f_0040[] = "AccelePort Xp"; +static const char pci_device_114f_0042[] = "AccelePort 2p PCI"; +static const char pci_device_114f_0070[] = "Datafire Micro V IOM2 (Europe)"; +static const char pci_device_114f_0071[] = "Datafire Micro V (Europe)"; +static const char pci_device_114f_0072[] = "Datafire Micro V IOM2 (North America)"; +static const char pci_device_114f_0073[] = "Datafire Micro V (North America)"; +static const char pci_device_114f_6001[] = "Avanstar"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1150[] = "Thinking Machines Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1151[] = "JAE Electronics Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1152[] = "Megatek"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1153[] = "Land Win Electronic Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1154[] = "Melco Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1155[] = "Pine Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1156[] = "Periscope Engineering"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1157[] = "Avsys Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1158[] = "Voarx R & D Inc"; +static const char pci_device_1158_3011[] = "Tokenet/vg 1001/10m anylan"; +static const char pci_device_1158_9050[] = "Lanfleet/Truevalue"; +static const char pci_device_1158_9051[] = "Lanfleet/Truevalue"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1159[] = "Mutech Corp"; +static const char pci_device_1159_0001[] = "MV-1000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115a[] = "Harlequin Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115b[] = "Parallax Graphics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115c[] = "Photron Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115d[] = "Xircom"; +static const char pci_device_115d_0003[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1014_0181[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1014_1181[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1014_8181[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1014_9181[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_115d_0181[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_115d_1181[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1179_0181[] = "Cardbus Ethernet 10/100"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_8086_8181[] = "EtherExpress PRO/100 Mobile CardBus 32 Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_8086_9181[] = "EtherExpress PRO/100 Mobile CardBus 32 Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_115d_0005[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0005_1014_0182[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0005_1014_1182[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0005_115d_0182[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0005_115d_1182[] = "Cardbus Ethernet 10/100"; +#endif +static const char pci_device_115d_0007[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0007_1014_0182[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0007_1014_1182[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0007_115d_0182[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0007_115d_1182[] = "Cardbus Ethernet 10/100"; +#endif +static const char pci_device_115d_000b[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_000b_1014_0183[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_000b_115d_0183[] = "Cardbus Ethernet 10/100"; +#endif +static const char pci_device_115d_000c[] = "Mini-PCI V.90 56k Modem"; +static const char pci_device_115d_000f[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_000f_1014_0183[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_000f_115d_0183[] = "Cardbus Ethernet 10/100"; +#endif +static const char pci_device_115d_0101[] = "Cardbus 56k modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0101_115d_1081[] = "Cardbus 56k Modem"; +#endif +static const char pci_device_115d_0103[] = "Cardbus Ethernet + 56k Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0103_1014_9181[] = "Cardbus 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0103_1115_1181[] = "Cardbus Ethernet 100 + 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0103_115d_1181[] = "CBEM56G-100 Ethernet + 56k Modem"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0103_8086_9181[] = "PRO/100 LAN + Modem56 CardBus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115e[] = "Peer Protocols Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115f[] = "Maxtor Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1160[] = "Megasoft Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1161[] = "PFU Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1162[] = "OA Laboratory Co Ltd"; +#endif +static const char pci_vendor_1163[] = "Rendition"; +static const char pci_device_1163_0001[] = "Verite 1000"; +static const char pci_device_1163_2000[] = "Verite V2000/V2100/V2200"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1163_2000_1092_2000[] = "Stealth II S220"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1164[] = "Advanced Peripherals Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1165[] = "Imagraph Corporation"; +static const char pci_device_1165_0001[] = "Motion TPEG Recorder/Player with audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1166[] = "ServerWorks"; +static const char pci_device_1166_0005[] = "CNB20-LE Host Bridge"; +static const char pci_device_1166_0007[] = "CNB20-LE Host Bridge"; +static const char pci_device_1166_0008[] = "CNB20HE Host Bridge"; +static const char pci_device_1166_0009[] = "CNB20LE Host Bridge"; +static const char pci_device_1166_0010[] = "CIOB30"; +static const char pci_device_1166_0011[] = "CMIC-HE"; +static const char pci_device_1166_0012[] = "CMIC-LE"; +static const char pci_device_1166_0013[] = "CNB20-HE Host Bridge"; +static const char pci_device_1166_0014[] = "CNB20-HE Host Bridge"; +static const char pci_device_1166_0015[] = "CMIC-GC Host Bridge"; +static const char pci_device_1166_0016[] = "CMIC-GC Host Bridge"; +static const char pci_device_1166_0017[] = "GCNB-LE Host Bridge"; +static const char pci_device_1166_0200[] = "OSB4 South Bridge"; +static const char pci_device_1166_0201[] = "CSB5 South Bridge"; +static const char pci_device_1166_0203[] = "CSB6 South Bridge"; +static const char pci_device_1166_0211[] = "OSB4 IDE Controller"; +static const char pci_device_1166_0212[] = "CSB5 IDE Controller"; +static const char pci_device_1166_0213[] = "CSB6 RAID/IDE Controller"; +static const char pci_device_1166_0220[] = "OSB4/CSB5 OHCI USB Controller"; +static const char pci_device_1166_0221[] = "CSB6 OHCI USB Controller"; +static const char pci_device_1166_0225[] = "GCLE Host Bridge"; +static const char pci_device_1166_0227[] = "GCLE-2 Host Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1167[] = "Mutoh Industries Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1168[] = "Thine Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1169[] = "Centre for Development of Advanced Computing"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116a[] = "Polaris Communications"; +static const char pci_device_116a_6100[] = "Bus/Tag Channel"; +static const char pci_device_116a_6800[] = "Escon Channel"; +static const char pci_device_116a_7100[] = "Bus/Tag Channel"; +static const char pci_device_116a_7800[] = "Escon Channel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116b[] = "Connectware Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116c[] = "Intelligent Resources Integrated Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116d[] = "Martin-Marietta"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116e[] = "Electronics for Imaging"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116f[] = "Workstation Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1170[] = "Inventec Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1171[] = "Loughborough Sound Images Plc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1172[] = "Altera Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1173[] = "Adobe Systems, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1174[] = "Bridgeport Machines"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1175[] = "Mitron Computer Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1176[] = "SBE Incorporated"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1177[] = "Silicon Engineering"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1178[] = "Alfa, Inc."; +static const char pci_device_1178_afa1[] = "Fast Ethernet Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1179[] = "Toshiba America Info Systems"; +static const char pci_device_1179_0103[] = "EX-IDE Type-B"; +static const char pci_device_1179_0404[] = "DVD Decoder card"; +static const char pci_device_1179_0406[] = "Tecra Video Capture device"; +static const char pci_device_1179_0407[] = "DVD Decoder card (Version 2)"; +static const char pci_device_1179_0601[] = "601"; +static const char pci_device_1179_0603[] = "ToPIC95 PCI to CardBus Bridge for Notebooks"; +static const char pci_device_1179_060a[] = "ToPIC95"; +static const char pci_device_1179_060f[] = "ToPIC97"; +static const char pci_device_1179_0617[] = "ToPIC95 PCI to Cardbus Bridge with ZV Support"; +static const char pci_device_1179_0618[] = "CPU to PCI and PCI to ISA bridge"; +static const char pci_device_1179_0701[] = "FIR Port"; +static const char pci_device_1179_0804[] = "TC6371AF SmartMedia Controller"; +static const char pci_device_1179_0805[] = "SD TypA Controller"; +static const char pci_device_1179_0d01[] = "FIR Port Type-DO"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1179_0d01_1179_0001[] = "FIR Port Type-DO"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117a[] = "A-Trend Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117b[] = "L G Electronics, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117c[] = "Atto Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117d[] = "Becton & Dickinson"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117e[] = "T/R Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117f[] = "Integrated Circuit Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1180[] = "Ricoh Co Ltd"; +static const char pci_device_1180_0465[] = "RL5c465"; +static const char pci_device_1180_0466[] = "RL5c466"; +static const char pci_device_1180_0475[] = "RL5c475"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0475_144d_c006[] = "vpr Matrix 170B4 CardBus bridge"; +#endif +static const char pci_device_1180_0476[] = "RL5c476 II"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_1014_0185[] = "ThinkPad A/T/X Series"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1180_0477[] = "RL5c477"; +static const char pci_device_1180_0478[] = "RL5c478"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0478_1014_0184[] = "ThinkPad A30p (2653-64G)"; +#endif +static const char pci_device_1180_0522[] = "R5C522 IEEE 1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0522_1014_01cf[] = "ThinkPad A30p (2653-64G)"; +#endif +static const char pci_device_1180_0551[] = "R5C551 IEEE 1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0551_144d_c006[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_1180_0552[] = "R5C552 IEEE 1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0552_1014_0511[] = "ThinkPad A/T/X Series"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1181[] = "Telmatics International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1183[] = "Fujikura Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1184[] = "Forks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1185[] = "Dataworld International Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1186[] = "D-Link System Inc"; +static const char pci_device_1186_0100[] = "DC21041"; +static const char pci_device_1186_1002[] = "DL10050 Sundance Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1002_1186_1002[] = "DFE-550TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1002_1186_1012[] = "DFE-580TX"; +#endif +static const char pci_device_1186_1300[] = "RTL8139 Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1300_1186_1300[] = "DFE-538TX 10/100 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1300_1186_1301[] = "DFE-530TX+ 10/100 Ethernet Adapter"; +#endif +static const char pci_device_1186_1340[] = "DFE-690TXD CardBus PC Card"; +static const char pci_device_1186_1561[] = "DRP-32TXD Cardbus PC Card"; +static const char pci_device_1186_4000[] = "DL2K Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1187[] = "Advanced Technology Laboratories, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1188[] = "Shima Seiki Manufacturing Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1189[] = "Matsushita Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118a[] = "Hilevel Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118b[] = "Hypertec Pty Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118c[] = "Corollary, Inc"; +static const char pci_device_118c_0014[] = "PCIB [C-bus II to PCI bus host bridge chip]"; +static const char pci_device_118c_1117[] = "Intel 8-way XEON Profusion Chipset [Cache Coherency Filter]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118d[] = "BitFlow Inc"; +static const char pci_device_118d_0001[] = "Raptor-PCI framegrabber"; +static const char pci_device_118d_0012[] = "Model 12 Road Runner Frame Grabber"; +static const char pci_device_118d_0014[] = "Model 14 Road Runner Frame Grabber"; +static const char pci_device_118d_0024[] = "Model 24 Road Runner Frame Grabber"; +static const char pci_device_118d_0044[] = "Model 44 Road Runner Frame Grabber"; +static const char pci_device_118d_0112[] = "Model 12 Road Runner Frame Grabber"; +static const char pci_device_118d_0114[] = "Model 14 Road Runner Frame Grabber"; +static const char pci_device_118d_0124[] = "Model 24 Road Runner Frame Grabber"; +static const char pci_device_118d_0144[] = "Model 44 Road Runner Frame Grabber"; +static const char pci_device_118d_0212[] = "Model 12 Road Runner Frame Grabber"; +static const char pci_device_118d_0214[] = "Model 14 Road Runner Frame Grabber"; +static const char pci_device_118d_0224[] = "Model 24 Road Runner Frame Grabber"; +static const char pci_device_118d_0244[] = "Model 44 Road Runner Frame Grabber"; +static const char pci_device_118d_0312[] = "Model 12 Road Runner Frame Grabber"; +static const char pci_device_118d_0314[] = "Model 14 Road Runner Frame Grabber"; +static const char pci_device_118d_0324[] = "Model 24 Road Runner Frame Grabber"; +static const char pci_device_118d_0344[] = "Model 44 Road Runner Frame Grabber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118e[] = "Hermstedt GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118f[] = "Green Logic"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1190[] = "Tripace"; +static const char pci_device_1190_c731[] = "TP-910/920/940 PCI Ultra(Wide) SCSI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1191[] = "Artop Electronic Corp"; +static const char pci_device_1191_0003[] = "SCSI Cache Host Adapter"; +static const char pci_device_1191_0004[] = "ATP8400"; +static const char pci_device_1191_0005[] = "ATP850UF"; +static const char pci_device_1191_0006[] = "ATP860 NO-BIOS"; +static const char pci_device_1191_0007[] = "ATP860"; +static const char pci_device_1191_0008[] = "ATP865 NO-ROM"; +static const char pci_device_1191_0009[] = "ATP865"; +static const char pci_device_1191_8002[] = "AEC6710 SCSI-2 Host Adapter"; +static const char pci_device_1191_8010[] = "AEC6712UW SCSI"; +static const char pci_device_1191_8020[] = "AEC6712U SCSI"; +static const char pci_device_1191_8030[] = "AEC6712S SCSI"; +static const char pci_device_1191_8040[] = "AEC6712D SCSI"; +static const char pci_device_1191_8050[] = "AEC6712SUW SCSI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1192[] = "Densan Company Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1193[] = "Zeitnet Inc."; +static const char pci_device_1193_0001[] = "1221"; +static const char pci_device_1193_0002[] = "1225"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1194[] = "Toucan Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1195[] = "Ratoc System Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1196[] = "Hytec Electronics Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1197[] = "Gage Applied Sciences, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1198[] = "Lambda Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1199[] = "Attachmate Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119a[] = "Mind Share, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119b[] = "Omega Micro Inc."; +static const char pci_device_119b_1221[] = "82C092G"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119c[] = "Information Technology Inst."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119d[] = "Bug, Inc. Sapporo Japan"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119e[] = "Fujitsu Microelectronics Ltd."; +static const char pci_device_119e_0001[] = "FireStream 155"; +static const char pci_device_119e_0003[] = "FireStream 50"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119f[] = "Bull HN Information Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a0[] = "Convex Computer Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a1[] = "Hamamatsu Photonics K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a2[] = "Sierra Research and Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a3[] = "Deuretzbacher GmbH & Co. Eng. KG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a4[] = "Barco Graphics NV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a5[] = "Microunity Systems Eng. Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a6[] = "Pure Data Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a7[] = "Power Computing Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a8[] = "Systech Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a9[] = "InnoSys Inc."; +static const char pci_device_11a9_4240[] = "AMCC S933Q Intelligent Serial Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11aa[] = "Actel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ab[] = "Galileo Technology Ltd."; +static const char pci_device_11ab_0146[] = "GT-64010/64010A System Controller"; +static const char pci_device_11ab_4611[] = "GT-64115 System Controller"; +static const char pci_device_11ab_4620[] = "GT-64120/64120A/64121A System Controller"; +static const char pci_device_11ab_4801[] = "GT-48001"; +static const char pci_device_11ab_f003[] = "GT-64010 Primary Image Piranha Image Generator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ac[] = "Canon Information Systems Research Aust."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ad[] = "Lite-On Communications Inc"; +static const char pci_device_11ad_0002[] = "LNE100TX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_11ad_0002[] = "LNE100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_11ad_0003[] = "LNE100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_11ad_f003[] = "LNE100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_11ad_ffff[] = "LNE100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_1385_f004[] = "FA310TX"; +#endif +static const char pci_device_11ad_c115[] = "LNE100TX [Linksys EtherFast 10/100]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_c115_11ad_c001[] = "LNE100TX [ver 2.0]"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ae[] = "Aztech System Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11af[] = "Avid Technology Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b0[] = "V3 Semiconductor Inc."; +static const char pci_device_11b0_0002[] = "V300PSC"; +static const char pci_device_11b0_0292[] = "V292PBC [Am29030/40 Bridge]"; +static const char pci_device_11b0_0960[] = "V96xPBC"; +static const char pci_device_11b0_c960[] = "V96DPC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b1[] = "Apricot Computers"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b2[] = "Eastman Kodak"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b3[] = "Barr Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b4[] = "Leitch Technology International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b5[] = "Radstone Technology Plc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b6[] = "United Video Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b7[] = "Motorola"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b8[] = "XPoint Technologies, Inc"; +static const char pci_device_11b8_0001[] = "Quad PeerMaster"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b9[] = "Pathlight Technology Inc."; +static const char pci_device_11b9_c0ed[] = "SSA Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ba[] = "Videotron Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11bb[] = "Pyramid Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11bc[] = "Network Peripherals Inc"; +static const char pci_device_11bc_0001[] = "NP-PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11bd[] = "Pinnacle Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11be[] = "International Microcircuits Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11bf[] = "Astrodesign, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c0[] = "Hewlett Packard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c1[] = "Lucent Microelectronics"; +static const char pci_device_11c1_0440[] = "56k WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_1033_8015[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_1033_8047[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_1033_804f[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_10cf_102c[] = "LB LT Modem V.90 56k"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_10cf_104a[] = "BIBLO LT Modem 56k"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_10cf_105f[] = "LB2 LT Modem V.90 56k"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_1179_0001[] = "Internal V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_11c1_0440[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_122d_4101[] = "MDP7800-U Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_122d_4102[] = "MDP7800SP-U Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_0040[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_0440[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_0441[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_0450[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_f100[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_f101[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_144d_2101[] = "LT56PV Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_149f_0440[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +static const char pci_device_11c1_0441[] = "56k WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1033_804d[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1033_8065[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1092_0440[] = "Supra 56i"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1179_0001[] = "Internal V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_11c1_0440[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_11c1_0441[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_122d_4100[] = "MDP7800-U Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0040[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0100[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0410[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0420[] = "TelePath Internet 56k WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0440[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0443[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_f102[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1416_9804[] = "CommWave 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_141d_0440[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_144f_0441[] = "Lucent 56k V.90 DF Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_144f_0449[] = "Lucent 56k V.90 DF Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_144f_110d[] = "Lucent Win Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1468_0441[] = "Presario 56k V.90 DF Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1668_0440[] = "Lucent Win Modem"; +#endif +static const char pci_device_11c1_0442[] = "56k WinModem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_11c1_0440[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_11c1_0442[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_13e0_0412[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_13e0_0442[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_13fc_2471[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_144d_2104[] = "LT56PT Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_144f_1104[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_149f_0440[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_1668_0440[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +static const char pci_device_11c1_0443[] = "LT WinModem"; +static const char pci_device_11c1_0444[] = "LT WinModem"; +static const char pci_device_11c1_0445[] = "LT WinModem"; +static const char pci_device_11c1_0446[] = "LT WinModem"; +static const char pci_device_11c1_0447[] = "LT WinModem"; +static const char pci_device_11c1_0448[] = "WinModem 56k"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_1014_0131[] = "Lucent Win Modem"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_1033_8066[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_13e0_0030[] = "56k Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_13e0_0040[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_1668_2400[] = "LT WinModem 56k (MiniPCI Ethernet+Modem)"; +#endif +static const char pci_device_11c1_0449[] = "WinModem 56k"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_0e11_b14d[] = "56k V.90 Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_13e0_0020[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_13e0_0041[] = "TelePath Internet 56k WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_1436_0440[] = "Lucent Win Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_144f_0449[] = "Lucent 56k V.90 DFi Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_1468_0410[] = "IBM ThinkPad T23 (2647-4MG)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_1468_0440[] = "Lucent Win Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_1468_0449[] = "Presario 56k V.90 DFi Modem"; +#endif +static const char pci_device_11c1_044a[] = "F-1156IV WinModem (V90, 56KFlex)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_044a_10cf_1072[] = "LB Global LT Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_044a_13e0_0012[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_044a_13e0_0042[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_044a_144f_1005[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +static const char pci_device_11c1_044b[] = "LT WinModem"; +static const char pci_device_11c1_044c[] = "LT WinModem"; +static const char pci_device_11c1_044d[] = "LT WinModem"; +static const char pci_device_11c1_044e[] = "LT WinModem"; +static const char pci_device_11c1_044f[] = "V90 WildWire Modem"; +static const char pci_device_11c1_0450[] = "LT WinModem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0450_144f_4005[] = "Magnia SG20"; +#endif +static const char pci_device_11c1_0451[] = "LT WinModem"; +static const char pci_device_11c1_0452[] = "LT WinModem"; +static const char pci_device_11c1_0453[] = "LT WinModem"; +static const char pci_device_11c1_0454[] = "LT WinModem"; +static const char pci_device_11c1_0455[] = "LT WinModem"; +static const char pci_device_11c1_0456[] = "LT WinModem"; +static const char pci_device_11c1_0457[] = "LT WinModem"; +static const char pci_device_11c1_0458[] = "LT WinModem"; +static const char pci_device_11c1_0459[] = "LT WinModem"; +static const char pci_device_11c1_045a[] = "LT WinModem"; +static const char pci_device_11c1_045c[] = "LT WinModem"; +static const char pci_device_11c1_0461[] = "V90 WildWire Modem"; +static const char pci_device_11c1_0462[] = "V90 WildWire Modem"; +static const char pci_device_11c1_0480[] = "Venus Modem (V90, 56KFlex)"; +static const char pci_device_11c1_5801[] = "USB"; +static const char pci_device_11c1_5802[] = "USS-312 USB Controller"; +static const char pci_device_11c1_5803[] = "USS-344S USB Controller"; +static const char pci_device_11c1_5811[] = "FW323"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_5811_dead_0800[] = "FireWire Host Bus Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c2[] = "Sand Microelectronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c3[] = "NEC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c4[] = "Document Technologies, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c5[] = "Shiva Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c6[] = "Dainippon Screen Mfg. Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c7[] = "D.C.M. Data Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c8[] = "Dolphin Interconnect Solutions AS"; +static const char pci_device_11c8_0658[] = "PSB32 SCI-Adapter D31x"; +static const char pci_device_11c8_d665[] = "PSB64 SCI-Adapter D32x"; +static const char pci_device_11c8_d667[] = "PSB66 SCI-Adapter D33x"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c9[] = "Magma"; +static const char pci_device_11c9_0010[] = "16-line serial port w/- DMA"; +static const char pci_device_11c9_0011[] = "4-line serial port w/- DMA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ca[] = "LSI Systems, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11cb[] = "Specialix Research Ltd."; +static const char pci_device_11cb_2000[] = "PCI_9050"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11cb_2000_11cb_0200[] = "SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11cb_2000_11cb_b008[] = "I/O8+"; +#endif +static const char pci_device_11cb_4000[] = "SUPI_1"; +static const char pci_device_11cb_8000[] = "T225"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11cc[] = "Michels & Kleberhoff Computer GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11cd[] = "HAL Computer Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ce[] = "Netaccess"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11cf[] = "Pioneer Electronic Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d0[] = "Lockheed Martin Federal Systems-Manassas"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d1[] = "Auravision"; +static const char pci_device_11d1_01f7[] = "VxP524"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d2[] = "Intercom Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d3[] = "Trancell Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d4[] = "Analog Devices"; +static const char pci_device_11d4_1805[] = "SM56 PCI modem"; +static const char pci_device_11d4_1889[] = "AD1889 sound chip"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d5[] = "Ikon Corporation"; +static const char pci_device_11d5_0115[] = "10115"; +static const char pci_device_11d5_0117[] = "10117"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d6[] = "Tekelec Telecom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d7[] = "Trenton Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d8[] = "Image Technologies Development"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d9[] = "TEC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11da[] = "Novell"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11db[] = "Sega Enterprises Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11dc[] = "Questra Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11dd[] = "Crosfield Electronics Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11de[] = "Zoran Corporation"; +static const char pci_device_11de_6057[] = "ZR36057PQC Video cutting chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6057_1031_7efe[] = "DC10 Plus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6057_1031_fc00[] = "MiroVIDEO DC50, Motion JPEG Capture/CODEC Board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6057_13ca_4231[] = "JPEG/TV Card"; +#endif +static const char pci_device_11de_6120[] = "ZR36120"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6120_1328_f001[] = "Cinemaster C DVD Decoder"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11df[] = "New Wave PDG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e0[] = "Cray Communications A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e1[] = "GEC Plessey Semi Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e2[] = "Samsung Information Systems America"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e3[] = "Quicklogic Corporation"; +static const char pci_device_11e3_5030[] = "PC Watchdog"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e4[] = "Second Wave Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e5[] = "IIX Consulting"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e6[] = "Mitsui-Zosen System Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e7[] = "Toshiba America, Elec. Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e8[] = "Digital Processing Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e9[] = "Highwater Designs Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ea[] = "Elsag Bailey"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11eb[] = "Formation Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ec[] = "Coreco Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ed[] = "Mediamatics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ee[] = "Dome Imaging Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ef[] = "Nicolet Technologies B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f0[] = "Compu-Shack"; +static const char pci_device_11f0_4231[] = "FDDI"; +static const char pci_device_11f0_4232[] = "FASTline UTP Quattro"; +static const char pci_device_11f0_4233[] = "FASTline FO"; +static const char pci_device_11f0_4234[] = "FASTline UTP"; +static const char pci_device_11f0_4235[] = "FASTline-II UTP"; +static const char pci_device_11f0_4236[] = "FASTline-II FO"; +static const char pci_device_11f0_4731[] = "GIGAline"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f1[] = "Symbios Logic Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f2[] = "Picture Tel Japan K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f3[] = "Keithley Metrabyte"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f4[] = "Kinetic Systems Corporation"; +static const char pci_device_11f4_2915[] = "CAMAC controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f5[] = "Computing Devices International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f6[] = "Compex"; +static const char pci_device_11f6_0112[] = "ENet100VG4"; +static const char pci_device_11f6_0113[] = "FreedomLine 100"; +static const char pci_device_11f6_1401[] = "ReadyLink 2000"; +static const char pci_device_11f6_2011[] = "RL100-ATX 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11f6_2011_11f6_2011[] = "RL100-ATX"; +#endif +static const char pci_device_11f6_2201[] = "ReadyLink 100TX (Winbond W89C840)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11f6_2201_11f6_2011[] = "ReadyLink 100TX"; +#endif +static const char pci_device_11f6_9881[] = "RL100TX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f7[] = "Scientific Atlanta"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f8[] = "PMC-Sierra Inc."; +static const char pci_device_11f8_7375[] = "PM7375 [LASAR-155 ATM SAR]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f9[] = "I-Cube Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fa[] = "Kasan Electronics Company, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fb[] = "Datel Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fc[] = "Silicon Magic"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fd[] = "High Street Consultants"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fe[] = "Comtrol Corporation"; +static const char pci_device_11fe_0001[] = "RocketPort 8 Oct"; +static const char pci_device_11fe_0002[] = "RocketPort 8 Intf"; +static const char pci_device_11fe_0003[] = "RocketPort 16 Intf"; +static const char pci_device_11fe_0004[] = "RocketPort 32 Intf"; +static const char pci_device_11fe_0005[] = "RocketPort Octacable"; +static const char pci_device_11fe_0006[] = "RocketPort 8J"; +static const char pci_device_11fe_0007[] = "RocketPort 4-port"; +static const char pci_device_11fe_0008[] = "RocketPort 8-port"; +static const char pci_device_11fe_0009[] = "RocketPort 16-port"; +static const char pci_device_11fe_000a[] = "RocketPort Plus Quadcable"; +static const char pci_device_11fe_000b[] = "RocketPort Plus Octacable"; +static const char pci_device_11fe_000c[] = "RocketPort 8-port Modem"; +static const char pci_device_11fe_8015[] = "RocketPort 4-port UART 16954"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ff[] = "Scion Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1200[] = "CSS Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1201[] = "Vista Controls Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1202[] = "Network General Corp."; +static const char pci_device_1202_4300[] = "Gigabit Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1202_4300_1202_9841[] = "SK-9841 LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1202_4300_1202_9842[] = "SK-9841 LX dual link"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1202_4300_1202_9843[] = "SK-9843 SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1202_4300_1202_9844[] = "SK-9843 SX dual link"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1203[] = "Bayer Corporation, Agfa Division"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1204[] = "Lattice Semiconductor Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1205[] = "Array Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1206[] = "Amdahl Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1208[] = "Parsytec GmbH"; +static const char pci_device_1208_4853[] = "HS-Link Device"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1209[] = "SCI Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120a[] = "Synaptel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120b[] = "Adaptive Solutions"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120c[] = "Technical Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120d[] = "Compression Labs, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120e[] = "Cyclades Corporation"; +static const char pci_device_120e_0100[] = "Cyclom-Y below first megabyte"; +static const char pci_device_120e_0101[] = "Cyclom-Y above first megabyte"; +static const char pci_device_120e_0102[] = "Cyclom-4Y below first megabyte"; +static const char pci_device_120e_0103[] = "Cyclom-4Y above first megabyte"; +static const char pci_device_120e_0104[] = "Cyclom-8Y below first megabyte"; +static const char pci_device_120e_0105[] = "Cyclom-8Y above first megabyte"; +static const char pci_device_120e_0200[] = "Cyclades-Z below first megabyte"; +static const char pci_device_120e_0201[] = "Cyclades-Z above first megabyte"; +static const char pci_device_120e_0300[] = "PC300/RSV or /X21 (2 ports)"; +static const char pci_device_120e_0301[] = "PC300/RSV or /X21 (1 port)"; +static const char pci_device_120e_0310[] = "PC300/TE (2 ports)"; +static const char pci_device_120e_0311[] = "PC300/TE (1 port)"; +static const char pci_device_120e_0320[] = "PC300/TE-M (2 ports)"; +static const char pci_device_120e_0321[] = "PC300/TE-M (1 port)"; +static const char pci_device_120e_0400[] = "PC400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120f[] = "Essential Communications"; +static const char pci_device_120f_0001[] = "Roadrunner serial HIPPI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1210[] = "Hyperparallel Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1211[] = "Braintech Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1212[] = "Kingston Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1213[] = "Applied Intelligent Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1214[] = "Performance Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1215[] = "Interware Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1216[] = "Purup Prepress A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1217[] = "O2 Micro, Inc."; +static const char pci_device_1217_6729[] = "OZ6729"; +static const char pci_device_1217_673a[] = "OZ6730"; +static const char pci_device_1217_6832[] = "OZ6832/6833 Cardbus Controller"; +static const char pci_device_1217_6836[] = "OZ6836/6860 Cardbus Controller"; +static const char pci_device_1217_6872[] = "OZ6812 Cardbus Controller"; +static const char pci_device_1217_6925[] = "OZ6922 Cardbus Controller"; +static const char pci_device_1217_6933[] = "OZ6933 Cardbus Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_6933_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1217_6972[] = "OZ6912 Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_6972_1179_0001[] = "Magnia Z310"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1218[] = "Hybricon Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1219[] = "First Virtual Corporation"; +#endif +static const char pci_vendor_121a[] = "3Dfx Interactive, Inc."; +static const char pci_device_121a_0001[] = "Voodoo"; +static const char pci_device_121a_0002[] = "Voodoo 2"; +static const char pci_device_121a_0003[] = "Voodoo Banshee"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_0003[] = "Monster Fusion"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_4000[] = "Monster Fusion"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_4002[] = "Monster Fusion"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_4801[] = "Monster Fusion AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_4803[] = "Monster Fusion AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_8030[] = "Monster Fusion"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_8035[] = "Monster Fusion AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_10b0_0001[] = "Dragon 4000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1102_1018[] = "3D Blaster Banshee VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_121a_0001[] = "Voodoo Banshee AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_121a_0003[] = "Voodoo Banshee AGP SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_121a_0004[] = "Voodoo Banshee"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_139c_0016[] = "Raven"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_139c_0017[] = "Raven"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_14af_0002[] = "Maxi Gamer Phoenix"; +#endif +static const char pci_device_121a_0004[] = "Voodoo Banshee [Velocity 100]"; +static const char pci_device_121a_0005[] = "Voodoo 3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0004[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0030[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0031[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0034[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0036[] = "Voodoo3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0037[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0038[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_003a[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0044[] = "Voodoo3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_004b[] = "Velocity 100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_004c[] = "Velocity 200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_004d[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_004e[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0051[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0052[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0060[] = "Voodoo3 3500 TV (NTSC)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0061[] = "Voodoo3 3500 TV (PAL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0062[] = "Voodoo3 3500 TV (SECAM)"; +#endif +static const char pci_device_121a_0009[] = "Voodoo 4 / Voodoo 5"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0009_121a_0009[] = "Voodoo5 AGP 5500/6000"; +#endif +static const char pci_device_121a_0057[] = "Voodoo 3/3000 [Avenger]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121b[] = "Advanced Telecommunications Modules"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121c[] = "Nippon Texaco., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121d[] = "Lippert Automationstechnik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121e[] = "CSPI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121f[] = "Arcus Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1220[] = "Ariel Corporation"; +static const char pci_device_1220_1220[] = "AMCC 5933 TMS320C80 DSP/Imaging board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1221[] = "Contec Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1222[] = "Ancor Communications, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1223[] = "Artesyn Communication Products"; +static const char pci_device_1223_0003[] = "PM/Link"; +static const char pci_device_1223_0004[] = "PM/T1"; +static const char pci_device_1223_0005[] = "PM/E1"; +static const char pci_device_1223_0008[] = "PM/SLS"; +static const char pci_device_1223_0009[] = "BajaSpan Resource Target"; +static const char pci_device_1223_000a[] = "BajaSpan Section 0"; +static const char pci_device_1223_000b[] = "BajaSpan Section 1"; +static const char pci_device_1223_000c[] = "BajaSpan Section 2"; +static const char pci_device_1223_000d[] = "BajaSpan Section 3"; +static const char pci_device_1223_000e[] = "PM/PPC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1224[] = "Interactive Images"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1225[] = "Power I/O, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1227[] = "Tech-Source"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1228[] = "Norsk Elektro Optikk A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1229[] = "Data Kinesis Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122a[] = "Integrated Telecom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122b[] = "LG Industrial Systems Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122c[] = "Sican GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122d[] = "Aztech System Ltd"; +static const char pci_device_122d_1206[] = "368DSP"; +static const char pci_device_122d_50dc[] = "3328 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_122d_50dc_122d_0001[] = "3328 Audio"; +#endif +static const char pci_device_122d_80da[] = "3328 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_122d_80da_122d_0001[] = "3328 Audio"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122e[] = "Xyratex"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122f[] = "Andrew Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1230[] = "Fishcamp Engineering"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1231[] = "Woodward McCoach, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1232[] = "GPT Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1233[] = "Bus-Tech, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1234[] = "Technical Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1235[] = "Risq Modular Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1236[] = "Sigma Designs Corporation"; +static const char pci_device_1236_0000[] = "RealMagic64/GX"; +static const char pci_device_1236_6401[] = "REALmagic 64/GX (SD 6425)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1237[] = "Alta Technology Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1238[] = "Adtran"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1239[] = "3DO Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123a[] = "Visicom Laboratories, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123b[] = "Seeq Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123c[] = "Century Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123d[] = "Engineering Design Team, Inc."; +static const char pci_device_123d_0000[] = "EasyConnect 8/32"; +static const char pci_device_123d_0002[] = "EasyConnect 8/64"; +static const char pci_device_123d_0003[] = "EasyIO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123e[] = "Simutech, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123f[] = "C-Cube Microsystems"; +static const char pci_device_123f_00e4[] = "MPEG"; +static const char pci_device_123f_8120[] = "E4?"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8120_11bd_0006[] = "DV500 E4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8120_11bd_000a[] = "DV500 E4"; +#endif +static const char pci_device_123f_8888[] = "Cinemaster C 3.0 DVD Decoder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8888_1002_0001[] = "Cinemaster C 3.0 DVD Decoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8888_1002_0002[] = "Cinemaster C 3.0 DVD Decoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8888_1328_0001[] = "Cinemaster C 3.0 DVD Decoder"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1240[] = "Marathon Technologies Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1241[] = "DSC Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1242[] = "JNI Corporation"; +static const char pci_device_1242_1560[] = "JNIC-1560 PCI-X Fibre Channel Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1242_1560_1242_6562[] = "FCX2-6562 Dual Channel PCI-X Fibre Channel Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1242_1560_1242_656a[] = "FCX-6562 PCI-X Fibre Channel Adapter"; +#endif +static const char pci_device_1242_4643[] = "FCI-1063 Fibre Channel Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1243[] = "Delphax"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1244[] = "AVM Audiovisuelles MKTG & Computer System GmbH"; +static const char pci_device_1244_0700[] = "B1 ISDN"; +static const char pci_device_1244_0800[] = "C4 ISDN"; +static const char pci_device_1244_0a00[] = "A1 ISDN [Fritz]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1244_0a00_1244_0a00[] = "FRITZ!Card ISDN Controller"; +#endif +static const char pci_device_1244_0e00[] = "Fritz!PCI v2.0 ISDN"; +static const char pci_device_1244_1100[] = "C2 ISDN"; +static const char pci_device_1244_1200[] = "T1 ISDN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1245[] = "A.P.D., S.A."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1246[] = "Dipix Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1247[] = "Xylon Research, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1248[] = "Central Data Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1249[] = "Samsung Electronics Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124a[] = "AEG Electrocom GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124b[] = "SBS/Greenspring Modular I/O"; +static const char pci_device_124b_0040[] = "PCI-40A or cPCI-200 Quad IndustryPack carrier"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_124b_0040_124b_9080[] = "PCI9080 Bridge"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124c[] = "Solitron Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124d[] = "Stallion Technologies, Inc."; +static const char pci_device_124d_0000[] = "EasyConnection 8/32"; +static const char pci_device_124d_0002[] = "EasyConnection 8/64"; +static const char pci_device_124d_0003[] = "EasyIO"; +static const char pci_device_124d_0004[] = "EasyConnection/RA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124e[] = "Cylink"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124f[] = "Infotrend Technology, Inc."; +static const char pci_device_124f_0041[] = "IFT-2000 Series RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1250[] = "Hitachi Microcomputer System Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1251[] = "VLSI Solutions Oy"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1253[] = "Guzik Technical Enterprises"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1254[] = "Linear Systems Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1255[] = "Optibase Ltd"; +static const char pci_device_1255_1110[] = "MPEG Forge"; +static const char pci_device_1255_1210[] = "MPEG Fusion"; +static const char pci_device_1255_2110[] = "VideoPlex"; +static const char pci_device_1255_2120[] = "VideoPlex CC"; +static const char pci_device_1255_2130[] = "VideoQuest"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1256[] = "Perceptive Solutions, Inc."; +static const char pci_device_1256_4201[] = "PCI-2220I"; +static const char pci_device_1256_4401[] = "PCI-2240I"; +static const char pci_device_1256_5201[] = "PCI-2000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1257[] = "Vertex Networks, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1258[] = "Gilbarco, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1259[] = "Allied Telesyn International"; +static const char pci_device_1259_2560[] = "AT-2560 Fast Ethernet Adapter (i82557B)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125a[] = "ABB Power Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125b[] = "Asix Electronics Corporation"; +static const char pci_device_125b_1400[] = "ALFA GFC2204"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125c[] = "Aurora Technologies, Inc."; +static const char pci_device_125c_0640[] = "Aries 16000P"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125d[] = "ESS Technology"; +static const char pci_device_125d_0000[] = "ES336H Fax Modem (Early Model)"; +static const char pci_device_125d_1948[] = "Solo?"; +static const char pci_device_125d_1968[] = "ES1968 Maestro 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1968_1028_0085[] = "ES1968 Maestro-2 PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1968_1033_8051[] = "ES1968 Maestro-2 Audiodrive"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_125d_1969[] = "ES1969 Solo-1 Audiodrive"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1969_1014_0166[] = "ES1969 SOLO-1 AudioDrive on IBM Aptiva Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1969_125d_8888[] = "Solo-1 Audio Adapter"; +#endif +static const char pci_device_125d_1978[] = "ES1978 Maestro 2E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_0e11_b112[] = "Armada M700"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_1033_803c[] = "ES1978 Maestro-2E Audiodrive"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_1033_8058[] = "ES1978 Maestro-2E Audiodrive"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_1092_4000[] = "Monster Sound MX400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_1179_0001[] = "ES1978 Maestro-2E Audiodrive"; +#endif +static const char pci_device_125d_1988[] = "ES1988 Allegro-1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1988_1092_4100[] = "Sonic Impact S100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1988_125d_1988[] = "ESS Allegro-1 Audiodrive"; +#endif +static const char pci_device_125d_1989[] = "ESS Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1989_125d_1989[] = "ESS Modem"; +#endif +static const char pci_device_125d_1998[] = "ES1983S Maestro-3i PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1998_1028_00e6[] = "ES1983S Maestro-3i (Dell Inspiron 8100)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_125d_1999[] = "ES1983S Maestro-3i PCI Modem Accelerator"; +static const char pci_device_125d_199a[] = "ES1983S Maestro-3i PCI Audio Accelerator"; +static const char pci_device_125d_199b[] = "ES1983S Maestro-3i PCI Modem Accelerator"; +static const char pci_device_125d_2808[] = "ES336H Fax Modem (Later Model)"; +static const char pci_device_125d_2838[] = "ES2838/2839 SuperLink Modem"; +static const char pci_device_125d_2898[] = "ES2898 Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0424[] = "ES56-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0425[] = "ES56T-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0426[] = "ES56V-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0427[] = "VW-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0428[] = "ES56ST-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0429[] = "ES56SV-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_147a_c001[] = "ES56-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_14fe_0428[] = "ES56-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_14fe_0429[] = "ES56-PI Data Fax Modem"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125e[] = "Specialvideo Engineering SRL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125f[] = "Concurrent Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1260[] = "Harris Semiconductor"; +static const char pci_device_1260_3873[] = "Prism 2.5 Wavelan chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1186_3501[] = "DWL-520 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1668_0414[] = "HWP01170-01 802.11b PCI Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1737_3874[] = "WMP11 Wireless 802.11b PCI Adapter"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_8086_2513[] = "Wireless 802.11b MiniPCI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1260_8130[] = "HMP8130 NTSC/PAL Video Decoder"; +static const char pci_device_1260_8131[] = "HMP8131 NTSC/PAL Video Decoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1261[] = "Matsushita-Kotobuki Electronics Industries, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1262[] = "ES Computer Company, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1263[] = "Sonic Solutions"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1264[] = "Aval Nagasaki Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1265[] = "Casio Computer Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1266[] = "Microdyne Corporation"; +static const char pci_device_1266_0001[] = "NE10/100 Adapter (i82557B)"; +static const char pci_device_1266_1910[] = "NE2000Plus (RT8029) Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1266_1910_1266_1910[] = "NE2000Plus Ethernet Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1267[] = "S. A. Telecommunications"; +static const char pci_device_1267_5352[] = "PCR2101"; +static const char pci_device_1267_5a4b[] = "Telsat Turbo"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1268[] = "Tektronix"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1269[] = "Thomson-CSF/TTM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126a[] = "Lexmark International, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126b[] = "Adax, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126c[] = "Northern Telecom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126d[] = "Splash Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126e[] = "Sumitomo Metal Industries, Ltd."; +#endif +static const char pci_vendor_126f[] = "Silicon Motion, Inc."; +static const char pci_device_126f_0710[] = "SM710 LynxEM"; +static const char pci_device_126f_0712[] = "SM712 LynxEM+"; +static const char pci_device_126f_0720[] = "SM720 Lynx3DM"; +static const char pci_device_126f_0810[] = "SM810 LynxE"; +static const char pci_device_126f_0811[] = "SM811 LynxE"; +static const char pci_device_126f_0820[] = "SM820 Lynx3D"; +static const char pci_device_126f_0910[] = "SM910"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1270[] = "Olympus Optical Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1271[] = "GW Instruments"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1272[] = "Telematics International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1273[] = "Hughes Network Systems"; +static const char pci_device_1273_0002[] = "DirecPC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1274[] = "Ensoniq"; +static const char pci_device_1274_1371[] = "ES1371 [AudioPCI-97]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_0e11_0024[] = "AudioPCI on Motherboard Compaq Deskpro"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_0e11_b1a7[] = "ES1371, ES1373 AudioPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1033_80ac[] = "ES1371, ES1373 AudioPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1042_1854[] = "Tazer"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_107b_8054[] = "Tabor2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1274_1371[] = "Creative Sound Blaster AudioPCI64V, AudioPCI128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6470[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6147 1.1A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6560[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6156 1.10"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6630[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6163BX 1.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6631[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6163VIA 1.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6632[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6163BX 2.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6633[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6163VIA 2.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6820[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6182 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6822[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6182 1.00A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6830[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6183 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6880[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6188 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6900[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6190 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6910[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6191"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6930[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6193"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6990[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6199BX 2.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6991[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6199VIA 2.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_14a4_2077[] = "ES1371, ES1373 AudioPCI On Motherboard KR639"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_14a4_2105[] = "ES1371, ES1373 AudioPCI On Motherboard MR800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_14a4_2107[] = "ES1371, ES1373 AudioPCI On Motherboard MR801"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_14a4_2172[] = "ES1371, ES1373 AudioPCI On Motherboard DR739"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1509_9902[] = "ES1371, ES1373 AudioPCI On Motherboard KW11"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1509_9903[] = "ES1371, ES1373 AudioPCI On Motherboard KW31"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1509_9904[] = "ES1371, ES1373 AudioPCI On Motherboard KA11"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1509_9905[] = "ES1371, ES1373 AudioPCI On Motherboard KC13"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8801[] = "ES1371, ES1373 AudioPCI On Motherboard CP810E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8802[] = "ES1371, ES1373 AudioPCI On Motherboard CP810"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8803[] = "ES1371, ES1373 AudioPCI On Motherboard P3810E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8804[] = "ES1371, ES1373 AudioPCI On Motherboard P3810-S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8805[] = "ES1371, ES1373 AudioPCI On Motherboard P3820-S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_2001[] = "ES1371, ES1373 AudioPCI On Motherboard 6CTR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_2200[] = "ES1371, ES1373 AudioPCI On Motherboard 6WTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_3000[] = "ES1371, ES1373 AudioPCI On Motherboard 6WSV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_3100[] = "ES1371, ES1373 AudioPCI On Motherboard 6WIV2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_3102[] = "ES1371, ES1373 AudioPCI On Motherboard 6WIV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_7060[] = "ES1371, ES1373 AudioPCI On Motherboard 6ASA2"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4249[] = "ES1371, ES1373 AudioPCI On Motherboard BI440ZX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_424c[] = "ES1371, ES1373 AudioPCI On Motherboard BL440ZX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_425a[] = "ES1371, ES1373 AudioPCI On Motherboard BZ440ZX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4341[] = "ES1371, ES1373 AudioPCI On Motherboard Cayman"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4343[] = "ES1371, ES1373 AudioPCI On Motherboard Cape Cod"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4649[] = "ES1371, ES1373 AudioPCI On Motherboard Fire Island"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_464a[] = "ES1371, ES1373 AudioPCI On Motherboard FJ440ZX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4d4f[] = "ES1371, ES1373 AudioPCI On Motherboard Montreal"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4f43[] = "ES1371, ES1373 AudioPCI On Motherboard OC440LX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_5243[] = "ES1371, ES1373 AudioPCI On Motherboard RC440BX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_5352[] = "ES1371, ES1373 AudioPCI On Motherboard SunRiver"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_5643[] = "ES1371, ES1373 AudioPCI On Motherboard Vancouver"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_5753[] = "ES1371, ES1373 AudioPCI On Motherboard WS440BX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1274_5000[] = "ES1370 [AudioPCI]"; +static const char pci_device_1274_5880[] = "5880 AudioPCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1274_2000[] = "Creative Sound Blaster AudioPCI128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1274_2003[] = "Creative SoundBlaster AudioPCI 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1274_5880[] = "Creative Sound Blaster AudioPCI128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1458_a000[] = "5880 AudioPCI On Motherboard 6OXET"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1462_6880[] = "5880 AudioPCI On Motherboard MS-6188 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_270f_2001[] = "5880 AudioPCI On Motherboard 6CTR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_270f_2200[] = "5880 AudioPCI On Motherboard 6WTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_270f_7040[] = "5880 AudioPCI On Motherboard 6ATA4"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1275[] = "Network Appliance Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1276[] = "Switched Network Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1277[] = "Comstream"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1278[] = "Transtech Parallel Systems Ltd."; +static const char pci_device_1278_0701[] = "TPE3/TM3 PowerPC Node"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1279[] = "Transmeta Corporation"; +static const char pci_device_1279_0295[] = "Northbridge"; +static const char pci_device_1279_0395[] = "LongRun Northbridge"; +static const char pci_device_1279_0396[] = "SDRAM controller"; +static const char pci_device_1279_0397[] = "BIOS scratchpad"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127a[] = "Rockwell International"; +static const char pci_device_127a_1002[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_1092_094c[] = "SupraExpress 56i PRO [Diamond SUP2380]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4002[] = "HPG / MDP3858-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4005[] = "MDP3858-E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4007[] = "MDP3858-A/-NZ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4012[] = "MDP3858-SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4017[] = "MDP3858-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4018[] = "MDP3858-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_127a_1002[] = "Rockwell 56K D/F HCF Modem"; +#endif +static const char pci_device_127a_1003[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_0e11_b0bc[] = "229-DF Zephyr"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_0e11_b114[] = "229-DF Cheetah"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_1033_802b[] = "229-DF"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13df_1003[] = "PCI56RX Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_0117[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_0147[] = "IBM F-1156IV+/R3 Spain V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_0197[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_01c7[] = "IBM F-1156IV+/R3 WW V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_01f7[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_1436_1003[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_1436_1103[] = "IBM 5614PM3G V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_1436_1602[] = "Compaq 229-DF Ducati"; +#endif +static const char pci_device_127a_1004[] = "HCF 56k Data/Fax/Voice Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1004_1048_1500[] = "MicroLink 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1004_10cf_1059[] = "Fujitsu 229-DFRT"; +#endif +static const char pci_device_127a_1005[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1033_8029[] = "229-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1033_8054[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_10cf_103c[] = "Fujitsu"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_10cf_1055[] = "Fujitsu 229-DFSV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_10cf_1056[] = "Fujitsu 229-DFSV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4003[] = "MDP3858SP-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4006[] = "Packard Bell MDP3858V-E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4008[] = "MDP3858SP-A/SP-NZ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4009[] = "MDP3858SP-E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4010[] = "MDP3858V-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4011[] = "MDP3858SP-SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4013[] = "MDP3858V-A/V-NZ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4015[] = "MDP3858SP-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4016[] = "MDP3858V-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4019[] = "MDP3858V-SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13df_1005[] = "PCI56RVP Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13e0_0187[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13e0_01a7[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13e0_01b7[] = "IBM DF-1156IV+/R3 Spain V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13e0_01d7[] = "IBM DF-1156IV+/R3 WW V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1436_1005[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1436_1105[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1437_1105[] = "IBM 5614PS3G V.90 Modem"; +#endif +static const char pci_device_127a_1022[] = "HCF 56k Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1022_1436_1303[] = "M3-5614PM3G V.90 Modem"; +#endif +static const char pci_device_127a_1023[] = "HCF 56k Data/Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_122d_4020[] = "Packard Bell MDP3858-WE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_122d_4023[] = "MDP3858-UE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_13e0_0247[] = "IBM F-1156IV+/R6 Spain V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_13e0_0297[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_13e0_02c7[] = "IBM F-1156IV+/R6 WW V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_1436_1203[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_1436_1303[] = "IBM"; +#endif +static const char pci_device_127a_1024[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_127a_1025[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_10cf_106a[] = "Fujitsu 235-DFSV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_122d_4021[] = "Packard Bell MDP3858V-WE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_122d_4022[] = "MDP3858SP-WE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_122d_4024[] = "MDP3858V-UE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_122d_4025[] = "MDP3858SP-UE"; +#endif +static const char pci_device_127a_1026[] = "HCF 56k PCI Speakerphone Modem"; +static const char pci_device_127a_1032[] = "HCF 56k Modem"; +static const char pci_device_127a_1033[] = "HCF 56k Modem"; +static const char pci_device_127a_1034[] = "HCF 56k Modem"; +static const char pci_device_127a_1035[] = "HCF 56k PCI Speakerphone Modem"; +static const char pci_device_127a_1036[] = "HCF 56k Modem"; +static const char pci_device_127a_1085[] = "HCF 56k Volcano PCI Modem"; +static const char pci_device_127a_2005[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8044[] = "229-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8045[] = "229-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8055[] = "PBE/Aztech 235W-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8056[] = "235-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_805a[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_805f[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8074[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_127a_2013[] = "HSF 56k Data/Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2013_1179_0001[] = "Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2013_1179_ff00[] = "Modem"; +#endif +static const char pci_device_127a_2014[] = "HSF 56k Data/Fax/Voice Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2014_10cf_1057[] = "Fujitsu Citicorp III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2014_122d_4050[] = "MSP3880-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2014_122d_4055[] = "MSP3880-W"; +#endif +static const char pci_device_127a_2015[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2015_10cf_1063[] = "Fujitsu"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2015_10cf_1064[] = "Fujitsu"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2015_1468_2015[] = "Fujitsu"; +#endif +static const char pci_device_127a_2016[] = "HSF 56k Data/Fax/Voice/Spkp Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4051[] = "MSP3880V-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4052[] = "MSP3880SP-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4054[] = "MSP3880V-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4056[] = "MSP3880SP-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4057[] = "MSP3880SP-A"; +#endif +static const char pci_device_127a_4311[] = "Riptide HSF 56k PCI Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4311_127a_4311[] = "Ring Modular? Riptide HSF RT HP Dom"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4311_13e0_0210[] = "HP-GVC"; +#endif +static const char pci_device_127a_4320[] = "Riptide PCI Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4320_1235_4320[] = "Riptide PCI Audio Controller"; +#endif +static const char pci_device_127a_4321[] = "Riptide HCF 56k PCI Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4321_1235_4321[] = "Hewlett Packard DF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4321_1235_4324[] = "Hewlett Packard DF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4321_13e0_0210[] = "Hewlett Packard DF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4321_144d_2321[] = "Riptide"; +#endif +static const char pci_device_127a_4322[] = "Riptide PCI Game Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4322_1235_4322[] = "Riptide PCI Game Controller"; +#endif +static const char pci_device_127a_8234[] = "RapidFire 616X ATM155 Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_8234_108d_0022[] = "RapidFire 616X ATM155 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_8234_108d_0027[] = "RapidFire 616X ATM155 Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127b[] = "Pixera Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127c[] = "Crosspoint Solutions, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127d[] = "Vela Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127e[] = "Winnov, L.P."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127f[] = "Fujifilm"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1280[] = "Photoscript Group Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1281[] = "Yokogawa Electric Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1282[] = "Davicom Semiconductor, Inc."; +static const char pci_device_1282_9009[] = "Ethernet 100/10 MBit"; +static const char pci_device_1282_9100[] = "Ethernet 100/10 MBit"; +static const char pci_device_1282_9102[] = "Ethernet 100/10 MBit"; +static const char pci_device_1282_9132[] = "Ethernet 100/10 MBit"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1283[] = "Integrated Technology Express, Inc."; +static const char pci_device_1283_673a[] = "IT8330G"; +static const char pci_device_1283_8330[] = "IT8330G"; +static const char pci_device_1283_8888[] = "IT8888F PCI to ISA Bridge with SMB"; +static const char pci_device_1283_8889[] = "IT8889F PCI to ISA Bridge"; +static const char pci_device_1283_e886[] = "IT8330G"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1284[] = "Sahara Networks, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1285[] = "Platform Technologies, Inc."; +static const char pci_device_1285_0100[] = "AGOGO sound chip (aka ESS Maestro 1)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1286[] = "Mazet GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1287[] = "M-Pact, Inc."; +static const char pci_device_1287_001e[] = "LS220D DVD Decoder"; +static const char pci_device_1287_001f[] = "LS220C DVD Decoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1288[] = "Timestep Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1289[] = "AVC Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128a[] = "Asante Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128b[] = "Transwitch Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128c[] = "Retix Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128d[] = "G2 Networks, Inc."; +static const char pci_device_128d_0021[] = "ATM155 Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128e[] = "Hoontech Corporation/Samho Multi Tech Ltd."; +static const char pci_device_128e_0008[] = "ST128 WSS/SB"; +static const char pci_device_128e_0009[] = "ST128 SAM9407"; +static const char pci_device_128e_000a[] = "ST128 Game Port"; +static const char pci_device_128e_000b[] = "ST128 MPU Port"; +static const char pci_device_128e_000c[] = "ST128 Ctrl Port"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128f[] = "Tateno Dennou, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1290[] = "Sord Computer Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1291[] = "NCS Computer Italia"; +#endif +static const char pci_vendor_1292[] = "Tritech Microelectronics Inc"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1293[] = "Media Reality Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1294[] = "Rhetorex, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1295[] = "Imagenation Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1296[] = "Kofax Image Products"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1297[] = "Holco Enterprise Co, Ltd/Shuttle Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1298[] = "Spellcaster Telecommunications Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1299[] = "Knowledge Technology Lab."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129a[] = "VMetro, inc."; +static const char pci_device_129a_0615[] = "PBT-615 PCI-X Bus Analyzer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129b[] = "Image Access"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129c[] = "Jaycor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129d[] = "Compcore Multimedia, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129e[] = "Victor Company of Japan, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129f[] = "OEC Medical Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a0[] = "Allen-Bradley Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a1[] = "Simpact Associates, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a2[] = "Newgen Systems Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a3[] = "Lucent Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a4[] = "NTT Electronics Technology Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a5[] = "Vision Dynamics Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a6[] = "Scalable Networks, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a7[] = "AMO GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a8[] = "News Datacom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a9[] = "Xiotech Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12aa[] = "SDL Communications, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ab[] = "Yuan Yuan Enterprise Co., Ltd."; +static const char pci_device_12ab_3000[] = "MPG-200C PCI DVD Decoder Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ac[] = "Measurex Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ad[] = "Multidata GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ae[] = "Alteon Networks Inc."; +static const char pci_device_12ae_0001[] = "AceNIC Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0001_12ae_0001[] = "Gigabit Ethernet-SX (Universal)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0001_1410_0104[] = "Gigabit Ethernet-SX PCI Adapter"; +#endif +static const char pci_device_12ae_0002[] = "AceNIC Gigabit Ethernet (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0002_12ae_0002[] = "Gigabit Ethernet-T (3C986-T)"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12af[] = "TDK USA Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b0[] = "Jorge Scientific Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b1[] = "GammaLink"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b2[] = "General Signal Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b3[] = "Inter-Face Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b4[] = "FutureTel Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b5[] = "Granite Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b6[] = "Natural Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b7[] = "Cognex Modular Vision Systems Div. - Acumen Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b8[] = "Korg"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b9[] = "US Robotics/3Com"; +static const char pci_device_12b9_1006[] = "WinModem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_005c[] = "USR 56k Internal Voice WinModem (Model 3472)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_005e[] = "USR 56k Internal WinModem (Models 662975)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0062[] = "USR 56k Internal Voice WinModem (Model 662978)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0068[] = "USR 56k Internal Voice WinModem (Model 5690)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_007a[] = "USR 56k Internal Voice WinModem (Model 662974)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_007f[] = "USR 56k Internal WinModem (Models 5698, 5699)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0080[] = "USR 56k Internal WinModem (Models 2975, 3528)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0081[] = "USR 56k Internal Voice WinModem (Models 2974, 3529)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0091[] = "USR 56k Internal Voice WinModem (Model 2978)"; +#endif +static const char pci_device_12b9_1007[] = "USR 56k Internal WinModem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1007_12b9_00a3[] = "USR 56k Internal WinModem (Model 3595)"; +#endif +static const char pci_device_12b9_1008[] = "56K FaxModem Model 5610"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00a2[] = "USR 56k Internal FAX Modem (Model 2977)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00aa[] = "USR 56k Internal Voice Modem (Model 2976)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00ab[] = "USR 56k Internal Voice Modem (Model 5609)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00ac[] = "USR 56k Internal Voice Modem (Model 3298)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00ad[] = "USR 56k Internal FAX Modem (Model 5610)"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ba[] = "BittWare, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12bb[] = "Nippon Unisoft Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12bc[] = "Array Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12bd[] = "Computerm Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12be[] = "Anchor Chips Inc."; +static const char pci_device_12be_3041[] = "AN3041Q CO-MEM"; +static const char pci_device_12be_3042[] = "AN3042Q CO-MEM Lite"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12be_3042_12be_3042[] = "Anchor Chips Lite Evaluation Board"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12bf[] = "Fujifilm Microdevices"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c0[] = "Infimed"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c1[] = "GMM Research Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c2[] = "Mentec Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c3[] = "Holtek Microelectronics Inc"; +static const char pci_device_12c3_0058[] = "PCI NE2K Ethernet"; +static const char pci_device_12c3_5598[] = "PCI NE2K Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c4[] = "Connect Tech Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c5[] = "Picture Elements Incorporated"; +static const char pci_device_12c5_007e[] = "Imaging/Scanning Subsystem Engine"; +static const char pci_device_12c5_007f[] = "Imaging/Scanning Subsystem Engine"; +static const char pci_device_12c5_0081[] = "PCIVST [Grayscale Thresholding Engine]"; +static const char pci_device_12c5_0085[] = "Video Simulator/Sender"; +static const char pci_device_12c5_0086[] = "THR2 Multi-scale Thresholder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c6[] = "Mitani Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c7[] = "Dialogic Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c8[] = "G Force Co, Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c9[] = "Gigi Operations"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ca[] = "Integrated Computing Engines"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12cb[] = "Antex Electronics Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12cc[] = "Pluto Technologies International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12cd[] = "Aims Lab"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ce[] = "Netspeed Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12cf[] = "Prophet Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d0[] = "GDE Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d1[] = "PSITech"; +#endif +static const char pci_vendor_12d2[] = "NVidia / SGS Thomson (Joint Venture)"; +static const char pci_device_12d2_0008[] = "NV1"; +static const char pci_device_12d2_0009[] = "DAC64"; +static const char pci_device_12d2_0018[] = "Riva128"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_1048_0c10[] = "VICTORY Erazor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_107b_8030[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_1092_0350[] = "Viper V330"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_1092_1092[] = "Viper V330"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b1b[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b1d[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b1e[] = "STB Velocity 128, PAL TV-Out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b20[] = "STB Velocity 128 Sapphire"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b21[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b22[] = "STB Velocity 128 AGP, NTSC TV-Out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b23[] = "STB Velocity 128 AGP, PAL TV-Out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b27[] = "STB Velocity 128 DVD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b88[] = "MVP Pro 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_222a[] = "STB Velocity 128 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_2230[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_2232[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_2235[] = "STB Velocity 128 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_2a15_54a3[] = "3DVision-SAGP / 3DexPlorer 3000"; +#endif +static const char pci_device_12d2_0019[] = "Riva128ZX"; +static const char pci_device_12d2_0020[] = "TNT"; +static const char pci_device_12d2_0028[] = "TNT2"; +static const char pci_device_12d2_0029[] = "UTNT2"; +static const char pci_device_12d2_002c[] = "VTNT2"; +static const char pci_device_12d2_00a0[] = "ITNT2"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d3[] = "Vingmed Sound A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d4[] = "Ulticom (Formerly DGM&S)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d5[] = "Equator Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d6[] = "Analogic Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d7[] = "Biotronic SRL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d8[] = "Pericom Semiconductor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d9[] = "Aculab PLC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12da[] = "True Time Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12db[] = "Annapolis Micro Systems, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12dc[] = "Symicron Computer Communication Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12dd[] = "Management Graphics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12de[] = "Rainbow Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12df[] = "SBS Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e0[] = "Chase Research"; +static const char pci_device_12e0_0010[] = "ST16C654 Quad UART"; +static const char pci_device_12e0_0020[] = "ST16C654 Quad UART"; +static const char pci_device_12e0_0030[] = "ST16C654 Quad UART"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e1[] = "Nintendo Co, Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e2[] = "Datum Inc. Bancomm-Timing Division"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e3[] = "Imation Corp - Medical Imaging Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e4[] = "Brooktrout Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e5[] = "Apex Semiconductor Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e6[] = "Cirel Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e7[] = "Sunsgroup Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e8[] = "Crisc Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e9[] = "GE Spacenet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ea[] = "Zuken"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12eb[] = "Aureal Semiconductor"; +static const char pci_device_12eb_0001[] = "Vortex 1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_104d_8036[] = "AU8820 Vortex Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_1092_2000[] = "Sonic Impact A3D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_1092_2100[] = "Sonic Impact A3D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_1092_2110[] = "Sonic Impact A3D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_1092_2200[] = "Sonic Impact A3D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_122d_1002[] = "AU8820 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_12eb_0001[] = "AU8820 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_5053_3355[] = "Montego"; +#endif +static const char pci_device_12eb_0002[] = "Vortex 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_104d_8049[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_104d_807b[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3000[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3001[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3002[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3003[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3004[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_12eb_0001[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_12eb_0002[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_12eb_0088[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_144d_3510[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_5053_3356[] = "Montego II"; +#endif +static const char pci_device_12eb_0003[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_104d_8049[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_104d_8077[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_109f_1000[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_12eb_0003[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_1462_6780[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_14a4_2073[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_14a4_2091[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_14a4_2104[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_14a4_2106[] = "AU8810 Vortex Digital Audio Processor"; +#endif +static const char pci_device_12eb_8803[] = "Vortex 56k Software Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_8803_12eb_8803[] = "Vortex 56k Software Modem"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ec[] = "3A International, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ed[] = "Optivision Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ee[] = "Orange Micro"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ef[] = "Vienna Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f0[] = "Pentek"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f1[] = "Sorenson Vision Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f2[] = "Gammagraphx, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f3[] = "Radstone Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f4[] = "Megatel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f5[] = "Forks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f6[] = "Dawson France"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f7[] = "Cognex"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f8[] = "Electronic Design GmbH"; +static const char pci_device_12f8_0002[] = "VideoMaker"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f9[] = "Four Fold Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12fb[] = "Spectrum Signal Processing"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12fc[] = "Capital Equipment Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12fd[] = "I2S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12fe[] = "ESD Electronic System Design GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ff[] = "Lexicon"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1300[] = "Harman International Industries Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1302[] = "Computer Sciences Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1303[] = "Innovative Integration"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1304[] = "Juniper Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1305[] = "Netphone, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1306[] = "Duet Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1307[] = "Computer Boards"; +static const char pci_device_1307_0001[] = "PCI-DAS1602/16"; +static const char pci_device_1307_000b[] = "PCI-DIO48H"; +static const char pci_device_1307_000c[] = "PCI-PDISO8"; +static const char pci_device_1307_000d[] = "PCI-PDISO16"; +static const char pci_device_1307_000f[] = "PCI-DAS1200"; +static const char pci_device_1307_0010[] = "PCI-DAS1602/12"; +static const char pci_device_1307_0014[] = "PCI-DIO24H"; +static const char pci_device_1307_0015[] = "PCI-DIO24H/CTR3"; +static const char pci_device_1307_0016[] = "PCI-DIO48H/CTR15"; +static const char pci_device_1307_0017[] = "PCI-DIO96H"; +static const char pci_device_1307_0018[] = "PCI-CTR05"; +static const char pci_device_1307_0019[] = "PCI-DAS1200/JR"; +static const char pci_device_1307_001a[] = "PCI-DAS1001"; +static const char pci_device_1307_001b[] = "PCI-DAS1002"; +static const char pci_device_1307_001c[] = "PCI-DAS1602JR/16"; +static const char pci_device_1307_001d[] = "PCI-DAS6402/16"; +static const char pci_device_1307_001e[] = "PCI-DAS6402/12"; +static const char pci_device_1307_001f[] = "PCI-DAS16/M1"; +static const char pci_device_1307_0020[] = "PCI-DDA02/12"; +static const char pci_device_1307_0021[] = "PCI-DDA04/12"; +static const char pci_device_1307_0022[] = "PCI-DDA08/12"; +static const char pci_device_1307_0023[] = "PCI-DDA02/16"; +static const char pci_device_1307_0024[] = "PCI-DDA04/16"; +static const char pci_device_1307_0025[] = "PCI-DDA08/16"; +static const char pci_device_1307_0026[] = "PCI-DAC04/12-HS"; +static const char pci_device_1307_0027[] = "PCI-DAC04/16-HS"; +static const char pci_device_1307_0028[] = "PCI-DIO24"; +static const char pci_device_1307_0029[] = "PCI-DAS08"; +static const char pci_device_1307_002c[] = "PCI-INT32"; +static const char pci_device_1307_0033[] = "PCI-DUAL-AC5"; +static const char pci_device_1307_0034[] = "PCI-DAS-TC"; +static const char pci_device_1307_0035[] = "PCI-DAS64/M1/16"; +static const char pci_device_1307_0036[] = "PCI-DAS64/M2/16"; +static const char pci_device_1307_0037[] = "PCI-DAS64/M3/16"; +static const char pci_device_1307_004c[] = "PCI-DAS1000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1308[] = "Jato Technologies Inc."; +static const char pci_device_1308_0001[] = "NetCelerator Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1308_0001_1308_0001[] = "NetCelerator Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1309[] = "AB Semiconductor Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130a[] = "Mitsubishi Electric Microcomputer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130b[] = "Colorgraphic Communications Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130c[] = "Ambex Technologies, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130d[] = "Accelerix Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130e[] = "Yamatake-Honeywell Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130f[] = "Advanet Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1310[] = "Gespac"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1311[] = "Videoserver, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1312[] = "Acuity Imaging, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1313[] = "Yaskawa Electric Co."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1316[] = "Teradyne Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1317[] = "Linksys"; +static const char pci_device_1317_0981[] = "Fast Ethernet 10/100"; +static const char pci_device_1317_0985[] = "Network Everywhere Fast Ethernet 10/100 model NC100"; +static const char pci_device_1317_1985[] = "Fast Ethernet 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1318[] = "Packet Engines Inc."; +static const char pci_device_1318_0911[] = "PCI Ethernet Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1319[] = "Fortemedia, Inc"; +static const char pci_device_1319_0801[] = "Xwave QS3000A [FM801]"; +static const char pci_device_1319_0802[] = "Xwave QS3000A [FM801 game port]"; +static const char pci_device_1319_1000[] = "FM801 PCI Audio"; +static const char pci_device_1319_1001[] = "FM801 PCI Joystick"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131a[] = "Finisar Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131c[] = "Nippon Electro-Sensory Devices Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131d[] = "Sysmic, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131e[] = "Xinex Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131f[] = "Siig Inc"; +static const char pci_device_131f_1000[] = "CyberSerial (1-port) 16550"; +static const char pci_device_131f_1001[] = "CyberSerial (1-port) 16650"; +static const char pci_device_131f_1002[] = "CyberSerial (1-port) 16850"; +static const char pci_device_131f_1010[] = "Duet 1S(16550)+1P"; +static const char pci_device_131f_1011[] = "Duet 1S(16650)+1P"; +static const char pci_device_131f_1012[] = "Duet 1S(16850)+1P"; +static const char pci_device_131f_1020[] = "CyberParallel (1-port)"; +static const char pci_device_131f_1021[] = "CyberParallel (2-port)"; +static const char pci_device_131f_1030[] = "CyberSerial (2-port) 16550"; +static const char pci_device_131f_1031[] = "CyberSerial (2-port) 16650"; +static const char pci_device_131f_1032[] = "CyberSerial (2-port) 16850"; +static const char pci_device_131f_1034[] = "Trio 2S(16550)+1P"; +static const char pci_device_131f_1035[] = "Trio 2S(16650)+1P"; +static const char pci_device_131f_1036[] = "Trio 2S(16850)+1P"; +static const char pci_device_131f_1050[] = "CyberSerial (4-port) 16550"; +static const char pci_device_131f_1051[] = "CyberSerial (4-port) 16650"; +static const char pci_device_131f_1052[] = "CyberSerial (4-port) 16850"; +static const char pci_device_131f_2000[] = "CyberSerial (1-port) 16550"; +static const char pci_device_131f_2001[] = "CyberSerial (1-port) 16650"; +static const char pci_device_131f_2002[] = "CyberSerial (1-port) 16850"; +static const char pci_device_131f_2010[] = "Duet 1S(16550)+1P"; +static const char pci_device_131f_2011[] = "Duet 1S(16650)+1P"; +static const char pci_device_131f_2012[] = "Duet 1S(16850)+1P"; +static const char pci_device_131f_2020[] = "CyberParallel (1-port)"; +static const char pci_device_131f_2021[] = "CyberParallel (2-port)"; +static const char pci_device_131f_2030[] = "CyberSerial (2-port) 16550"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_131f_2030_131f_2030[] = "PCI Serial Card"; +#endif +static const char pci_device_131f_2031[] = "CyberSerial (2-port) 16650"; +static const char pci_device_131f_2032[] = "CyberSerial (2-port) 16850"; +static const char pci_device_131f_2040[] = "Trio 1S(16550)+2P"; +static const char pci_device_131f_2041[] = "Trio 1S(16650)+2P"; +static const char pci_device_131f_2042[] = "Trio 1S(16850)+2P"; +static const char pci_device_131f_2050[] = "CyberSerial (4-port) 16550"; +static const char pci_device_131f_2051[] = "CyberSerial (4-port) 16650"; +static const char pci_device_131f_2052[] = "CyberSerial (4-port) 16850"; +static const char pci_device_131f_2060[] = "Trio 2S(16550)+1P"; +static const char pci_device_131f_2061[] = "Trio 2S(16650)+1P"; +static const char pci_device_131f_2062[] = "Trio 2S(16850)+1P"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1320[] = "Crypto AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1321[] = "Arcobel Graphics BV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1322[] = "MTT Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1323[] = "Dome Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1324[] = "Sphere Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1325[] = "Salix Technologies, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1326[] = "Seachange international"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1327[] = "Voss scientific"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1328[] = "quadrant international"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1329[] = "Productivity Enhancement"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_132a[] = "Microcom Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_132b[] = "Broadband Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_132c[] = "Micrel Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_132d[] = "Integrated Silicon Solution, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1330[] = "MMC Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1331[] = "Radisys Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1332[] = "Micro Memory"; +static const char pci_device_1332_5415[] = "MM-5415CN PCI Memory Module with Battery Backup"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1334[] = "Redcreek Communications, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1335[] = "Videomail, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1337[] = "Third Planet Publishing"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1338[] = "BT Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133a[] = "Vtel Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133b[] = "Softcom Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133c[] = "Holontech Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133d[] = "SS Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133e[] = "Virtual Computer Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133f[] = "SCM Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1340[] = "Atalla Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1341[] = "Kyoto Microcomputer Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1342[] = "Promax Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1343[] = "Phylon Communications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1344[] = "Crucial Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1345[] = "Arescom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1347[] = "Odetics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1349[] = "Sumitomo Electric Industries, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134a[] = "DTC Technology Corp."; +static const char pci_device_134a_0001[] = "Domex 536"; +static const char pci_device_134a_0002[] = "Domex DMX3194UP SCSI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134b[] = "ARK Research Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134c[] = "Chori Joho System Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134d[] = "PCTel Inc"; +static const char pci_device_134d_7890[] = "HSP MicroModem 56"; +static const char pci_device_134d_7891[] = "HSP MicroModem 56"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_134d_7891_134d_0001[] = "HSP MicroModem 56"; +#endif +static const char pci_device_134d_7892[] = "HSP MicroModem 56"; +static const char pci_device_134d_7893[] = "HSP MicroModem 56"; +static const char pci_device_134d_7894[] = "HSP MicroModem 56"; +static const char pci_device_134d_7895[] = "HSP MicroModem 56"; +static const char pci_device_134d_7896[] = "HSP MicroModem 56"; +static const char pci_device_134d_7897[] = "HSP MicroModem 56"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134e[] = "CSTI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134f[] = "Algo System Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1350[] = "Systec Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1351[] = "Sonix Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1353[] = "Thales Idatys"; +static const char pci_device_1353_0002[] = "Proserver"; +static const char pci_device_1353_0003[] = "PCI-FUT"; +static const char pci_device_1353_0004[] = "PCI-S0"; +static const char pci_device_1353_0005[] = "PCI-FUT-S0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1354[] = "Dwave System Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1355[] = "Kratos Analytical Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1356[] = "The Logical Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1359[] = "Prisa Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135a[] = "Brain Boxes"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135b[] = "Giganet Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135c[] = "Quatech Inc"; +static const char pci_device_135c_0010[] = "QSC-100"; +static const char pci_device_135c_0020[] = "DSC-100"; +static const char pci_device_135c_0030[] = "DSC-200/300"; +static const char pci_device_135c_0040[] = "QSC-200/300"; +static const char pci_device_135c_0050[] = "ESC-100D"; +static const char pci_device_135c_0060[] = "ESC-100M"; +static const char pci_device_135c_00f0[] = "MPAC-100 Syncronous Serial Card (Zilog 85230)"; +static const char pci_device_135c_0170[] = "QSCLP-100"; +static const char pci_device_135c_0180[] = "DSCLP-100"; +static const char pci_device_135c_0190[] = "SSCLP-100"; +static const char pci_device_135c_01a0[] = "QSCLP-200/300"; +static const char pci_device_135c_01b0[] = "DSCLP-200/300"; +static const char pci_device_135c_01c0[] = "SSCLP-200/300"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135d[] = "ABB Network Partner AB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135e[] = "Sealevel Systems Inc"; +static const char pci_device_135e_7101[] = "Single Port RS-232/422/485/530"; +static const char pci_device_135e_7201[] = "Dual Port RS-232/422/485 Interface"; +static const char pci_device_135e_7202[] = "Dual Port RS-232 Interface"; +static const char pci_device_135e_7401[] = "Four Port RS-232 Interface"; +static const char pci_device_135e_7402[] = "Four Port RS-422/485 Interface"; +static const char pci_device_135e_7801[] = "Eight Port RS-232 Interface"; +static const char pci_device_135e_8001[] = "8001 Digital I/O Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135f[] = "I-Data International A-S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1360[] = "Meinberg Funkuhren"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1361[] = "Soliton Systems K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1362[] = "Fujifacom Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1363[] = "Phoenix Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1364[] = "ATM Communications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1365[] = "Hypercope GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1366[] = "Teijin Seiki Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1367[] = "Hitachi Zosen Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1368[] = "Skyware Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1369[] = "Digigram"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136a[] = "High Soft Tech"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136b[] = "Kawasaki Steel Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136c[] = "Adtek System Science Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136d[] = "Gigalabs Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136f[] = "Applied Magic Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1370[] = "ATL Products"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1371[] = "CNet Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1373[] = "Silicon Vision Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1374[] = "Silicom Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1375[] = "Argosystems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1376[] = "LMC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1377[] = "Electronic Equipment Production & Distribution GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1378[] = "Telemann Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1379[] = "Asahi Kasei Microsystems Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137a[] = "Mark of the Unicorn Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137b[] = "PPT Vision"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137c[] = "Iwatsu Electric Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137d[] = "Dynachip Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137e[] = "Patriot Scientific Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137f[] = "Japan Satellite Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1380[] = "Sanritz Automation Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1381[] = "Brains Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1382[] = "Marian - Electronic & Software"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1383[] = "Controlnet Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1384[] = "Reality Simulation Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1385[] = "Netgear"; +static const char pci_device_1385_4100[] = "802.11b Wireless Adapter (MA301)"; +static const char pci_device_1385_620a[] = "GA620"; +static const char pci_device_1385_622a[] = "GA622"; +static const char pci_device_1385_630a[] = "GA630"; +static const char pci_device_1385_f311[] = "FA311"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1386[] = "Video Domain Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1387[] = "Systran Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1388[] = "Hitachi Information Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1389[] = "Applicom International"; +static const char pci_device_1389_0001[] = "PCI1500PFB [Intelligent fieldbus adaptor]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138a[] = "Fusion Micromedia Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138b[] = "Tokimec Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138c[] = "Silicon Reality"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138d[] = "Future Techno Designs pte Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138e[] = "Basler GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138f[] = "Patapsco Designs Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1390[] = "Concept Development Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1391[] = "Development Concepts Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1392[] = "Medialight Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1393[] = "Moxa Technologies Co Ltd"; +static const char pci_device_1393_1040[] = "Smartio C104H/PCI"; +static const char pci_device_1393_1680[] = "Smartio C168H/PCI"; +static const char pci_device_1393_2040[] = "Intellio CP-204J"; +static const char pci_device_1393_2180[] = "Intellio C218 Turbo PCI"; +static const char pci_device_1393_3200[] = "Intellio C320 Turbo PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1394[] = "Level One Communications"; +static const char pci_device_1394_0001[] = "LXT1001 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1394_0001_1394_0001[] = "NetCelerator Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1395[] = "Ambicom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1396[] = "Cipher Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1397[] = "Cologne Chip Designs GmbH"; +static const char pci_device_1397_2bd0[] = "ISDN network controller [HFC-PCI]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1397_2bd0_1397_2bd0[] = "ISDN Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1397_2bd0_e4bf_1000[] = "CI1-1-Harp"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1398[] = "Clarion co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1399[] = "Rios systems Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139a[] = "Alacritech Inc"; +static const char pci_device_139a_0001[] = "Quad Port 10/100 Server Accelerator"; +static const char pci_device_139a_0003[] = "Single Port 10/100 Server Accelerator"; +static const char pci_device_139a_0005[] = "Single Port Gigabit Server Accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139b[] = "Mediasonic Multimedia Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139c[] = "Quantum 3d Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139d[] = "EPL limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139e[] = "Media4"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139f[] = "Aethra s.r.l."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a0[] = "Crystal Group Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a1[] = "Kawasaki Heavy Industries Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a2[] = "Ositech Communications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a3[] = "Hifn Inc."; +static const char pci_device_13a3_0005[] = "7751 Security Processor"; +static const char pci_device_13a3_0006[] = "6500 Public Key Processor"; +static const char pci_device_13a3_0007[] = "7811 Security Processor"; +static const char pci_device_13a3_0012[] = "7951 Security Processor"; +static const char pci_device_13a3_0014[] = "78XX Security Processor"; +static const char pci_device_13a3_0016[] = "8065 Security Processor"; +static const char pci_device_13a3_0017[] = "8165 Security Processor"; +static const char pci_device_13a3_0018[] = "8154 Security Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a4[] = "Rascom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a5[] = "Audio Digital Imaging Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a6[] = "Videonics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a7[] = "Teles AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a8[] = "Exar Corp."; +static const char pci_device_13a8_0158[] = "XR17C158 Octal UART"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a9[] = "Siemens Medical Systems, Ultrasound Group"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13aa[] = "Broadband Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ab[] = "Arcom Control Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ac[] = "Motion Media Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ad[] = "Nexus Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ae[] = "ALD Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13af[] = "T.Sqware"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b0[] = "Maxspeed Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b1[] = "Tamura corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b2[] = "Techno Chips Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b3[] = "Lanart Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b4[] = "Wellbean Co Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b5[] = "ARM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b6[] = "Dlog GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b7[] = "Logic Devices Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b8[] = "Nokia Telecommunications oy"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b9[] = "Elecom Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ba[] = "Oxford Instruments"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13bb[] = "Sanyo Technosound Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13bc[] = "Bitran Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13bd[] = "Sharp corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13be[] = "Miroku Jyoho Service Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13bf[] = "Sharewave Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c0[] = "Microgate Corporation"; +static const char pci_device_13c0_0010[] = "SyncLink WAN Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c1[] = "3ware Inc"; +static const char pci_device_13c1_1000[] = "3ware ATA-RAID"; +static const char pci_device_13c1_1001[] = "3ware 7000-series ATA-RAID"; +static const char pci_device_13c1_1002[] = "3ware ATA-RAID"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c2[] = "Technotrend Systemtechnik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c3[] = "Janz Computer AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c4[] = "Phase Metrics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c5[] = "Alphi Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c6[] = "Condor Engineering Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c7[] = "Blue Chip Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c8[] = "Apptech Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c9[] = "Eaton Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ca[] = "Iomega Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13cb[] = "Yano Electric Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13cc[] = "Metheus Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13cd[] = "Compatible Systems Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ce[] = "Cocom A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13cf[] = "Studio Audio & Video Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d0[] = "Techsan Electronics Co Ltd"; +static const char pci_device_13d0_2103[] = "B2C2 Sky2PC PCI [SkyStar2]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d1[] = "Abocom Systems Inc"; +static const char pci_device_13d1_ab02[] = "ADMtek Centaur-C rev 17 [D-Link DFE-680TX] CardBus Fast Ethernet Adapter"; +static const char pci_device_13d1_ab06[] = "RTL8139 [FE2000VX] CardBus Fast Ethernet Attached Port Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d2[] = "Shark Multimedia Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d3[] = "IMC Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d4[] = "Graphics Microsystems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d5[] = "Media 100 Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d6[] = "K.I. Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d7[] = "Toshiba Engineering Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d8[] = "Phobos corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d9[] = "Apex PC Solutions Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13da[] = "Intresource Systems pte Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13db[] = "Janich & Klass Computertechnik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13dc[] = "Netboost Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13dd[] = "Multimedia Bundle Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13de[] = "ABB Robotics Products AB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13df[] = "E-Tech Inc"; +static const char pci_device_13df_0001[] = "PCI56RVP Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13df_0001_13df_0001[] = "PCI56RVP Modem"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e0[] = "GVC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e1[] = "Silicom Multimedia Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e2[] = "Dynamics Research Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e3[] = "Nest Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e4[] = "Calculex Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e5[] = "Telesoft Design Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e6[] = "Argosy research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e7[] = "NAC Incorporated"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e8[] = "Chip Express Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e9[] = "Chip Express Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ea[] = "Dallas Semiconductor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13eb[] = "Hauppauge Computer Works Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ec[] = "Zydacron Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ed[] = "Raytheion E-Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ee[] = "Hayes Microcomputer Products Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ef[] = "Coppercom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f0[] = "Sundance Technology Inc"; +static const char pci_device_13f0_0201[] = "ST201 Sundance Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f1[] = "Oce' - Technologies B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f2[] = "Ford Microelectronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f3[] = "Mcdata Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f4[] = "Troika Networks, Inc."; +static const char pci_device_13f4_1401[] = "Zentai Fibre Channel Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f5[] = "Kansai Electric Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f6[] = "C-Media Electronics Inc"; +static const char pci_device_13f6_0100[] = "CM8338A"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0100_13f6_ffff[] = "CMI8338/C3DX PCI Audio Device"; +#endif +static const char pci_device_13f6_0101[] = "CM8338B"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0101_13f6_0101[] = "CMI8338-031 PCI Audio Device"; +#endif +static const char pci_device_13f6_0111[] = "CM8738"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1019_0970[] = "P6STP-FL motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1043_8077[] = "CMI8738 6-channel audio controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1043_80e2[] = "CMI8738 6ch-MX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_13f6_0111[] = "CMI8738/C3DX PCI Audio Device"; +#endif +static const char pci_device_13f6_0211[] = "CM8738"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f7[] = "Wildfire Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f8[] = "Ad Lib Multimedia Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f9[] = "NTT Advanced Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fa[] = "Pentland Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fb[] = "Aydin Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fc[] = "Computer Peripherals International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fd[] = "Micro Science Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fe[] = "Advantech Co. Ltd"; +static const char pci_device_13fe_1756[] = "PCI-1756"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ff[] = "Silicon Spice Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1400[] = "Artx Inc"; +static const char pci_device_1400_1401[] = "9432 TX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1401[] = "CR-Systems A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1402[] = "Meilhaus Electronic GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1403[] = "Ascor Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1404[] = "Fundamental Software Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1405[] = "Excalibur Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1406[] = "Oce' Printing Systems GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1407[] = "Lava Computer mfg Inc"; +static const char pci_device_1407_0100[] = "Lava Dual Serial"; +static const char pci_device_1407_0101[] = "Lava Quatro A"; +static const char pci_device_1407_0102[] = "Lava Quatro B"; +static const char pci_device_1407_0200[] = "Lava Port Plus"; +static const char pci_device_1407_0201[] = "Lava Quad A"; +static const char pci_device_1407_0202[] = "Lava Quad B"; +static const char pci_device_1407_0500[] = "Lava Single Serial"; +static const char pci_device_1407_0600[] = "Lava Port 650"; +static const char pci_device_1407_8000[] = "Lava Parallel"; +static const char pci_device_1407_8001[] = "Dual parallel port controller A"; +static const char pci_device_1407_8002[] = "Lava Dual Parallel port A"; +static const char pci_device_1407_8003[] = "Lava Dual Parallel port B"; +static const char pci_device_1407_8800[] = "BOCA Research IOPPAR"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1408[] = "Aloka Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1409[] = "Timedia Technology Co Ltd"; +static const char pci_device_1409_7168[] = "PCI2S550 (Dual 16550 UART)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140a[] = "DSP Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140b[] = "Ramix Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140c[] = "Elmic Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140d[] = "Matsushita Electric Works Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140e[] = "Goepel Electronic GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140f[] = "Salient Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1410[] = "Midas lab Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1411[] = "Ikos Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1412[] = "IC Ensemble Inc"; +static const char pci_device_1412_1712[] = "ICE1712 [Envy24]"; +static const char pci_device_1412_1724[] = "ICE1724 [Envy24HT]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1413[] = "Addonics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1414[] = "Microsoft Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1415[] = "Oxford Semiconductor Ltd"; +static const char pci_device_1415_8403[] = "VScom 011H-EP1 1 port parallel adaptor"; +static const char pci_device_1415_9501[] = "OX16PCI954 (Quad 16950 UART) function 0"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9501_15ed_2000[] = "MCCR Serial p0-3 of 8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9501_15ed_2001[] = "MCCR Serial p0-3 of 16"; +#endif +static const char pci_device_1415_950a[] = "EXSYS EX-41092 Dual 16950 Serial adapter"; +static const char pci_device_1415_950b[] = "OXCB950 Cardbus 16950 UART"; +static const char pci_device_1415_9511[] = "OX16PCI954 (Quad 16950 UART) function 1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9511_15ed_2000[] = "MCCR Serial p4-7 of 8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9511_15ed_2001[] = "MCCR Serial p4-15 of 16"; +#endif +static const char pci_device_1415_9521[] = "OX16PCI952 (Dual 16950 UART)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1416[] = "Multiwave Innovation pte Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1417[] = "Convergenet Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1418[] = "Kyushu electronics systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1419[] = "Excel Switching Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141a[] = "Apache Micro Peripherals Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141b[] = "Zoom Telephonics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141d[] = "Digitan Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141e[] = "Fanuc Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141f[] = "Visiontech Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1420[] = "Psion Dacom plc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1421[] = "Ads Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1422[] = "Ygrec Systems Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1423[] = "Custom Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1424[] = "Videoserver Connections"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1425[] = "ASIC Designers Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1426[] = "Storage Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1427[] = "Better On-Line Solutions"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1428[] = "Edec Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1429[] = "Unex Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142a[] = "Kingmax Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142b[] = "Radiolan"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142c[] = "Minton Optic Industry Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142d[] = "Pix stream Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142e[] = "Vitec Multimedia"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142f[] = "Radicom Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1430[] = "ITT Aerospace/Communications Division"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1431[] = "Gilat Satellite Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1432[] = "Edimax Computer Co."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1433[] = "Eltec Elektronik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1435[] = "Real Time Devices US Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1436[] = "CIS Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1437[] = "Nissin Inc Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1438[] = "Atmel-dream"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1439[] = "Outsource Engineering & Mfg. Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143a[] = "Stargate Solutions Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143b[] = "Canon Research Center, America"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143c[] = "Amlogic Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143d[] = "Tamarack Microelectronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143e[] = "Jones Futurex Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143f[] = "Lightwell Co Ltd - Zax Division"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1440[] = "ALGOL Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1441[] = "AGIE Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1442[] = "Phoenix Contact GmbH & Co."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1443[] = "Unibrain S.A."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1444[] = "TRW"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1445[] = "Logical DO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1446[] = "Graphin Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1447[] = "AIM GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1448[] = "Alesis Studio Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1449[] = "TUT Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144a[] = "Adlink Technology"; +static const char pci_device_144a_7296[] = "PCI-7296"; +static const char pci_device_144a_7432[] = "PCI-7432"; +static const char pci_device_144a_7433[] = "PCI-7433"; +static const char pci_device_144a_7434[] = "PCI-7434"; +static const char pci_device_144a_7841[] = "PCI-7841"; +static const char pci_device_144a_8133[] = "PCI-8133"; +static const char pci_device_144a_8554[] = "PCI-8554"; +static const char pci_device_144a_9111[] = "PCI-9111"; +static const char pci_device_144a_9113[] = "PCI-9113"; +static const char pci_device_144a_9114[] = "PCI-9114"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144b[] = "Loronix Information Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144c[] = "Catalina Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144d[] = "Samsung Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144e[] = "OLITEC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144f[] = "Askey Computer Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1450[] = "Octave Communications Ind."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1451[] = "SP3D Chip Design GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1453[] = "MYCOM Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1454[] = "Altiga Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1455[] = "Logic Plus Plus Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1456[] = "Advanced Hardware Architectures"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1457[] = "Nuera Communications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1458[] = "Giga-byte Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1459[] = "DOOIN Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145a[] = "Escalate Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145b[] = "PRAIM SRL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145c[] = "Cryptek"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145d[] = "Gallant Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145e[] = "Aashima Technology B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145f[] = "Baldor Electric Company"; +static const char pci_device_145f_0001[] = "NextMove PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1460[] = "DYNARC INC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1461[] = "Avermedia Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1462[] = "Micro-Star International Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1463[] = "Fast Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1464[] = "Interactive Circuits & Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1465[] = "GN NETTEST Telecom DIV."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1466[] = "Designpro Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1467[] = "DIGICOM SPA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1468[] = "AMBIT Microsystem Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1469[] = "Cleveland Motion Controls"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146a[] = "IFR"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146b[] = "Parascan Technologies Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146c[] = "Ruby Tech Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146d[] = "Tachyon, INC."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146e[] = "Williams Electronics Games, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146f[] = "Multi Dimensional Consulting Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1470[] = "Bay Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1471[] = "Integrated Telecom Express Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1472[] = "DAIKIN Industries, Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1473[] = "ZAPEX Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1474[] = "Doug Carson & Associates"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1475[] = "PICAZO Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1476[] = "MORTARA Instrument Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1477[] = "Net Insight"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1478[] = "DIATREND Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1479[] = "TORAY Industries Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147a[] = "FORMOSA Industrial Computing"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147b[] = "ABIT Computer Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147c[] = "AWARE, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147d[] = "Interworks Computer Products"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147e[] = "Matsushita Graphic Communication Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147f[] = "NIHON UNISYS, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1480[] = "SCII Telecom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1481[] = "BIOPAC Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1482[] = "ISYTEC - Integrierte Systemtechnik GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1483[] = "LABWAY Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1484[] = "Logic Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1485[] = "ERMA - Electronic GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1486[] = "L3 Communications Telemetry & Instrumentation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1487[] = "MARQUETTE Medical Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1488[] = "KONTRON Electronik GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1489[] = "KYE Systems Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148a[] = "OPTO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148b[] = "INNOMEDIALOGIC Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148c[] = "C.P. Technology Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148d[] = "DIGICOM Systems, Inc."; +static const char pci_device_148d_1003[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148e[] = "OSI Plus Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148f[] = "Plant Equipment, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1490[] = "Stone Microsystems PTY Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1491[] = "ZEAL Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1492[] = "Time Logic Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1493[] = "MAKER Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1494[] = "WINTOP Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1495[] = "TOKAI Communications Industry Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1496[] = "JOYTECH Computer Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1497[] = "SMA Regelsysteme GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1498[] = "TEWS Datentechnik GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1499[] = "EMTEC CO., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149a[] = "ANDOR Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149b[] = "SEIKO Instruments Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149c[] = "OVISLINK Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149d[] = "NEWTEK Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149e[] = "Mapletree Networks Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149f[] = "LECTRON Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a0[] = "SOFTING GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a1[] = "Systembase Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a2[] = "Millennium Engineering Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a3[] = "Maverick Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a4[] = "GVC/BCM Advanced Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a5[] = "XIONICS Document Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a6[] = "INOVA Computers GmBH & Co KG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a7[] = "MYTHOS Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a8[] = "FEATRON Technologies Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a9[] = "HIVERTEC Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14aa[] = "Advanced MOS Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ab[] = "Mentor Graphics Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ac[] = "Novaweb Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ad[] = "Time Space Radio AB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ae[] = "CTI, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14af[] = "Guillemot Corporation"; +static const char pci_device_14af_7102[] = "3D Prophet II MX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b0[] = "BST Communication Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b1[] = "Nextcom K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b2[] = "ENNOVATE Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b3[] = "XPEED Inc"; +static const char pci_device_14b3_0000[] = "DSL NIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b4[] = "PHILIPS Business Electronics B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b5[] = "Creamware GmBH"; +static const char pci_device_14b5_0200[] = "Scope"; +static const char pci_device_14b5_0300[] = "Pulsar"; +static const char pci_device_14b5_0400[] = "Pulsar2"; +static const char pci_device_14b5_0600[] = "Pulsar2"; +static const char pci_device_14b5_0800[] = "DSP-Board"; +static const char pci_device_14b5_0900[] = "DSP-Board"; +static const char pci_device_14b5_0a00[] = "DSP-Board"; +static const char pci_device_14b5_0b00[] = "DSP-Board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b6[] = "Quantum Data Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b7[] = "PROXIM Inc"; +static const char pci_device_14b7_0001[] = "Symphony 4110"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b8[] = "Techsoft Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b9[] = "AIRONET Wireless Communications"; +static const char pci_device_14b9_0001[] = "PC4800"; +static const char pci_device_14b9_0340[] = "PC4800"; +static const char pci_device_14b9_0350[] = "PC4800"; +static const char pci_device_14b9_4500[] = "PC4500"; +static const char pci_device_14b9_4800[] = "PC4800"; +static const char pci_device_14b9_a504[] = "Cisco Aironet Wireless 802.11b"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ba[] = "INTERNIX Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14bb[] = "SEMTECH Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14bc[] = "Globespan Semiconductor Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14bd[] = "CARDIO Control N.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14be[] = "L3 Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14bf[] = "SPIDER Communications Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c0[] = "COMPAL Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c1[] = "MYRICOM Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c2[] = "DTK Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c3[] = "MEDIATEK Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c4[] = "IWASAKI Information Systems Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c5[] = "Automation Products AB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c6[] = "Data Race Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c7[] = "Modular Technology Holdings Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c8[] = "Turbocomm Tech. Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c9[] = "ODIN Telesystems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ca[] = "PE Logic Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14cb[] = "Billionton Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14cc[] = "NAKAYO Telecommunications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14cd[] = "Universal Scientific Ind."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ce[] = "Whistle Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14cf[] = "TEK Microsystems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d0[] = "Ericsson Axe R & D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d1[] = "Computer Hi-Tech Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d2[] = "Titan Electronics Inc"; +static const char pci_device_14d2_8001[] = "VScom 010L 1 port parallel adaptor"; +static const char pci_device_14d2_8002[] = "VScom 020L 2 port parallel adaptor"; +static const char pci_device_14d2_8010[] = "VScom 100L 1 port serial adaptor"; +static const char pci_device_14d2_8011[] = "VScom 110L 1 port serial and 1 port parallel adaptor"; +static const char pci_device_14d2_8020[] = "VScom 200L 1 port serial adaptor"; +static const char pci_device_14d2_8021[] = "VScom 210L 2 port serial and 1 port parallel adaptor"; +static const char pci_device_14d2_8040[] = "VScom 400L 4 port serial adaptor"; +static const char pci_device_14d2_8080[] = "VScom 800L 8 port serial adaptor"; +static const char pci_device_14d2_a000[] = "VScom 010H 1 port parallel adaptor"; +static const char pci_device_14d2_a001[] = "VScom 100H 1 port serial adaptor"; +static const char pci_device_14d2_a003[] = "VScom 400H 4 port serial adaptor"; +static const char pci_device_14d2_a004[] = "VScom 400HF1 4 port serial adaptor"; +static const char pci_device_14d2_a005[] = "VScom 200H 2 port serial adaptor"; +static const char pci_device_14d2_e001[] = "VScom 010HV2 1 port parallel adaptor"; +static const char pci_device_14d2_e010[] = "VScom 100HV2 1 port serial adaptor"; +static const char pci_device_14d2_e020[] = "VScom 200HV2 2 port serial adaptor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d3[] = "CIRTECH (UK) Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d4[] = "Panacom Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d5[] = "Nitsuko Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d6[] = "Accusys Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d7[] = "Hirakawa Hewtech Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d8[] = "HOPF Elektronik GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d9[] = "Alpha Processor Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14da[] = "National Aerospace Laboratories"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14db[] = "AFAVLAB Technology Inc"; +static const char pci_device_14db_2120[] = "TK9902"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14dc[] = "Amplicon Liveline Ltd"; +static const char pci_device_14dc_0000[] = "PCI230"; +static const char pci_device_14dc_0001[] = "PCI242"; +static const char pci_device_14dc_0002[] = "PCI244"; +static const char pci_device_14dc_0003[] = "PCI247"; +static const char pci_device_14dc_0004[] = "PCI248"; +static const char pci_device_14dc_0005[] = "PCI249"; +static const char pci_device_14dc_0006[] = "PCI260"; +static const char pci_device_14dc_0007[] = "PCI224"; +static const char pci_device_14dc_0008[] = "PCI234"; +static const char pci_device_14dc_0009[] = "PCI236"; +static const char pci_device_14dc_000a[] = "PCI272"; +static const char pci_device_14dc_000b[] = "PCI215"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14dd[] = "Boulder Design Labs Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14de[] = "Applied Integration Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14df[] = "ASIC Communications Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e1[] = "INVERTEX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e2[] = "INFOLIBRIA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e3[] = "AMTELCO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e4[] = "Broadcom Corporation"; +static const char pci_device_14e4_1644[] = "NetXtreme BCM5700 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1014_0277[] = "Broadcom Vigil B5700 1000Base-T"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1028_00d1[] = "Broadcom BCM5700"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1028_0106[] = "Broadcom BCM5700"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1028_0109[] = "Broadcom BCM5700 1000Base-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1028_010a[] = "Broadcom BCM5700 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1000[] = "3C996-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1001[] = "3C996B-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1002[] = "3C996C-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1003[] = "3C997-T 1000Base-T Dual Port"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1004[] = "3C996-SX 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1005[] = "3C997-SX 1000Base-SX Dual Port"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1008[] = "3C942 Gigabit LOM (31X31)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_0002[] = "NetXtreme 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_0003[] = "NetXtreme 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_0004[] = "NetXtreme 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_1028[] = "NetXtreme 1000BaseTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_1644[] = "BCM5700 1000Base-T"; +#endif +static const char pci_device_14e4_1645[] = "NetXtreme BCM5701 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_007c[] = "NC7770 Gigabit Server Adapter (PCI-X, 10/100/1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_007d[] = "NC6770 Gigabit Server Adapter (PCI-X, 1000-SX)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_0085[] = "NC7780 Gigabit Server Adapter (embedded, WOL)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_0099[] = "NC7780 Gigabit Server Adapter (embedded, WOL)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_009a[] = "NC7770 Gigabit Server Adapter (PCI-X, 10/100/1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_00c1[] = "NC6770 Gigabit Server Adapter (PCI-X, 1000-SX)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_1028_0121[] = "Broadcom BCM5701 1000Base-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10b7_1004[] = "3C996-SX 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10b7_1006[] = "3C996B-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10b7_1007[] = "3C1000-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10b7_1008[] = "3C940-BR01 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0001[] = "BCM5701 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0005[] = "BCM5701 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0006[] = "BCM5701 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0007[] = "BCM5701 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0008[] = "BCM5701 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_8008[] = "BCM5701 1000Base-T"; +#endif +static const char pci_device_14e4_1646[] = "NetXtreme BCM5702 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1646_0e11_00bb[] = "NC7760 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1646_1028_0126[] = "Broadcom BCM5702 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1646_14e4_8009[] = "BCM5702 1000BaseTX"; +#endif +static const char pci_device_14e4_1647[] = "NetXtreme BCM5703 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_0e11_0099[] = "NC7780 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_0e11_009a[] = "NC7770 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_0009[] = "BCM5703 1000BaseTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_000a[] = "BCM5703 1000BaseSX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_000b[] = "BCM5703 1000BaseTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_8009[] = "BCM5703 1000BaseTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_800a[] = "BCM5703 1000BaseTX"; +#endif +static const char pci_device_14e4_1648[] = "NetXtreme BCM5704 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_0e11_00cf[] = "NC7772 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_0e11_00d0[] = "NC7782 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_0e11_00d1[] = "NC7783 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_10b7_2000[] = "3C998-T Dual Port 10/100/1000 PCI-X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_10b7_3000[] = "3C999-T Quad Port 10/100/1000 PCI-X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_1166_1648[] = "NetXtreme CIOB-E 1000Base-T"; +#endif +static const char pci_device_14e4_164d[] = "NetXtreme BCM5702FE Gigabit Ethernet"; +static const char pci_device_14e4_1653[] = "NetXtreme BCM5705 Gigabit Ethernet"; +static const char pci_device_14e4_165d[] = "NetXtreme BCM5705M Gigabit Ethernet"; +static const char pci_device_14e4_1696[] = "NetXtreme BCM5782 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1696_14e4_000d[] = "NetXtreme BCM5782 1000Base-T"; +#endif +static const char pci_device_14e4_16a6[] = "NetXtreme BCM5702 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a6_0e11_00bb[] = "NC7760 Gigabit Server Adapter (PCI-X, 10/100/1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a6_1028_0126[] = "BCM5702 1000Base-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a6_14e4_000c[] = "BCM5702 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a6_14e4_8009[] = "BCM5702 1000Base-T"; +#endif +static const char pci_device_14e4_16a7[] = "NetXtreme BCM5703 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_0e11_00ca[] = "NC7771 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_0e11_00cb[] = "NC7781 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_14e4_0009[] = "NetXtreme BCM5703 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_14e4_000a[] = "NetXtreme BCM5703 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_14e4_000b[] = "NetXtreme BCM5703 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_14e4_800a[] = "NetXtreme BCM5703 1000Base-T"; +#endif +static const char pci_device_14e4_16a8[] = "NetXtreme BCM5704S Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a8_10b7_2001[] = "3C998-SX Dual Port 1000-SX PCI-X"; +#endif +static const char pci_device_14e4_16c6[] = "NetXtreme BCM5702 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c6_10b7_1100[] = "3C1000B-T 10/100/1000 PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c6_14e4_000c[] = "BCM5702 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c6_14e4_8009[] = "BCM5702 1000Base-T"; +#endif +static const char pci_device_14e4_16c7[] = "NetXtreme BCM5703 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_14e4_0009[] = "NetXtreme BCM5703 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_14e4_000a[] = "NetXtreme BCM5703 1000Base-SX"; +#endif +static const char pci_device_14e4_4210[] = "BCM4210 iLine10 HomePNA 2.0"; +static const char pci_device_14e4_4211[] = "BCM4211 iLine10 HomePNA 2.0 + V.90 56k modem"; +static const char pci_device_14e4_4212[] = "BCM4212 v.90 56k modem"; +static const char pci_device_14e4_4301[] = "BCM4301 802.11b"; +static const char pci_device_14e4_4401[] = "BCM4401 100Base-T"; +static const char pci_device_14e4_4402[] = "BCM4402 Integrated 10/100BaseT"; +static const char pci_device_14e4_4410[] = "BCM4413 iLine32 HomePNA 2.0"; +static const char pci_device_14e4_4411[] = "BCM4413 V.90 56k modem"; +static const char pci_device_14e4_4412[] = "BCM4413 10/100BaseT"; +static const char pci_device_14e4_5820[] = "BCM5820 Crypto Accelerator"; +static const char pci_device_14e4_5821[] = "BCM5821 Crypto Accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e5[] = "Pixelfusion Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e6[] = "SHINING Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e7[] = "3CX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e8[] = "RAYCER Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e9[] = "GARNETS System CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ea[] = "Planex Communications, Inc"; +static const char pci_device_14ea_ab06[] = "FNW-3603-TX CardBus Fast Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14eb[] = "SEIKO EPSON Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ec[] = "ACQIRIS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ed[] = "DATAKINETICS Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ee[] = "MASPRO KENKOH Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ef[] = "CARRY Computer ENG. CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f0[] = "CANON RESEACH CENTRE FRANCE"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f1[] = "Conexant"; +static const char pci_device_14f1_1002[] = "HCF 56k Modem"; +static const char pci_device_14f1_1003[] = "HCF 56k Modem"; +static const char pci_device_14f1_1004[] = "HCF 56k Modem"; +static const char pci_device_14f1_1005[] = "HCF 56k Modem"; +static const char pci_device_14f1_1006[] = "HCF 56k Modem"; +static const char pci_device_14f1_1022[] = "HCF 56k Modem"; +static const char pci_device_14f1_1023[] = "HCF 56k Modem"; +static const char pci_device_14f1_1024[] = "HCF 56k Modem"; +static const char pci_device_14f1_1025[] = "HCF 56k Modem"; +static const char pci_device_14f1_1026[] = "HCF 56k Modem"; +static const char pci_device_14f1_1032[] = "HCF 56k Modem"; +static const char pci_device_14f1_1033[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_1033_8077[] = "NEC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_122d_4027[] = "Dell Zeus - MDP3880-W(B) Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_122d_4030[] = "Dell Mercury - MDP3880-U(B) Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_122d_4034[] = "Dell Thor - MDP3880-W(U) Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_020d[] = "Dell Copper"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_020e[] = "Dell Silver"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_0261[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_0290[] = "Compaq Goldwing"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_02a0[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_02b0[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_02c0[] = "Compaq Scooter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_02d0[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_1500[] = "IBM P85-DF (1)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_1501[] = "IBM P85-DF (2)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_150a[] = "IBM P85-DF (3)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_150b[] = "IBM P85-DF Low Profile (1)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_1510[] = "IBM P85-DF Low Profile (2)"; +#endif +static const char pci_device_14f1_1034[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_1035[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1035_10cf_1098[] = "Fujitsu P85-DFSV"; +#endif +static const char pci_device_14f1_1036[] = "HCF 56k Data/Fax/Voice/Spkp Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_104d_8067[] = "HCF 56k Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_122d_4029[] = "MDP3880SP-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_122d_4031[] = "MDP3880SP-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_13e0_0209[] = "Dell Titanium"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_13e0_020a[] = "Dell Graphite"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_13e0_0260[] = "Gateway Red Owl"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_13e0_0270[] = "Gateway White Horse"; +#endif +static const char pci_device_14f1_1052[] = "HCF 56k Data/Fax Modem (Worldwide)"; +static const char pci_device_14f1_1053[] = "HCF 56k Data/Fax Modem (Worldwide)"; +static const char pci_device_14f1_1054[] = "HCF 56k Data/Fax/Voice Modem (Worldwide)"; +static const char pci_device_14f1_1055[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (Worldwide)"; +static const char pci_device_14f1_1056[] = "HCF 56k Data/Fax/Voice/Spkp Modem (Worldwide)"; +static const char pci_device_14f1_1057[] = "HCF 56k Data/Fax/Voice/Spkp Modem (Worldwide)"; +static const char pci_device_14f1_1059[] = "HCF 56k Data/Fax/Voice Modem (Worldwide)"; +static const char pci_device_14f1_1063[] = "HCF 56k Data/Fax Modem"; +static const char pci_device_14f1_1064[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_1065[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_1066[] = "HCF 56k Data/Fax/Voice/Spkp Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1066_122d_4033[] = "Dell Athena - MDP3900V-U"; +#endif +static const char pci_device_14f1_1433[] = "HCF 56k Data/Fax Modem"; +static const char pci_device_14f1_1434[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_1435[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_1436[] = "HCF 56k Data/Fax Modem"; +static const char pci_device_14f1_1453[] = "HCF 56k Data/Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1453_13e0_0240[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1453_13e0_0250[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1453_144f_1502[] = "IBM P95-DF (1)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1453_144f_1503[] = "IBM P95-DF (2)"; +#endif +static const char pci_device_14f1_1454[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_1455[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_1456[] = "HCF 56k Data/Fax/Voice/Spkp Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1456_122d_4035[] = "Dell Europa - MDP3900V-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1456_122d_4302[] = "Dell MP3930V-W(C) MiniPCI"; +#endif +static const char pci_device_14f1_1610[] = "ADSL AccessRunner PCI Arbitration Device"; +static const char pci_device_14f1_1611[] = "AccessRunner PCI ADSL Interface Device"; +static const char pci_device_14f1_1803[] = "HCF 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1803_0e11_0023[] = "623-LAN Grizzly"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1803_0e11_0043[] = "623-LAN Yogi"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14f1_1815[] = "HCF 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1815_0e11_0022[] = "Grizzly"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1815_0e11_0042[] = "Yogi"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14f1_2003[] = "HSF 56k Data/Fax Modem"; +static const char pci_device_14f1_2004[] = "HSF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_2005[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_2006[] = "HSF 56k Data/Fax/Voice/Spkp Modem"; +static const char pci_device_14f1_2013[] = "HSF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_0e11_b195[] = "Bear"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_0e11_b196[] = "Seminole 1"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_0e11_b1be[] = "Seminole 2"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_1025_8013[] = "Acer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_1033_809d[] = "NEC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_1033_80bc[] = "NEC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_155d_6793[] = "HP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_155d_8850[] = "E Machines"; +#endif +static const char pci_device_14f1_2014[] = "HSF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_2015[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_2016[] = "HSF 56k Data/Fax/Voice/Spkp Modem"; +static const char pci_device_14f1_2043[] = "HSF 56k Data/Fax Modem (WorldW SmartDAA)"; +static const char pci_device_14f1_2044[] = "HSF 56k Data/Fax/Voice Modem (WorldW SmartDAA)"; +static const char pci_device_14f1_2045[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (WorldW SmartDAA)"; +static const char pci_device_14f1_2046[] = "HSF 56k Data/Fax/Voice/Spkp Modem (WorldW SmartDAA)"; +static const char pci_device_14f1_2063[] = "HSF 56k Data/Fax Modem (SmartDAA)"; +static const char pci_device_14f1_2064[] = "HSF 56k Data/Fax/Voice Modem (SmartDAA)"; +static const char pci_device_14f1_2065[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (SmartDAA)"; +static const char pci_device_14f1_2066[] = "HSF 56k Data/Fax/Voice/Spkp Modem (SmartDAA)"; +static const char pci_device_14f1_2093[] = "HSF 56k Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2093_155d_2f07[] = "Legend"; +#endif +static const char pci_device_14f1_2143[] = "HSF 56k Data/Fax/Cell Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2144[] = "HSF 56k Data/Fax/Voice/Cell Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2145[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS)/Cell Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2146[] = "HSF 56k Data/Fax/Voice/Spkp/Cell Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2163[] = "HSF 56k Data/Fax/Cell Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2164[] = "HSF 56k Data/Fax/Voice/Cell Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2165[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS)/Cell Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2166[] = "HSF 56k Data/Fax/Voice/Spkp/Cell Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2343[] = "HSF 56k Data/Fax CardBus Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2344[] = "HSF 56k Data/Fax/Voice CardBus Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2345[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS) CardBus Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2346[] = "HSF 56k Data/Fax/Voice/Spkp CardBus Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2363[] = "HSF 56k Data/Fax CardBus Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2364[] = "HSF 56k Data/Fax/Voice CardBus Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2365[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS) CardBus Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2366[] = "HSF 56k Data/Fax/Voice/Spkp CardBus Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2443[] = "HSF 56k Data/Fax Modem (Mob WorldW SmartDAA)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2443_104d_8075[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2443_104d_8083[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2443_104d_8097[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14f1_2444[] = "HSF 56k Data/Fax/Voice Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2445[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS) Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2446[] = "HSF 56k Data/Fax/Voice/Spkp Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2463[] = "HSF 56k Data/Fax Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2464[] = "HSF 56k Data/Fax/Voice Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2465[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS) Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2466[] = "HSF 56k Data/Fax/Voice/Spkp Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2f00[] = "HSF 56k HSFi Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2f00_13e0_8d84[] = "IBM HSFi V.90"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2f00_13e0_8d85[] = "Compaq Stinger"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2f00_14f1_2004[] = "Dynalink 56PMi"; +#endif +static const char pci_device_14f1_8234[] = "RS8234 ATM SAR Controller [ServiceSAR Plus]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f2[] = "MOBILITY Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f3[] = "BROADLOGIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f4[] = "TOKYO Electronic Industry CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f5[] = "SOPAC Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f6[] = "COYOTE Technologies LLC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f7[] = "WOLF Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f8[] = "AUDIOCODES Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f9[] = "AG COMMUNICATIONS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fa[] = "WANDEL & GOCHERMANN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fb[] = "TRANSAS MARINE (UK) Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fc[] = "QUADRICS Supercomputers World"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fd[] = "JAPAN Computer Industry Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fe[] = "ARCHTEK TELECOM Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ff[] = "TWINHEAD INTERNATIONAL Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1500[] = "DELTA Electronics, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1501[] = "BANKSOFT CANADA Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1502[] = "MITSUBISHI ELECTRIC LOGISTICS SUPPORT Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1503[] = "KAWASAKI LSI USA Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1504[] = "KAISER Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1505[] = "ITA INGENIEURBURO FUR TESTAUFGABEN GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1506[] = "CHAMELEON Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1507[] = "Motorola ? / HTEC"; +static const char pci_device_1507_0001[] = "MPC105 [Eagle]"; +static const char pci_device_1507_0002[] = "MPC106 [Grackle]"; +static const char pci_device_1507_0003[] = "MPC8240 [Kahlua]"; +static const char pci_device_1507_0100[] = "MC145575 [HFC-PCI]"; +static const char pci_device_1507_0431[] = "KTI829c 100VG"; +static const char pci_device_1507_4801[] = "Raven"; +static const char pci_device_1507_4802[] = "Falcon"; +static const char pci_device_1507_4803[] = "Hawk"; +static const char pci_device_1507_4806[] = "CPX8216"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1508[] = "HONDA CONNECTORS/MHOTRONICS Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1509[] = "FIRST INTERNATIONAL Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150a[] = "FORVUS RESEARCH Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150b[] = "YAMASHITA Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150c[] = "KYOPAL CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150d[] = "WARPSPPED Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150e[] = "C-PORT Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150f[] = "INTEC GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1510[] = "BEHAVIOR TECH Computer Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1511[] = "CENTILLIUM Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1512[] = "ROSUN Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1513[] = "Raychem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1514[] = "TFL LAN Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1515[] = "Advent design"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1516[] = "MYSON Technology Inc"; +static const char pci_device_1516_0803[] = "SURECOM EP-320X-S 100/10M Ethernet PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1516_0803_1320_10bd[] = "SURECOM EP-320X-S 100/10M Ethernet PCI Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1517[] = "ECHOTEK Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1518[] = "PEP MODULAR Computers GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1519[] = "TELEFON AKTIEBOLAGET LM Ericsson"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151a[] = "Globetek"; +static const char pci_device_151a_1002[] = "PCI-1002"; +static const char pci_device_151a_1004[] = "PCI-1004"; +static const char pci_device_151a_1008[] = "PCI-1008"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151b[] = "COMBOX Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151c[] = "DIGITAL AUDIO LABS Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151d[] = "Fujitsu Computer Products Of America"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151e[] = "MATRIX Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151f[] = "TOPIC SEMICONDUCTOR Corp"; +static const char pci_device_151f_0000[] = "TP560 Data/Fax/Voice 56k modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1520[] = "CHAPLET System Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1521[] = "BELL Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1522[] = "MainPine Ltd"; +static const char pci_device_1522_0100[] = "PCI <-> IOBus Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0200[] = "RockForceDUO 2 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0300[] = "RockForceQUATRO 4 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0400[] = "RockForceDUO+ 2 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0500[] = "RockForceQUATRO+ 4 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0600[] = "RockForce+ 2 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0700[] = "RockForce+ 4 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0800[] = "RockForceOCTO+ 8 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1523[] = "MUSIC Semiconductors"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1524[] = "ENE Technology Inc"; +static const char pci_device_1524_1211[] = "CB1211 Cardbus Controller"; +static const char pci_device_1524_1225[] = "CB1225 Cardbus Controller"; +static const char pci_device_1524_1410[] = "CB1410 Cardbus Controller"; +static const char pci_device_1524_1420[] = "CB1420 Cardbus Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1525[] = "IMPACT Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1526[] = "ISS, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1527[] = "SOLECTRON"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1528[] = "ACKSYS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1529[] = "AMERICAN MICROSystems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152a[] = "QUICKTURN DESIGN Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152b[] = "FLYTECH Technology CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152c[] = "MACRAIGOR Systems LLC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152d[] = "QUANTA Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152e[] = "MELEC Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152f[] = "PHILIPS - CRYPTO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1530[] = "ACQIS Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1531[] = "CHRYON Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1532[] = "ECHELON Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1533[] = "BALTIMORE"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1534[] = "ROAD Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1535[] = "EVERGREEN Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1537[] = "DATALEX COMMUNCATIONS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1538[] = "ARALION Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1539[] = "ATELIER INFORMATIQUES et ELECTRONIQUE ETUDES S.A."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153a[] = "ONO SOKKI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153b[] = "TERRATEC Electronic GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153c[] = "ANTAL Electronic"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153d[] = "FILANET Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153e[] = "TECHWELL Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153f[] = "MIPS DENMARK"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1540[] = "PROVIDEO MULTIMEDIA Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1541[] = "MACHONE Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1542[] = "VIVID Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1543[] = "SILICON Laboratories"; +static const char pci_device_1543_3052[] = "Intel 537 [Winmodem]"; +static const char pci_device_1543_4c22[] = "Si3036 MC'97 DAA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1544[] = "DCM DATA Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1545[] = "VISIONTEK"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1546[] = "IOI Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1547[] = "MITUTOYO Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1548[] = "JET PROPULSION Laboratory"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1549[] = "INTERCONNECT Systems Solutions"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154a[] = "MAX Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154b[] = "COMPUTEX Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154c[] = "VISUAL Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154d[] = "PAN INTERNATIONAL Industrial Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154e[] = "SERVOTEST Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154f[] = "STRATABEAM Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1550[] = "OPEN NETWORK Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1551[] = "SMART Electronic DEVELOPMENT GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1552[] = "RACAL AIRTECH Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1553[] = "CHICONY Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1554[] = "PROLINK Microsystems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1555[] = "GESYTEC GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1556[] = "PLD APPLICATIONS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1557[] = "MEDIASTAR Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1558[] = "CLEVO/KAPOK Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1559[] = "SI LOGIC Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155a[] = "INNOMEDIA Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155b[] = "PROTAC INTERNATIONAL Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155c[] = "Cemax-Icon Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155d[] = "Mac System Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155e[] = "LP Elektronik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155f[] = "Perle Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1560[] = "Terayon Communications Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1561[] = "Viewgraphics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1562[] = "Symbol Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1563[] = "A-Trend Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1564[] = "Yamakatsu Electronics Industry Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1565[] = "Biostar Microtech Int'l Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1566[] = "Ardent Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1567[] = "Jungsoft"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1568[] = "DDK Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1569[] = "Palit Microsystems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156a[] = "Avtec Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156b[] = "2wire Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156c[] = "Vidac Electronics GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156d[] = "Alpha-Top Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156e[] = "Alfa Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156f[] = "M-Systems Flash Disk Pioneers Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1570[] = "Lecroy Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1571[] = "Contemporary Controls"; +static const char pci_device_1571_a001[] = "CCSI PCI20-485 ARCnet"; +static const char pci_device_1571_a002[] = "CCSI PCI20-485D ARCnet"; +static const char pci_device_1571_a003[] = "CCSI PCI20-485X ARCnet"; +static const char pci_device_1571_a004[] = "CCSI PCI20-CXB ARCnet"; +static const char pci_device_1571_a005[] = "CCSI PCI20-CXS ARCnet"; +static const char pci_device_1571_a006[] = "CCSI PCI20-FOG-SMA ARCnet"; +static const char pci_device_1571_a007[] = "CCSI PCI20-FOG-ST ARCnet"; +static const char pci_device_1571_a008[] = "CCSI PCI20-TB5 ARCnet"; +static const char pci_device_1571_a009[] = "CCSI PCI20-5-485 5Mbit ARCnet"; +static const char pci_device_1571_a00a[] = "CCSI PCI20-5-485D 5Mbit ARCnet"; +static const char pci_device_1571_a00b[] = "CCSI PCI20-5-485X 5Mbit ARCnet"; +static const char pci_device_1571_a00c[] = "CCSI PCI20-5-FOG-ST 5Mbit ARCnet"; +static const char pci_device_1571_a00d[] = "CCSI PCI20-5-FOG-SMA 5Mbit ARCnet"; +static const char pci_device_1571_a201[] = "CCSI PCI22-485 10Mbit ARCnet"; +static const char pci_device_1571_a202[] = "CCSI PCI22-485D 10Mbit ARCnet"; +static const char pci_device_1571_a203[] = "CCSI PCI22-485X 10Mbit ARCnet"; +static const char pci_device_1571_a204[] = "CCSI PCI22-CHB 10Mbit ARCnet"; +static const char pci_device_1571_a205[] = "CCSI PCI22-FOG_ST 10Mbit ARCnet"; +static const char pci_device_1571_a206[] = "CCSI PCI22-THB 10Mbit ARCnet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1572[] = "Otis Elevator Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1573[] = "Lattice - Vantis"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1574[] = "Fairchild Semiconductor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1575[] = "Voltaire Advanced Data Security Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1576[] = "Viewcast COM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1578[] = "HITT"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1579[] = "Dual Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157a[] = "Japan Elecronics Ind Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157b[] = "Star Multimedia Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157c[] = "Eurosoft (UK)"; +static const char pci_device_157c_8001[] = "Fix2000 PCI Y2K Compliance Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157d[] = "Gemflex Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157e[] = "Transition Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157f[] = "PX Instruments Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1580[] = "Primex Aerospace Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1581[] = "SEH Computertechnik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1582[] = "Cytec Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1583[] = "Inet Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1584[] = "Uniwill Computer Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1585[] = "Logitron"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1586[] = "Lancast Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1587[] = "Konica Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1588[] = "Solidum Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1589[] = "Atlantek Microsystems Pty Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158a[] = "Digalog Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158b[] = "Allied Data Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158c[] = "Hitachi Semiconductor & Devices Sales Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158d[] = "Point Multimedia Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158e[] = "Lara Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158f[] = "Ditect Coop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1590[] = "3pardata Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1591[] = "ARN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1592[] = "Syba Tech Ltd"; +static const char pci_device_1592_0781[] = "Multi-IO Card"; +static const char pci_device_1592_0782[] = "Parallel Port Card 2xEPP"; +static const char pci_device_1592_0783[] = "Multi-IO Card"; +static const char pci_device_1592_0785[] = "Multi-IO Card"; +static const char pci_device_1592_0786[] = "Multi-IO Card"; +static const char pci_device_1592_0787[] = "Multi-IO Card"; +static const char pci_device_1592_0788[] = "Multi-IO Card"; +static const char pci_device_1592_078a[] = "Multi-IO Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1593[] = "Bops Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1594[] = "Netgame Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1595[] = "Diva Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1596[] = "Folsom Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1597[] = "Memec Design Services"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1598[] = "Granite Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1599[] = "Delta Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159a[] = "General Instrument"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159b[] = "Faraday Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159c[] = "Stratus Computer Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159d[] = "Ningbo Harrison Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159e[] = "A-Max Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159f[] = "Galea Network Security"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a0[] = "Compumaster SRL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a1[] = "Geocast Network Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a2[] = "Catalyst Enterprises Inc"; +static const char pci_device_15a2_0001[] = "TA700 PCI Bus Analyzer/Exerciser"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a3[] = "Italtel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a4[] = "X-Net OY"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a5[] = "Toyota Macs Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a6[] = "Sunlight Ultrasound Technologies Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a7[] = "SSE Telecom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a8[] = "Shanghai Communications Technologies Center"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15aa[] = "Moreton Bay"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ab[] = "Bluesteel Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ac[] = "North Atlantic Instruments"; +#endif +static const char pci_vendor_15ad[] = "VMWare Inc"; +static const char pci_device_15ad_0710[] = "Virtual SVGA"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ae[] = "Amersham Pharmacia Biotech"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b0[] = "Zoltrix International Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b1[] = "Source Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b2[] = "Mosaid Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b3[] = "Mellanox Technology"; +static const char pci_device_15b3_5274[] = "MT21108 InfiniBridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b4[] = "CCI/TRIAD"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b5[] = "Cimetrics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b6[] = "Texas Memory Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b7[] = "Sandisk Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b8[] = "ADDI-DATA GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b9[] = "Maestro Digital Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ba[] = "Impacct Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15bb[] = "Portwell Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15bc[] = "Agilent Technologies"; +static const char pci_device_15bc_2929[] = "E2929A PCI/PCI-X Bus Analyzer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15bd[] = "DFI Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15be[] = "Sola Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15bf[] = "High Tech Computer Corp (HTC)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c0[] = "BVM Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c1[] = "Quantel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c2[] = "Newer Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c3[] = "Taiwan Mycomp Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c4[] = "EVSX Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c5[] = "Procomp Informatics Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c6[] = "Technical University of Budapest"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c7[] = "Tateyama System Laboratory Co Ltd"; +static const char pci_device_15c7_0349[] = "Tateyama C-PCI PLC/NC card Rev.01A"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c8[] = "Penta Media Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c9[] = "Serome Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ca[] = "Bitboys OY"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15cb[] = "AG Electronics Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15cc[] = "Hotrail Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15cd[] = "Dreamtech Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ce[] = "Genrad Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15cf[] = "Hilscher GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d1[] = "Infineon Technologies AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d2[] = "FIC (First International Computer Inc)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d3[] = "NDS Technologies Israel Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d4[] = "Iwill Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d5[] = "Tatung Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d6[] = "Entridia Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d7[] = "Rockwell-Collins Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d8[] = "Cybernetics Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d9[] = "Super Micro Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15da[] = "Cyberfirm Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15db[] = "Applied Computing Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15dc[] = "Litronic Inc"; +static const char pci_device_15dc_0001[] = "Argus 300 PCI Cryptography Module"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15dd[] = "Sigmatel Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15de[] = "Malleable Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15df[] = "Infinilink Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e0[] = "Cacheflow Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e1[] = "Voice Technologies Group Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e2[] = "Quicknet Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e3[] = "Networth Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e4[] = "VSN Systemen BV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e5[] = "Valley technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e6[] = "Agere Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e7[] = "Get Engineering Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e8[] = "National Datacomm Corp"; +static const char pci_device_15e8_0130[] = "Wireless PCI Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e9[] = "Pacific Digital Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ea[] = "Tokyo Denshi Sekei K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15eb[] = "Drsearch GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ec[] = "Beckhoff GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ed[] = "Macrolink Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ee[] = "In Win Development Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ef[] = "Intelligent Paradigm Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f0[] = "B-Tree Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f1[] = "Times N Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f2[] = "Diagnostic Instruments Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f3[] = "Digitmedia Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f4[] = "Valuesoft"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f5[] = "Power Micro Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f6[] = "Extreme Packet Device Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f7[] = "Banctec"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f8[] = "Koga Electronics Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f9[] = "Zenith Electronics Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fa[] = "J.P. Axzam Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fb[] = "Zilog Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fc[] = "Techsan Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fd[] = "N-CUBED.NET"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fe[] = "Kinpo Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ff[] = "Fastpoint Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1600[] = "Northrop Grumman - Canada Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1601[] = "Tenta Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1602[] = "Prosys-tec Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1603[] = "Nokia Wireless Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1604[] = "Central System Research Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1605[] = "Pairgain Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1606[] = "Europop AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1607[] = "Lava Semiconductor Manufacturing Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1608[] = "Automated Wagering International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1609[] = "Scimetric Instruments Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1612[] = "Telesynergy Research Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1619[] = "FarSite Communications Ltd"; +static const char pci_device_1619_0400[] = "FarSync T2P (2 port X.21/V.35/V.24)"; +static const char pci_device_1619_0440[] = "FarSync T4P (4 port X.21/V.35/V.24)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1629[] = "Kongsberg Spacetec AS"; +static const char pci_device_1629_1003[] = "Format synchronizer v3.0"; +static const char pci_device_1629_2002[] = "Fast Universal Data Output"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1638[] = "Standard Microsystems Corp [SMC]"; +static const char pci_device_1638_1100[] = "SMC2602W EZConnect / Addtron AWA-100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_163c[] = "Smart Link Ltd."; +static const char pci_device_163c_5449[] = "SmartPCI561 Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1657[] = "Brocade Communications Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_165a[] = "Epix Inc"; +static const char pci_device_165a_c100[] = "PIXCI(R) CL1 Camera Link Video Capture Board [custom QL5232]"; +static const char pci_device_165a_d200[] = "PIXCI(R) D2X Digital Video Capture Board [custom QL5232]"; +static const char pci_device_165a_d300[] = "PIXCI(R) D3X Digital Video Capture Board [custom QL5232]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_165d[] = "Hsing Tech. Enterprise Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1661[] = "Worldspace Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1668[] = "Actiontec Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1681[] = "Hercules"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ab[] = "Global Sun Technology Inc"; +static const char pci_device_16ab_1102[] = "PCMCIA-to-PCI Wireless Network Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16be[] = "Creatix Polymedia GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ec[] = "U.S. Robotics"; +static const char pci_device_16ec_3685[] = "Wireless Access PCI Adapter Model 022415"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16f6[] = "VideoTele.com, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1705[] = "Digital First, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_170b[] = "NetOctave Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_170c[] = "YottaYotta Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_172a[] = "Accelerated Encryption"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1737[] = "Linksys"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_173b[] = "Altima (nee Broadcom)"; +static const char pci_device_173b_03e8[] = "AC1000 Gigabit Ethernet"; +static const char pci_device_173b_03ea[] = "AC9100 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_173b_03ea_173b_0001[] = "AC1002"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1743[] = "Peppercon AG"; +static const char pci_device_1743_8139[] = "ROL/F-100 Fast Ethernet Adapter with ROL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_174b[] = "PC Partner Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_175e[] = "Sanera Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1787[] = "Hightech Information System Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1796[] = "Research Centre Juelich"; +static const char pci_device_1796_0001[] = "SIS1100 [Gigabit link]"; +static const char pci_device_1796_0002[] = "HOTlink"; +static const char pci_device_1796_0003[] = "Counter Timer"; +static const char pci_device_1796_0004[] = "CAMAC Controller"; +static const char pci_device_1796_0005[] = "PROFIBUS"; +static const char pci_device_1796_0006[] = "AMCC HOTlink"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1799[] = "Belkin"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17af[] = "Hightech Information System Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17cc[] = "NetChip Technology, Inc"; +static const char pci_device_17cc_2280[] = "USB 2.0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1813[] = "Ambient Technologies Inc"; +static const char pci_device_1813_4000[] = "HaM controllerless modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1813_4000_16be_0001[] = "V9x HAM Data Fax Modem"; +#endif +static const char pci_device_1813_4100[] = "HaM plus Data Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1813_4100_16be_0002[] = "V9x HAM 1394"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1851[] = "Microtune, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1852[] = "Anritsu Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1888[] = "Varisys Ltd"; +static const char pci_device_1888_0301[] = "VMFX1 FPGA PMC module"; +static const char pci_device_1888_0601[] = "VSM2 dual PMC carrier"; +static const char pci_device_1888_0710[] = "VS14x series PowerPC PCI board"; +static const char pci_device_1888_0720[] = "VS24x series PowerPC PCI board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1a08[] = "Sierra semiconductor"; +static const char pci_device_1a08_0000[] = "SC15064"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1b13[] = "Jaton Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1c1c[] = "Symphony"; +static const char pci_device_1c1c_0001[] = "82C101"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1d44[] = "DPT"; +static const char pci_device_1d44_a400[] = "PM2x24/PM3224"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1de1[] = "Tekram Technology Co.,Ltd."; +static const char pci_device_1de1_0391[] = "TRM-S1040"; +static const char pci_device_1de1_2020[] = "DC-390"; +static const char pci_device_1de1_690c[] = "690c"; +static const char pci_device_1de1_dc29[] = "DC290"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2000[] = "Smart Link Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2001[] = "Temporal Research Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2003[] = "Smart Link Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2004[] = "Smart Link Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_21c3[] = "21st Century Computer Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2348[] = "Racore"; +static const char pci_device_2348_2010[] = "8142 100VG/AnyLAN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2646[] = "Kingston Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_270b[] = "Xantel Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_270f[] = "Chaintech Computer Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2711[] = "AVID Technology Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2a15[] = "3D Vision(?)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3000[] = "Hansol Electronics Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3142[] = "Post Impression Systems."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3388[] = "Hint Corp"; +static const char pci_device_3388_0013[] = "HiNT HC4 PCI to ISDN bridge, Multimedia audio controller"; +static const char pci_device_3388_0014[] = "HiNT HC4 PCI to ISDN bridge, Network controller"; +static const char pci_device_3388_0021[] = "HB1-SE33 PCI-PCI Bridge"; +static const char pci_device_3388_8011[] = "VXPro II Chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_8011_3388_8011[] = "VXPro II Chipset CPU to PCI Bridge"; +#endif +static const char pci_device_3388_8012[] = "VXPro II Chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_8012_3388_8012[] = "VXPro II Chipset PCI to ISA Bridge"; +#endif +static const char pci_device_3388_8013[] = "VXPro II IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_8013_3388_8013[] = "VXPro II Chipset EIDE Controller"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3411[] = "Quantum Designs (H.K.) Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3513[] = "ARCOM Control Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_38ef[] = "4Links"; +#endif +static const char pci_vendor_3d3d[] = "3DLabs"; +static const char pci_device_3d3d_0001[] = "GLINT 300SX"; +static const char pci_device_3d3d_0002[] = "GLINT 500TX"; +static const char pci_device_3d3d_0003[] = "GLINT Delta"; +static const char pci_device_3d3d_0004[] = "Permedia"; +static const char pci_device_3d3d_0005[] = "Permedia"; +static const char pci_device_3d3d_0006[] = "GLINT MX"; +static const char pci_device_3d3d_0007[] = "3D Extreme"; +static const char pci_device_3d3d_0008[] = "GLINT Gamma G1"; +static const char pci_device_3d3d_0009[] = "Permedia II 2D+3D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_1040_0011[] = "AccelStar II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0100[] = "AccelStar II 3D Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0111[] = "Permedia 3:16"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0114[] = "Santa Ana"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0116[] = "Oxygen GVX1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0119[] = "Scirocco"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0120[] = "Santa Ana PCL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0125[] = "Oxygen VX1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0127[] = "Permedia3 Create!"; +#endif +static const char pci_device_3d3d_000a[] = "GLINT R3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_000a_3d3d_0121[] = "Oxygen VX1"; +#endif +static const char pci_device_3d3d_000c[] = "GLINT R3 [Oxygen VX1]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_000c_3d3d_0144[] = "Oxygen VX1-4X AGP [Permedia 4]"; +#endif +static const char pci_device_3d3d_0100[] = "Permedia II 2D+3D"; +static const char pci_device_3d3d_1004[] = "Permedia"; +static const char pci_device_3d3d_3d04[] = "Permedia"; +static const char pci_device_3d3d_ffff[] = "Glint VGA"; +static const char pci_vendor_4005[] = "Avance Logic Inc."; +static const char pci_device_4005_0300[] = "ALS300 PCI Audio Device"; +static const char pci_device_4005_0308[] = "ALS300+ PCI Audio Device"; +static const char pci_device_4005_0309[] = "PCI Input Controller"; +static const char pci_device_4005_1064[] = "ALG-2064"; +static const char pci_device_4005_2064[] = "ALG-2064i"; +static const char pci_device_4005_2128[] = "ALG-2364A GUI Accelerator"; +static const char pci_device_4005_2301[] = "ALG-2301"; +static const char pci_device_4005_2302[] = "ALG-2302"; +static const char pci_device_4005_2303[] = "AVG-2302 GUI Accelerator"; +static const char pci_device_4005_2364[] = "ALG-2364A"; +static const char pci_device_4005_2464[] = "ALG-2464"; +static const char pci_device_4005_2501[] = "ALG-2564A/25128A"; +static const char pci_device_4005_4000[] = "ALS4000 Audio Chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4005_4000_4005_4000[] = "ALS4000 Audio Chipset"; +#endif +static const char pci_device_4005_4710[] = "ALC200/200P"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4033[] = "Addtron Technology Co, Inc."; +static const char pci_device_4033_1360[] = "RTL8139 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4143[] = "Digital Equipment Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_416c[] = "Aladdin Knowledge Systems"; +static const char pci_device_416c_0100[] = "AladdinCARD"; +static const char pci_device_416c_0200[] = "CPC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4444[] = "Internext Compression Inc"; +static const char pci_device_4444_0803[] = "iTVC15 MPEG-2 Encoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4468[] = "Bridgeport machines"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4594[] = "Cogetec Informatique Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_45fb[] = "Baldor Electric Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4680[] = "Umax Computer Corp"; +#endif +static const char pci_vendor_4843[] = "Hercules Computer Technology Inc"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4916[] = "RedCreek Communications Inc"; +static const char pci_device_4916_1960[] = "RedCreek PCI adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4943[] = "Growth Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4978[] = "Axil Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4a14[] = "NetVin"; +static const char pci_device_4a14_5000[] = "NV5000SC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4a14_5000_4a14_5000[] = "RT8029-Based Ethernet Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4b10[] = "Buslogic Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4c48[] = "LUNG HWA Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4c53[] = "SBS Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4ca1[] = "Seanix Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4d51[] = "MediaQ Inc."; +static const char pci_device_4d51_0200[] = "MQ-200"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4d54[] = "Microtechnica Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4ddc[] = "ILC Data Device Corp"; +static const char pci_device_4ddc_0100[] = "DD-42924I5-300 (ARINC 429 Data Bus)"; +static const char pci_device_4ddc_0801[] = "BU-65570I1 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0802[] = "BU-65570I2 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0811[] = "BU-65572I1 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0812[] = "BU-65572I2 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0881[] = "BU-65570T1 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0882[] = "BU-65570T2 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0891[] = "BU-65572T1 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0892[] = "BU-65572T2 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0901[] = "BU-65565C1 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0902[] = "BU-65565C2 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0903[] = "BU-65565C3 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0904[] = "BU-65565C4 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0b01[] = "BU-65569I1 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0b02[] = "BU-65569I2 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0b03[] = "BU-65569I3 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0b04[] = "BU-65569I4 MIL-STD-1553 Data Bus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5046[] = "GemTek Technology Corporation"; +static const char pci_device_5046_1001[] = "PCI Radio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5053[] = "Voyetra Technologies"; +static const char pci_device_5053_2010[] = "Daytona Audio Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5136[] = "S S Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5143[] = "Qualcomm Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5145[] = "Ensoniq (Old)"; +static const char pci_device_5145_3031[] = "Concert AudioPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5168[] = "Animation Technologies Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5301[] = "Alliance Semiconductor Corp."; +static const char pci_device_5301_0001[] = "ProMotion aT3D"; +#endif +static const char pci_vendor_5333[] = "S3 Inc."; +static const char pci_device_5333_0551[] = "Plato/PX (system)"; +static const char pci_device_5333_5631[] = "86c325 [ViRGE]"; +static const char pci_device_5333_8800[] = "86c866 [Vision 866]"; +static const char pci_device_5333_8801[] = "86c964 [Vision 964]"; +static const char pci_device_5333_8810[] = "86c764_0 [Trio 32 vers 0]"; +static const char pci_device_5333_8811[] = "86c764/765 [Trio32/64/64V+]"; +static const char pci_device_5333_8812[] = "86cM65 [Aurora64V+]"; +static const char pci_device_5333_8813[] = "86c764_3 [Trio 32/64 vers 3]"; +static const char pci_device_5333_8814[] = "86c767 [Trio 64UV+]"; +static const char pci_device_5333_8815[] = "86cM65 [Aurora 128]"; +static const char pci_device_5333_883d[] = "86c988 [ViRGE/VX]"; +static const char pci_device_5333_8870[] = "FireGL"; +static const char pci_device_5333_8880[] = "86c868 [Vision 868 VRAM] vers 0"; +static const char pci_device_5333_8881[] = "86c868 [Vision 868 VRAM] vers 1"; +static const char pci_device_5333_8882[] = "86c868 [Vision 868 VRAM] vers 2"; +static const char pci_device_5333_8883[] = "86c868 [Vision 868 VRAM] vers 3"; +static const char pci_device_5333_88b0[] = "86c928 [Vision 928 VRAM] vers 0"; +static const char pci_device_5333_88b1[] = "86c928 [Vision 928 VRAM] vers 1"; +static const char pci_device_5333_88b2[] = "86c928 [Vision 928 VRAM] vers 2"; +static const char pci_device_5333_88b3[] = "86c928 [Vision 928 VRAM] vers 3"; +static const char pci_device_5333_88c0[] = "86c864 [Vision 864 DRAM] vers 0"; +static const char pci_device_5333_88c1[] = "86c864 [Vision 864 DRAM] vers 1"; +static const char pci_device_5333_88c2[] = "86c864 [Vision 864-P DRAM] vers 2"; +static const char pci_device_5333_88c3[] = "86c864 [Vision 864-P DRAM] vers 3"; +static const char pci_device_5333_88d0[] = "86c964 [Vision 964 VRAM] vers 0"; +static const char pci_device_5333_88d1[] = "86c964 [Vision 964 VRAM] vers 1"; +static const char pci_device_5333_88d2[] = "86c964 [Vision 964-P VRAM] vers 2"; +static const char pci_device_5333_88d3[] = "86c964 [Vision 964-P VRAM] vers 3"; +static const char pci_device_5333_88f0[] = "86c968 [Vision 968 VRAM] rev 0"; +static const char pci_device_5333_88f1[] = "86c968 [Vision 968 VRAM] rev 1"; +static const char pci_device_5333_88f2[] = "86c968 [Vision 968 VRAM] rev 2"; +static const char pci_device_5333_88f3[] = "86c968 [Vision 968 VRAM] rev 3"; +static const char pci_device_5333_8900[] = "86c755 [Trio 64V2/DX]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8900_5333_8900[] = "86C775 Trio64V2/DX"; +#endif +static const char pci_device_5333_8901[] = "86c775/86c785 [Trio 64V2/DX or /GX]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8901_5333_8901[] = "86C775 Trio64V2/DX, 86C785 Trio64V2/GX"; +#endif +static const char pci_device_5333_8902[] = "Plato/PX"; +static const char pci_device_5333_8903[] = "Trio 3D business multimedia"; +static const char pci_device_5333_8904[] = "Trio 64 3D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8904_1014_00db[] = "Integrated Trio3D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8904_5333_8904[] = "86C365 Trio3D AGP"; +#endif +static const char pci_device_5333_8905[] = "Trio 64V+ family"; +static const char pci_device_5333_8906[] = "Trio 64V+ family"; +static const char pci_device_5333_8907[] = "Trio 64V+ family"; +static const char pci_device_5333_8908[] = "Trio 64V+ family"; +static const char pci_device_5333_8909[] = "Trio 64V+ family"; +static const char pci_device_5333_890a[] = "Trio 64V+ family"; +static const char pci_device_5333_890b[] = "Trio 64V+ family"; +static const char pci_device_5333_890c[] = "Trio 64V+ family"; +static const char pci_device_5333_890d[] = "Trio 64V+ family"; +static const char pci_device_5333_890e[] = "Trio 64V+ family"; +static const char pci_device_5333_890f[] = "Trio 64V+ family"; +static const char pci_device_5333_8a01[] = "ViRGE/DX or /GX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a01_0e11_b032[] = "ViRGE/GX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a01_10b4_1617[] = "Nitro 3D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a01_10b4_1717[] = "Nitro 3D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a01_5333_8a01[] = "ViRGE/DX"; +#endif +static const char pci_device_5333_8a10[] = "ViRGE/GX2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a10_1092_8a10[] = "Stealth 3D 4000"; +#endif +static const char pci_device_5333_8a13[] = "86c368 [Trio 3D/2X]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a13_5333_8a13[] = "Trio3D/2X"; +#endif +static const char pci_device_5333_8a20[] = "86c794 [Savage 3D]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a20_5333_8a20[] = "86C391 Savage3D"; +#endif +static const char pci_device_5333_8a21[] = "86c390 [Savage 3D/MV]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a21_5333_8a21[] = "86C390 Savage3D/MV"; +#endif +static const char pci_device_5333_8a22[] = "Savage 4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1033_8068[] = "Savage 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1033_8069[] = "Savage 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_105d_0018[] = "SR9 8Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_105d_002a[] = "SR9 Pro 16Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_105d_003a[] = "SR9 Pro 32Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_105d_092f[] = "SR9 Pro+ 16Mb SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4207[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4800[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4807[] = "SpeedStar A90"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4808[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4809[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_480e[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4904[] = "Stealth III S520"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4905[] = "SpeedStar A200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4a09[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4a0b[] = "Stealth III S540 Xtreme"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4a0f[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4e01[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1102_101d[] = "3d Blaster Savage 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1102_101e[] = "3d Blaster Savage 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8100[] = "86C394-397 Savage4 SDRAM 100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8110[] = "86C394-397 Savage4 SDRAM 110"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8125[] = "86C394-397 Savage4 SDRAM 125"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8143[] = "86C394-397 Savage4 SDRAM 143"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8a22[] = "86C394-397 Savage4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8a2e[] = "86C394-397 Savage4 32bit"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_9125[] = "86C394-397 Savage4 SGRAM 125"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_9143[] = "86C394-397 Savage4 SGRAM 143"; +#endif +static const char pci_device_5333_8a23[] = "Savage 4"; +static const char pci_device_5333_8a25[] = "ProSavage PM133"; +static const char pci_device_5333_8a26[] = "ProSavage KM133"; +static const char pci_device_5333_8c00[] = "ViRGE/M3"; +static const char pci_device_5333_8c01[] = "ViRGE/MX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c01_1179_0001[] = "ViRGE/MX"; +#endif +static const char pci_device_5333_8c02[] = "ViRGE/MX+"; +static const char pci_device_5333_8c03[] = "ViRGE/MX+MV"; +static const char pci_device_5333_8c10[] = "86C270-294 Savage/MX-MV"; +static const char pci_device_5333_8c11[] = "82C270-294 Savage/MX"; +static const char pci_device_5333_8c12[] = "86C270-294 Savage/IX-MV"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c12_1014_017f[] = "ThinkPad T20"; +#endif +static const char pci_device_5333_8c13[] = "86C270-294 Savage/IX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c13_1179_0001[] = "Magnia Z310"; +#endif +static const char pci_device_5333_8c22[] = "SuperSavage MX/128"; +static const char pci_device_5333_8c24[] = "SuperSavage MX/64"; +static const char pci_device_5333_8c26[] = "SuperSavage MX/64C"; +static const char pci_device_5333_8c2a[] = "SuperSavage IX/128 SDR"; +static const char pci_device_5333_8c2b[] = "SuperSavage IX/128 DDR"; +static const char pci_device_5333_8c2c[] = "SuperSavage IX/64 SDR"; +static const char pci_device_5333_8c2d[] = "SuperSavage IX/64 DDR"; +static const char pci_device_5333_8c2e[] = "SuperSavage IX/C SDR"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c2e_1014_01fc[] = "ThinkPad T23 (2647-4MG)"; +#endif +static const char pci_device_5333_8c2f[] = "SuperSavage IX/C DDR"; +static const char pci_device_5333_8d01[] = "86C380 [ProSavageDDR K4M266]"; +static const char pci_device_5333_8d02[] = "VT8636A [ProSavage KN133] AGP4X VGA Controller (TwisterK)"; +static const char pci_device_5333_8d03[] = "VT8751 [ProSavageDDR P4M266]"; +static const char pci_device_5333_8d04[] = "[ProSavageDDR K4M266]"; +static const char pci_device_5333_9102[] = "86C410 Savage 2000"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5932[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5934[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5952[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5954[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5a35[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5a37[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5a55[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5a57[] = "Viper II Z200"; +#endif +static const char pci_device_5333_ca00[] = "SonicVibes"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_544c[] = "Teralogic Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5455[] = "Technische University Berlin"; +static const char pci_device_5455_4458[] = "S5933"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5519[] = "Cnet Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5544[] = "Dunord Technologies"; +static const char pci_device_5544_0001[] = "I-30xx Scanner Interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5555[] = "Genroco, Inc"; +static const char pci_device_5555_0003[] = "TURBOstor HFP-832 [HiPPI NIC]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5654[] = "VoiceTronix Pty Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5700[] = "Netpower"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_6356[] = "UltraStor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_6374[] = "c't Magazin für Computertechnik"; +static const char pci_device_6374_6773[] = "GPPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_6409[] = "Logitec Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_6666[] = "Decision Computer International Co."; +static const char pci_device_6666_0001[] = "PCCOM4"; +static const char pci_device_6666_0002[] = "PCCOM8"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_7604[] = "O.N. Electronic Co Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_7bde[] = "MIDAC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_7fed[] = "PowerTV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8008[] = "Quancom Electronic GmbH"; +static const char pci_device_8008_0010[] = "WDOG1 [PCI-Watchdog 1]"; +static const char pci_device_8008_0011[] = "PWDOG2 [PCI-Watchdog 2]"; +#endif +static const char pci_vendor_8086[] = "Intel Corp."; +static const char pci_device_8086_0007[] = "82379AB"; +static const char pci_device_8086_0008[] = "Extended Express System Support Controller"; +static const char pci_device_8086_0039[] = "21145"; +static const char pci_device_8086_0122[] = "82437FX"; +static const char pci_device_8086_0482[] = "82375EB"; +static const char pci_device_8086_0483[] = "82424ZX [Saturn]"; +static const char pci_device_8086_0484[] = "82378IB [SIO ISA Bridge]"; +static const char pci_device_8086_0486[] = "82430ZX [Aries]"; +static const char pci_device_8086_04a3[] = "82434LX [Mercury/Neptune]"; +static const char pci_device_8086_04d0[] = "82437FX [Triton FX]"; +static const char pci_device_8086_0600[] = "RAID Controller"; +static const char pci_device_8086_0960[] = "80960RP [i960 RP Microprocessor/Bridge]"; +static const char pci_device_8086_0962[] = "80960RM [i960RM Bridge]"; +static const char pci_device_8086_0964[] = "80960RP [i960 RP Microprocessor/Bridge]"; +static const char pci_device_8086_1000[] = "82542 Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_0e11_b0df[] = "NC1632 Gigabit Ethernet Adapter (1000-SX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_0e11_b0e0[] = "NC1633 Gigabit Ethernet Adapter (1000-LX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_0e11_b123[] = "NC1634 Gigabit Ethernet Adapter (1000-SX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_1014_0119[] = "Netfinity Gigabit Ethernet SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_8086_1000[] = "PRO/1000 Gigabit Server Adapter"; +#endif +static const char pci_device_8086_1001[] = "82543GC Gigabit Ethernet Controller (Fiber)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1001_0e11_004a[] = "NC6136 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1001_1014_01ea[] = "Netfinity Gigabit Ethernet SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1001_8086_1003[] = "PRO/1000 F Server Adapter"; +#endif +static const char pci_device_8086_1002[] = "Pro 100 LAN+Modem 56 Cardbus II"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1002_8086_200e[] = "Pro 100 LAN+Modem 56 Cardbus II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1002_8086_2013[] = "Pro 100 SR Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1002_8086_2017[] = "Pro 100 S Combo Mobile Adapter"; +#endif +static const char pci_device_8086_1004[] = "82543GC Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_0e11_0049[] = "NC7132 Gigabit Upgrade Module"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_0e11_b1a4[] = "NC7131 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_1014_10f2[] = "Gigabit Ethernet Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_8086_1004[] = "PRO/1000 T Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_8086_2004[] = "PRO/1000 T Server Adapter"; +#endif +static const char pci_device_8086_1008[] = "82544EI Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_8086_1107[] = "PRO/1000 XT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_8086_2107[] = "PRO/1000 XT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_8086_2110[] = "PRO/1000 XT Server Adapter"; +#endif +static const char pci_device_8086_1009[] = "82544EI Gigabit Ethernet Controller (Fiber)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1009_8086_1109[] = "PRO/1000 XF Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1009_8086_2109[] = "PRO/1000 XF Server Adapter"; +#endif +static const char pci_device_8086_100c[] = "82544GC Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100c_8086_1112[] = "PRO/1000 T Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100c_8086_2112[] = "PRO/1000 T Desktop Adapter"; +#endif +static const char pci_device_8086_100d[] = "82544GC Gigabit Ethernet Controller (LOM)"; +static const char pci_device_8086_100e[] = "82540EM Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_8086_001e[] = "PRO/1000 MT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_8086_002e[] = "PRO/1000 MT Desktop Adapter"; +#endif +static const char pci_device_8086_100f[] = "82545EM Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100f_8086_1001[] = "PRO/1000 MT Server Adapter"; +#endif +static const char pci_device_8086_1010[] = "82546EB Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_8086_1011[] = "PRO/1000 MT Dual Port Server Adapter"; +#endif +static const char pci_device_8086_1011[] = "82545EM Gigabit Ethernet Controller (Fiber)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1011_8086_1002[] = "PRO/1000 MF Server Adapter"; +#endif +static const char pci_device_8086_1012[] = "82546EB Gigabit Ethernet Controller (Fiber)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1012_8086_1012[] = "PRO/1000 MF Dual Port Server Adapter"; +#endif +static const char pci_device_8086_1015[] = "82540EM Gigabit Ethernet Controller (LOM)"; +static const char pci_device_8086_1029[] = "82559 Ethernet Controller"; +static const char pci_device_8086_1030[] = "82559 InBusiness 10/100"; +static const char pci_device_8086_1031[] = "82801CAM (ICH3) PRO/100 VE (LOM) Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_1014_0209[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_104d_80e7[] = "Vaio PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_107b_5350[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_1179_0001[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_144d_c000[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_144d_c001[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_144d_c003[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_144d_c006[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_1032[] = "82801CAM (ICH3) PRO/100 VE Ethernet Controller"; +static const char pci_device_8086_1033[] = "82801CAM (ICH3) PRO/100 VM (LOM) Ethernet Controller"; +static const char pci_device_8086_1034[] = "82801CAM (ICH3) PRO/100 VM Ethernet Controller"; +static const char pci_device_8086_1035[] = "82801CAM (ICH3)/82562EH (LOM) Ethernet Controller"; +static const char pci_device_8086_1036[] = "82801CAM (ICH3) 82562EH Ethernet Controller"; +static const char pci_device_8086_1037[] = "82801CAM (ICH3) Chipset Ethernet Controller"; +static const char pci_device_8086_1038[] = "82801CAM (ICH3) PRO/100 VM (KM) Ethernet Controller"; +static const char pci_device_8086_1039[] = "82801BD PRO/100 VE (LOM) Ethernet Controller"; +static const char pci_device_8086_103a[] = "82801BD PRO/100 VE (CNR) Ethernet Controller"; +static const char pci_device_8086_103b[] = "82801BD PRO/100 VM (LOM) Ethernet Controller"; +static const char pci_device_8086_103c[] = "82801BD PRO/100 VM (CNR) Ethernet Controller"; +static const char pci_device_8086_103d[] = "82801BD PRO/100 VE (MOB) Ethernet Controller"; +static const char pci_device_8086_103e[] = "82801BD PRO/100 VM (MOB) Ethernet Controller"; +static const char pci_device_8086_1040[] = "536EP Data Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1040_16be_1040[] = "V.9X DSP Data Fax Modem"; +#endif +static const char pci_device_8086_1059[] = "82551QM Ethernet Controller"; +static const char pci_device_8086_1130[] = "82815 815 Chipset Host Bridge and Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_104d_80df[] = "Vaio PCG-FX403"; +#endif +static const char pci_device_8086_1131[] = "82815 815 Chipset AGP Bridge"; +static const char pci_device_8086_1132[] = "82815 CGC [Chipset Graphics Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1132_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1132_104d_80df[] = "Vaio PCG-FX403"; +#endif +static const char pci_device_8086_1161[] = "82806AA PCI64 Hub Advanced Programmable Interrupt Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1161_8086_1161[] = "82806AA PCI64 Hub APIC"; +#endif +static const char pci_device_8086_1162[] = "Xscale 80200 Big Endian Companion Chip"; +static const char pci_device_8086_1200[] = "Intel IXP1200 Network Processor"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1200_172a_0000[] = "AEP SSL Accelerator"; +#endif +static const char pci_device_8086_1209[] = "82559ER"; +static const char pci_device_8086_1221[] = "82092AA_0"; +static const char pci_device_8086_1222[] = "82092AA_1"; +static const char pci_device_8086_1223[] = "SAA7116"; +static const char pci_device_8086_1225[] = "82452KX/GX [Orion]"; +static const char pci_device_8086_1226[] = "82596 PRO/10 PCI"; +static const char pci_device_8086_1227[] = "82865 EtherExpress PRO/100A"; +static const char pci_device_8086_1228[] = "82556 EtherExpress PRO/100 Smart"; +static const char pci_device_8086_1229[] = "82557/8/9 [Ethernet Pro 100]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3001[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3002[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3003[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3004[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3005[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3006[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3007[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b01e[] = "NC3120 Fast Ethernet NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b01f[] = "NC3122 Fast Ethernet NIC (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b02f[] = "NC1120 Ethernet NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b04a[] = "Netelligent 10/100TX NIC with Wake on LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0c6[] = "NC3161 Fast Ethernet NIC (embedded, WOL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0c7[] = "NC3160 Fast Ethernet NIC (embedded)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0d7[] = "NC3121 Fast Ethernet NIC (WOL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0dd[] = "NC3131 Fast Ethernet NIC (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0de[] = "NC3132 Fast Ethernet Module (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0e1[] = "NC3133 Fast Ethernet Module (100-FX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b134[] = "NC3163 Fast Ethernet NIC (embedded, WOL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b13c[] = "NC3162 Fast Ethernet NIC (embedded)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b144[] = "NC3123 Fast Ethernet NIC (WOL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b163[] = "NC3134 Fast Ethernet NIC (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b164[] = "NC3135 Fast Ethernet Upgrade Module (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b1a4[] = "NC7131 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_005c[] = "82558B Ethernet Pro 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_01bc[] = "82559 Fast Ethernet LAN On Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_01f1[] = "10/100 Ethernet Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_01f2[] = "10/100 Ethernet Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_0207[] = "Ethernet Pro/100 S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_0232[] = "10/100 Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_023a[] = "ThinkPad R30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_105c[] = "Netfinity 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_2205[] = "ThinkPad A22p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_305c[] = "10/100 EtherJet Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_405c[] = "10/100 EtherJet Adapter with Alert on LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_505c[] = "10/100 EtherJet Secure Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_605c[] = "10/100 EtherJet Secure Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_705c[] = "10/100 Netfinity 10/100 Ethernet Security Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_805c[] = "10/100 Netfinity 10/100 Ethernet Security Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1028_009b[] = "PowerEdge 2550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8000[] = "PC-9821X-B06"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8016[] = "PK-UG-X006"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_801f[] = "PK-UG-X006"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8026[] = "PK-UG-X006"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8063[] = "82559-based Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8064[] = "82559-based Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10c0[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10c3[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10ca[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10cb[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10e3[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10e4[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_1200[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_10c3_1100[] = "SmartEther100 SC1100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_10cf_1115[] = "8255x-based Ethernet Adapter (10/100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_10cf_1143[] = "8255x-based Ethernet Adapter (10/100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1179_0001[] = "8255x-based Ethernet Adapter (10/100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1179_0002[] = "PCI FastEther LAN on Docker"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1179_0003[] = "8255x-based Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1259_2560[] = "AT-2560 100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1259_2561[] = "AT-2560 100 FX Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1266_0001[] = "NE10/100 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_144d_2501[] = "SEM-2000 MiniPCI LAN Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_144d_2502[] = "SEM-2100IL MiniPCI LAN Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1668_1100[] = "EtherExpress PRO/100B (TX) (MiniPCI Ethernet+Modem)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0001[] = "EtherExpress PRO/100B (TX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0002[] = "EtherExpress PRO/100B (T4)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0003[] = "EtherExpress PRO/10+"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0004[] = "EtherExpress PRO/100 WfM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0005[] = "82557 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0006[] = "82557 10/100 with Wake on LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0007[] = "82558 10/100 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0008[] = "82558 10/100 with Wake on LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0009[] = "EtherExpress PRO/100+"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000a[] = "EtherExpress PRO/100+ Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000b[] = "EtherExpress PRO/100+"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000c[] = "EtherExpress PRO/100+ Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000d[] = "EtherExpress PRO/100+ Alert On LAN II* Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000e[] = "EtherExpress PRO/100+ Management Adapter with Alert On LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000f[] = "EtherExpress PRO/100 Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0010[] = "EtherExpress PRO/100 S Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0011[] = "EtherExpress PRO/100 S Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0012[] = "EtherExpress PRO/100 S Advanced Management Adapter (D)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0013[] = "EtherExpress PRO/100 S Advanced Management Adapter (E)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0030[] = "EtherExpress PRO/100 Management Adapter with Alert On LAN* GC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0031[] = "EtherExpress PRO/100 Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0040[] = "EtherExpress PRO/100 S Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0041[] = "EtherExpress PRO/100 S Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0042[] = "EtherExpress PRO/100 Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0050[] = "EtherExpress PRO/100 S Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1009[] = "EtherExpress PRO/100+ Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_100c[] = "EtherExpress PRO/100+ Server Adapter (PILA8470B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1012[] = "EtherExpress PRO/100 S Server Adapter (D)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1013[] = "EtherExpress PRO/100 S Server Adapter (E)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1015[] = "EtherExpress PRO/100 S Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1017[] = "EtherExpress PRO/100+ Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1030[] = "EtherExpress PRO/100+ Management Adapter with Alert On LAN* G Server"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1040[] = "EtherExpress PRO/100 S Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1041[] = "EtherExpress PRO/100 S Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1042[] = "EtherExpress PRO/100 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1050[] = "EtherExpress PRO/100 S Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1051[] = "EtherExpress PRO/100 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1052[] = "EtherExpress PRO/100 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_10f0[] = "EtherExpress PRO/100+ Dual Port Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2009[] = "EtherExpress PRO/100 S Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_200d[] = "EtherExpress PRO/100 Cardbus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_200e[] = "EtherExpress PRO/100 LAN+V90 Cardbus Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_200f[] = "EtherExpress PRO/100 SR Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2010[] = "EtherExpress PRO/100 S Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2013[] = "EtherExpress PRO/100 SR Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2016[] = "EtherExpress PRO/100 S Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2017[] = "EtherExpress PRO/100 S Combo Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2018[] = "EtherExpress PRO/100 SR Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2019[] = "EtherExpress PRO/100 SR Combo Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2101[] = "EtherExpress PRO/100 P Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2102[] = "EtherExpress PRO/100 SP Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2103[] = "EtherExpress PRO/100 SP Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2104[] = "EtherExpress PRO/100 SP Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2105[] = "EtherExpress PRO/100 SP Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2106[] = "EtherExpress PRO/100 P Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2107[] = "EtherExpress PRO/100 Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2108[] = "EtherExpress PRO/100 Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2200[] = "EtherExpress PRO/100 P Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2201[] = "EtherExpress PRO/100 P Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2202[] = "EtherExpress PRO/100 SP Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2203[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2204[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2205[] = "EtherExpress PRO/100 SP Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2206[] = "EtherExpress PRO/100 SP Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2207[] = "EtherExpress PRO/100 SP Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2208[] = "EtherExpress PRO/100 P Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2402[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2407[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2408[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2409[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_240f[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2410[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2411[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2412[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2413[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3000[] = "82559 Fast Ethernet LAN on Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3001[] = "82559 Fast Ethernet LOM with Basic Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3002[] = "82559 Fast Ethernet LOM with Alert on LAN II*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3006[] = "EtherExpress PRO/100 S Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3007[] = "EtherExpress PRO/100 S Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3008[] = "EtherExpress PRO/100 Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3010[] = "EtherExpress PRO/100 S Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3011[] = "EtherExpress PRO/100 S Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3012[] = "EtherExpress PRO/100 Network Connection"; +#endif +static const char pci_device_8086_122d[] = "430FX - 82437FX TSC [Triton I]"; +static const char pci_device_8086_122e[] = "82371FB PIIX ISA [Triton I]"; +static const char pci_device_8086_1230[] = "82371FB PIIX IDE [Triton I]"; +static const char pci_device_8086_1231[] = "DSVD Modem"; +static const char pci_device_8086_1234[] = "430MX - 82371MX Mobile PCI I/O IDE Xcelerator (MPIIX)"; +static const char pci_device_8086_1235[] = "430MX - 82437MX Mob. System Ctrlr (MTSC) & 82438MX Data Path (MTDP)"; +static const char pci_device_8086_1237[] = "440FX - 82441FX PMC [Natoma]"; +static const char pci_device_8086_1239[] = "82371FB"; +static const char pci_device_8086_123b[] = "82380PB"; +static const char pci_device_8086_123c[] = "82380AB"; +static const char pci_device_8086_123d[] = "683053 Programmable Interrupt Device"; +static const char pci_device_8086_123f[] = "82466GX Integrated Hot-Plug Controller (IHPC)"; +static const char pci_device_8086_1240[] = "752 AGP"; +static const char pci_device_8086_124b[] = "82380FB"; +static const char pci_device_8086_1250[] = "430HX - 82439HX TXC [Triton II]"; +static const char pci_device_8086_1360[] = "82806AA PCI64 Hub PCI Bridge"; +static const char pci_device_8086_1361[] = "82806AA PCI64 Hub Controller (HRes)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1361_8086_1361[] = "82806AA PCI64 Hub Controller (HRes)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1361_8086_8000[] = "82806AA PCI64 Hub Controller (HRes)"; +#endif +static const char pci_device_8086_1460[] = "82870P2 P64H2 Hub PCI Bridge"; +static const char pci_device_8086_1461[] = "82870P2 P64H2 I/OxAPIC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1461_15d9_3480[] = "P4DP6"; +#endif +static const char pci_device_8086_1462[] = "82870P2 P64H2 Hot Plug Controller"; +static const char pci_device_8086_1960[] = "80960RP [i960RP Microprocessor]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0431[] = "MegaRAID 431 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0438[] = "MegaRAID 438 Ultra2 LVD RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0466[] = "MegaRAID 466 Express Plus RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0467[] = "MegaRAID 467 Enterprise 1500 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0490[] = "MegaRAID 490 Express 300 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0762[] = "MegaRAID 762 Express RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_09a0[] = "PowerEdge Expandable RAID Controller 2/SC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_1028_0467[] = "PowerEdge Expandable RAID Controller 2/DC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_1028_1111[] = "PowerEdge Expandable RAID Controller 2/SC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_03a2[] = "MegaRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_10c6[] = "MegaRAID 438, HP NetRAID-3Si"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_10c7[] = "MegaRAID T5, Integrated HP NetRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_10cc[] = "MegaRAID, Integrated HP NetRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_10cd[] = "HP NetRAID-1Si"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_105a_0000[] = "SuperTrak"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_105a_2168[] = "SuperTrak Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_105a_5168[] = "SuperTrak66/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_1111_1111[] = "MegaRAID 466, PowerEdge Expandable RAID Controller 2/SC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_1111_1112[] = "PowerEdge Expandable RAID Controller 2/SC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_113c_03a2[] = "MegaRAID"; +#endif +static const char pci_device_8086_1962[] = "80960RM [i960RM Microprocessor]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1962_105a_0000[] = "SuperTrak SX6000 I2O CPU"; +#endif +static const char pci_device_8086_1a21[] = "82840 840 (Carmel) Chipset Host Bridge (Hub A)"; +static const char pci_device_8086_1a23[] = "82840 840 (Carmel) Chipset AGP Bridge"; +static const char pci_device_8086_1a24[] = "82840 840 (Carmel) Chipset PCI Bridge (Hub B)"; +static const char pci_device_8086_1a30[] = "82845 845 (Brookdale) Chipset Host Bridge"; +static const char pci_device_8086_1a31[] = "82845 845 (Brookdale) Chipset AGP Bridge"; +static const char pci_device_8086_2410[] = "82801AA ISA Bridge (LPC)"; +static const char pci_device_8086_2411[] = "82801AA IDE"; +static const char pci_device_8086_2412[] = "82801AA USB"; +static const char pci_device_8086_2413[] = "82801AA SMBus"; +static const char pci_device_8086_2415[] = "82801AA AC'97 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_1028_0095[] = "Precision Workstation 220 Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_11d4_0040[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_11d4_0048[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_11d4_5340[] = "SoundMAX Integrated Digital Audio"; +#endif +static const char pci_device_8086_2416[] = "82801AA AC'97 Modem"; +static const char pci_device_8086_2418[] = "82801AA PCI Bridge"; +static const char pci_device_8086_2420[] = "82801AB ISA Bridge (LPC)"; +static const char pci_device_8086_2421[] = "82801AB IDE"; +static const char pci_device_8086_2422[] = "82801AB USB"; +static const char pci_device_8086_2423[] = "82801AB SMBus"; +static const char pci_device_8086_2425[] = "82801AB AC'97 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2425_11d4_0040[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2425_11d4_0048[] = "SoundMAX Integrated Digital Audio"; +#endif +static const char pci_device_8086_2426[] = "82801AB AC'97 Modem"; +static const char pci_device_8086_2428[] = "82801AB PCI Bridge"; +static const char pci_device_8086_2440[] = "82801BA ISA Bridge (LPC)"; +static const char pci_device_8086_2442[] = "82801BA/BAM USB (Hub #1)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_1014_01c6[] = "Netvista A40/A40p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_147b_0507[] = "TH7II-RAID"; +#endif +static const char pci_device_8086_2443[] = "82801BA/BAM SMBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_1014_01c6[] = "Netvista A40/A40p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_147b_0507[] = "TH7II-RAID"; +#endif +static const char pci_device_8086_2444[] = "82801BA/BAM USB (Hub #2)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_147b_0507[] = "TH7II-RAID"; +#endif +static const char pci_device_8086_2445[] = "82801BA/BAM AC'97 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_1014_01c6[] = "Netvista A40/A40p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_1462_3370[] = "STAC9721 AC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_147b_0507[] = "TH7II-RAID"; +#endif +static const char pci_device_8086_2446[] = "Intel 537 [82801BA/BAM AC'97 Modem]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2446_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2446_104d_80df[] = "Vaio PCG-FX403"; +#endif +static const char pci_device_8086_2448[] = "82801BAM/CAM PCI Bridge"; +static const char pci_device_8086_2449[] = "82801BA/BAM/CA/CAM Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_0e11_0012[] = "EtherExpress PRO/100 VM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_0e11_0091[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_01ce[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_01dc[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_01eb[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_01ec[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0202[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0205[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0217[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0234[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_023d[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0244[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0245[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_109f_315d[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_109f_3181[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1186_7801[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_144d_2602[] = "HomePNA 1M CNR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3010[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3011[] = "EtherExpress PRO/100 VM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3012[] = "82562EH based Phoneline"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3013[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3014[] = "EtherExpress PRO/100 VM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3015[] = "82562EH based Phoneline"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3016[] = "EtherExpress PRO/100 P Mobile Combo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3017[] = "EtherExpress PRO/100 P Mobile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3018[] = "EtherExpress PRO/100"; +#endif +static const char pci_device_8086_244a[] = "82801BAM IDE U100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244a_1025_1016[] = "Travelmate 612TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244a_104d_80df[] = "Vaio PCG-FX403"; +#endif +static const char pci_device_8086_244b[] = "82801BA IDE U100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_1014_01c6[] = "Netvista A40/A40p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_147b_0507[] = "TH7II-RAID"; +#endif +static const char pci_device_8086_244c[] = "82801BAM ISA Bridge (LPC)"; +static const char pci_device_8086_244e[] = "82801BA/CA/DB PCI Bridge"; +static const char pci_device_8086_2450[] = "82801E ISA Bridge (LPC)"; +static const char pci_device_8086_2452[] = "82801E USB"; +static const char pci_device_8086_2453[] = "82801E SMBus"; +static const char pci_device_8086_2459[] = "82801E Ethernet Controller 0"; +static const char pci_device_8086_245b[] = "82801E IDE U100"; +static const char pci_device_8086_245d[] = "82801E Ethernet Controller 1"; +static const char pci_device_8086_245e[] = "82801E PCI Bridge"; +static const char pci_device_8086_2480[] = "82801CA ISA Bridge (LPC)"; +static const char pci_device_8086_2482[] = "82801CA/CAM USB (Hub #1)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_8086_1958[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_2483[] = "82801CA/CAM SMBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2483_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2483_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2483_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2483_8086_1958[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_2484[] = "82801CA/CAM USB (Hub #2)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_8086_1958[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_2485[] = "82801CA/CAM AC'97 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_1014_0222[] = "ThinkPad T23 (2647-4MG) or A30p (2653-64G)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_1014_0508[] = "ThinkPad T30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_1014_051c[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_144d_c006[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_2486[] = "82801CA/CAM AC'97 Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_1014_0223[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_1014_0503[] = "ThinkPad R31 2656BBG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_1014_051a[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_1179_0001[] = "Toshiba Satellite 1110 Z15 internal Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_134d_4c21[] = "Dell Inspiron 2100 internal modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_144d_2115[] = "vpr Matrix 170B4 internal modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_14f1_5421[] = "MD56ORD V.92 MDC Modem"; +#endif +static const char pci_device_8086_2487[] = "82801CA/CAM USB (Hub #3)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_8086_1958[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_248a[] = "82801CAM IDE U100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_8086_1958[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_248b[] = "82801CA IDE U100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248b_15d9_3480[] = "P4DP6"; +#endif +static const char pci_device_8086_248c[] = "82801CAM ISA Bridge (LPC)"; +static const char pci_device_8086_24c0[] = "82801DB ISA Bridge (LPC)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c0_1462_5800[] = "845PE Max (MS-6580)"; +#endif +static const char pci_device_8086_24c2[] = "82801DB USB (Hub #1)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1462_5800[] = "845PE Max (MS-6580)"; +#endif +static const char pci_device_8086_24c3[] = "82801DB SMBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1462_5800[] = "845PE Max (MS-6580)"; +#endif +static const char pci_device_8086_24c4[] = "82801DB USB (Hub #2)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1462_5800[] = "845PE Max (MS-6580)"; +#endif +static const char pci_device_8086_24c5[] = "82801DB AC'97 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1462_5800[] = "845PE Max (MS-6580)"; +#endif +static const char pci_device_8086_24c6[] = "82801DB AC'97 Modem"; +static const char pci_device_8086_24c7[] = "82801DB USB (Hub #3)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1462_5800[] = "845PE Max (MS-6580)"; +#endif +static const char pci_device_8086_24cb[] = "82801DB ICH4 IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cb_1462_5800[] = "845PE Max (MS-6580)"; +#endif +static const char pci_device_8086_24cd[] = "82801DB USB EHCI Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1462_3981[] = "845PE Max (MS-6580) Onboard USB EHCI Controller"; +#endif +static const char pci_device_8086_2500[] = "82820 820 (Camino) Chipset Host Bridge (MCH)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2500_1028_0095[] = "Precision Workstation 220 Chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2500_1043_801c[] = "P3C-2000 system chipset"; +#endif +static const char pci_device_8086_2501[] = "82820 820 (Camino) Chipset Host Bridge (MCH)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2501_1043_801c[] = "P3C-2000 system chipset"; +#endif +static const char pci_device_8086_250b[] = "82820 820 (Camino) Chipset Host Bridge"; +static const char pci_device_8086_250f[] = "82820 820 (Camino) Chipset AGP Bridge"; +static const char pci_device_8086_2520[] = "82805AA MTH Memory Translator Hub"; +static const char pci_device_8086_2521[] = "82804AA MRH-S Memory Repeater Hub for SDRAM"; +static const char pci_device_8086_2530[] = "82850 850 (Tehama) Chipset Host Bridge (MCH)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2530_147b_0507[] = "TH7II-RAID"; +#endif +static const char pci_device_8086_2531[] = "82860 860 (Wombat) Chipset Host Bridge (MCH)"; +static const char pci_device_8086_2532[] = "82850 850 (Tehama) Chipset AGP Bridge"; +static const char pci_device_8086_2533[] = "82860 860 (Wombat) Chipset AGP Bridge"; +static const char pci_device_8086_2534[] = "82860 860 (Wombat) Chipset PCI Bridge"; +static const char pci_device_8086_2540[] = "e7500 [Plumas] DRAM Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2540_15d9_3480[] = "P4DP6"; +#endif +static const char pci_device_8086_2541[] = "e7500 [Plumas] DRAM Controller Error Reporting"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2541_15d9_3480[] = "P4DP6"; +#endif +static const char pci_device_8086_2543[] = "e7500 [Plumas] HI_B Virtual PCI Bridge (F0)"; +static const char pci_device_8086_2544[] = "e7500 [Plumas] HI_B Virtual PCI Bridge (F1)"; +static const char pci_device_8086_2545[] = "e7500 [Plumas] HI_C Virtual PCI Bridge (F0)"; +static const char pci_device_8086_2546[] = "e7500 [Plumas] HI_C Virtual PCI Bridge (F1)"; +static const char pci_device_8086_2547[] = "e7500 [Plumas] HI_D Virtual PCI Bridge (F0)"; +static const char pci_device_8086_2548[] = "e7500 [Plumas] HI_D Virtual PCI Bridge (F1)"; +static const char pci_device_8086_2560[] = "82845G/GL [Brookdale-G] Chipset Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2560_1462_5800[] = "845PE Max (MS-6580)"; +#endif +static const char pci_device_8086_2561[] = "82845G/GL [Brookdale-G] Chipset AGP Bridge"; +static const char pci_device_8086_2562[] = "82845G/GL [Brookdale-G] Chipset Integrated Graphics Device"; +static const char pci_device_8086_2570[] = "865G Chipset Host-Hub Bridge"; +static const char pci_device_8086_2572[] = "865G Chipset Graphics Controller"; +static const char pci_device_8086_3092[] = "Integrated RAID"; +static const char pci_device_8086_3575[] = "82830 830 Chipset Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3575_1014_021d[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3575_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +static const char pci_device_8086_3576[] = "82830 830 Chipset AGP Bridge"; +static const char pci_device_8086_3577[] = "82830 CGC [Chipset Graphics Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3577_1014_0513[] = "ThinkPad A/T/X Series"; +#endif +static const char pci_device_8086_3578[] = "82830 830 Chipset Host Bridge"; +static const char pci_device_8086_3580[] = "852GM/852GME/855GM/855GME Chipset Host-Hub Bridge"; +static const char pci_device_8086_3582[] = "852GM/852GME/855GM/855GME Chipset Graphics Controller"; +static const char pci_device_8086_5200[] = "EtherExpress PRO/100 Intelligent Server"; +static const char pci_device_8086_5201[] = "EtherExpress PRO/100 Intelligent Server"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_5201_8086_0001[] = "EtherExpress PRO/100 Server Ethernet Adapter"; +#endif +static const char pci_device_8086_530d[] = "80310 IOP [IO Processor]"; +static const char pci_device_8086_7000[] = "82371SB PIIX3 ISA [Natoma/Triton II]"; +static const char pci_device_8086_7010[] = "82371SB PIIX3 IDE [Natoma/Triton II]"; +static const char pci_device_8086_7020[] = "82371SB PIIX3 USB [Natoma/Triton II]"; +static const char pci_device_8086_7030[] = "430VX - 82437VX TVX [Triton VX]"; +static const char pci_device_8086_7100[] = "430TX - 82439TX MTXC"; +static const char pci_device_8086_7110[] = "82371AB/EB/MB PIIX4 ISA"; +static const char pci_device_8086_7111[] = "82371AB/EB/MB PIIX4 IDE"; +static const char pci_device_8086_7112[] = "82371AB/EB/MB PIIX4 USB"; +static const char pci_device_8086_7113[] = "82371AB/EB/MB PIIX4 ACPI"; +static const char pci_device_8086_7120[] = "82810 GMCH [Graphics Memory Controller Hub]"; +static const char pci_device_8086_7121[] = "82810 CGC [Chipset Graphics Controller]"; +static const char pci_device_8086_7122[] = "82810 DC-100 GMCH [Graphics Memory Controller Hub]"; +static const char pci_device_8086_7123[] = "82810 DC-100 CGC [Chipset Graphics Controller]"; +static const char pci_device_8086_7124[] = "82810E DC-133 GMCH [Graphics Memory Controller Hub]"; +static const char pci_device_8086_7125[] = "82810E DC-133 CGC [Chipset Graphics Controller]"; +static const char pci_device_8086_7126[] = "82810 DC-133 System and Graphics Controller"; +static const char pci_device_8086_7128[] = "82810-M DC-100 System and Graphics Controller"; +static const char pci_device_8086_712a[] = "82810-M DC-133 System and Graphics Controller"; +static const char pci_device_8086_7180[] = "440LX/EX - 82443LX/EX Host bridge"; +static const char pci_device_8086_7181[] = "440LX/EX - 82443LX/EX AGP bridge"; +static const char pci_device_8086_7190[] = "440BX/ZX/DX - 82443BX/ZX/DX Host bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_0e11_0500[] = "Armada 1750 Laptop System Chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_0e11_b110[] = "Armada M700"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_1179_0001[] = "Toshiba Tecra 8100 Laptop System Chipset"; +#endif +static const char pci_device_8086_7191[] = "440BX/ZX/DX - 82443BX/ZX/DX AGP bridge"; +static const char pci_device_8086_7192[] = "440BX/ZX/DX - 82443BX/ZX/DX Host bridge (AGP disabled)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7192_0e11_0460[] = "Armada 1700 Laptop System Chipset"; +#endif +static const char pci_device_8086_7194[] = "82440MX Host Bridge"; +static const char pci_device_8086_7195[] = "82440MX AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7195_10cf_1099[] = "QSound_SigmaTel Stac97 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7195_11d4_0040[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7195_11d4_0048[] = "SoundMAX Integrated Digital Audio"; +#endif +static const char pci_device_8086_7196[] = "82440MX AC'97 Modem Controller"; +static const char pci_device_8086_7198[] = "82440MX ISA Bridge"; +static const char pci_device_8086_7199[] = "82440MX EIDE Controller"; +static const char pci_device_8086_719a[] = "82440MX USB Universal Host Controller"; +static const char pci_device_8086_719b[] = "82440MX Power Management Controller"; +static const char pci_device_8086_71a0[] = "440GX - 82443GX Host bridge"; +static const char pci_device_8086_71a1[] = "440GX - 82443GX AGP bridge"; +static const char pci_device_8086_71a2[] = "440GX - 82443GX Host bridge (AGP disabled)"; +static const char pci_device_8086_7600[] = "82372FB PIIX5 ISA"; +static const char pci_device_8086_7601[] = "82372FB PIIX5 IDE"; +static const char pci_device_8086_7602[] = "82372FB PIIX5 USB"; +static const char pci_device_8086_7603[] = "82372FB PIIX5 SMBus"; +static const char pci_device_8086_7800[] = "i740"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_003d_0008[] = "Starfighter AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_003d_000b[] = "Starfighter AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_1092_0100[] = "Stealth II G460"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_10b4_201a[] = "Lightspeed 740"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_10b4_202f[] = "Lightspeed 740"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_8086_0000[] = "Terminator 2x/i"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_8086_0100[] = "Intel740 Graphics Accelerator"; +#endif +static const char pci_device_8086_84c4[] = "450KX/GX [Orion] - 82454KX/GX PCI bridge"; +static const char pci_device_8086_84c5[] = "450KX/GX [Orion] - 82453KX/GX Memory controller"; +static const char pci_device_8086_84ca[] = "450NX - 82451NX Memory & I/O Controller"; +static const char pci_device_8086_84cb[] = "450NX - 82454NX/84460GX PCI Expander Bridge"; +static const char pci_device_8086_84e0[] = "460GX - 84460GX System Address Controller (SAC)"; +static const char pci_device_8086_84e1[] = "460GX - 84460GX System Data Controller (SDC)"; +static const char pci_device_8086_84e2[] = "460GX - 84460GX AGP Bridge (GXB function 2)"; +static const char pci_device_8086_84e3[] = "460GX - 84460GX Memory Address Controller (MAC)"; +static const char pci_device_8086_84e4[] = "460GX - 84460GX Memory Data Controller (MDC)"; +static const char pci_device_8086_84e6[] = "460GX - 82466GX Wide and fast PCI eXpander Bridge (WXB)"; +static const char pci_device_8086_84ea[] = "460GX - 84460GX AGP Bridge (GXB function 1)"; +static const char pci_device_8086_9621[] = "Integrated RAID"; +static const char pci_device_8086_9622[] = "Integrated RAID"; +static const char pci_device_8086_9641[] = "Integrated RAID"; +static const char pci_device_8086_96a1[] = "Integrated RAID"; +static const char pci_device_8086_b152[] = "21152 PCI-to-PCI Bridge"; +static const char pci_device_8086_b154[] = "21154 PCI-to-PCI Bridge"; +static const char pci_device_8086_b555[] = "21555 Non transparent PCI-to-PCI Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_b555_e4bf_1000[] = "CC8-1-BLUES"; +#endif +static const char pci_device_8086_ffff[] = "450NX/GX [Orion] - 82453KX/GX Memory controller [BUG]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8800[] = "Trigem Computer Inc."; +static const char pci_device_8800_2008[] = "Video assistent component"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8866[] = "T-Square Design Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8888[] = "Silicon Magic"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8e0e[] = "Computone Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8e2e[] = "KTI"; +static const char pci_device_8e2e_3000[] = "ET32P2"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_9004[] = "Adaptec"; +static const char pci_device_9004_1078[] = "AIC-7810"; +static const char pci_device_9004_1160[] = "AIC-1160 [Family Fibre Channel Adapter]"; +static const char pci_device_9004_2178[] = "AIC-7821"; +static const char pci_device_9004_3860[] = "AHA-2930CU"; +static const char pci_device_9004_3b78[] = "AHA-4844W/4844UW"; +static const char pci_device_9004_5075[] = "AIC-755x"; +static const char pci_device_9004_5078[] = "AHA-7850"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_5078_9004_7850[] = "AHA-2904/Integrated AIC-7850"; +#endif +static const char pci_device_9004_5175[] = "AIC-755x"; +static const char pci_device_9004_5178[] = "AIC-7851"; +static const char pci_device_9004_5275[] = "AIC-755x"; +static const char pci_device_9004_5278[] = "AIC-7852"; +static const char pci_device_9004_5375[] = "AIC-755x"; +static const char pci_device_9004_5378[] = "AIC-7850"; +static const char pci_device_9004_5475[] = "AIC-755x"; +static const char pci_device_9004_5478[] = "AIC-7850"; +static const char pci_device_9004_5575[] = "AVA-2930"; +static const char pci_device_9004_5578[] = "AIC-7855"; +static const char pci_device_9004_5647[] = "ANA-7711 TCP Offload Engine"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_5647_9004_7710[] = "ANA-7711F TCP Offload Engine - Optical"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_5647_9004_7711[] = "ANA-7711LP TCP Offload Engine - Copper"; +#endif +static const char pci_device_9004_5675[] = "AIC-755x"; +static const char pci_device_9004_5678[] = "AIC-7856"; +static const char pci_device_9004_5775[] = "AIC-755x"; +static const char pci_device_9004_5778[] = "AIC-7850"; +static const char pci_device_9004_5800[] = "AIC-5800"; +static const char pci_device_9004_5900[] = "ANA-5910/5930/5940 ATM155 & 25 LAN Adapter"; +static const char pci_device_9004_5905[] = "ANA-5910A/5930A/5940A ATM Adapter"; +static const char pci_device_9004_6038[] = "AIC-3860"; +static const char pci_device_9004_6075[] = "AIC-1480 / APA-1480"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6075_9004_7560[] = "AIC-1480 / APA-1480 Cardbus"; +#endif +static const char pci_device_9004_6078[] = "AIC-7860"; +static const char pci_device_9004_6178[] = "AIC-7861"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6178_9004_7861[] = "AHA-2940AU Single"; +#endif +static const char pci_device_9004_6278[] = "AIC-7860"; +static const char pci_device_9004_6378[] = "AIC-7860"; +static const char pci_device_9004_6478[] = "AIC-786x"; +static const char pci_device_9004_6578[] = "AIC-786x"; +static const char pci_device_9004_6678[] = "AIC-786x"; +static const char pci_device_9004_6778[] = "AIC-786x"; +static const char pci_device_9004_6915[] = "ANA620xx/ANA69011A"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0008[] = "ANA69011A/TX 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0009[] = "ANA69011A/TX 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0010[] = "ANA62022 2-port 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0018[] = "ANA62044 4-port 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0019[] = "ANA62044 4-port 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0020[] = "ANA62022 2-port 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0028[] = "ANA69011A/TX 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8008[] = "ANA69011A/TX 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8009[] = "ANA69011A/TX 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8010[] = "ANA62022 2-port 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8018[] = "ANA62044 4-port 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8019[] = "ANA62044 4-port 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8020[] = "ANA62022 2-port 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8028[] = "ANA69011A/TX 64 bit 10/100"; +#endif +static const char pci_device_9004_7078[] = "AHA-294x / AIC-7870"; +static const char pci_device_9004_7178[] = "AHA-2940/2940W / AIC-7871"; +static const char pci_device_9004_7278[] = "AHA-3940/3940W / AIC-7872"; +static const char pci_device_9004_7378[] = "AHA-3985 / AIC-7873"; +static const char pci_device_9004_7478[] = "AHA-2944/2944W / AIC-7874"; +static const char pci_device_9004_7578[] = "AHA-3944/3944W / AIC-7875"; +static const char pci_device_9004_7678[] = "AHA-4944W/UW / AIC-7876"; +static const char pci_device_9004_7778[] = "AIC-787x"; +static const char pci_device_9004_7810[] = "AIC-7810"; +static const char pci_device_9004_7815[] = "AIC-7815 RAID+Memory Controller IC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7815_9004_7815[] = "ARO-1130U2 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7815_9004_7840[] = "AIC-7815 RAID+Memory Controller IC"; +#endif +static const char pci_device_9004_7850[] = "AIC-7850"; +static const char pci_device_9004_7855[] = "AHA-2930"; +static const char pci_device_9004_7860[] = "AIC-7860"; +static const char pci_device_9004_7870[] = "AIC-7870"; +static const char pci_device_9004_7871[] = "AHA-2940"; +static const char pci_device_9004_7872[] = "AHA-3940"; +static const char pci_device_9004_7873[] = "AHA-3980"; +static const char pci_device_9004_7874[] = "AHA-2944"; +static const char pci_device_9004_7880[] = "AIC-7880P"; +static const char pci_device_9004_7890[] = "AIC-7890"; +static const char pci_device_9004_7891[] = "AIC-789x"; +static const char pci_device_9004_7892[] = "AIC-789x"; +static const char pci_device_9004_7893[] = "AIC-789x"; +static const char pci_device_9004_7894[] = "AIC-789x"; +static const char pci_device_9004_7895[] = "AHA-2940U/UW / AHA-39xx / AIC-7895"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7890[] = "AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7891[] = "AHA-2940U/2940UW Dual"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7892[] = "AHA-3940AU/AUW/AUWD/UWD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7894[] = "AHA-3944AUWD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7895[] = "AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7896[] = "AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7897[] = "AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B"; +#endif +static const char pci_device_9004_7896[] = "AIC-789x"; +static const char pci_device_9004_7897[] = "AIC-789x"; +static const char pci_device_9004_8078[] = "AIC-7880U"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_8078_9004_7880[] = "AIC-7880P Ultra/Ultra Wide SCSI Chipset"; +#endif +static const char pci_device_9004_8178[] = "AHA-2940U/UW/D / AIC-7881U"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_8178_9004_7881[] = "AHA-2940UW SCSI Host Adapter"; +#endif +static const char pci_device_9004_8278[] = "AHA-3940U/UW/UWD / AIC-7882U"; +static const char pci_device_9004_8378[] = "AHA-3940U/UW / AIC-7883U"; +static const char pci_device_9004_8478[] = "AHA-2944UW / AIC-7884U"; +static const char pci_device_9004_8578[] = "AHA-3944U/UWD / AIC-7885"; +static const char pci_device_9004_8678[] = "AHA-4944UW / AIC-7886"; +static const char pci_device_9004_8778[] = "AHA-2940UW Pro / AIC-788x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_8778_9004_7887[] = "2940UW Pro Ultra-Wide SCSI Controller"; +#endif +static const char pci_device_9004_8878[] = "AHA-2930UW / AIC-7888"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_8878_9004_7888[] = "AHA-2930UW SCSI Controller"; +#endif +static const char pci_device_9004_8b78[] = "ABA-1030"; +static const char pci_device_9004_ec78[] = "AHA-4944W/UW"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_9005[] = "Adaptec"; +static const char pci_device_9005_0010[] = "AHA-2940U2/U2W"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0010_9005_2180[] = "AHA-2940U2 SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0010_9005_8100[] = "AHA-2940U2B SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0010_9005_a180[] = "AHA-2940U2W SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0010_9005_e100[] = "AHA-2950U2B SCSI Controller"; +#endif +static const char pci_device_9005_0011[] = "AHA-2930U2"; +static const char pci_device_9005_0013[] = "78902"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0013_9005_0003[] = "AAA-131U2 Array1000 1 Channel RAID Controller"; +#endif +static const char pci_device_9005_001f[] = "AHA-2940U2/U2W / 7890/7891"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_001f_9005_000f[] = "2940U2W SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_001f_9005_a180[] = "2940U2W SCSI Controller"; +#endif +static const char pci_device_9005_0020[] = "AIC-7890"; +static const char pci_device_9005_002f[] = "AIC-7890"; +static const char pci_device_9005_0030[] = "AIC-7890"; +static const char pci_device_9005_003f[] = "AIC-7890"; +static const char pci_device_9005_0050[] = "AHA-3940U2x/395U2x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0050_9005_f500[] = "AHA-3950U2B"; +#endif +static const char pci_device_9005_0051[] = "AHA-3950U2D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0051_9005_b500[] = "AHA-3950U2D"; +#endif +static const char pci_device_9005_0053[] = "AIC-7896 SCSI Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0053_9005_ffff[] = "AIC-7896 SCSI Controller mainboard implementation"; +#endif +static const char pci_device_9005_005f[] = "AIC-7896U2/7897U2"; +static const char pci_device_9005_0080[] = "AIC-7892A U160/m"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0080_0e11_e2a0[] = "Compaq 64-Bit/66MHz Wide Ultra3 SCSI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0080_9005_62a0[] = "29160N Ultra160 SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0080_9005_e220[] = "29160LP Low Profile Ultra160 SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0080_9005_e2a0[] = "29160 Ultra160 SCSI Controller"; +#endif +static const char pci_device_9005_0081[] = "AIC-7892B U160/m"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0081_9005_62a1[] = "19160 Ultra160 SCSI Controller"; +#endif +static const char pci_device_9005_0083[] = "AIC-7892D U160/m"; +static const char pci_device_9005_008f[] = "AIC-7892P U160/m"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_008f_1179_0001[] = "Magnia Z310"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_008f_15d9_9005[] = "Onboard SCSI Host Adapter"; +#endif +static const char pci_device_9005_00c0[] = "AHA-3960D / AIC-7899A U160/m"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00c0_0e11_f620[] = "Compaq 64-Bit/66MHz Dual Channel Wide Ultra3 SCSI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00c0_9005_f620[] = "AHA-3960D U160/m"; +#endif +static const char pci_device_9005_00c1[] = "AIC-7899B U160/m"; +static const char pci_device_9005_00c3[] = "AIC-7899D U160/m"; +static const char pci_device_9005_00c5[] = "RAID subsystem HBA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00c5_1028_00c5[] = "PowerEdge 2550"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_9005_00cf[] = "AIC-7899P U160/m"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00cf_1028_00d1[] = "PowerEdge 2550"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00cf_10f1_2462[] = "Thunder K7 S2462"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00cf_15d9_9005[] = "Onboard SCSI Host Adapter"; +#endif +static const char pci_device_9005_0250[] = "ServeRAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0250_1014_0279[] = "ServeRAID-xx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0250_1014_028c[] = "ServeRAID-xx"; +#endif +static const char pci_device_9005_0285[] = "AAC-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_1028_0287[] = "PowerEdge Expandable RAID Controller 320/DC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_9005_8000[] = "ASC-29320A U320"; +static const char pci_device_9005_800f[] = "AIC-7901 U320"; +static const char pci_device_9005_8010[] = "ASC-39320 U320"; +static const char pci_device_9005_8011[] = "ASC-32320D U320"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_8011_0e11_00ac[] = "U320"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_8011_9005_0041[] = "ASC-39320D U320"; +#endif +static const char pci_device_9005_8012[] = "ASC-29320 U320"; +static const char pci_device_9005_8013[] = "ASC-29320B U320"; +static const char pci_device_9005_8014[] = "ASC-29320LP U320"; +static const char pci_device_9005_801e[] = "AIC-7901A U320"; +static const char pci_device_9005_801f[] = "AIC-7902 U320"; +static const char pci_device_9005_8090[] = "ASC-39320 U320 w/HostRAID"; +static const char pci_device_9005_8091[] = "ASC-39320D U320 w/HostRAID"; +static const char pci_device_9005_8092[] = "ASC-29320 U320 w/HostRAID"; +static const char pci_device_9005_8093[] = "ASC-29320B U320 w/HostRAID"; +static const char pci_device_9005_8094[] = "ASC-29320LP U320 w/HostRAID"; +static const char pci_device_9005_809e[] = "AIC-7901A U320 w/HostRAID"; +static const char pci_device_9005_809f[] = "AIC-7902 U320 w/HostRAID"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_907f[] = "Atronics"; +static const char pci_device_907f_2015[] = "IDE-2015PL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_919a[] = "Gigapixel Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_9412[] = "Holtek"; +static const char pci_device_9412_6565[] = "6565"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_9699[] = "Omni Media Technology Inc"; +static const char pci_device_9699_6565[] = "6565"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_9710[] = "NetMos Technology"; +static const char pci_device_9710_9815[] = "VScom 021H-EP2 2 port parallel adaptor"; +static const char pci_device_9710_9835[] = "222N-2 I/O Card (2S+1P)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a0a0[] = "AOPEN Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a0f1[] = "UNISYS Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a200[] = "NEC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a259[] = "Hewlett Packard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a25b[] = "Hewlett Packard GmbH PL24-MKT"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a304[] = "Sony"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a727[] = "3Com Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_aa42[] = "Scitex Digital Video"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ac1e[] = "Digital Receiver Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_b1b3[] = "Shiva Europe Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_bd11[] = "Pinnacle Systems, Inc. (Wrong ID)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_c001[] = "TSI Telsys"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_c0a9[] = "Micron/Crucial Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_c0de[] = "Motorola"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_c0fe[] = "Motion Engineering, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ca50[] = "Varian Australia Pty Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_cafe[] = "Chrysalis-ITS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_cccc[] = "Catapult Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_cddd[] = "Tyzx, Inc."; +static const char pci_device_cddd_0101[] = "DeepSea 1 High Speed Stereo Vision Frame Grabber"; +static const char pci_device_cddd_0200[] = "DeepSea 2 High Speed Stereo Vision Frame Grabber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_d4d4[] = "Dy4 Systems Inc"; +static const char pci_device_d4d4_0601[] = "PCI Mezzanine Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_d531[] = "I+ME ACTIA GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_d84d[] = "Exsys"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_dead[] = "Indigita Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_e000[] = "Winbond"; +static const char pci_device_e000_e000[] = "W89C940"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_e159[] = "Tiger Jet Network Inc."; +static const char pci_device_e159_0001[] = "Intel 537"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_e159_0001_0059_0001[] = "128k ISDN-S/T Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_e159_0001_0059_0003[] = "128k ISDN-U Adapter"; +#endif +static const char pci_device_e159_0002[] = "Tiger100APC ISDN chipset"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_e4bf[] = "EKF Elektronik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ea01[] = "Eagle Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ea60[] = "RME"; +static const char pci_device_ea60_9896[] = "Digi32"; +static const char pci_device_ea60_9897[] = "Digi32 Pro"; +static const char pci_device_ea60_9898[] = "Digi32/8"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_eabb[] = "Aashima Technology B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_eace[] = "Endace Measurement Systems, Ltd"; +static const char pci_device_eace_3100[] = "DAG 3.10 OC-3/OC-12"; +static const char pci_device_eace_3200[] = "DAG 3.2x OC-3/OC-12"; +static const char pci_device_eace_320e[] = "DAG 3.2E Fast Ethernet"; +static const char pci_device_eace_340e[] = "DAG 3.4E Fast Ethernet"; +static const char pci_device_eace_341e[] = "DAG 3.41E Fast Ethernet"; +static const char pci_device_eace_3500[] = "DAG 3.5 OC-3/OC-12"; +static const char pci_device_eace_351c[] = "DAG 3.5ECM Fast Ethernet"; +static const char pci_device_eace_4100[] = "DAG 4.10 OC-48"; +static const char pci_device_eace_4110[] = "DAG 4.11 OC-48"; +static const char pci_device_eace_4220[] = "DAG 4.2 OC-48"; +static const char pci_device_eace_422e[] = "DAG 4.2E Dual Gigabit Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ec80[] = "Belkin Corporation"; +static const char pci_device_ec80_ec00[] = "F5D6000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ecc0[] = "Echo Digital Audio Corporation"; +static const char pci_device_ecc0_0050[] = "Gina24_301"; +static const char pci_device_ecc0_0051[] = "Gina24_361"; +static const char pci_device_ecc0_0060[] = "Layla24"; +static const char pci_device_ecc0_0070[] = "Mona_301_80"; +static const char pci_device_ecc0_0071[] = "Mona_301_66"; +static const char pci_device_ecc0_0072[] = "Mona_361"; +static const char pci_device_ecc0_0080[] = "Mia"; +#endif +static const char pci_vendor_edd8[] = "ARK Logic Inc"; +static const char pci_device_edd8_a091[] = "1000PV [Stingray]"; +static const char pci_device_edd8_a099[] = "2000PV [Stingray]"; +static const char pci_device_edd8_a0a1[] = "2000MT"; +static const char pci_device_edd8_a0a9[] = "2000MI"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_f1d0[] = "AJA Video"; +static const char pci_device_f1d0_cafe[] = "KONA SD SMPTE 259M I/O"; +static const char pci_device_f1d0_efac[] = "KONA SD SMPTE 259M I/O"; +static const char pci_device_f1d0_facd[] = "KONA HD SMPTE 292M I/O"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_fa57[] = "Fast Search & Transfer ASA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_febd[] = "Ultraview Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_feda[] = "Broadcom Inc (nee Epigram)"; +static const char pci_device_feda_a0fa[] = "BCM4210 iLine10 HomePNA 2.0"; +static const char pci_device_feda_a10e[] = "BCM4230 iLine10 HomePNA 2.0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_fffe[] = "VMWare Inc"; +static const char pci_device_fffe_0710[] = "Virtual SVGA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ffff[] = "Illegal Vendor ID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const pciSubsystemInfo pci_ss_info_0e11_a0f7_8086_002a = + {0x8086, 0x002a, pci_subsys_0e11_a0f7_8086_002a, 0}; +#undef pci_ss_info_8086_002a +#define pci_ss_info_8086_002a pci_ss_info_0e11_a0f7_8086_002a +static const pciSubsystemInfo pci_ss_info_0e11_a0f7_8086_002b = + {0x8086, 0x002b, pci_subsys_0e11_a0f7_8086_002b, 0}; +#undef pci_ss_info_8086_002b +#define pci_ss_info_8086_002b pci_ss_info_0e11_a0f7_8086_002b +static const pciSubsystemInfo pci_ss_info_0e11_ae10_0e11_4030 = + {0x0e11, 0x4030, pci_subsys_0e11_ae10_0e11_4030, 0}; +#undef pci_ss_info_0e11_4030 +#define pci_ss_info_0e11_4030 pci_ss_info_0e11_ae10_0e11_4030 +static const pciSubsystemInfo pci_ss_info_0e11_ae10_0e11_4031 = + {0x0e11, 0x4031, pci_subsys_0e11_ae10_0e11_4031, 0}; +#undef pci_ss_info_0e11_4031 +#define pci_ss_info_0e11_4031 pci_ss_info_0e11_ae10_0e11_4031 +static const pciSubsystemInfo pci_ss_info_0e11_ae10_0e11_4032 = + {0x0e11, 0x4032, pci_subsys_0e11_ae10_0e11_4032, 0}; +#undef pci_ss_info_0e11_4032 +#define pci_ss_info_0e11_4032 pci_ss_info_0e11_ae10_0e11_4032 +static const pciSubsystemInfo pci_ss_info_0e11_ae10_0e11_4033 = + {0x0e11, 0x4033, pci_subsys_0e11_ae10_0e11_4033, 0}; +#undef pci_ss_info_0e11_4033 +#define pci_ss_info_0e11_4033 pci_ss_info_0e11_ae10_0e11_4033 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0001_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0001_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0001_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_000c_1de1_3907 = + {0x1de1, 0x3907, pci_subsys_1000_000c_1de1_3907, 0}; +#undef pci_ss_info_1de1_3907 +#define pci_ss_info_1de1_3907 pci_ss_info_1000_000c_1de1_3907 +#endif +static const pciSubsystemInfo pci_ss_info_1000_000f_0e11_7004 = + {0x0e11, 0x7004, pci_subsys_1000_000f_0e11_7004, 0}; +#undef pci_ss_info_0e11_7004 +#define pci_ss_info_0e11_7004 pci_ss_info_1000_000f_0e11_7004 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_000f_1092_8760 = + {0x1092, 0x8760, pci_subsys_1000_000f_1092_8760, 0}; +#undef pci_ss_info_1092_8760 +#define pci_ss_info_1092_8760 pci_ss_info_1000_000f_1092_8760 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_000f_1de1_3904 = + {0x1de1, 0x3904, pci_subsys_1000_000f_1de1_3904, 0}; +#undef pci_ss_info_1de1_3904 +#define pci_ss_info_1de1_3904 pci_ss_info_1000_000f_1de1_3904 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0010_0e11_4040 = + {0x0e11, 0x4040, pci_subsys_1000_0010_0e11_4040, 0}; +#undef pci_ss_info_0e11_4040 +#define pci_ss_info_0e11_4040 pci_ss_info_1000_0010_0e11_4040 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0010_0e11_4048 = + {0x0e11, 0x4048, pci_subsys_1000_0010_0e11_4048, 0}; +#undef pci_ss_info_0e11_4048 +#define pci_ss_info_0e11_4048 pci_ss_info_1000_0010_0e11_4048 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0020_1de1_1020 = + {0x1de1, 0x1020, pci_subsys_1000_0020_1de1_1020, 0}; +#undef pci_ss_info_1de1_1020 +#define pci_ss_info_1de1_1020 pci_ss_info_1000_0020_1de1_1020 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_1028_1010 = + {0x1028, 0x1010, pci_subsys_1000_0030_1028_1010, 0}; +#undef pci_ss_info_1028_1010 +#define pci_ss_info_1028_1010 pci_ss_info_1000_0030_1028_1010 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_008f_1092_8000 = + {0x1092, 0x8000, pci_subsys_1000_008f_1092_8000, 0}; +#undef pci_ss_info_1092_8000 +#define pci_ss_info_1092_8000 pci_ss_info_1000_008f_1092_8000 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_008f_1092_8760 = + {0x1092, 0x8760, pci_subsys_1000_008f_1092_8760, 0}; +#undef pci_ss_info_1092_8760 +#define pci_ss_info_1092_8760 pci_ss_info_1000_008f_1092_8760 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0702_1318_0000 = + {0x1318, 0x0000, pci_subsys_1000_0702_1318_0000, 0}; +#undef pci_ss_info_1318_0000 +#define pci_ss_info_1318_0000 pci_ss_info_1000_0702_1318_0000 +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_1028_0518 = + {0x1028, 0x0518, pci_subsys_1000_1960_1028_0518, 0}; +#undef pci_ss_info_1028_0518 +#define pci_ss_info_1028_0518 pci_ss_info_1000_1960_1028_0518 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_1028_0520 = + {0x1028, 0x0520, pci_subsys_1000_1960_1028_0520, 0}; +#undef pci_ss_info_1028_0520 +#define pci_ss_info_1028_0520 pci_ss_info_1000_1960_1028_0520 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_1028_0531 = + {0x1028, 0x0531, pci_subsys_1000_1960_1028_0531, 0}; +#undef pci_ss_info_1028_0531 +#define pci_ss_info_1028_0531 pci_ss_info_1000_1960_1028_0531 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1002_4242_1002_02aa = + {0x1002, 0x02aa, pci_subsys_1002_4242_1002_02aa, 0}; +#undef pci_ss_info_1002_02aa +#define pci_ss_info_1002_02aa pci_ss_info_1002_4242_1002_02aa +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0040 = + {0x1002, 0x0040, pci_subsys_1002_4742_1002_0040, 0}; +#undef pci_ss_info_1002_0040 +#define pci_ss_info_1002_0040 pci_ss_info_1002_4742_1002_0040 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_4742_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_4742_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0061 = + {0x1002, 0x0061, pci_subsys_1002_4742_1002_0061, 0}; +#undef pci_ss_info_1002_0061 +#define pci_ss_info_1002_0061 pci_ss_info_1002_4742_1002_0061 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0062 = + {0x1002, 0x0062, pci_subsys_1002_4742_1002_0062, 0}; +#undef pci_ss_info_1002_0062 +#define pci_ss_info_1002_0062 pci_ss_info_1002_4742_1002_0062 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0063 = + {0x1002, 0x0063, pci_subsys_1002_4742_1002_0063, 0}; +#undef pci_ss_info_1002_0063 +#define pci_ss_info_1002_0063 pci_ss_info_1002_4742_1002_0063 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0080 = + {0x1002, 0x0080, pci_subsys_1002_4742_1002_0080, 0}; +#undef pci_ss_info_1002_0080 +#define pci_ss_info_1002_0080 pci_ss_info_1002_4742_1002_0080 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_4742_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_4742_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_4742 = + {0x1002, 0x4742, pci_subsys_1002_4742_1002_4742, 0}; +#undef pci_ss_info_1002_4742 +#define pci_ss_info_1002_4742 pci_ss_info_1002_4742_1002_4742 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_8001 = + {0x1002, 0x8001, pci_subsys_1002_4742_1002_8001, 0}; +#undef pci_ss_info_1002_8001 +#define pci_ss_info_1002_8001 pci_ss_info_1002_4742_1002_8001 +static const pciSubsystemInfo pci_ss_info_1002_4742_1028_0082 = + {0x1028, 0x0082, pci_subsys_1002_4742_1028_0082, 0}; +#undef pci_ss_info_1028_0082 +#define pci_ss_info_1028_0082 pci_ss_info_1002_4742_1028_0082 +static const pciSubsystemInfo pci_ss_info_1002_4742_1028_4082 = + {0x1028, 0x4082, pci_subsys_1002_4742_1028_4082, 0}; +#undef pci_ss_info_1028_4082 +#define pci_ss_info_1028_4082 pci_ss_info_1002_4742_1028_4082 +static const pciSubsystemInfo pci_ss_info_1002_4742_1028_8082 = + {0x1028, 0x8082, pci_subsys_1002_4742_1028_8082, 0}; +#undef pci_ss_info_1028_8082 +#define pci_ss_info_1028_8082 pci_ss_info_1002_4742_1028_8082 +static const pciSubsystemInfo pci_ss_info_1002_4742_1028_c082 = + {0x1028, 0xc082, pci_subsys_1002_4742_1028_c082, 0}; +#undef pci_ss_info_1028_c082 +#define pci_ss_info_1028_c082 pci_ss_info_1002_4742_1028_c082 +static const pciSubsystemInfo pci_ss_info_1002_4742_8086_4152 = + {0x8086, 0x4152, pci_subsys_1002_4742_8086_4152, 0}; +#undef pci_ss_info_8086_4152 +#define pci_ss_info_8086_4152 pci_ss_info_1002_4742_8086_4152 +static const pciSubsystemInfo pci_ss_info_1002_4742_8086_464a = + {0x8086, 0x464a, pci_subsys_1002_4742_8086_464a, 0}; +#undef pci_ss_info_8086_464a +#define pci_ss_info_8086_464a pci_ss_info_1002_4742_8086_464a +static const pciSubsystemInfo pci_ss_info_1002_4744_1002_4744 = + {0x1002, 0x4744, pci_subsys_1002_4744_1002_4744, 0}; +#undef pci_ss_info_1002_4744 +#define pci_ss_info_1002_4744 pci_ss_info_1002_4744_1002_4744 +static const pciSubsystemInfo pci_ss_info_1002_4749_1002_0061 = + {0x1002, 0x0061, pci_subsys_1002_4749_1002_0061, 0}; +#undef pci_ss_info_1002_0061 +#define pci_ss_info_1002_0061 pci_ss_info_1002_4749_1002_0061 +static const pciSubsystemInfo pci_ss_info_1002_4749_1002_0062 = + {0x1002, 0x0062, pci_subsys_1002_4749_1002_0062, 0}; +#undef pci_ss_info_1002_0062 +#define pci_ss_info_1002_0062 pci_ss_info_1002_4749_1002_0062 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_474d_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_474d_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_474d_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_474d_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_0080 = + {0x1002, 0x0080, pci_subsys_1002_474d_1002_0080, 0}; +#undef pci_ss_info_1002_0080 +#define pci_ss_info_1002_0080 pci_ss_info_1002_474d_1002_0080 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_474d_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_474d_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_474d = + {0x1002, 0x474d, pci_subsys_1002_474d_1002_474d, 0}; +#undef pci_ss_info_1002_474d +#define pci_ss_info_1002_474d pci_ss_info_1002_474d_1002_474d +static const pciSubsystemInfo pci_ss_info_1002_474d_1033_806a = + {0x1033, 0x806a, pci_subsys_1002_474d_1033_806a, 0}; +#undef pci_ss_info_1033_806a +#define pci_ss_info_1033_806a pci_ss_info_1002_474d_1033_806a +static const pciSubsystemInfo pci_ss_info_1002_474e_1002_474e = + {0x1002, 0x474e, pci_subsys_1002_474e_1002_474e, 0}; +#undef pci_ss_info_1002_474e +#define pci_ss_info_1002_474e pci_ss_info_1002_474e_1002_474e +static const pciSubsystemInfo pci_ss_info_1002_474f_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_474f_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_474f_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_474f_1002_474f = + {0x1002, 0x474f, pci_subsys_1002_474f_1002_474f, 0}; +#undef pci_ss_info_1002_474f +#define pci_ss_info_1002_474f pci_ss_info_1002_474f_1002_474f +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_0040 = + {0x1002, 0x0040, pci_subsys_1002_4750_1002_0040, 0}; +#undef pci_ss_info_1002_0040 +#define pci_ss_info_1002_0040 pci_ss_info_1002_4750_1002_0040 +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_4750_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_4750_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_0080 = + {0x1002, 0x0080, pci_subsys_1002_4750_1002_0080, 0}; +#undef pci_ss_info_1002_0080 +#define pci_ss_info_1002_0080 pci_ss_info_1002_4750_1002_0080 +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_4750_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_4750_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_4750 = + {0x1002, 0x4750, pci_subsys_1002_4750_1002_4750, 0}; +#undef pci_ss_info_1002_4750 +#define pci_ss_info_1002_4750 pci_ss_info_1002_4750_1002_4750 +static const pciSubsystemInfo pci_ss_info_1002_4752_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_4752_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_4752_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_4752_1002_4752 = + {0x1002, 0x4752, pci_subsys_1002_4752_1002_4752, 0}; +#undef pci_ss_info_1002_4752 +#define pci_ss_info_1002_4752 pci_ss_info_1002_4752_1002_4752 +static const pciSubsystemInfo pci_ss_info_1002_4752_1002_8008 = + {0x1002, 0x8008, pci_subsys_1002_4752_1002_8008, 0}; +#undef pci_ss_info_1002_8008 +#define pci_ss_info_1002_8008 pci_ss_info_1002_4752_1002_8008 +static const pciSubsystemInfo pci_ss_info_1002_4752_1028_00d1 = + {0x1028, 0x00d1, pci_subsys_1002_4752_1028_00d1, 0}; +#undef pci_ss_info_1028_00d1 +#define pci_ss_info_1028_00d1 pci_ss_info_1002_4752_1028_00d1 +static const pciSubsystemInfo pci_ss_info_1002_4753_1002_4753 = + {0x1002, 0x4753, pci_subsys_1002_4753_1002_4753, 0}; +#undef pci_ss_info_1002_4753 +#define pci_ss_info_1002_4753 pci_ss_info_1002_4753_1002_4753 +static const pciSubsystemInfo pci_ss_info_1002_4756_1002_4756 = + {0x1002, 0x4756, pci_subsys_1002_4756_1002_4756, 0}; +#undef pci_ss_info_1002_4756 +#define pci_ss_info_1002_4756 pci_ss_info_1002_4756_1002_4756 +static const pciSubsystemInfo pci_ss_info_1002_4757_1002_4757 = + {0x1002, 0x4757, pci_subsys_1002_4757_1002_4757, 0}; +#undef pci_ss_info_1002_4757 +#define pci_ss_info_1002_4757 pci_ss_info_1002_4757_1002_4757 +static const pciSubsystemInfo pci_ss_info_1002_4757_1028_0089 = + {0x1028, 0x0089, pci_subsys_1002_4757_1028_0089, 0}; +#undef pci_ss_info_1028_0089 +#define pci_ss_info_1028_0089 pci_ss_info_1002_4757_1028_0089 +static const pciSubsystemInfo pci_ss_info_1002_4757_1028_4082 = + {0x1028, 0x4082, pci_subsys_1002_4757_1028_4082, 0}; +#undef pci_ss_info_1028_4082 +#define pci_ss_info_1028_4082 pci_ss_info_1002_4757_1028_4082 +static const pciSubsystemInfo pci_ss_info_1002_4757_1028_8082 = + {0x1028, 0x8082, pci_subsys_1002_4757_1028_8082, 0}; +#undef pci_ss_info_1028_8082 +#define pci_ss_info_1028_8082 pci_ss_info_1002_4757_1028_8082 +static const pciSubsystemInfo pci_ss_info_1002_4757_1028_c082 = + {0x1028, 0xc082, pci_subsys_1002_4757_1028_c082, 0}; +#undef pci_ss_info_1028_c082 +#define pci_ss_info_1028_c082 pci_ss_info_1002_4757_1028_c082 +static const pciSubsystemInfo pci_ss_info_1002_475a_1002_0087 = + {0x1002, 0x0087, pci_subsys_1002_475a_1002_0087, 0}; +#undef pci_ss_info_1002_0087 +#define pci_ss_info_1002_0087 pci_ss_info_1002_475a_1002_0087 +static const pciSubsystemInfo pci_ss_info_1002_475a_1002_475a = + {0x1002, 0x475a, pci_subsys_1002_475a_1002_475a, 0}; +#undef pci_ss_info_1002_475a +#define pci_ss_info_1002_475a pci_ss_info_1002_475a_1002_475a +static const pciSubsystemInfo pci_ss_info_1002_4966_10f1_0002 = + {0x10f1, 0x0002, pci_subsys_1002_4966_10f1_0002, 0}; +#undef pci_ss_info_10f1_0002 +#define pci_ss_info_10f1_0002 pci_ss_info_1002_4966_10f1_0002 +static const pciSubsystemInfo pci_ss_info_1002_4966_148c_2039 = + {0x148c, 0x2039, pci_subsys_1002_4966_148c_2039, 0}; +#undef pci_ss_info_148c_2039 +#define pci_ss_info_148c_2039 pci_ss_info_1002_4966_148c_2039 +static const pciSubsystemInfo pci_ss_info_1002_4966_1509_9a00 = + {0x1509, 0x9a00, pci_subsys_1002_4966_1509_9a00, 0}; +#undef pci_ss_info_1509_9a00 +#define pci_ss_info_1509_9a00 pci_ss_info_1002_4966_1509_9a00 +static const pciSubsystemInfo pci_ss_info_1002_4966_1681_0040 = + {0x1681, 0x0040, pci_subsys_1002_4966_1681_0040, 0}; +#undef pci_ss_info_1681_0040 +#define pci_ss_info_1681_0040 pci_ss_info_1002_4966_1681_0040 +static const pciSubsystemInfo pci_ss_info_1002_4966_174b_7176 = + {0x174b, 0x7176, pci_subsys_1002_4966_174b_7176, 0}; +#undef pci_ss_info_174b_7176 +#define pci_ss_info_174b_7176 pci_ss_info_1002_4966_174b_7176 +static const pciSubsystemInfo pci_ss_info_1002_4966_174b_7192 = + {0x174b, 0x7192, pci_subsys_1002_4966_174b_7192, 0}; +#undef pci_ss_info_174b_7192 +#define pci_ss_info_174b_7192 pci_ss_info_1002_4966_174b_7192 +static const pciSubsystemInfo pci_ss_info_1002_4966_17af_2005 = + {0x17af, 0x2005, pci_subsys_1002_4966_17af_2005, 0}; +#undef pci_ss_info_17af_2005 +#define pci_ss_info_17af_2005 pci_ss_info_1002_4966_17af_2005 +static const pciSubsystemInfo pci_ss_info_1002_4966_17af_2006 = + {0x17af, 0x2006, pci_subsys_1002_4966_17af_2006, 0}; +#undef pci_ss_info_17af_2006 +#define pci_ss_info_17af_2006 pci_ss_info_1002_4966_17af_2006 +static const pciSubsystemInfo pci_ss_info_1002_4c42_0e11_b0e8 = + {0x0e11, 0xb0e8, pci_subsys_1002_4c42_0e11_b0e8, 0}; +#undef pci_ss_info_0e11_b0e8 +#define pci_ss_info_0e11_b0e8 pci_ss_info_1002_4c42_0e11_b0e8 +static const pciSubsystemInfo pci_ss_info_1002_4c42_0e11_b10e = + {0x0e11, 0xb10e, pci_subsys_1002_4c42_0e11_b10e, 0}; +#undef pci_ss_info_0e11_b10e +#define pci_ss_info_0e11_b10e pci_ss_info_1002_4c42_0e11_b10e +static const pciSubsystemInfo pci_ss_info_1002_4c42_1002_0040 = + {0x1002, 0x0040, pci_subsys_1002_4c42_1002_0040, 0}; +#undef pci_ss_info_1002_0040 +#define pci_ss_info_1002_0040 pci_ss_info_1002_4c42_1002_0040 +static const pciSubsystemInfo pci_ss_info_1002_4c42_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_4c42_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_4c42_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_4c42_1002_4c42 = + {0x1002, 0x4c42, pci_subsys_1002_4c42_1002_4c42, 0}; +#undef pci_ss_info_1002_4c42 +#define pci_ss_info_1002_4c42 pci_ss_info_1002_4c42_1002_4c42 +static const pciSubsystemInfo pci_ss_info_1002_4c42_1002_8001 = + {0x1002, 0x8001, pci_subsys_1002_4c42_1002_8001, 0}; +#undef pci_ss_info_1002_8001 +#define pci_ss_info_1002_8001 pci_ss_info_1002_4c42_1002_8001 +static const pciSubsystemInfo pci_ss_info_1002_4c42_1028_0085 = + {0x1028, 0x0085, pci_subsys_1002_4c42_1028_0085, 0}; +#undef pci_ss_info_1028_0085 +#define pci_ss_info_1028_0085 pci_ss_info_1002_4c42_1028_0085 +static const pciSubsystemInfo pci_ss_info_1002_4c49_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_4c49_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_4c49_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_4c49_1002_0040 = + {0x1002, 0x0040, pci_subsys_1002_4c49_1002_0040, 0}; +#undef pci_ss_info_1002_0040 +#define pci_ss_info_1002_0040 pci_ss_info_1002_4c49_1002_0040 +static const pciSubsystemInfo pci_ss_info_1002_4c49_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_4c49_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_4c49_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_4c49_1002_4c49 = + {0x1002, 0x4c49, pci_subsys_1002_4c49_1002_4c49, 0}; +#undef pci_ss_info_1002_4c49 +#define pci_ss_info_1002_4c49 pci_ss_info_1002_4c49_1002_4c49 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_0e11_b111 = + {0x0e11, 0xb111, pci_subsys_1002_4c4d_0e11_b111, 0}; +#undef pci_ss_info_0e11_b111 +#define pci_ss_info_0e11_b111 pci_ss_info_1002_4c4d_0e11_b111 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_4c4d_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_4c4d_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_1014_0154 = + {0x1014, 0x0154, pci_subsys_1002_4c4d_1014_0154, 0}; +#undef pci_ss_info_1014_0154 +#define pci_ss_info_1014_0154 pci_ss_info_1002_4c4d_1014_0154 +static const pciSubsystemInfo pci_ss_info_1002_4c50_1002_4c50 = + {0x1002, 0x4c50, pci_subsys_1002_4c50_1002_4c50, 0}; +#undef pci_ss_info_1002_4c50 +#define pci_ss_info_1002_4c50 pci_ss_info_1002_4c50_1002_4c50 +static const pciSubsystemInfo pci_ss_info_1002_4c57_1014_0517 = + {0x1014, 0x0517, pci_subsys_1002_4c57_1014_0517, 0}; +#undef pci_ss_info_1014_0517 +#define pci_ss_info_1014_0517 pci_ss_info_1002_4c57_1014_0517 +static const pciSubsystemInfo pci_ss_info_1002_4c57_1028_00e6 = + {0x1028, 0x00e6, pci_subsys_1002_4c57_1028_00e6, 0}; +#undef pci_ss_info_1028_00e6 +#define pci_ss_info_1028_00e6 pci_ss_info_1002_4c57_1028_00e6 +static const pciSubsystemInfo pci_ss_info_1002_4c57_144d_c006 = + {0x144d, 0xc006, pci_subsys_1002_4c57_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_1002_4c57_144d_c006 +static const pciSubsystemInfo pci_ss_info_1002_4c59_1014_0235 = + {0x1014, 0x0235, pci_subsys_1002_4c59_1014_0235, 0}; +#undef pci_ss_info_1014_0235 +#define pci_ss_info_1014_0235 pci_ss_info_1002_4c59_1014_0235 +static const pciSubsystemInfo pci_ss_info_1002_4c59_1014_0239 = + {0x1014, 0x0239, pci_subsys_1002_4c59_1014_0239, 0}; +#undef pci_ss_info_1014_0239 +#define pci_ss_info_1014_0239 pci_ss_info_1002_4c59_1014_0239 +static const pciSubsystemInfo pci_ss_info_1002_4c59_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_1002_4c59_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_1002_4c59_104d_80e7 +static const pciSubsystemInfo pci_ss_info_1002_5044_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5044_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5044_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5044_1002_0029 = + {0x1002, 0x0029, pci_subsys_1002_5044_1002_0029, 0}; +#undef pci_ss_info_1002_0029 +#define pci_ss_info_1002_0029 pci_ss_info_1002_5044_1002_0029 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_5046_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_5046_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5046_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5046_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0014 = + {0x1002, 0x0014, pci_subsys_1002_5046_1002_0014, 0}; +#undef pci_ss_info_1002_0014 +#define pci_ss_info_1002_0014 pci_ss_info_1002_5046_1002_0014 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0018 = + {0x1002, 0x0018, pci_subsys_1002_5046_1002_0018, 0}; +#undef pci_ss_info_1002_0018 +#define pci_ss_info_1002_0018 pci_ss_info_1002_5046_1002_0018 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5046_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5046_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_002a = + {0x1002, 0x002a, pci_subsys_1002_5046_1002_002a, 0}; +#undef pci_ss_info_1002_002a +#define pci_ss_info_1002_002a pci_ss_info_1002_5046_1002_002a +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0048 = + {0x1002, 0x0048, pci_subsys_1002_5046_1002_0048, 0}; +#undef pci_ss_info_1002_0048 +#define pci_ss_info_1002_0048 pci_ss_info_1002_5046_1002_0048 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_2000 = + {0x1002, 0x2000, pci_subsys_1002_5046_1002_2000, 0}; +#undef pci_ss_info_1002_2000 +#define pci_ss_info_1002_2000 pci_ss_info_1002_5046_1002_2000 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_2001 = + {0x1002, 0x2001, pci_subsys_1002_5046_1002_2001, 0}; +#undef pci_ss_info_1002_2001 +#define pci_ss_info_1002_2001 pci_ss_info_1002_5046_1002_2001 +static const pciSubsystemInfo pci_ss_info_1002_5050_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5050_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5050_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5144_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5144_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0009 = + {0x1002, 0x0009, pci_subsys_1002_5144_1002_0009, 0}; +#undef pci_ss_info_1002_0009 +#define pci_ss_info_1002_0009 pci_ss_info_1002_5144_1002_0009 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_000a = + {0x1002, 0x000a, pci_subsys_1002_5144_1002_000a, 0}; +#undef pci_ss_info_1002_000a +#define pci_ss_info_1002_000a pci_ss_info_1002_5144_1002_000a +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_001a = + {0x1002, 0x001a, pci_subsys_1002_5144_1002_001a, 0}; +#undef pci_ss_info_1002_001a +#define pci_ss_info_1002_001a pci_ss_info_1002_5144_1002_001a +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0029 = + {0x1002, 0x0029, pci_subsys_1002_5144_1002_0029, 0}; +#undef pci_ss_info_1002_0029 +#define pci_ss_info_1002_0029 pci_ss_info_1002_5144_1002_0029 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0038 = + {0x1002, 0x0038, pci_subsys_1002_5144_1002_0038, 0}; +#undef pci_ss_info_1002_0038 +#define pci_ss_info_1002_0038 pci_ss_info_1002_5144_1002_0038 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0039 = + {0x1002, 0x0039, pci_subsys_1002_5144_1002_0039, 0}; +#undef pci_ss_info_1002_0039 +#define pci_ss_info_1002_0039 pci_ss_info_1002_5144_1002_0039 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_008a = + {0x1002, 0x008a, pci_subsys_1002_5144_1002_008a, 0}; +#undef pci_ss_info_1002_008a +#define pci_ss_info_1002_008a pci_ss_info_1002_5144_1002_008a +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_00ba = + {0x1002, 0x00ba, pci_subsys_1002_5144_1002_00ba, 0}; +#undef pci_ss_info_1002_00ba +#define pci_ss_info_1002_00ba pci_ss_info_1002_5144_1002_00ba +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0139 = + {0x1002, 0x0139, pci_subsys_1002_5144_1002_0139, 0}; +#undef pci_ss_info_1002_0139 +#define pci_ss_info_1002_0139 pci_ss_info_1002_5144_1002_0139 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_028a = + {0x1002, 0x028a, pci_subsys_1002_5144_1002_028a, 0}; +#undef pci_ss_info_1002_028a +#define pci_ss_info_1002_028a pci_ss_info_1002_5144_1002_028a +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_02aa = + {0x1002, 0x02aa, pci_subsys_1002_5144_1002_02aa, 0}; +#undef pci_ss_info_1002_02aa +#define pci_ss_info_1002_02aa pci_ss_info_1002_5144_1002_02aa +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_053a = + {0x1002, 0x053a, pci_subsys_1002_5144_1002_053a, 0}; +#undef pci_ss_info_1002_053a +#define pci_ss_info_1002_053a pci_ss_info_1002_5144_1002_053a +static const pciSubsystemInfo pci_ss_info_1002_5148_1002_010a = + {0x1002, 0x010a, pci_subsys_1002_5148_1002_010a, 0}; +#undef pci_ss_info_1002_010a +#define pci_ss_info_1002_010a pci_ss_info_1002_5148_1002_010a +static const pciSubsystemInfo pci_ss_info_1002_5148_1002_0152 = + {0x1002, 0x0152, pci_subsys_1002_5148_1002_0152, 0}; +#undef pci_ss_info_1002_0152 +#define pci_ss_info_1002_0152 pci_ss_info_1002_5148_1002_0152 +static const pciSubsystemInfo pci_ss_info_1002_5148_1002_0162 = + {0x1002, 0x0162, pci_subsys_1002_5148_1002_0162, 0}; +#undef pci_ss_info_1002_0162 +#define pci_ss_info_1002_0162 pci_ss_info_1002_5148_1002_0162 +static const pciSubsystemInfo pci_ss_info_1002_5148_1002_0172 = + {0x1002, 0x0172, pci_subsys_1002_5148_1002_0172, 0}; +#undef pci_ss_info_1002_0172 +#define pci_ss_info_1002_0172 pci_ss_info_1002_5148_1002_0172 +static const pciSubsystemInfo pci_ss_info_1002_514c_1002_003a = + {0x1002, 0x003a, pci_subsys_1002_514c_1002_003a, 0}; +#undef pci_ss_info_1002_003a +#define pci_ss_info_1002_003a pci_ss_info_1002_514c_1002_003a +static const pciSubsystemInfo pci_ss_info_1002_514c_1002_013a = + {0x1002, 0x013a, pci_subsys_1002_514c_1002_013a, 0}; +#undef pci_ss_info_1002_013a +#define pci_ss_info_1002_013a pci_ss_info_1002_514c_1002_013a +static const pciSubsystemInfo pci_ss_info_1002_514c_148c_2026 = + {0x148c, 0x2026, pci_subsys_1002_514c_148c_2026, 0}; +#undef pci_ss_info_148c_2026 +#define pci_ss_info_148c_2026 pci_ss_info_1002_514c_148c_2026 +static const pciSubsystemInfo pci_ss_info_1002_514c_174b_7149 = + {0x174b, 0x7149, pci_subsys_1002_514c_174b_7149, 0}; +#undef pci_ss_info_174b_7149 +#define pci_ss_info_174b_7149 pci_ss_info_1002_514c_174b_7149 +static const pciSubsystemInfo pci_ss_info_1002_5157_1002_013a = + {0x1002, 0x013a, pci_subsys_1002_5157_1002_013a, 0}; +#undef pci_ss_info_1002_013a +#define pci_ss_info_1002_013a pci_ss_info_1002_5157_1002_013a +static const pciSubsystemInfo pci_ss_info_1002_5157_1458_4000 = + {0x1458, 0x4000, pci_subsys_1002_5157_1458_4000, 0}; +#undef pci_ss_info_1458_4000 +#define pci_ss_info_1458_4000 pci_ss_info_1002_5157_1458_4000 +static const pciSubsystemInfo pci_ss_info_1002_5157_148c_2024 = + {0x148c, 0x2024, pci_subsys_1002_5157_148c_2024, 0}; +#undef pci_ss_info_148c_2024 +#define pci_ss_info_148c_2024 pci_ss_info_1002_5157_148c_2024 +static const pciSubsystemInfo pci_ss_info_1002_5157_148c_2025 = + {0x148c, 0x2025, pci_subsys_1002_5157_148c_2025, 0}; +#undef pci_ss_info_148c_2025 +#define pci_ss_info_148c_2025 pci_ss_info_1002_5157_148c_2025 +static const pciSubsystemInfo pci_ss_info_1002_5157_148c_2036 = + {0x148c, 0x2036, pci_subsys_1002_5157_148c_2036, 0}; +#undef pci_ss_info_148c_2036 +#define pci_ss_info_148c_2036 pci_ss_info_1002_5157_148c_2036 +static const pciSubsystemInfo pci_ss_info_1002_5157_174b_7147 = + {0x174b, 0x7147, pci_subsys_1002_5157_174b_7147, 0}; +#undef pci_ss_info_174b_7147 +#define pci_ss_info_174b_7147 pci_ss_info_1002_5157_174b_7147 +static const pciSubsystemInfo pci_ss_info_1002_5157_174b_7161 = + {0x174b, 0x7161, pci_subsys_1002_5157_174b_7161, 0}; +#undef pci_ss_info_174b_7161 +#define pci_ss_info_174b_7161 pci_ss_info_1002_5157_174b_7161 +static const pciSubsystemInfo pci_ss_info_1002_5157_17af_0202 = + {0x17af, 0x0202, pci_subsys_1002_5157_17af_0202, 0}; +#undef pci_ss_info_17af_0202 +#define pci_ss_info_17af_0202 pci_ss_info_1002_5157_17af_0202 +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_000a = + {0x1002, 0x000a, pci_subsys_1002_5159_1002_000a, 0}; +#undef pci_ss_info_1002_000a +#define pci_ss_info_1002_000a pci_ss_info_1002_5159_1002_000a +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_000b = + {0x1002, 0x000b, pci_subsys_1002_5159_1002_000b, 0}; +#undef pci_ss_info_1002_000b +#define pci_ss_info_1002_000b pci_ss_info_1002_5159_1002_000b +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_0038 = + {0x1002, 0x0038, pci_subsys_1002_5159_1002_0038, 0}; +#undef pci_ss_info_1002_0038 +#define pci_ss_info_1002_0038 pci_ss_info_1002_5159_1002_0038 +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_003a = + {0x1002, 0x003a, pci_subsys_1002_5159_1002_003a, 0}; +#undef pci_ss_info_1002_003a +#define pci_ss_info_1002_003a pci_ss_info_1002_5159_1002_003a +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_00ba = + {0x1002, 0x00ba, pci_subsys_1002_5159_1002_00ba, 0}; +#undef pci_ss_info_1002_00ba +#define pci_ss_info_1002_00ba pci_ss_info_1002_5159_1002_00ba +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_013a = + {0x1002, 0x013a, pci_subsys_1002_5159_1002_013a, 0}; +#undef pci_ss_info_1002_013a +#define pci_ss_info_1002_013a pci_ss_info_1002_5159_1002_013a +static const pciSubsystemInfo pci_ss_info_1002_5159_1458_4002 = + {0x1458, 0x4002, pci_subsys_1002_5159_1458_4002, 0}; +#undef pci_ss_info_1458_4002 +#define pci_ss_info_1458_4002 pci_ss_info_1002_5159_1458_4002 +static const pciSubsystemInfo pci_ss_info_1002_5159_148c_2003 = + {0x148c, 0x2003, pci_subsys_1002_5159_148c_2003, 0}; +#undef pci_ss_info_148c_2003 +#define pci_ss_info_148c_2003 pci_ss_info_1002_5159_148c_2003 +static const pciSubsystemInfo pci_ss_info_1002_5159_148c_2023 = + {0x148c, 0x2023, pci_subsys_1002_5159_148c_2023, 0}; +#undef pci_ss_info_148c_2023 +#define pci_ss_info_148c_2023 pci_ss_info_1002_5159_148c_2023 +static const pciSubsystemInfo pci_ss_info_1002_5159_174b_7112 = + {0x174b, 0x7112, pci_subsys_1002_5159_174b_7112, 0}; +#undef pci_ss_info_174b_7112 +#define pci_ss_info_174b_7112 pci_ss_info_1002_5159_174b_7112 +static const pciSubsystemInfo pci_ss_info_1002_5159_1787_0202 = + {0x1787, 0x0202, pci_subsys_1002_5159_1787_0202, 0}; +#undef pci_ss_info_1787_0202 +#define pci_ss_info_1787_0202 pci_ss_info_1002_5159_1787_0202 +static const pciSubsystemInfo pci_ss_info_1002_5245_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5245_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5245_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5245_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5245_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5245_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5245_1002_0029 = + {0x1002, 0x0029, pci_subsys_1002_5245_1002_0029, 0}; +#undef pci_ss_info_1002_0029 +#define pci_ss_info_1002_0029 pci_ss_info_1002_5245_1002_0029 +static const pciSubsystemInfo pci_ss_info_1002_5245_1002_0068 = + {0x1002, 0x0068, pci_subsys_1002_5245_1002_0068, 0}; +#undef pci_ss_info_1002_0068 +#define pci_ss_info_1002_0068 pci_ss_info_1002_5245_1002_0068 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_5246_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_5246_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5246_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5246_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5246_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5246_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_5246_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_5246_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0068 = + {0x1002, 0x0068, pci_subsys_1002_5246_1002_0068, 0}; +#undef pci_ss_info_1002_0068 +#define pci_ss_info_1002_0068 pci_ss_info_1002_5246_1002_0068 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0448 = + {0x1002, 0x0448, pci_subsys_1002_5246_1002_0448, 0}; +#undef pci_ss_info_1002_0448 +#define pci_ss_info_1002_0448 pci_ss_info_1002_5246_1002_0448 +static const pciSubsystemInfo pci_ss_info_1002_524c_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_524c_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_524c_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_524c_1002_0088 = + {0x1002, 0x0088, pci_subsys_1002_524c_1002_0088, 0}; +#undef pci_ss_info_1002_0088 +#define pci_ss_info_1002_0088 pci_ss_info_1002_524c_1002_0088 +static const pciSubsystemInfo pci_ss_info_1002_534d_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_534d_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_534d_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_534d_1002_0018 = + {0x1002, 0x0018, pci_subsys_1002_534d_1002_0018, 0}; +#undef pci_ss_info_1002_0018 +#define pci_ss_info_1002_0018 pci_ss_info_1002_534d_1002_0018 +static const pciSubsystemInfo pci_ss_info_1002_5354_1002_5654 = + {0x1002, 0x5654, pci_subsys_1002_5354_1002_5654, 0}; +#undef pci_ss_info_1002_5654 +#define pci_ss_info_1002_5654 pci_ss_info_1002_5354_1002_5654 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_5446_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_5446_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5446_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5446_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0018 = + {0x1002, 0x0018, pci_subsys_1002_5446_1002_0018, 0}; +#undef pci_ss_info_1002_0018 +#define pci_ss_info_1002_0018 pci_ss_info_1002_5446_1002_0018 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5446_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5446_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0029 = + {0x1002, 0x0029, pci_subsys_1002_5446_1002_0029, 0}; +#undef pci_ss_info_1002_0029 +#define pci_ss_info_1002_0029 pci_ss_info_1002_5446_1002_0029 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_002a = + {0x1002, 0x002a, pci_subsys_1002_5446_1002_002a, 0}; +#undef pci_ss_info_1002_002a +#define pci_ss_info_1002_002a pci_ss_info_1002_5446_1002_002a +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_002b = + {0x1002, 0x002b, pci_subsys_1002_5446_1002_002b, 0}; +#undef pci_ss_info_1002_002b +#define pci_ss_info_1002_002b pci_ss_info_1002_5446_1002_002b +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0048 = + {0x1002, 0x0048, pci_subsys_1002_5446_1002_0048, 0}; +#undef pci_ss_info_1002_0048 +#define pci_ss_info_1002_0048 pci_ss_info_1002_5446_1002_0048 +static const pciSubsystemInfo pci_ss_info_1002_5452_1002_001c = + {0x1002, 0x001c, pci_subsys_1002_5452_1002_001c, 0}; +#undef pci_ss_info_1002_001c +#define pci_ss_info_1002_001c pci_ss_info_1002_5452_1002_001c +static const pciSubsystemInfo pci_ss_info_1002_5452_103c_1279 = + {0x103c, 0x1279, pci_subsys_1002_5452_103c_1279, 0}; +#undef pci_ss_info_103c_1279 +#define pci_ss_info_103c_1279 pci_ss_info_1002_5452_103c_1279 +static const pciSubsystemInfo pci_ss_info_1002_5654_1002_5654 = + {0x1002, 0x5654, pci_subsys_1002_5654_1002_5654, 0}; +#undef pci_ss_info_1002_5654 +#define pci_ss_info_1002_5654 pci_ss_info_1002_5654_1002_5654 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1004_0304_1004_0304 = + {0x1004, 0x0304, pci_subsys_1004_0304_1004_0304, 0}; +#undef pci_ss_info_1004_0304 +#define pci_ss_info_1004_0304 pci_ss_info_1004_0304_1004_0304 +static const pciSubsystemInfo pci_ss_info_1004_0304_122d_1206 = + {0x122d, 0x1206, pci_subsys_1004_0304_122d_1206, 0}; +#undef pci_ss_info_122d_1206 +#define pci_ss_info_122d_1206 pci_ss_info_1004_0304_122d_1206 +static const pciSubsystemInfo pci_ss_info_1004_0304_1483_5020 = + {0x1483, 0x5020, pci_subsys_1004_0304_1483_5020, 0}; +#undef pci_ss_info_1483_5020 +#define pci_ss_info_1483_5020 pci_ss_info_1004_0304_1483_5020 +static const pciSubsystemInfo pci_ss_info_1004_0305_1004_0305 = + {0x1004, 0x0305, pci_subsys_1004_0305_1004_0305, 0}; +#undef pci_ss_info_1004_0305 +#define pci_ss_info_1004_0305 pci_ss_info_1004_0305_1004_0305 +static const pciSubsystemInfo pci_ss_info_1004_0305_122d_1207 = + {0x122d, 0x1207, pci_subsys_1004_0305_122d_1207, 0}; +#undef pci_ss_info_122d_1207 +#define pci_ss_info_122d_1207 pci_ss_info_1004_0305_122d_1207 +static const pciSubsystemInfo pci_ss_info_1004_0305_1483_5021 = + {0x1483, 0x5021, pci_subsys_1004_0305_1483_5021, 0}; +#undef pci_ss_info_1483_5021 +#define pci_ss_info_1483_5021 pci_ss_info_1004_0305_1483_5021 +static const pciSubsystemInfo pci_ss_info_1004_0306_1004_0306 = + {0x1004, 0x0306, pci_subsys_1004_0306_1004_0306, 0}; +#undef pci_ss_info_1004_0306 +#define pci_ss_info_1004_0306 pci_ss_info_1004_0306_1004_0306 +static const pciSubsystemInfo pci_ss_info_1004_0306_122d_1208 = + {0x122d, 0x1208, pci_subsys_1004_0306_122d_1208, 0}; +#undef pci_ss_info_122d_1208 +#define pci_ss_info_122d_1208 pci_ss_info_1004_0306_122d_1208 +static const pciSubsystemInfo pci_ss_info_1004_0306_1483_5022 = + {0x1483, 0x5022, pci_subsys_1004_0306_1483_5022, 0}; +#undef pci_ss_info_1483_5022 +#define pci_ss_info_1483_5022 pci_ss_info_1004_0306_1483_5022 +#endif +static const pciSubsystemInfo pci_ss_info_1011_0009_1025_0310 = + {0x1025, 0x0310, pci_subsys_1011_0009_1025_0310, 0}; +#undef pci_ss_info_1025_0310 +#define pci_ss_info_1025_0310 pci_ss_info_1011_0009_1025_0310 +static const pciSubsystemInfo pci_ss_info_1011_0009_10b8_2001 = + {0x10b8, 0x2001, pci_subsys_1011_0009_10b8_2001, 0}; +#undef pci_ss_info_10b8_2001 +#define pci_ss_info_10b8_2001 pci_ss_info_1011_0009_10b8_2001 +static const pciSubsystemInfo pci_ss_info_1011_0009_10b8_2002 = + {0x10b8, 0x2002, pci_subsys_1011_0009_10b8_2002, 0}; +#undef pci_ss_info_10b8_2002 +#define pci_ss_info_10b8_2002 pci_ss_info_1011_0009_10b8_2002 +static const pciSubsystemInfo pci_ss_info_1011_0009_10b8_2003 = + {0x10b8, 0x2003, pci_subsys_1011_0009_10b8_2003, 0}; +#undef pci_ss_info_10b8_2003 +#define pci_ss_info_10b8_2003 pci_ss_info_1011_0009_10b8_2003 +static const pciSubsystemInfo pci_ss_info_1011_0009_1109_2400 = + {0x1109, 0x2400, pci_subsys_1011_0009_1109_2400, 0}; +#undef pci_ss_info_1109_2400 +#define pci_ss_info_1109_2400 pci_ss_info_1011_0009_1109_2400 +static const pciSubsystemInfo pci_ss_info_1011_0009_1112_2300 = + {0x1112, 0x2300, pci_subsys_1011_0009_1112_2300, 0}; +#undef pci_ss_info_1112_2300 +#define pci_ss_info_1112_2300 pci_ss_info_1011_0009_1112_2300 +static const pciSubsystemInfo pci_ss_info_1011_0009_1112_2320 = + {0x1112, 0x2320, pci_subsys_1011_0009_1112_2320, 0}; +#undef pci_ss_info_1112_2320 +#define pci_ss_info_1112_2320 pci_ss_info_1011_0009_1112_2320 +static const pciSubsystemInfo pci_ss_info_1011_0009_1112_2340 = + {0x1112, 0x2340, pci_subsys_1011_0009_1112_2340, 0}; +#undef pci_ss_info_1112_2340 +#define pci_ss_info_1112_2340 pci_ss_info_1011_0009_1112_2340 +static const pciSubsystemInfo pci_ss_info_1011_0009_1113_1207 = + {0x1113, 0x1207, pci_subsys_1011_0009_1113_1207, 0}; +#undef pci_ss_info_1113_1207 +#define pci_ss_info_1113_1207 pci_ss_info_1011_0009_1113_1207 +static const pciSubsystemInfo pci_ss_info_1011_0009_1186_1100 = + {0x1186, 0x1100, pci_subsys_1011_0009_1186_1100, 0}; +#undef pci_ss_info_1186_1100 +#define pci_ss_info_1186_1100 pci_ss_info_1011_0009_1186_1100 +static const pciSubsystemInfo pci_ss_info_1011_0009_1186_1112 = + {0x1186, 0x1112, pci_subsys_1011_0009_1186_1112, 0}; +#undef pci_ss_info_1186_1112 +#define pci_ss_info_1186_1112 pci_ss_info_1011_0009_1186_1112 +static const pciSubsystemInfo pci_ss_info_1011_0009_1186_1140 = + {0x1186, 0x1140, pci_subsys_1011_0009_1186_1140, 0}; +#undef pci_ss_info_1186_1140 +#define pci_ss_info_1186_1140 pci_ss_info_1011_0009_1186_1140 +static const pciSubsystemInfo pci_ss_info_1011_0009_1186_1142 = + {0x1186, 0x1142, pci_subsys_1011_0009_1186_1142, 0}; +#undef pci_ss_info_1186_1142 +#define pci_ss_info_1186_1142 pci_ss_info_1011_0009_1186_1142 +static const pciSubsystemInfo pci_ss_info_1011_0009_11f6_0503 = + {0x11f6, 0x0503, pci_subsys_1011_0009_11f6_0503, 0}; +#undef pci_ss_info_11f6_0503 +#define pci_ss_info_11f6_0503 pci_ss_info_1011_0009_11f6_0503 +static const pciSubsystemInfo pci_ss_info_1011_0009_1282_9100 = + {0x1282, 0x9100, pci_subsys_1011_0009_1282_9100, 0}; +#undef pci_ss_info_1282_9100 +#define pci_ss_info_1282_9100 pci_ss_info_1011_0009_1282_9100 +static const pciSubsystemInfo pci_ss_info_1011_0009_1385_1100 = + {0x1385, 0x1100, pci_subsys_1011_0009_1385_1100, 0}; +#undef pci_ss_info_1385_1100 +#define pci_ss_info_1385_1100 pci_ss_info_1011_0009_1385_1100 +static const pciSubsystemInfo pci_ss_info_1011_0009_2646_0001 = + {0x2646, 0x0001, pci_subsys_1011_0009_2646_0001, 0}; +#undef pci_ss_info_2646_0001 +#define pci_ss_info_2646_0001 pci_ss_info_1011_0009_2646_0001 +static const pciSubsystemInfo pci_ss_info_1011_0014_1186_0100 = + {0x1186, 0x0100, pci_subsys_1011_0014_1186_0100, 0}; +#undef pci_ss_info_1186_0100 +#define pci_ss_info_1186_0100 pci_ss_info_1011_0014_1186_0100 +static const pciSubsystemInfo pci_ss_info_1011_0019_1011_500a = + {0x1011, 0x500a, pci_subsys_1011_0019_1011_500a, 0}; +#undef pci_ss_info_1011_500a +#define pci_ss_info_1011_500a pci_ss_info_1011_0019_1011_500a +static const pciSubsystemInfo pci_ss_info_1011_0019_1011_500b = + {0x1011, 0x500b, pci_subsys_1011_0019_1011_500b, 0}; +#undef pci_ss_info_1011_500b +#define pci_ss_info_1011_500b pci_ss_info_1011_0019_1011_500b +static const pciSubsystemInfo pci_ss_info_1011_0019_1014_0001 = + {0x1014, 0x0001, pci_subsys_1011_0019_1014_0001, 0}; +#undef pci_ss_info_1014_0001 +#define pci_ss_info_1014_0001 pci_ss_info_1011_0019_1014_0001 +static const pciSubsystemInfo pci_ss_info_1011_0019_1025_0315 = + {0x1025, 0x0315, pci_subsys_1011_0019_1025_0315, 0}; +#undef pci_ss_info_1025_0315 +#define pci_ss_info_1025_0315 pci_ss_info_1011_0019_1025_0315 +static const pciSubsystemInfo pci_ss_info_1011_0019_1033_800c = + {0x1033, 0x800c, pci_subsys_1011_0019_1033_800c, 0}; +#undef pci_ss_info_1033_800c +#define pci_ss_info_1033_800c pci_ss_info_1011_0019_1033_800c +static const pciSubsystemInfo pci_ss_info_1011_0019_1033_800d = + {0x1033, 0x800d, pci_subsys_1011_0019_1033_800d, 0}; +#undef pci_ss_info_1033_800d +#define pci_ss_info_1033_800d pci_ss_info_1011_0019_1033_800d +static const pciSubsystemInfo pci_ss_info_1011_0019_108d_0016 = + {0x108d, 0x0016, pci_subsys_1011_0019_108d_0016, 0}; +#undef pci_ss_info_108d_0016 +#define pci_ss_info_108d_0016 pci_ss_info_1011_0019_108d_0016 +static const pciSubsystemInfo pci_ss_info_1011_0019_108d_0017 = + {0x108d, 0x0017, pci_subsys_1011_0019_108d_0017, 0}; +#undef pci_ss_info_108d_0017 +#define pci_ss_info_108d_0017 pci_ss_info_1011_0019_108d_0017 +static const pciSubsystemInfo pci_ss_info_1011_0019_10b8_2005 = + {0x10b8, 0x2005, pci_subsys_1011_0019_10b8_2005, 0}; +#undef pci_ss_info_10b8_2005 +#define pci_ss_info_10b8_2005 pci_ss_info_1011_0019_10b8_2005 +static const pciSubsystemInfo pci_ss_info_1011_0019_10b8_8034 = + {0x10b8, 0x8034, pci_subsys_1011_0019_10b8_8034, 0}; +#undef pci_ss_info_10b8_8034 +#define pci_ss_info_10b8_8034 pci_ss_info_1011_0019_10b8_8034 +static const pciSubsystemInfo pci_ss_info_1011_0019_10ef_8169 = + {0x10ef, 0x8169, pci_subsys_1011_0019_10ef_8169, 0}; +#undef pci_ss_info_10ef_8169 +#define pci_ss_info_10ef_8169 pci_ss_info_1011_0019_10ef_8169 +static const pciSubsystemInfo pci_ss_info_1011_0019_1109_2a00 = + {0x1109, 0x2a00, pci_subsys_1011_0019_1109_2a00, 0}; +#undef pci_ss_info_1109_2a00 +#define pci_ss_info_1109_2a00 pci_ss_info_1011_0019_1109_2a00 +static const pciSubsystemInfo pci_ss_info_1011_0019_1109_2b00 = + {0x1109, 0x2b00, pci_subsys_1011_0019_1109_2b00, 0}; +#undef pci_ss_info_1109_2b00 +#define pci_ss_info_1109_2b00 pci_ss_info_1011_0019_1109_2b00 +static const pciSubsystemInfo pci_ss_info_1011_0019_1109_3000 = + {0x1109, 0x3000, pci_subsys_1011_0019_1109_3000, 0}; +#undef pci_ss_info_1109_3000 +#define pci_ss_info_1109_3000 pci_ss_info_1011_0019_1109_3000 +static const pciSubsystemInfo pci_ss_info_1011_0019_1113_1207 = + {0x1113, 0x1207, pci_subsys_1011_0019_1113_1207, 0}; +#undef pci_ss_info_1113_1207 +#define pci_ss_info_1113_1207 pci_ss_info_1011_0019_1113_1207 +static const pciSubsystemInfo pci_ss_info_1011_0019_1113_2220 = + {0x1113, 0x2220, pci_subsys_1011_0019_1113_2220, 0}; +#undef pci_ss_info_1113_2220 +#define pci_ss_info_1113_2220 pci_ss_info_1011_0019_1113_2220 +static const pciSubsystemInfo pci_ss_info_1011_0019_115d_0002 = + {0x115d, 0x0002, pci_subsys_1011_0019_115d_0002, 0}; +#undef pci_ss_info_115d_0002 +#define pci_ss_info_115d_0002 pci_ss_info_1011_0019_115d_0002 +static const pciSubsystemInfo pci_ss_info_1011_0019_1179_0203 = + {0x1179, 0x0203, pci_subsys_1011_0019_1179_0203, 0}; +#undef pci_ss_info_1179_0203 +#define pci_ss_info_1179_0203 pci_ss_info_1011_0019_1179_0203 +static const pciSubsystemInfo pci_ss_info_1011_0019_1179_0204 = + {0x1179, 0x0204, pci_subsys_1011_0019_1179_0204, 0}; +#undef pci_ss_info_1179_0204 +#define pci_ss_info_1179_0204 pci_ss_info_1011_0019_1179_0204 +static const pciSubsystemInfo pci_ss_info_1011_0019_1186_1100 = + {0x1186, 0x1100, pci_subsys_1011_0019_1186_1100, 0}; +#undef pci_ss_info_1186_1100 +#define pci_ss_info_1186_1100 pci_ss_info_1011_0019_1186_1100 +static const pciSubsystemInfo pci_ss_info_1011_0019_1186_1101 = + {0x1186, 0x1101, pci_subsys_1011_0019_1186_1101, 0}; +#undef pci_ss_info_1186_1101 +#define pci_ss_info_1186_1101 pci_ss_info_1011_0019_1186_1101 +static const pciSubsystemInfo pci_ss_info_1011_0019_1186_1102 = + {0x1186, 0x1102, pci_subsys_1011_0019_1186_1102, 0}; +#undef pci_ss_info_1186_1102 +#define pci_ss_info_1186_1102 pci_ss_info_1011_0019_1186_1102 +static const pciSubsystemInfo pci_ss_info_1011_0019_1259_2800 = + {0x1259, 0x2800, pci_subsys_1011_0019_1259_2800, 0}; +#undef pci_ss_info_1259_2800 +#define pci_ss_info_1259_2800 pci_ss_info_1011_0019_1259_2800 +static const pciSubsystemInfo pci_ss_info_1011_0019_1266_0004 = + {0x1266, 0x0004, pci_subsys_1011_0019_1266_0004, 0}; +#undef pci_ss_info_1266_0004 +#define pci_ss_info_1266_0004 pci_ss_info_1011_0019_1266_0004 +static const pciSubsystemInfo pci_ss_info_1011_0019_12af_0019 = + {0x12af, 0x0019, pci_subsys_1011_0019_12af_0019, 0}; +#undef pci_ss_info_12af_0019 +#define pci_ss_info_12af_0019 pci_ss_info_1011_0019_12af_0019 +static const pciSubsystemInfo pci_ss_info_1011_0019_1374_0001 = + {0x1374, 0x0001, pci_subsys_1011_0019_1374_0001, 0}; +#undef pci_ss_info_1374_0001 +#define pci_ss_info_1374_0001 pci_ss_info_1011_0019_1374_0001 +static const pciSubsystemInfo pci_ss_info_1011_0019_1374_0002 = + {0x1374, 0x0002, pci_subsys_1011_0019_1374_0002, 0}; +#undef pci_ss_info_1374_0002 +#define pci_ss_info_1374_0002 pci_ss_info_1011_0019_1374_0002 +static const pciSubsystemInfo pci_ss_info_1011_0019_1374_0007 = + {0x1374, 0x0007, pci_subsys_1011_0019_1374_0007, 0}; +#undef pci_ss_info_1374_0007 +#define pci_ss_info_1374_0007 pci_ss_info_1011_0019_1374_0007 +static const pciSubsystemInfo pci_ss_info_1011_0019_1374_0008 = + {0x1374, 0x0008, pci_subsys_1011_0019_1374_0008, 0}; +#undef pci_ss_info_1374_0008 +#define pci_ss_info_1374_0008 pci_ss_info_1011_0019_1374_0008 +static const pciSubsystemInfo pci_ss_info_1011_0019_1385_2100 = + {0x1385, 0x2100, pci_subsys_1011_0019_1385_2100, 0}; +#undef pci_ss_info_1385_2100 +#define pci_ss_info_1385_2100 pci_ss_info_1011_0019_1385_2100 +static const pciSubsystemInfo pci_ss_info_1011_0019_1395_0001 = + {0x1395, 0x0001, pci_subsys_1011_0019_1395_0001, 0}; +#undef pci_ss_info_1395_0001 +#define pci_ss_info_1395_0001 pci_ss_info_1011_0019_1395_0001 +static const pciSubsystemInfo pci_ss_info_1011_0019_13d1_ab01 = + {0x13d1, 0xab01, pci_subsys_1011_0019_13d1_ab01, 0}; +#undef pci_ss_info_13d1_ab01 +#define pci_ss_info_13d1_ab01 pci_ss_info_1011_0019_13d1_ab01 +static const pciSubsystemInfo pci_ss_info_1011_0019_8086_0001 = + {0x8086, 0x0001, pci_subsys_1011_0019_8086_0001, 0}; +#undef pci_ss_info_8086_0001 +#define pci_ss_info_8086_0001 pci_ss_info_1011_0019_8086_0001 +static const pciSubsystemInfo pci_ss_info_1011_0034_1374_0003 = + {0x1374, 0x0003, pci_subsys_1011_0034_1374_0003, 0}; +#undef pci_ss_info_1374_0003 +#define pci_ss_info_1374_0003 pci_ss_info_1011_0034_1374_0003 +static const pciSubsystemInfo pci_ss_info_1011_0046_0e11_4050 = + {0x0e11, 0x4050, pci_subsys_1011_0046_0e11_4050, 0}; +#undef pci_ss_info_0e11_4050 +#define pci_ss_info_0e11_4050 pci_ss_info_1011_0046_0e11_4050 +static const pciSubsystemInfo pci_ss_info_1011_0046_0e11_4051 = + {0x0e11, 0x4051, pci_subsys_1011_0046_0e11_4051, 0}; +#undef pci_ss_info_0e11_4051 +#define pci_ss_info_0e11_4051 pci_ss_info_1011_0046_0e11_4051 +static const pciSubsystemInfo pci_ss_info_1011_0046_0e11_4058 = + {0x0e11, 0x4058, pci_subsys_1011_0046_0e11_4058, 0}; +#undef pci_ss_info_0e11_4058 +#define pci_ss_info_0e11_4058 pci_ss_info_1011_0046_0e11_4058 +static const pciSubsystemInfo pci_ss_info_1011_0046_103c_10c2 = + {0x103c, 0x10c2, pci_subsys_1011_0046_103c_10c2, 0}; +#undef pci_ss_info_103c_10c2 +#define pci_ss_info_103c_10c2 pci_ss_info_1011_0046_103c_10c2 +static const pciSubsystemInfo pci_ss_info_1011_0046_12d9_000a = + {0x12d9, 0x000a, pci_subsys_1011_0046_12d9_000a, 0}; +#undef pci_ss_info_12d9_000a +#define pci_ss_info_12d9_000a pci_ss_info_1011_0046_12d9_000a +static const pciSubsystemInfo pci_ss_info_1011_0046_9005_0365 = + {0x9005, 0x0365, pci_subsys_1011_0046_9005_0365, 0}; +#undef pci_ss_info_9005_0365 +#define pci_ss_info_9005_0365 pci_ss_info_1011_0046_9005_0365 +static const pciSubsystemInfo pci_ss_info_1011_0046_9005_1364 = + {0x9005, 0x1364, pci_subsys_1011_0046_9005_1364, 0}; +#undef pci_ss_info_9005_1364 +#define pci_ss_info_9005_1364 pci_ss_info_1011_0046_9005_1364 +static const pciSubsystemInfo pci_ss_info_1011_0046_9005_1365 = + {0x9005, 0x1365, pci_subsys_1011_0046_9005_1365, 0}; +#undef pci_ss_info_9005_1365 +#define pci_ss_info_9005_1365 pci_ss_info_1011_0046_9005_1365 +static const pciSubsystemInfo pci_ss_info_1011_0046_e4bf_1000 = + {0xe4bf, 0x1000, pci_subsys_1011_0046_e4bf_1000, 0}; +#undef pci_ss_info_e4bf_1000 +#define pci_ss_info_e4bf_1000 pci_ss_info_1011_0046_e4bf_1000 +static const pciSubsystemInfo pci_ss_info_1011_1065_1069_0020 = + {0x1069, 0x0020, pci_subsys_1011_1065_1069_0020, 0}; +#undef pci_ss_info_1069_0020 +#define pci_ss_info_1069_0020 pci_ss_info_1011_1065_1069_0020 +static const pciSubsystemInfo pci_ss_info_1013_00bc_1013_00bc = + {0x1013, 0x00bc, pci_subsys_1013_00bc_1013_00bc, 0}; +#undef pci_ss_info_1013_00bc +#define pci_ss_info_1013_00bc pci_ss_info_1013_00bc_1013_00bc +static const pciSubsystemInfo pci_ss_info_1013_00d6_13ce_8031 = + {0x13ce, 0x8031, pci_subsys_1013_00d6_13ce_8031, 0}; +#undef pci_ss_info_13ce_8031 +#define pci_ss_info_13ce_8031 pci_ss_info_1013_00d6_13ce_8031 +static const pciSubsystemInfo pci_ss_info_1013_00d6_13cf_8031 = + {0x13cf, 0x8031, pci_subsys_1013_00d6_13cf_8031, 0}; +#undef pci_ss_info_13cf_8031 +#define pci_ss_info_13cf_8031 pci_ss_info_1013_00d6_13cf_8031 +static const pciSubsystemInfo pci_ss_info_1013_6001_1014_1010 = + {0x1014, 0x1010, pci_subsys_1013_6001_1014_1010, 0}; +#undef pci_ss_info_1014_1010 +#define pci_ss_info_1014_1010 pci_ss_info_1013_6001_1014_1010 +static const pciSubsystemInfo pci_ss_info_1013_6003_1013_4280 = + {0x1013, 0x4280, pci_subsys_1013_6003_1013_4280, 0}; +#undef pci_ss_info_1013_4280 +#define pci_ss_info_1013_4280 pci_ss_info_1013_6003_1013_4280 +static const pciSubsystemInfo pci_ss_info_1013_6003_1681_0050 = + {0x1681, 0x0050, pci_subsys_1013_6003_1681_0050, 0}; +#undef pci_ss_info_1681_0050 +#define pci_ss_info_1681_0050 pci_ss_info_1013_6003_1681_0050 +static const pciSubsystemInfo pci_ss_info_1013_6003_1681_a011 = + {0x1681, 0xa011, pci_subsys_1013_6003_1681_a011, 0}; +#undef pci_ss_info_1681_a011 +#define pci_ss_info_1681_a011 pci_ss_info_1013_6003_1681_a011 +static const pciSubsystemInfo pci_ss_info_1013_6005_1013_4281 = + {0x1013, 0x4281, pci_subsys_1013_6005_1013_4281, 0}; +#undef pci_ss_info_1013_4281 +#define pci_ss_info_1013_4281 pci_ss_info_1013_6005_1013_4281 +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10a8 = + {0x10cf, 0x10a8, pci_subsys_1013_6005_10cf_10a8, 0}; +#undef pci_ss_info_10cf_10a8 +#define pci_ss_info_10cf_10a8 pci_ss_info_1013_6005_10cf_10a8 +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10a9 = + {0x10cf, 0x10a9, pci_subsys_1013_6005_10cf_10a9, 0}; +#undef pci_ss_info_10cf_10a9 +#define pci_ss_info_10cf_10a9 pci_ss_info_1013_6005_10cf_10a9 +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10aa = + {0x10cf, 0x10aa, pci_subsys_1013_6005_10cf_10aa, 0}; +#undef pci_ss_info_10cf_10aa +#define pci_ss_info_10cf_10aa pci_ss_info_1013_6005_10cf_10aa +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10ab = + {0x10cf, 0x10ab, pci_subsys_1013_6005_10cf_10ab, 0}; +#undef pci_ss_info_10cf_10ab +#define pci_ss_info_10cf_10ab pci_ss_info_1013_6005_10cf_10ab +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10ac = + {0x10cf, 0x10ac, pci_subsys_1013_6005_10cf_10ac, 0}; +#undef pci_ss_info_10cf_10ac +#define pci_ss_info_10cf_10ac pci_ss_info_1013_6005_10cf_10ac +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10ad = + {0x10cf, 0x10ad, pci_subsys_1013_6005_10cf_10ad, 0}; +#undef pci_ss_info_10cf_10ad +#define pci_ss_info_10cf_10ad pci_ss_info_1013_6005_10cf_10ad +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10b4 = + {0x10cf, 0x10b4, pci_subsys_1013_6005_10cf_10b4, 0}; +#undef pci_ss_info_10cf_10b4 +#define pci_ss_info_10cf_10b4 pci_ss_info_1013_6005_10cf_10b4 +static const pciSubsystemInfo pci_ss_info_1013_6005_1179_0001 = + {0x1179, 0x0001, pci_subsys_1013_6005_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1013_6005_1179_0001 +static const pciSubsystemInfo pci_ss_info_1013_6005_14c0_000c = + {0x14c0, 0x000c, pci_subsys_1013_6005_14c0_000c, 0}; +#undef pci_ss_info_14c0_000c +#define pci_ss_info_14c0_000c pci_ss_info_1013_6005_14c0_000c +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1014_002e_1014_002e = + {0x1014, 0x002e, pci_subsys_1014_002e_1014_002e, 0}; +#undef pci_ss_info_1014_002e +#define pci_ss_info_1014_002e pci_ss_info_1014_002e_1014_002e +static const pciSubsystemInfo pci_ss_info_1014_002e_1014_022e = + {0x1014, 0x022e, pci_subsys_1014_002e_1014_022e, 0}; +#undef pci_ss_info_1014_022e +#define pci_ss_info_1014_022e pci_ss_info_1014_002e_1014_022e +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_003e = + {0x1014, 0x003e, pci_subsys_1014_003e_1014_003e, 0}; +#undef pci_ss_info_1014_003e +#define pci_ss_info_1014_003e pci_ss_info_1014_003e_1014_003e +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00cd = + {0x1014, 0x00cd, pci_subsys_1014_003e_1014_00cd, 0}; +#undef pci_ss_info_1014_00cd +#define pci_ss_info_1014_00cd pci_ss_info_1014_003e_1014_00cd +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00ce = + {0x1014, 0x00ce, pci_subsys_1014_003e_1014_00ce, 0}; +#undef pci_ss_info_1014_00ce +#define pci_ss_info_1014_00ce pci_ss_info_1014_003e_1014_00ce +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00cf = + {0x1014, 0x00cf, pci_subsys_1014_003e_1014_00cf, 0}; +#undef pci_ss_info_1014_00cf +#define pci_ss_info_1014_00cf pci_ss_info_1014_003e_1014_00cf +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00e4 = + {0x1014, 0x00e4, pci_subsys_1014_003e_1014_00e4, 0}; +#undef pci_ss_info_1014_00e4 +#define pci_ss_info_1014_00e4 pci_ss_info_1014_003e_1014_00e4 +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00e5 = + {0x1014, 0x00e5, pci_subsys_1014_003e_1014_00e5, 0}; +#undef pci_ss_info_1014_00e5 +#define pci_ss_info_1014_00e5 pci_ss_info_1014_003e_1014_00e5 +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_016d = + {0x1014, 0x016d, pci_subsys_1014_003e_1014_016d, 0}; +#undef pci_ss_info_1014_016d +#define pci_ss_info_1014_016d pci_ss_info_1014_003e_1014_016d +static const pciSubsystemInfo pci_ss_info_1014_0090_1014_008e = + {0x1014, 0x008e, pci_subsys_1014_0090_1014_008e, 0}; +#undef pci_ss_info_1014_008e +#define pci_ss_info_1014_008e pci_ss_info_1014_0090_1014_008e +static const pciSubsystemInfo pci_ss_info_1014_0096_1014_0097 = + {0x1014, 0x0097, pci_subsys_1014_0096_1014_0097, 0}; +#undef pci_ss_info_1014_0097 +#define pci_ss_info_1014_0097 pci_ss_info_1014_0096_1014_0097 +static const pciSubsystemInfo pci_ss_info_1014_0096_1014_0098 = + {0x1014, 0x0098, pci_subsys_1014_0096_1014_0098, 0}; +#undef pci_ss_info_1014_0098 +#define pci_ss_info_1014_0098 pci_ss_info_1014_0096_1014_0098 +static const pciSubsystemInfo pci_ss_info_1014_0096_1014_0099 = + {0x1014, 0x0099, pci_subsys_1014_0096_1014_0099, 0}; +#undef pci_ss_info_1014_0099 +#define pci_ss_info_1014_0099 pci_ss_info_1014_0096_1014_0099 +static const pciSubsystemInfo pci_ss_info_1014_0142_1014_0143 = + {0x1014, 0x0143, pci_subsys_1014_0142_1014_0143, 0}; +#undef pci_ss_info_1014_0143 +#define pci_ss_info_1014_0143 pci_ss_info_1014_0142_1014_0143 +static const pciSubsystemInfo pci_ss_info_1014_0144_1014_0145 = + {0x1014, 0x0145, pci_subsys_1014_0144_1014_0145, 0}; +#undef pci_ss_info_1014_0145 +#define pci_ss_info_1014_0145 pci_ss_info_1014_0144_1014_0145 +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_01be = + {0x1014, 0x01be, pci_subsys_1014_01bd_1014_01be, 0}; +#undef pci_ss_info_1014_01be +#define pci_ss_info_1014_01be pci_ss_info_1014_01bd_1014_01be +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_01bf = + {0x1014, 0x01bf, pci_subsys_1014_01bd_1014_01bf, 0}; +#undef pci_ss_info_1014_01bf +#define pci_ss_info_1014_01bf pci_ss_info_1014_01bd_1014_01bf +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_0208 = + {0x1014, 0x0208, pci_subsys_1014_01bd_1014_0208, 0}; +#undef pci_ss_info_1014_0208 +#define pci_ss_info_1014_0208 pci_ss_info_1014_01bd_1014_0208 +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_020e = + {0x1014, 0x020e, pci_subsys_1014_01bd_1014_020e, 0}; +#undef pci_ss_info_1014_020e +#define pci_ss_info_1014_020e pci_ss_info_1014_01bd_1014_020e +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_022e = + {0x1014, 0x022e, pci_subsys_1014_01bd_1014_022e, 0}; +#undef pci_ss_info_1014_022e +#define pci_ss_info_1014_022e pci_ss_info_1014_01bd_1014_022e +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_0258 = + {0x1014, 0x0258, pci_subsys_1014_01bd_1014_0258, 0}; +#undef pci_ss_info_1014_0258 +#define pci_ss_info_1014_0258 pci_ss_info_1014_01bd_1014_0258 +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_0259 = + {0x1014, 0x0259, pci_subsys_1014_01bd_1014_0259, 0}; +#undef pci_ss_info_1014_0259 +#define pci_ss_info_1014_0259 pci_ss_info_1014_01bd_1014_0259 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0471 = + {0x101e, 0x0471, pci_subsys_101e_1960_101e_0471, 0}; +#undef pci_ss_info_101e_0471 +#define pci_ss_info_101e_0471 pci_ss_info_101e_1960_101e_0471 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0475 = + {0x101e, 0x0475, pci_subsys_101e_1960_101e_0475, 0}; +#undef pci_ss_info_101e_0475 +#define pci_ss_info_101e_0475 pci_ss_info_101e_1960_101e_0475 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0493 = + {0x101e, 0x0493, pci_subsys_101e_1960_101e_0493, 0}; +#undef pci_ss_info_101e_0493 +#define pci_ss_info_101e_0493 pci_ss_info_101e_1960_101e_0493 +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_1028_0471 = + {0x1028, 0x0471, pci_subsys_101e_1960_1028_0471, 0}; +#undef pci_ss_info_1028_0471 +#define pci_ss_info_1028_0471 pci_ss_info_101e_1960_1028_0471 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_1028_0475 = + {0x1028, 0x0475, pci_subsys_101e_1960_1028_0475, 0}; +#undef pci_ss_info_1028_0475 +#define pci_ss_info_1028_0475 pci_ss_info_101e_1960_1028_0475 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_1028_0493 = + {0x1028, 0x0493, pci_subsys_101e_1960_1028_0493, 0}; +#undef pci_ss_info_1028_0493 +#define pci_ss_info_1028_0493 pci_ss_info_101e_1960_1028_0493 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_1028_0511 = + {0x1028, 0x0511, pci_subsys_101e_1960_1028_0511, 0}; +#undef pci_ss_info_1028_0511 +#define pci_ss_info_1028_0511 pci_ss_info_101e_1960_1028_0511 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_101e_9063_101e_0767 = + {0x101e, 0x0767, pci_subsys_101e_9063_101e_0767, 0}; +#undef pci_ss_info_101e_0767 +#define pci_ss_info_101e_0767 pci_ss_info_101e_9063_101e_0767 +#endif +static const pciSubsystemInfo pci_ss_info_1022_2000_1014_2000 = + {0x1014, 0x2000, pci_subsys_1022_2000_1014_2000, 0}; +#undef pci_ss_info_1014_2000 +#define pci_ss_info_1014_2000 pci_ss_info_1022_2000_1014_2000 +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_104c = + {0x103c, 0x104c, pci_subsys_1022_2000_103c_104c, 0}; +#undef pci_ss_info_103c_104c +#define pci_ss_info_103c_104c pci_ss_info_1022_2000_103c_104c +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_1064 = + {0x103c, 0x1064, pci_subsys_1022_2000_103c_1064, 0}; +#undef pci_ss_info_103c_1064 +#define pci_ss_info_103c_1064 pci_ss_info_1022_2000_103c_1064 +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_1065 = + {0x103c, 0x1065, pci_subsys_1022_2000_103c_1065, 0}; +#undef pci_ss_info_103c_1065 +#define pci_ss_info_103c_1065 pci_ss_info_1022_2000_103c_1065 +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_106c = + {0x103c, 0x106c, pci_subsys_1022_2000_103c_106c, 0}; +#undef pci_ss_info_103c_106c +#define pci_ss_info_103c_106c pci_ss_info_1022_2000_103c_106c +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_106e = + {0x103c, 0x106e, pci_subsys_1022_2000_103c_106e, 0}; +#undef pci_ss_info_103c_106e +#define pci_ss_info_103c_106e pci_ss_info_1022_2000_103c_106e +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_10ea = + {0x103c, 0x10ea, pci_subsys_1022_2000_103c_10ea, 0}; +#undef pci_ss_info_103c_10ea +#define pci_ss_info_103c_10ea pci_ss_info_1022_2000_103c_10ea +static const pciSubsystemInfo pci_ss_info_1022_2000_1113_1220 = + {0x1113, 0x1220, pci_subsys_1022_2000_1113_1220, 0}; +#undef pci_ss_info_1113_1220 +#define pci_ss_info_1113_1220 pci_ss_info_1022_2000_1113_1220 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2450 = + {0x1259, 0x2450, pci_subsys_1022_2000_1259_2450, 0}; +#undef pci_ss_info_1259_2450 +#define pci_ss_info_1259_2450 pci_ss_info_1022_2000_1259_2450 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2454 = + {0x1259, 0x2454, pci_subsys_1022_2000_1259_2454, 0}; +#undef pci_ss_info_1259_2454 +#define pci_ss_info_1259_2454 pci_ss_info_1022_2000_1259_2454 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2700 = + {0x1259, 0x2700, pci_subsys_1022_2000_1259_2700, 0}; +#undef pci_ss_info_1259_2700 +#define pci_ss_info_1259_2700 pci_ss_info_1022_2000_1259_2700 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2701 = + {0x1259, 0x2701, pci_subsys_1022_2000_1259_2701, 0}; +#undef pci_ss_info_1259_2701 +#define pci_ss_info_1259_2701 pci_ss_info_1022_2000_1259_2701 +static const pciSubsystemInfo pci_ss_info_1022_2001_1092_0a78 = + {0x1092, 0x0a78, pci_subsys_1022_2001_1092_0a78, 0}; +#undef pci_ss_info_1092_0a78 +#define pci_ss_info_1092_0a78 pci_ss_info_1022_2001_1092_0a78 +static const pciSubsystemInfo pci_ss_info_1022_2001_1668_0299 = + {0x1668, 0x0299, pci_subsys_1022_2001_1668_0299, 0}; +#undef pci_ss_info_1668_0299 +#define pci_ss_info_1668_0299 pci_ss_info_1022_2001_1668_0299 +static const pciSubsystemInfo pci_ss_info_1022_7440_1043_8044 = + {0x1043, 0x8044, pci_subsys_1022_7440_1043_8044, 0}; +#undef pci_ss_info_1043_8044 +#define pci_ss_info_1043_8044 pci_ss_info_1022_7440_1043_8044 +static const pciSubsystemInfo pci_ss_info_1022_7443_1043_8044 = + {0x1043, 0x8044, pci_subsys_1022_7443_1043_8044, 0}; +#undef pci_ss_info_1043_8044 +#define pci_ss_info_1043_8044 pci_ss_info_1022_7443_1043_8044 +static const pciSubsystemInfo pci_ss_info_1023_8400_1023_8400 = + {0x1023, 0x8400, pci_subsys_1023_8400_1023_8400, 0}; +#undef pci_ss_info_1023_8400 +#define pci_ss_info_1023_8400 pci_ss_info_1023_8400_1023_8400 +static const pciSubsystemInfo pci_ss_info_1023_8420_0e11_b15a = + {0x0e11, 0xb15a, pci_subsys_1023_8420_0e11_b15a, 0}; +#undef pci_ss_info_0e11_b15a +#define pci_ss_info_0e11_b15a pci_ss_info_1023_8420_0e11_b15a +static const pciSubsystemInfo pci_ss_info_1023_8520_0e11_b16e = + {0x0e11, 0xb16e, pci_subsys_1023_8520_0e11_b16e, 0}; +#undef pci_ss_info_0e11_b16e +#define pci_ss_info_0e11_b16e pci_ss_info_1023_8520_0e11_b16e +static const pciSubsystemInfo pci_ss_info_1023_8520_1023_8520 = + {0x1023, 0x8520, pci_subsys_1023_8520_1023_8520, 0}; +#undef pci_ss_info_1023_8520 +#define pci_ss_info_1023_8520 pci_ss_info_1023_8520_1023_8520 +static const pciSubsystemInfo pci_ss_info_1023_8620_1014_0502 = + {0x1014, 0x0502, pci_subsys_1023_8620_1014_0502, 0}; +#undef pci_ss_info_1014_0502 +#define pci_ss_info_1014_0502 pci_ss_info_1023_8620_1014_0502 +static const pciSubsystemInfo pci_ss_info_1023_9525_10cf_1094 = + {0x10cf, 0x1094, pci_subsys_1023_9525_10cf_1094, 0}; +#undef pci_ss_info_10cf_1094 +#define pci_ss_info_10cf_1094 pci_ss_info_1023_9525_10cf_1094 +static const pciSubsystemInfo pci_ss_info_1023_9750_1014_9750 = + {0x1014, 0x9750, pci_subsys_1023_9750_1014_9750, 0}; +#undef pci_ss_info_1014_9750 +#define pci_ss_info_1014_9750 pci_ss_info_1023_9750_1014_9750 +static const pciSubsystemInfo pci_ss_info_1023_9750_1023_9750 = + {0x1023, 0x9750, pci_subsys_1023_9750_1023_9750, 0}; +#undef pci_ss_info_1023_9750 +#define pci_ss_info_1023_9750 pci_ss_info_1023_9750_1023_9750 +static const pciSubsystemInfo pci_ss_info_1023_9880_1023_9880 = + {0x1023, 0x9880, pci_subsys_1023_9880_1023_9880, 0}; +#undef pci_ss_info_1023_9880 +#define pci_ss_info_1023_9880 pci_ss_info_1023_9880_1023_9880 +static const pciSubsystemInfo pci_ss_info_1025_1521_10b9_1521 = + {0x10b9, 0x1521, pci_subsys_1025_1521_10b9_1521, 0}; +#undef pci_ss_info_10b9_1521 +#define pci_ss_info_10b9_1521 pci_ss_info_1025_1521_10b9_1521 +static const pciSubsystemInfo pci_ss_info_1025_1523_10b9_1523 = + {0x10b9, 0x1523, pci_subsys_1025_1523_10b9_1523, 0}; +#undef pci_ss_info_10b9_1523 +#define pci_ss_info_10b9_1523 pci_ss_info_1025_1523_10b9_1523 +static const pciSubsystemInfo pci_ss_info_1025_1533_10b9_1533 = + {0x10b9, 0x1533, pci_subsys_1025_1533_10b9_1533, 0}; +#undef pci_ss_info_10b9_1533 +#define pci_ss_info_10b9_1533 pci_ss_info_1025_1533_10b9_1533 +static const pciSubsystemInfo pci_ss_info_1025_1541_10b9_1541 = + {0x10b9, 0x1541, pci_subsys_1025_1541_10b9_1541, 0}; +#undef pci_ss_info_10b9_1541 +#define pci_ss_info_10b9_1541 pci_ss_info_1025_1541_10b9_1541 +static const pciSubsystemInfo pci_ss_info_1025_7101_10b9_7101 = + {0x10b9, 0x7101, pci_subsys_1025_7101_10b9_7101, 0}; +#undef pci_ss_info_10b9_7101 +#define pci_ss_info_10b9_7101 pci_ss_info_1025_7101_10b9_7101 +static const pciSubsystemInfo pci_ss_info_1028_0001_1028_0001 = + {0x1028, 0x0001, pci_subsys_1028_0001_1028_0001, 0}; +#undef pci_ss_info_1028_0001 +#define pci_ss_info_1028_0001 pci_ss_info_1028_0001_1028_0001 +static const pciSubsystemInfo pci_ss_info_1028_0002_1028_0002 = + {0x1028, 0x0002, pci_subsys_1028_0002_1028_0002, 0}; +#undef pci_ss_info_1028_0002 +#define pci_ss_info_1028_0002 pci_ss_info_1028_0002_1028_0002 +static const pciSubsystemInfo pci_ss_info_1028_0002_1028_00d1 = + {0x1028, 0x00d1, pci_subsys_1028_0002_1028_00d1, 0}; +#undef pci_ss_info_1028_00d1 +#define pci_ss_info_1028_00d1 pci_ss_info_1028_0002_1028_00d1 +static const pciSubsystemInfo pci_ss_info_1028_0002_1028_00d9 = + {0x1028, 0x00d9, pci_subsys_1028_0002_1028_00d9, 0}; +#undef pci_ss_info_1028_00d9 +#define pci_ss_info_1028_00d9 pci_ss_info_1028_0002_1028_00d9 +static const pciSubsystemInfo pci_ss_info_1028_0003_1028_0003 = + {0x1028, 0x0003, pci_subsys_1028_0003_1028_0003, 0}; +#undef pci_ss_info_1028_0003 +#define pci_ss_info_1028_0003 pci_ss_info_1028_0003_1028_0003 +static const pciSubsystemInfo pci_ss_info_1028_0004_1028_00d0 = + {0x1028, 0x00d0, pci_subsys_1028_0004_1028_00d0, 0}; +#undef pci_ss_info_1028_00d0 +#define pci_ss_info_1028_00d0 pci_ss_info_1028_0004_1028_00d0 +static const pciSubsystemInfo pci_ss_info_1028_000a_1028_0106 = + {0x1028, 0x0106, pci_subsys_1028_000a_1028_0106, 0}; +#undef pci_ss_info_1028_0106 +#define pci_ss_info_1028_0106 pci_ss_info_1028_000a_1028_0106 +static const pciSubsystemInfo pci_ss_info_1028_000a_1028_011b = + {0x1028, 0x011b, pci_subsys_1028_000a_1028_011b, 0}; +#undef pci_ss_info_1028_011b +#define pci_ss_info_1028_011b pci_ss_info_1028_000a_1028_011b +static const pciSubsystemInfo pci_ss_info_1028_000a_1028_0121 = + {0x1028, 0x0121, pci_subsys_1028_000a_1028_0121, 0}; +#undef pci_ss_info_1028_0121 +#define pci_ss_info_1028_0121 pci_ss_info_1028_000a_1028_0121 +static const pciSubsystemInfo pci_ss_info_102b_051a_102b_0100 = + {0x102b, 0x0100, pci_subsys_102b_051a_102b_0100, 0}; +#undef pci_ss_info_102b_0100 +#define pci_ss_info_102b_0100 pci_ss_info_102b_051a_102b_0100 +static const pciSubsystemInfo pci_ss_info_102b_051a_102b_1100 = + {0x102b, 0x1100, pci_subsys_102b_051a_102b_1100, 0}; +#undef pci_ss_info_102b_1100 +#define pci_ss_info_102b_1100 pci_ss_info_102b_051a_102b_1100 +static const pciSubsystemInfo pci_ss_info_102b_051a_102b_1200 = + {0x102b, 0x1200, pci_subsys_102b_051a_102b_1200, 0}; +#undef pci_ss_info_102b_1200 +#define pci_ss_info_102b_1200 pci_ss_info_102b_051a_102b_1200 +static const pciSubsystemInfo pci_ss_info_102b_051a_1100_102b = + {0x1100, 0x102b, pci_subsys_102b_051a_1100_102b, 0}; +#undef pci_ss_info_1100_102b +#define pci_ss_info_1100_102b pci_ss_info_102b_051a_1100_102b +static const pciSubsystemInfo pci_ss_info_102b_051a_110a_0018 = + {0x110a, 0x0018, pci_subsys_102b_051a_110a_0018, 0}; +#undef pci_ss_info_110a_0018 +#define pci_ss_info_110a_0018 pci_ss_info_102b_051a_110a_0018 +static const pciSubsystemInfo pci_ss_info_102b_051b_102b_051b = + {0x102b, 0x051b, pci_subsys_102b_051b_102b_051b, 0}; +#undef pci_ss_info_102b_051b +#define pci_ss_info_102b_051b pci_ss_info_102b_051b_102b_051b +static const pciSubsystemInfo pci_ss_info_102b_051b_102b_1100 = + {0x102b, 0x1100, pci_subsys_102b_051b_102b_1100, 0}; +#undef pci_ss_info_102b_1100 +#define pci_ss_info_102b_1100 pci_ss_info_102b_051b_102b_1100 +static const pciSubsystemInfo pci_ss_info_102b_051b_102b_1200 = + {0x102b, 0x1200, pci_subsys_102b_051b_102b_1200, 0}; +#undef pci_ss_info_102b_1200 +#define pci_ss_info_102b_1200 pci_ss_info_102b_051b_102b_1200 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_dbc2 = + {0x102b, 0xdbc2, pci_subsys_102b_0520_102b_dbc2, 0}; +#undef pci_ss_info_102b_dbc2 +#define pci_ss_info_102b_dbc2 pci_ss_info_102b_0520_102b_dbc2 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_dbc8 = + {0x102b, 0xdbc8, pci_subsys_102b_0520_102b_dbc8, 0}; +#undef pci_ss_info_102b_dbc8 +#define pci_ss_info_102b_dbc8 pci_ss_info_102b_0520_102b_dbc8 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_dbe2 = + {0x102b, 0xdbe2, pci_subsys_102b_0520_102b_dbe2, 0}; +#undef pci_ss_info_102b_dbe2 +#define pci_ss_info_102b_dbe2 pci_ss_info_102b_0520_102b_dbe2 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_dbe8 = + {0x102b, 0xdbe8, pci_subsys_102b_0520_102b_dbe8, 0}; +#undef pci_ss_info_102b_dbe8 +#define pci_ss_info_102b_dbe8 pci_ss_info_102b_0520_102b_dbe8 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_ff03 = + {0x102b, 0xff03, pci_subsys_102b_0520_102b_ff03, 0}; +#undef pci_ss_info_102b_ff03 +#define pci_ss_info_102b_ff03 pci_ss_info_102b_0520_102b_ff03 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_ff04 = + {0x102b, 0xff04, pci_subsys_102b_0520_102b_ff04, 0}; +#undef pci_ss_info_102b_ff04 +#define pci_ss_info_102b_ff04 pci_ss_info_102b_0520_102b_ff04 +static const pciSubsystemInfo pci_ss_info_102b_0521_1014_ff03 = + {0x1014, 0xff03, pci_subsys_102b_0521_1014_ff03, 0}; +#undef pci_ss_info_1014_ff03 +#define pci_ss_info_1014_ff03 pci_ss_info_102b_0521_1014_ff03 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_48e9 = + {0x102b, 0x48e9, pci_subsys_102b_0521_102b_48e9, 0}; +#undef pci_ss_info_102b_48e9 +#define pci_ss_info_102b_48e9 pci_ss_info_102b_0521_102b_48e9 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_48f8 = + {0x102b, 0x48f8, pci_subsys_102b_0521_102b_48f8, 0}; +#undef pci_ss_info_102b_48f8 +#define pci_ss_info_102b_48f8 pci_ss_info_102b_0521_102b_48f8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_4a60 = + {0x102b, 0x4a60, pci_subsys_102b_0521_102b_4a60, 0}; +#undef pci_ss_info_102b_4a60 +#define pci_ss_info_102b_4a60 pci_ss_info_102b_0521_102b_4a60 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_4a64 = + {0x102b, 0x4a64, pci_subsys_102b_0521_102b_4a64, 0}; +#undef pci_ss_info_102b_4a64 +#define pci_ss_info_102b_4a64 pci_ss_info_102b_0521_102b_4a64 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_c93c = + {0x102b, 0xc93c, pci_subsys_102b_0521_102b_c93c, 0}; +#undef pci_ss_info_102b_c93c +#define pci_ss_info_102b_c93c pci_ss_info_102b_0521_102b_c93c +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_c9b0 = + {0x102b, 0xc9b0, pci_subsys_102b_0521_102b_c9b0, 0}; +#undef pci_ss_info_102b_c9b0 +#define pci_ss_info_102b_c9b0 pci_ss_info_102b_0521_102b_c9b0 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_c9bc = + {0x102b, 0xc9bc, pci_subsys_102b_0521_102b_c9bc, 0}; +#undef pci_ss_info_102b_c9bc +#define pci_ss_info_102b_c9bc pci_ss_info_102b_0521_102b_c9bc +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ca60 = + {0x102b, 0xca60, pci_subsys_102b_0521_102b_ca60, 0}; +#undef pci_ss_info_102b_ca60 +#define pci_ss_info_102b_ca60 pci_ss_info_102b_0521_102b_ca60 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ca6c = + {0x102b, 0xca6c, pci_subsys_102b_0521_102b_ca6c, 0}; +#undef pci_ss_info_102b_ca6c +#define pci_ss_info_102b_ca6c pci_ss_info_102b_0521_102b_ca6c +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbbc = + {0x102b, 0xdbbc, pci_subsys_102b_0521_102b_dbbc, 0}; +#undef pci_ss_info_102b_dbbc +#define pci_ss_info_102b_dbbc pci_ss_info_102b_0521_102b_dbbc +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbc2 = + {0x102b, 0xdbc2, pci_subsys_102b_0521_102b_dbc2, 0}; +#undef pci_ss_info_102b_dbc2 +#define pci_ss_info_102b_dbc2 pci_ss_info_102b_0521_102b_dbc2 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbc3 = + {0x102b, 0xdbc3, pci_subsys_102b_0521_102b_dbc3, 0}; +#undef pci_ss_info_102b_dbc3 +#define pci_ss_info_102b_dbc3 pci_ss_info_102b_0521_102b_dbc3 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbc8 = + {0x102b, 0xdbc8, pci_subsys_102b_0521_102b_dbc8, 0}; +#undef pci_ss_info_102b_dbc8 +#define pci_ss_info_102b_dbc8 pci_ss_info_102b_0521_102b_dbc8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd2 = + {0x102b, 0xdbd2, pci_subsys_102b_0521_102b_dbd2, 0}; +#undef pci_ss_info_102b_dbd2 +#define pci_ss_info_102b_dbd2 pci_ss_info_102b_0521_102b_dbd2 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd3 = + {0x102b, 0xdbd3, pci_subsys_102b_0521_102b_dbd3, 0}; +#undef pci_ss_info_102b_dbd3 +#define pci_ss_info_102b_dbd3 pci_ss_info_102b_0521_102b_dbd3 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd4 = + {0x102b, 0xdbd4, pci_subsys_102b_0521_102b_dbd4, 0}; +#undef pci_ss_info_102b_dbd4 +#define pci_ss_info_102b_dbd4 pci_ss_info_102b_0521_102b_dbd4 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd5 = + {0x102b, 0xdbd5, pci_subsys_102b_0521_102b_dbd5, 0}; +#undef pci_ss_info_102b_dbd5 +#define pci_ss_info_102b_dbd5 pci_ss_info_102b_0521_102b_dbd5 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd8 = + {0x102b, 0xdbd8, pci_subsys_102b_0521_102b_dbd8, 0}; +#undef pci_ss_info_102b_dbd8 +#define pci_ss_info_102b_dbd8 pci_ss_info_102b_0521_102b_dbd8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd9 = + {0x102b, 0xdbd9, pci_subsys_102b_0521_102b_dbd9, 0}; +#undef pci_ss_info_102b_dbd9 +#define pci_ss_info_102b_dbd9 pci_ss_info_102b_0521_102b_dbd9 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbe2 = + {0x102b, 0xdbe2, pci_subsys_102b_0521_102b_dbe2, 0}; +#undef pci_ss_info_102b_dbe2 +#define pci_ss_info_102b_dbe2 pci_ss_info_102b_0521_102b_dbe2 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbe3 = + {0x102b, 0xdbe3, pci_subsys_102b_0521_102b_dbe3, 0}; +#undef pci_ss_info_102b_dbe3 +#define pci_ss_info_102b_dbe3 pci_ss_info_102b_0521_102b_dbe3 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbe8 = + {0x102b, 0xdbe8, pci_subsys_102b_0521_102b_dbe8, 0}; +#undef pci_ss_info_102b_dbe8 +#define pci_ss_info_102b_dbe8 pci_ss_info_102b_0521_102b_dbe8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf2 = + {0x102b, 0xdbf2, pci_subsys_102b_0521_102b_dbf2, 0}; +#undef pci_ss_info_102b_dbf2 +#define pci_ss_info_102b_dbf2 pci_ss_info_102b_0521_102b_dbf2 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf3 = + {0x102b, 0xdbf3, pci_subsys_102b_0521_102b_dbf3, 0}; +#undef pci_ss_info_102b_dbf3 +#define pci_ss_info_102b_dbf3 pci_ss_info_102b_0521_102b_dbf3 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf4 = + {0x102b, 0xdbf4, pci_subsys_102b_0521_102b_dbf4, 0}; +#undef pci_ss_info_102b_dbf4 +#define pci_ss_info_102b_dbf4 pci_ss_info_102b_0521_102b_dbf4 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf5 = + {0x102b, 0xdbf5, pci_subsys_102b_0521_102b_dbf5, 0}; +#undef pci_ss_info_102b_dbf5 +#define pci_ss_info_102b_dbf5 pci_ss_info_102b_0521_102b_dbf5 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf8 = + {0x102b, 0xdbf8, pci_subsys_102b_0521_102b_dbf8, 0}; +#undef pci_ss_info_102b_dbf8 +#define pci_ss_info_102b_dbf8 pci_ss_info_102b_0521_102b_dbf8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf9 = + {0x102b, 0xdbf9, pci_subsys_102b_0521_102b_dbf9, 0}; +#undef pci_ss_info_102b_dbf9 +#define pci_ss_info_102b_dbf9 pci_ss_info_102b_0521_102b_dbf9 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_f806 = + {0x102b, 0xf806, pci_subsys_102b_0521_102b_f806, 0}; +#undef pci_ss_info_102b_f806 +#define pci_ss_info_102b_f806 pci_ss_info_102b_0521_102b_f806 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ff00 = + {0x102b, 0xff00, pci_subsys_102b_0521_102b_ff00, 0}; +#undef pci_ss_info_102b_ff00 +#define pci_ss_info_102b_ff00 pci_ss_info_102b_0521_102b_ff00 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ff02 = + {0x102b, 0xff02, pci_subsys_102b_0521_102b_ff02, 0}; +#undef pci_ss_info_102b_ff02 +#define pci_ss_info_102b_ff02 pci_ss_info_102b_0521_102b_ff02 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ff03 = + {0x102b, 0xff03, pci_subsys_102b_0521_102b_ff03, 0}; +#undef pci_ss_info_102b_ff03 +#define pci_ss_info_102b_ff03 pci_ss_info_102b_0521_102b_ff03 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ff04 = + {0x102b, 0xff04, pci_subsys_102b_0521_102b_ff04, 0}; +#undef pci_ss_info_102b_ff04 +#define pci_ss_info_102b_ff04 pci_ss_info_102b_0521_102b_ff04 +static const pciSubsystemInfo pci_ss_info_102b_0521_110a_0032 = + {0x110a, 0x0032, pci_subsys_102b_0521_110a_0032, 0}; +#undef pci_ss_info_110a_0032 +#define pci_ss_info_110a_0032 pci_ss_info_102b_0521_110a_0032 +static const pciSubsystemInfo pci_ss_info_102b_0525_0e11_b16f = + {0x0e11, 0xb16f, pci_subsys_102b_0525_0e11_b16f, 0}; +#undef pci_ss_info_0e11_b16f +#define pci_ss_info_0e11_b16f pci_ss_info_102b_0525_0e11_b16f +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0328 = + {0x102b, 0x0328, pci_subsys_102b_0525_102b_0328, 0}; +#undef pci_ss_info_102b_0328 +#define pci_ss_info_102b_0328 pci_ss_info_102b_0525_102b_0328 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0338 = + {0x102b, 0x0338, pci_subsys_102b_0525_102b_0338, 0}; +#undef pci_ss_info_102b_0338 +#define pci_ss_info_102b_0338 pci_ss_info_102b_0525_102b_0338 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0378 = + {0x102b, 0x0378, pci_subsys_102b_0525_102b_0378, 0}; +#undef pci_ss_info_102b_0378 +#define pci_ss_info_102b_0378 pci_ss_info_102b_0525_102b_0378 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0541 = + {0x102b, 0x0541, pci_subsys_102b_0525_102b_0541, 0}; +#undef pci_ss_info_102b_0541 +#define pci_ss_info_102b_0541 pci_ss_info_102b_0525_102b_0541 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0542 = + {0x102b, 0x0542, pci_subsys_102b_0525_102b_0542, 0}; +#undef pci_ss_info_102b_0542 +#define pci_ss_info_102b_0542 pci_ss_info_102b_0525_102b_0542 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0543 = + {0x102b, 0x0543, pci_subsys_102b_0525_102b_0543, 0}; +#undef pci_ss_info_102b_0543 +#define pci_ss_info_102b_0543 pci_ss_info_102b_0525_102b_0543 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0641 = + {0x102b, 0x0641, pci_subsys_102b_0525_102b_0641, 0}; +#undef pci_ss_info_102b_0641 +#define pci_ss_info_102b_0641 pci_ss_info_102b_0525_102b_0641 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0642 = + {0x102b, 0x0642, pci_subsys_102b_0525_102b_0642, 0}; +#undef pci_ss_info_102b_0642 +#define pci_ss_info_102b_0642 pci_ss_info_102b_0525_102b_0642 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0643 = + {0x102b, 0x0643, pci_subsys_102b_0525_102b_0643, 0}; +#undef pci_ss_info_102b_0643 +#define pci_ss_info_102b_0643 pci_ss_info_102b_0525_102b_0643 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_07c0 = + {0x102b, 0x07c0, pci_subsys_102b_0525_102b_07c0, 0}; +#undef pci_ss_info_102b_07c0 +#define pci_ss_info_102b_07c0 pci_ss_info_102b_0525_102b_07c0 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_07c1 = + {0x102b, 0x07c1, pci_subsys_102b_0525_102b_07c1, 0}; +#undef pci_ss_info_102b_07c1 +#define pci_ss_info_102b_07c1 pci_ss_info_102b_0525_102b_07c1 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0d41 = + {0x102b, 0x0d41, pci_subsys_102b_0525_102b_0d41, 0}; +#undef pci_ss_info_102b_0d41 +#define pci_ss_info_102b_0d41 pci_ss_info_102b_0525_102b_0d41 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0d42 = + {0x102b, 0x0d42, pci_subsys_102b_0525_102b_0d42, 0}; +#undef pci_ss_info_102b_0d42 +#define pci_ss_info_102b_0d42 pci_ss_info_102b_0525_102b_0d42 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0e00 = + {0x102b, 0x0e00, pci_subsys_102b_0525_102b_0e00, 0}; +#undef pci_ss_info_102b_0e00 +#define pci_ss_info_102b_0e00 pci_ss_info_102b_0525_102b_0e00 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0e01 = + {0x102b, 0x0e01, pci_subsys_102b_0525_102b_0e01, 0}; +#undef pci_ss_info_102b_0e01 +#define pci_ss_info_102b_0e01 pci_ss_info_102b_0525_102b_0e01 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0e02 = + {0x102b, 0x0e02, pci_subsys_102b_0525_102b_0e02, 0}; +#undef pci_ss_info_102b_0e02 +#define pci_ss_info_102b_0e02 pci_ss_info_102b_0525_102b_0e02 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0e03 = + {0x102b, 0x0e03, pci_subsys_102b_0525_102b_0e03, 0}; +#undef pci_ss_info_102b_0e03 +#define pci_ss_info_102b_0e03 pci_ss_info_102b_0525_102b_0e03 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0f80 = + {0x102b, 0x0f80, pci_subsys_102b_0525_102b_0f80, 0}; +#undef pci_ss_info_102b_0f80 +#define pci_ss_info_102b_0f80 pci_ss_info_102b_0525_102b_0f80 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0f81 = + {0x102b, 0x0f81, pci_subsys_102b_0525_102b_0f81, 0}; +#undef pci_ss_info_102b_0f81 +#define pci_ss_info_102b_0f81 pci_ss_info_102b_0525_102b_0f81 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0f82 = + {0x102b, 0x0f82, pci_subsys_102b_0525_102b_0f82, 0}; +#undef pci_ss_info_102b_0f82 +#define pci_ss_info_102b_0f82 pci_ss_info_102b_0525_102b_0f82 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0f83 = + {0x102b, 0x0f83, pci_subsys_102b_0525_102b_0f83, 0}; +#undef pci_ss_info_102b_0f83 +#define pci_ss_info_102b_0f83 pci_ss_info_102b_0525_102b_0f83 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_19d8 = + {0x102b, 0x19d8, pci_subsys_102b_0525_102b_19d8, 0}; +#undef pci_ss_info_102b_19d8 +#define pci_ss_info_102b_19d8 pci_ss_info_102b_0525_102b_19d8 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_19f8 = + {0x102b, 0x19f8, pci_subsys_102b_0525_102b_19f8, 0}; +#undef pci_ss_info_102b_19f8 +#define pci_ss_info_102b_19f8 pci_ss_info_102b_0525_102b_19f8 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_2159 = + {0x102b, 0x2159, pci_subsys_102b_0525_102b_2159, 0}; +#undef pci_ss_info_102b_2159 +#define pci_ss_info_102b_2159 pci_ss_info_102b_0525_102b_2159 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_2179 = + {0x102b, 0x2179, pci_subsys_102b_0525_102b_2179, 0}; +#undef pci_ss_info_102b_2179 +#define pci_ss_info_102b_2179 pci_ss_info_102b_0525_102b_2179 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_217d = + {0x102b, 0x217d, pci_subsys_102b_0525_102b_217d, 0}; +#undef pci_ss_info_102b_217d +#define pci_ss_info_102b_217d pci_ss_info_102b_0525_102b_217d +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_23c0 = + {0x102b, 0x23c0, pci_subsys_102b_0525_102b_23c0, 0}; +#undef pci_ss_info_102b_23c0 +#define pci_ss_info_102b_23c0 pci_ss_info_102b_0525_102b_23c0 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_23c1 = + {0x102b, 0x23c1, pci_subsys_102b_0525_102b_23c1, 0}; +#undef pci_ss_info_102b_23c1 +#define pci_ss_info_102b_23c1 pci_ss_info_102b_0525_102b_23c1 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_23c2 = + {0x102b, 0x23c2, pci_subsys_102b_0525_102b_23c2, 0}; +#undef pci_ss_info_102b_23c2 +#define pci_ss_info_102b_23c2 pci_ss_info_102b_0525_102b_23c2 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_23c3 = + {0x102b, 0x23c3, pci_subsys_102b_0525_102b_23c3, 0}; +#undef pci_ss_info_102b_23c3 +#define pci_ss_info_102b_23c3 pci_ss_info_102b_0525_102b_23c3 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_2f58 = + {0x102b, 0x2f58, pci_subsys_102b_0525_102b_2f58, 0}; +#undef pci_ss_info_102b_2f58 +#define pci_ss_info_102b_2f58 pci_ss_info_102b_0525_102b_2f58 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_2f78 = + {0x102b, 0x2f78, pci_subsys_102b_0525_102b_2f78, 0}; +#undef pci_ss_info_102b_2f78 +#define pci_ss_info_102b_2f78 pci_ss_info_102b_0525_102b_2f78 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_3693 = + {0x102b, 0x3693, pci_subsys_102b_0525_102b_3693, 0}; +#undef pci_ss_info_102b_3693 +#define pci_ss_info_102b_3693 pci_ss_info_102b_0525_102b_3693 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_5dd0 = + {0x102b, 0x5dd0, pci_subsys_102b_0525_102b_5dd0, 0}; +#undef pci_ss_info_102b_5dd0 +#define pci_ss_info_102b_5dd0 pci_ss_info_102b_0525_102b_5dd0 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_5f50 = + {0x102b, 0x5f50, pci_subsys_102b_0525_102b_5f50, 0}; +#undef pci_ss_info_102b_5f50 +#define pci_ss_info_102b_5f50 pci_ss_info_102b_0525_102b_5f50 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_5f51 = + {0x102b, 0x5f51, pci_subsys_102b_0525_102b_5f51, 0}; +#undef pci_ss_info_102b_5f51 +#define pci_ss_info_102b_5f51 pci_ss_info_102b_0525_102b_5f51 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_5f52 = + {0x102b, 0x5f52, pci_subsys_102b_0525_102b_5f52, 0}; +#undef pci_ss_info_102b_5f52 +#define pci_ss_info_102b_5f52 pci_ss_info_102b_0525_102b_5f52 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_9010 = + {0x102b, 0x9010, pci_subsys_102b_0525_102b_9010, 0}; +#undef pci_ss_info_102b_9010 +#define pci_ss_info_102b_9010 pci_ss_info_102b_0525_102b_9010 +static const pciSubsystemInfo pci_ss_info_102b_0525_1458_0400 = + {0x1458, 0x0400, pci_subsys_102b_0525_1458_0400, 0}; +#undef pci_ss_info_1458_0400 +#define pci_ss_info_1458_0400 pci_ss_info_102b_0525_1458_0400 +static const pciSubsystemInfo pci_ss_info_102b_0525_1705_0001 = + {0x1705, 0x0001, pci_subsys_102b_0525_1705_0001, 0}; +#undef pci_ss_info_1705_0001 +#define pci_ss_info_1705_0001 pci_ss_info_102b_0525_1705_0001 +static const pciSubsystemInfo pci_ss_info_102b_0525_1705_0002 = + {0x1705, 0x0002, pci_subsys_102b_0525_1705_0002, 0}; +#undef pci_ss_info_1705_0002 +#define pci_ss_info_1705_0002 pci_ss_info_102b_0525_1705_0002 +static const pciSubsystemInfo pci_ss_info_102b_0525_1705_0003 = + {0x1705, 0x0003, pci_subsys_102b_0525_1705_0003, 0}; +#undef pci_ss_info_1705_0003 +#define pci_ss_info_1705_0003 pci_ss_info_102b_0525_1705_0003 +static const pciSubsystemInfo pci_ss_info_102b_0525_1705_0004 = + {0x1705, 0x0004, pci_subsys_102b_0525_1705_0004, 0}; +#undef pci_ss_info_1705_0004 +#define pci_ss_info_1705_0004 pci_ss_info_102b_0525_1705_0004 +static const pciSubsystemInfo pci_ss_info_102b_0527_102b_0840 = + {0x102b, 0x0840, pci_subsys_102b_0527_102b_0840, 0}; +#undef pci_ss_info_102b_0840 +#define pci_ss_info_102b_0840 pci_ss_info_102b_0527_102b_0840 +static const pciSubsystemInfo pci_ss_info_102b_1000_102b_ff01 = + {0x102b, 0xff01, pci_subsys_102b_1000_102b_ff01, 0}; +#undef pci_ss_info_102b_ff01 +#define pci_ss_info_102b_ff01 pci_ss_info_102b_1000_102b_ff01 +static const pciSubsystemInfo pci_ss_info_102b_1000_102b_ff05 = + {0x102b, 0xff05, pci_subsys_102b_1000_102b_ff05, 0}; +#undef pci_ss_info_102b_ff05 +#define pci_ss_info_102b_ff05 pci_ss_info_102b_1000_102b_ff05 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_1001 = + {0x102b, 0x1001, pci_subsys_102b_1001_102b_1001, 0}; +#undef pci_ss_info_102b_1001 +#define pci_ss_info_102b_1001 pci_ss_info_102b_1001_102b_1001 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff00 = + {0x102b, 0xff00, pci_subsys_102b_1001_102b_ff00, 0}; +#undef pci_ss_info_102b_ff00 +#define pci_ss_info_102b_ff00 pci_ss_info_102b_1001_102b_ff00 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff01 = + {0x102b, 0xff01, pci_subsys_102b_1001_102b_ff01, 0}; +#undef pci_ss_info_102b_ff01 +#define pci_ss_info_102b_ff01 pci_ss_info_102b_1001_102b_ff01 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff03 = + {0x102b, 0xff03, pci_subsys_102b_1001_102b_ff03, 0}; +#undef pci_ss_info_102b_ff03 +#define pci_ss_info_102b_ff03 pci_ss_info_102b_1001_102b_ff03 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff04 = + {0x102b, 0xff04, pci_subsys_102b_1001_102b_ff04, 0}; +#undef pci_ss_info_102b_ff04 +#define pci_ss_info_102b_ff04 pci_ss_info_102b_1001_102b_ff04 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff05 = + {0x102b, 0xff05, pci_subsys_102b_1001_102b_ff05, 0}; +#undef pci_ss_info_102b_ff05 +#define pci_ss_info_102b_ff05 pci_ss_info_102b_1001_102b_ff05 +static const pciSubsystemInfo pci_ss_info_102b_1001_110a_001e = + {0x110a, 0x001e, pci_subsys_102b_1001_110a_001e, 0}; +#undef pci_ss_info_110a_001e +#define pci_ss_info_110a_001e pci_ss_info_102b_1001_110a_001e +static const pciSubsystemInfo pci_ss_info_102b_2527_102b_0f83 = + {0x102b, 0x0f83, pci_subsys_102b_2527_102b_0f83, 0}; +#undef pci_ss_info_102b_0f83 +#define pci_ss_info_102b_0f83 pci_ss_info_102b_2527_102b_0f83 +static const pciSubsystemInfo pci_ss_info_102b_2527_102b_0f84 = + {0x102b, 0x0f84, pci_subsys_102b_2527_102b_0f84, 0}; +#undef pci_ss_info_102b_0f84 +#define pci_ss_info_102b_0f84 pci_ss_info_102b_2527_102b_0f84 +static const pciSubsystemInfo pci_ss_info_102b_2527_102b_1e41 = + {0x102b, 0x1e41, pci_subsys_102b_2527_102b_1e41, 0}; +#undef pci_ss_info_102b_1e41 +#define pci_ss_info_102b_1e41 pci_ss_info_102b_2527_102b_1e41 +static const pciSubsystemInfo pci_ss_info_102c_00c0_102c_00c0 = + {0x102c, 0x00c0, pci_subsys_102c_00c0_102c_00c0, 0}; +#undef pci_ss_info_102c_00c0 +#define pci_ss_info_102c_00c0 pci_ss_info_102c_00c0_102c_00c0 +static const pciSubsystemInfo pci_ss_info_102c_00e5_0e11_b049 = + {0x0e11, 0xb049, pci_subsys_102c_00e5_0e11_b049, 0}; +#undef pci_ss_info_0e11_b049 +#define pci_ss_info_0e11_b049 pci_ss_info_102c_00e5_0e11_b049 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_102f_0020_102f_00f8 = + {0x102f, 0x00f8, pci_subsys_102f_0020_102f_00f8, 0}; +#undef pci_ss_info_102f_00f8 +#define pci_ss_info_102f_00f8 pci_ss_info_102f_0020_102f_00f8 +#endif +static const pciSubsystemInfo pci_ss_info_1033_0035_1179_0001 = + {0x1179, 0x0001, pci_subsys_1033_0035_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1033_0035_1179_0001 +static const pciSubsystemInfo pci_ss_info_1033_0035_12ee_7000 = + {0x12ee, 0x7000, pci_subsys_1033_0035_12ee_7000, 0}; +#undef pci_ss_info_12ee_7000 +#define pci_ss_info_12ee_7000 pci_ss_info_1033_0035_12ee_7000 +static const pciSubsystemInfo pci_ss_info_1033_0035_1799_0001 = + {0x1799, 0x0001, pci_subsys_1033_0035_1799_0001, 0}; +#undef pci_ss_info_1799_0001 +#define pci_ss_info_1799_0001 pci_ss_info_1033_0035_1799_0001 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0020 = + {0x1010, 0x0020, pci_subsys_1033_0067_1010_0020, 0}; +#undef pci_ss_info_1010_0020 +#define pci_ss_info_1010_0020 pci_ss_info_1033_0067_1010_0020 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0080 = + {0x1010, 0x0080, pci_subsys_1033_0067_1010_0080, 0}; +#undef pci_ss_info_1010_0080 +#define pci_ss_info_1010_0080 pci_ss_info_1033_0067_1010_0080 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0088 = + {0x1010, 0x0088, pci_subsys_1033_0067_1010_0088, 0}; +#undef pci_ss_info_1010_0088 +#define pci_ss_info_1010_0088 pci_ss_info_1033_0067_1010_0088 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0090 = + {0x1010, 0x0090, pci_subsys_1033_0067_1010_0090, 0}; +#undef pci_ss_info_1010_0090 +#define pci_ss_info_1010_0090 pci_ss_info_1033_0067_1010_0090 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0098 = + {0x1010, 0x0098, pci_subsys_1033_0067_1010_0098, 0}; +#undef pci_ss_info_1010_0098 +#define pci_ss_info_1010_0098 pci_ss_info_1033_0067_1010_0098 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_00a0 = + {0x1010, 0x00a0, pci_subsys_1033_0067_1010_00a0, 0}; +#undef pci_ss_info_1010_00a0 +#define pci_ss_info_1010_00a0 pci_ss_info_1033_0067_1010_00a0 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_00a8 = + {0x1010, 0x00a8, pci_subsys_1033_0067_1010_00a8, 0}; +#undef pci_ss_info_1010_00a8 +#define pci_ss_info_1010_00a8 pci_ss_info_1033_0067_1010_00a8 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0120 = + {0x1010, 0x0120, pci_subsys_1033_0067_1010_0120, 0}; +#undef pci_ss_info_1010_0120 +#define pci_ss_info_1010_0120 pci_ss_info_1033_0067_1010_0120 +static const pciSubsystemInfo pci_ss_info_1033_0074_1033_8014 = + {0x1033, 0x8014, pci_subsys_1033_0074_1033_8014, 0}; +#undef pci_ss_info_1033_8014 +#define pci_ss_info_1033_8014 pci_ss_info_1033_0074_1033_8014 +static const pciSubsystemInfo pci_ss_info_1033_00cd_12ee_8011 = + {0x12ee, 0x8011, pci_subsys_1033_00cd_12ee_8011, 0}; +#undef pci_ss_info_12ee_8011 +#define pci_ss_info_12ee_8011 pci_ss_info_1033_00cd_12ee_8011 +static const pciSubsystemInfo pci_ss_info_1033_00e0_12ee_7001 = + {0x12ee, 0x7001, pci_subsys_1033_00e0_12ee_7001, 0}; +#undef pci_ss_info_12ee_7001 +#define pci_ss_info_12ee_7001 pci_ss_info_1033_00e0_12ee_7001 +static const pciSubsystemInfo pci_ss_info_1033_00e0_1799_0002 = + {0x1799, 0x0002, pci_subsys_1033_00e0_1799_0002, 0}; +#undef pci_ss_info_1799_0002 +#define pci_ss_info_1799_0002 pci_ss_info_1033_00e0_1799_0002 +static const pciSubsystemInfo pci_ss_info_1039_0200_1039_0000 = + {0x1039, 0x0000, pci_subsys_1039_0200_1039_0000, 0}; +#undef pci_ss_info_1039_0000 +#define pci_ss_info_1039_0000 pci_ss_info_1039_0200_1039_0000 +static const pciSubsystemInfo pci_ss_info_1039_0300_107d_2720 = + {0x107d, 0x2720, pci_subsys_1039_0300_107d_2720, 0}; +#undef pci_ss_info_107d_2720 +#define pci_ss_info_107d_2720 pci_ss_info_1039_0300_107d_2720 +static const pciSubsystemInfo pci_ss_info_1039_0900_1039_0900 = + {0x1039, 0x0900, pci_subsys_1039_0900_1039_0900, 0}; +#undef pci_ss_info_1039_0900 +#define pci_ss_info_1039_0900 pci_ss_info_1039_0900_1039_0900 +static const pciSubsystemInfo pci_ss_info_1039_5513_1019_0970 = + {0x1019, 0x0970, pci_subsys_1039_5513_1019_0970, 0}; +#undef pci_ss_info_1019_0970 +#define pci_ss_info_1019_0970 pci_ss_info_1039_5513_1019_0970 +static const pciSubsystemInfo pci_ss_info_1039_5513_1039_5513 = + {0x1039, 0x5513, pci_subsys_1039_5513_1039_5513, 0}; +#undef pci_ss_info_1039_5513 +#define pci_ss_info_1039_5513 pci_ss_info_1039_5513_1039_5513 +static const pciSubsystemInfo pci_ss_info_1039_6300_1019_0970 = + {0x1019, 0x0970, pci_subsys_1039_6300_1019_0970, 0}; +#undef pci_ss_info_1019_0970 +#define pci_ss_info_1019_0970 pci_ss_info_1039_6300_1019_0970 +static const pciSubsystemInfo pci_ss_info_1039_6306_1039_6306 = + {0x1039, 0x6306, pci_subsys_1039_6306_1039_6306, 0}; +#undef pci_ss_info_1039_6306 +#define pci_ss_info_1039_6306 pci_ss_info_1039_6306_1039_6306 +static const pciSubsystemInfo pci_ss_info_1039_6326_1039_6326 = + {0x1039, 0x6326, pci_subsys_1039_6326_1039_6326, 0}; +#undef pci_ss_info_1039_6326 +#define pci_ss_info_1039_6326 pci_ss_info_1039_6326_1039_6326 +static const pciSubsystemInfo pci_ss_info_1039_6326_1092_0a50 = + {0x1092, 0x0a50, pci_subsys_1039_6326_1092_0a50, 0}; +#undef pci_ss_info_1092_0a50 +#define pci_ss_info_1092_0a50 pci_ss_info_1039_6326_1092_0a50 +static const pciSubsystemInfo pci_ss_info_1039_6326_1092_0a70 = + {0x1092, 0x0a70, pci_subsys_1039_6326_1092_0a70, 0}; +#undef pci_ss_info_1092_0a70 +#define pci_ss_info_1092_0a70 pci_ss_info_1039_6326_1092_0a70 +static const pciSubsystemInfo pci_ss_info_1039_6326_1092_4910 = + {0x1092, 0x4910, pci_subsys_1039_6326_1092_4910, 0}; +#undef pci_ss_info_1092_4910 +#define pci_ss_info_1092_4910 pci_ss_info_1039_6326_1092_4910 +static const pciSubsystemInfo pci_ss_info_1039_6326_1092_4920 = + {0x1092, 0x4920, pci_subsys_1039_6326_1092_4920, 0}; +#undef pci_ss_info_1092_4920 +#define pci_ss_info_1092_4920 pci_ss_info_1039_6326_1092_4920 +static const pciSubsystemInfo pci_ss_info_1039_6326_1569_6326 = + {0x1569, 0x6326, pci_subsys_1039_6326_1569_6326, 0}; +#undef pci_ss_info_1569_6326 +#define pci_ss_info_1569_6326 pci_ss_info_1039_6326_1569_6326 +static const pciSubsystemInfo pci_ss_info_1039_7001_1039_7000 = + {0x1039, 0x7000, pci_subsys_1039_7001_1039_7000, 0}; +#undef pci_ss_info_1039_7000 +#define pci_ss_info_1039_7000 pci_ss_info_1039_7001_1039_7000 +static const pciSubsystemInfo pci_ss_info_1039_7002_1509_7002 = + {0x1509, 0x7002, pci_subsys_1039_7002_1509_7002, 0}; +#undef pci_ss_info_1509_7002 +#define pci_ss_info_1509_7002 pci_ss_info_1039_7002_1509_7002 +static const pciSubsystemInfo pci_ss_info_1039_7016_1039_7016 = + {0x1039, 0x7016, pci_subsys_1039_7016_1039_7016, 0}; +#undef pci_ss_info_1039_7016 +#define pci_ss_info_1039_7016 pci_ss_info_1039_7016_1039_7016 +static const pciSubsystemInfo pci_ss_info_1039_7018_1014_01b6 = + {0x1014, 0x01b6, pci_subsys_1039_7018_1014_01b6, 0}; +#undef pci_ss_info_1014_01b6 +#define pci_ss_info_1014_01b6 pci_ss_info_1039_7018_1014_01b6 +static const pciSubsystemInfo pci_ss_info_1039_7018_1014_01b7 = + {0x1014, 0x01b7, pci_subsys_1039_7018_1014_01b7, 0}; +#undef pci_ss_info_1014_01b7 +#define pci_ss_info_1014_01b7 pci_ss_info_1039_7018_1014_01b7 +static const pciSubsystemInfo pci_ss_info_1039_7018_1019_7018 = + {0x1019, 0x7018, pci_subsys_1039_7018_1019_7018, 0}; +#undef pci_ss_info_1019_7018 +#define pci_ss_info_1019_7018 pci_ss_info_1039_7018_1019_7018 +static const pciSubsystemInfo pci_ss_info_1039_7018_1025_000e = + {0x1025, 0x000e, pci_subsys_1039_7018_1025_000e, 0}; +#undef pci_ss_info_1025_000e +#define pci_ss_info_1025_000e pci_ss_info_1039_7018_1025_000e +static const pciSubsystemInfo pci_ss_info_1039_7018_1025_0018 = + {0x1025, 0x0018, pci_subsys_1039_7018_1025_0018, 0}; +#undef pci_ss_info_1025_0018 +#define pci_ss_info_1025_0018 pci_ss_info_1039_7018_1025_0018 +static const pciSubsystemInfo pci_ss_info_1039_7018_1039_7018 = + {0x1039, 0x7018, pci_subsys_1039_7018_1039_7018, 0}; +#undef pci_ss_info_1039_7018 +#define pci_ss_info_1039_7018 pci_ss_info_1039_7018_1039_7018 +static const pciSubsystemInfo pci_ss_info_1039_7018_1043_800b = + {0x1043, 0x800b, pci_subsys_1039_7018_1043_800b, 0}; +#undef pci_ss_info_1043_800b +#define pci_ss_info_1043_800b pci_ss_info_1039_7018_1043_800b +static const pciSubsystemInfo pci_ss_info_1039_7018_1054_7018 = + {0x1054, 0x7018, pci_subsys_1039_7018_1054_7018, 0}; +#undef pci_ss_info_1054_7018 +#define pci_ss_info_1054_7018 pci_ss_info_1039_7018_1054_7018 +static const pciSubsystemInfo pci_ss_info_1039_7018_107d_5330 = + {0x107d, 0x5330, pci_subsys_1039_7018_107d_5330, 0}; +#undef pci_ss_info_107d_5330 +#define pci_ss_info_107d_5330 pci_ss_info_1039_7018_107d_5330 +static const pciSubsystemInfo pci_ss_info_1039_7018_107d_5350 = + {0x107d, 0x5350, pci_subsys_1039_7018_107d_5350, 0}; +#undef pci_ss_info_107d_5350 +#define pci_ss_info_107d_5350 pci_ss_info_1039_7018_107d_5350 +static const pciSubsystemInfo pci_ss_info_1039_7018_1170_3209 = + {0x1170, 0x3209, pci_subsys_1039_7018_1170_3209, 0}; +#undef pci_ss_info_1170_3209 +#define pci_ss_info_1170_3209 pci_ss_info_1039_7018_1170_3209 +static const pciSubsystemInfo pci_ss_info_1039_7018_1462_400a = + {0x1462, 0x400a, pci_subsys_1039_7018_1462_400a, 0}; +#undef pci_ss_info_1462_400a +#define pci_ss_info_1462_400a pci_ss_info_1039_7018_1462_400a +static const pciSubsystemInfo pci_ss_info_1039_7018_14a4_2089 = + {0x14a4, 0x2089, pci_subsys_1039_7018_14a4_2089, 0}; +#undef pci_ss_info_14a4_2089 +#define pci_ss_info_14a4_2089 pci_ss_info_1039_7018_14a4_2089 +static const pciSubsystemInfo pci_ss_info_1039_7018_14cd_2194 = + {0x14cd, 0x2194, pci_subsys_1039_7018_14cd_2194, 0}; +#undef pci_ss_info_14cd_2194 +#define pci_ss_info_14cd_2194 pci_ss_info_1039_7018_14cd_2194 +static const pciSubsystemInfo pci_ss_info_1039_7018_14ff_1100 = + {0x14ff, 0x1100, pci_subsys_1039_7018_14ff_1100, 0}; +#undef pci_ss_info_14ff_1100 +#define pci_ss_info_14ff_1100 pci_ss_info_1039_7018_14ff_1100 +static const pciSubsystemInfo pci_ss_info_1039_7018_152d_8808 = + {0x152d, 0x8808, pci_subsys_1039_7018_152d_8808, 0}; +#undef pci_ss_info_152d_8808 +#define pci_ss_info_152d_8808 pci_ss_info_1039_7018_152d_8808 +static const pciSubsystemInfo pci_ss_info_1039_7018_1558_1103 = + {0x1558, 0x1103, pci_subsys_1039_7018_1558_1103, 0}; +#undef pci_ss_info_1558_1103 +#define pci_ss_info_1558_1103 pci_ss_info_1039_7018_1558_1103 +static const pciSubsystemInfo pci_ss_info_1039_7018_1558_2200 = + {0x1558, 0x2200, pci_subsys_1039_7018_1558_2200, 0}; +#undef pci_ss_info_1558_2200 +#define pci_ss_info_1558_2200 pci_ss_info_1039_7018_1558_2200 +static const pciSubsystemInfo pci_ss_info_1039_7018_1563_7018 = + {0x1563, 0x7018, pci_subsys_1039_7018_1563_7018, 0}; +#undef pci_ss_info_1563_7018 +#define pci_ss_info_1563_7018 pci_ss_info_1039_7018_1563_7018 +static const pciSubsystemInfo pci_ss_info_1039_7018_15c5_0111 = + {0x15c5, 0x0111, pci_subsys_1039_7018_15c5_0111, 0}; +#undef pci_ss_info_15c5_0111 +#define pci_ss_info_15c5_0111 pci_ss_info_1039_7018_15c5_0111 +static const pciSubsystemInfo pci_ss_info_1039_7018_270f_a171 = + {0x270f, 0xa171, pci_subsys_1039_7018_270f_a171, 0}; +#undef pci_ss_info_270f_a171 +#define pci_ss_info_270f_a171 pci_ss_info_1039_7018_270f_a171 +static const pciSubsystemInfo pci_ss_info_1039_7018_a0a0_0022 = + {0xa0a0, 0x0022, pci_subsys_1039_7018_a0a0_0022, 0}; +#undef pci_ss_info_a0a0_0022 +#define pci_ss_info_a0a0_0022 pci_ss_info_1039_7018_a0a0_0022 +static const pciSubsystemInfo pci_ss_info_103c_1029_107e_000f = + {0x107e, 0x000f, pci_subsys_103c_1029_107e_000f, 0}; +#undef pci_ss_info_107e_000f +#define pci_ss_info_107e_000f pci_ss_info_103c_1029_107e_000f +static const pciSubsystemInfo pci_ss_info_103c_1029_9004_9210 = + {0x9004, 0x9210, pci_subsys_103c_1029_9004_9210, 0}; +#undef pci_ss_info_9004_9210 +#define pci_ss_info_9004_9210 pci_ss_info_103c_1029_9004_9210 +static const pciSubsystemInfo pci_ss_info_103c_1029_9004_9211 = + {0x9004, 0x9211, pci_subsys_103c_1029_9004_9211, 0}; +#undef pci_ss_info_9004_9211 +#define pci_ss_info_9004_9211 pci_ss_info_103c_1029_9004_9211 +static const pciSubsystemInfo pci_ss_info_103c_102a_107e_000e = + {0x107e, 0x000e, pci_subsys_103c_102a_107e_000e, 0}; +#undef pci_ss_info_107e_000e +#define pci_ss_info_107e_000e pci_ss_info_103c_102a_107e_000e +static const pciSubsystemInfo pci_ss_info_103c_102a_9004_9110 = + {0x9004, 0x9110, pci_subsys_103c_102a_9004_9110, 0}; +#undef pci_ss_info_9004_9110 +#define pci_ss_info_9004_9110 pci_ss_info_103c_102a_9004_9110 +static const pciSubsystemInfo pci_ss_info_103c_102a_9004_9111 = + {0x9004, 0x9111, pci_subsys_103c_102a_9004_9111, 0}; +#undef pci_ss_info_9004_9111 +#define pci_ss_info_9004_9111 pci_ss_info_103c_102a_9004_9111 +static const pciSubsystemInfo pci_ss_info_103c_1031_103c_1040 = + {0x103c, 0x1040, pci_subsys_103c_1031_103c_1040, 0}; +#undef pci_ss_info_103c_1040 +#define pci_ss_info_103c_1040 pci_ss_info_103c_1031_103c_1040 +static const pciSubsystemInfo pci_ss_info_103c_1031_103c_1041 = + {0x103c, 0x1041, pci_subsys_103c_1031_103c_1041, 0}; +#undef pci_ss_info_103c_1041 +#define pci_ss_info_103c_1041 pci_ss_info_103c_1031_103c_1041 +static const pciSubsystemInfo pci_ss_info_103c_1031_103c_1042 = + {0x103c, 0x1042, pci_subsys_103c_1031_103c_1042, 0}; +#undef pci_ss_info_103c_1042 +#define pci_ss_info_103c_1042 pci_ss_info_103c_1031_103c_1042 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1049 = + {0x103c, 0x1049, pci_subsys_103c_1048_103c_1049, 0}; +#undef pci_ss_info_103c_1049 +#define pci_ss_info_103c_1049 pci_ss_info_103c_1048_103c_1049 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_104a = + {0x103c, 0x104a, pci_subsys_103c_1048_103c_104a, 0}; +#undef pci_ss_info_103c_104a +#define pci_ss_info_103c_104a pci_ss_info_103c_1048_103c_104a +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_104b = + {0x103c, 0x104b, pci_subsys_103c_1048_103c_104b, 0}; +#undef pci_ss_info_103c_104b +#define pci_ss_info_103c_104b pci_ss_info_103c_1048_103c_104b +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1223 = + {0x103c, 0x1223, pci_subsys_103c_1048_103c_1223, 0}; +#undef pci_ss_info_103c_1223 +#define pci_ss_info_103c_1223 pci_ss_info_103c_1048_103c_1223 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1226 = + {0x103c, 0x1226, pci_subsys_103c_1048_103c_1226, 0}; +#undef pci_ss_info_103c_1226 +#define pci_ss_info_103c_1226 pci_ss_info_103c_1048_103c_1226 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1227 = + {0x103c, 0x1227, pci_subsys_103c_1048_103c_1227, 0}; +#undef pci_ss_info_103c_1227 +#define pci_ss_info_103c_1227 pci_ss_info_103c_1048_103c_1227 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1282 = + {0x103c, 0x1282, pci_subsys_103c_1048_103c_1282, 0}; +#undef pci_ss_info_103c_1282 +#define pci_ss_info_103c_1282 pci_ss_info_103c_1048_103c_1282 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c001 = + {0x1044, 0xc001, pci_subsys_1044_a501_1044_c001, 0}; +#undef pci_ss_info_1044_c001 +#define pci_ss_info_1044_c001 pci_ss_info_1044_a501_1044_c001 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c002 = + {0x1044, 0xc002, pci_subsys_1044_a501_1044_c002, 0}; +#undef pci_ss_info_1044_c002 +#define pci_ss_info_1044_c002 pci_ss_info_1044_a501_1044_c002 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c003 = + {0x1044, 0xc003, pci_subsys_1044_a501_1044_c003, 0}; +#undef pci_ss_info_1044_c003 +#define pci_ss_info_1044_c003 pci_ss_info_1044_a501_1044_c003 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c004 = + {0x1044, 0xc004, pci_subsys_1044_a501_1044_c004, 0}; +#undef pci_ss_info_1044_c004 +#define pci_ss_info_1044_c004 pci_ss_info_1044_a501_1044_c004 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c005 = + {0x1044, 0xc005, pci_subsys_1044_a501_1044_c005, 0}; +#undef pci_ss_info_1044_c005 +#define pci_ss_info_1044_c005 pci_ss_info_1044_a501_1044_c005 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00a = + {0x1044, 0xc00a, pci_subsys_1044_a501_1044_c00a, 0}; +#undef pci_ss_info_1044_c00a +#define pci_ss_info_1044_c00a pci_ss_info_1044_a501_1044_c00a +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00b = + {0x1044, 0xc00b, pci_subsys_1044_a501_1044_c00b, 0}; +#undef pci_ss_info_1044_c00b +#define pci_ss_info_1044_c00b pci_ss_info_1044_a501_1044_c00b +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00c = + {0x1044, 0xc00c, pci_subsys_1044_a501_1044_c00c, 0}; +#undef pci_ss_info_1044_c00c +#define pci_ss_info_1044_c00c pci_ss_info_1044_a501_1044_c00c +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00d = + {0x1044, 0xc00d, pci_subsys_1044_a501_1044_c00d, 0}; +#undef pci_ss_info_1044_c00d +#define pci_ss_info_1044_c00d pci_ss_info_1044_a501_1044_c00d +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00e = + {0x1044, 0xc00e, pci_subsys_1044_a501_1044_c00e, 0}; +#undef pci_ss_info_1044_c00e +#define pci_ss_info_1044_c00e pci_ss_info_1044_a501_1044_c00e +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00f = + {0x1044, 0xc00f, pci_subsys_1044_a501_1044_c00f, 0}; +#undef pci_ss_info_1044_c00f +#define pci_ss_info_1044_c00f pci_ss_info_1044_a501_1044_c00f +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c014 = + {0x1044, 0xc014, pci_subsys_1044_a501_1044_c014, 0}; +#undef pci_ss_info_1044_c014 +#define pci_ss_info_1044_c014 pci_ss_info_1044_a501_1044_c014 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c015 = + {0x1044, 0xc015, pci_subsys_1044_a501_1044_c015, 0}; +#undef pci_ss_info_1044_c015 +#define pci_ss_info_1044_c015 pci_ss_info_1044_a501_1044_c015 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c016 = + {0x1044, 0xc016, pci_subsys_1044_a501_1044_c016, 0}; +#undef pci_ss_info_1044_c016 +#define pci_ss_info_1044_c016 pci_ss_info_1044_a501_1044_c016 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c01e = + {0x1044, 0xc01e, pci_subsys_1044_a501_1044_c01e, 0}; +#undef pci_ss_info_1044_c01e +#define pci_ss_info_1044_c01e pci_ss_info_1044_a501_1044_c01e +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c01f = + {0x1044, 0xc01f, pci_subsys_1044_a501_1044_c01f, 0}; +#undef pci_ss_info_1044_c01f +#define pci_ss_info_1044_c01f pci_ss_info_1044_a501_1044_c01f +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c020 = + {0x1044, 0xc020, pci_subsys_1044_a501_1044_c020, 0}; +#undef pci_ss_info_1044_c020 +#define pci_ss_info_1044_c020 pci_ss_info_1044_a501_1044_c020 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c021 = + {0x1044, 0xc021, pci_subsys_1044_a501_1044_c021, 0}; +#undef pci_ss_info_1044_c021 +#define pci_ss_info_1044_c021 pci_ss_info_1044_a501_1044_c021 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c028 = + {0x1044, 0xc028, pci_subsys_1044_a501_1044_c028, 0}; +#undef pci_ss_info_1044_c028 +#define pci_ss_info_1044_c028 pci_ss_info_1044_a501_1044_c028 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c029 = + {0x1044, 0xc029, pci_subsys_1044_a501_1044_c029, 0}; +#undef pci_ss_info_1044_c029 +#define pci_ss_info_1044_c029 pci_ss_info_1044_a501_1044_c029 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c02a = + {0x1044, 0xc02a, pci_subsys_1044_a501_1044_c02a, 0}; +#undef pci_ss_info_1044_c02a +#define pci_ss_info_1044_c02a pci_ss_info_1044_a501_1044_c02a +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c03c = + {0x1044, 0xc03c, pci_subsys_1044_a501_1044_c03c, 0}; +#undef pci_ss_info_1044_c03c +#define pci_ss_info_1044_c03c pci_ss_info_1044_a501_1044_c03c +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c03d = + {0x1044, 0xc03d, pci_subsys_1044_a501_1044_c03d, 0}; +#undef pci_ss_info_1044_c03d +#define pci_ss_info_1044_c03d pci_ss_info_1044_a501_1044_c03d +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c03e = + {0x1044, 0xc03e, pci_subsys_1044_a501_1044_c03e, 0}; +#undef pci_ss_info_1044_c03e +#define pci_ss_info_1044_c03e pci_ss_info_1044_a501_1044_c03e +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c046 = + {0x1044, 0xc046, pci_subsys_1044_a501_1044_c046, 0}; +#undef pci_ss_info_1044_c046 +#define pci_ss_info_1044_c046 pci_ss_info_1044_a501_1044_c046 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c047 = + {0x1044, 0xc047, pci_subsys_1044_a501_1044_c047, 0}; +#undef pci_ss_info_1044_c047 +#define pci_ss_info_1044_c047 pci_ss_info_1044_a501_1044_c047 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c048 = + {0x1044, 0xc048, pci_subsys_1044_a501_1044_c048, 0}; +#undef pci_ss_info_1044_c048 +#define pci_ss_info_1044_c048 pci_ss_info_1044_a501_1044_c048 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c050 = + {0x1044, 0xc050, pci_subsys_1044_a501_1044_c050, 0}; +#undef pci_ss_info_1044_c050 +#define pci_ss_info_1044_c050 pci_ss_info_1044_a501_1044_c050 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c051 = + {0x1044, 0xc051, pci_subsys_1044_a501_1044_c051, 0}; +#undef pci_ss_info_1044_c051 +#define pci_ss_info_1044_c051 pci_ss_info_1044_a501_1044_c051 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c052 = + {0x1044, 0xc052, pci_subsys_1044_a501_1044_c052, 0}; +#undef pci_ss_info_1044_c052 +#define pci_ss_info_1044_c052 pci_ss_info_1044_a501_1044_c052 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c05a = + {0x1044, 0xc05a, pci_subsys_1044_a501_1044_c05a, 0}; +#undef pci_ss_info_1044_c05a +#define pci_ss_info_1044_c05a pci_ss_info_1044_a501_1044_c05a +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c05b = + {0x1044, 0xc05b, pci_subsys_1044_a501_1044_c05b, 0}; +#undef pci_ss_info_1044_c05b +#define pci_ss_info_1044_c05b pci_ss_info_1044_a501_1044_c05b +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c064 = + {0x1044, 0xc064, pci_subsys_1044_a501_1044_c064, 0}; +#undef pci_ss_info_1044_c064 +#define pci_ss_info_1044_c064 pci_ss_info_1044_a501_1044_c064 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c065 = + {0x1044, 0xc065, pci_subsys_1044_a501_1044_c065, 0}; +#undef pci_ss_info_1044_c065 +#define pci_ss_info_1044_c065 pci_ss_info_1044_a501_1044_c065 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c066 = + {0x1044, 0xc066, pci_subsys_1044_a501_1044_c066, 0}; +#undef pci_ss_info_1044_c066 +#define pci_ss_info_1044_c066 pci_ss_info_1044_a501_1044_c066 +#endif +static const pciSubsystemInfo pci_ss_info_104c_3d07_1011_4d10 = + {0x1011, 0x4d10, pci_subsys_104c_3d07_1011_4d10, 0}; +#undef pci_ss_info_1011_4d10 +#define pci_ss_info_1011_4d10 pci_ss_info_104c_3d07_1011_4d10 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1040_000f = + {0x1040, 0x000f, pci_subsys_104c_3d07_1040_000f, 0}; +#undef pci_ss_info_1040_000f +#define pci_ss_info_1040_000f pci_ss_info_104c_3d07_1040_000f +static const pciSubsystemInfo pci_ss_info_104c_3d07_1040_0011 = + {0x1040, 0x0011, pci_subsys_104c_3d07_1040_0011, 0}; +#undef pci_ss_info_1040_0011 +#define pci_ss_info_1040_0011 pci_ss_info_104c_3d07_1040_0011 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a31 = + {0x1048, 0x0a31, pci_subsys_104c_3d07_1048_0a31, 0}; +#undef pci_ss_info_1048_0a31 +#define pci_ss_info_1048_0a31 pci_ss_info_104c_3d07_1048_0a31 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a32 = + {0x1048, 0x0a32, pci_subsys_104c_3d07_1048_0a32, 0}; +#undef pci_ss_info_1048_0a32 +#define pci_ss_info_1048_0a32 pci_ss_info_104c_3d07_1048_0a32 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a35 = + {0x1048, 0x0a35, pci_subsys_104c_3d07_1048_0a35, 0}; +#undef pci_ss_info_1048_0a35 +#define pci_ss_info_1048_0a35 pci_ss_info_104c_3d07_1048_0a35 +static const pciSubsystemInfo pci_ss_info_104c_3d07_107d_2633 = + {0x107d, 0x2633, pci_subsys_104c_3d07_107d_2633, 0}; +#undef pci_ss_info_107d_2633 +#define pci_ss_info_107d_2633 pci_ss_info_104c_3d07_107d_2633 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0127 = + {0x1092, 0x0127, pci_subsys_104c_3d07_1092_0127, 0}; +#undef pci_ss_info_1092_0127 +#define pci_ss_info_1092_0127 pci_ss_info_104c_3d07_1092_0127 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0136 = + {0x1092, 0x0136, pci_subsys_104c_3d07_1092_0136, 0}; +#undef pci_ss_info_1092_0136 +#define pci_ss_info_1092_0136 pci_ss_info_104c_3d07_1092_0136 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0141 = + {0x1092, 0x0141, pci_subsys_104c_3d07_1092_0141, 0}; +#undef pci_ss_info_1092_0141 +#define pci_ss_info_1092_0141 pci_ss_info_104c_3d07_1092_0141 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0146 = + {0x1092, 0x0146, pci_subsys_104c_3d07_1092_0146, 0}; +#undef pci_ss_info_1092_0146 +#define pci_ss_info_1092_0146 pci_ss_info_104c_3d07_1092_0146 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0148 = + {0x1092, 0x0148, pci_subsys_104c_3d07_1092_0148, 0}; +#undef pci_ss_info_1092_0148 +#define pci_ss_info_1092_0148 pci_ss_info_104c_3d07_1092_0148 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0149 = + {0x1092, 0x0149, pci_subsys_104c_3d07_1092_0149, 0}; +#undef pci_ss_info_1092_0149 +#define pci_ss_info_1092_0149 pci_ss_info_104c_3d07_1092_0149 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0152 = + {0x1092, 0x0152, pci_subsys_104c_3d07_1092_0152, 0}; +#undef pci_ss_info_1092_0152 +#define pci_ss_info_1092_0152 pci_ss_info_104c_3d07_1092_0152 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0154 = + {0x1092, 0x0154, pci_subsys_104c_3d07_1092_0154, 0}; +#undef pci_ss_info_1092_0154 +#define pci_ss_info_1092_0154 pci_ss_info_104c_3d07_1092_0154 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0155 = + {0x1092, 0x0155, pci_subsys_104c_3d07_1092_0155, 0}; +#undef pci_ss_info_1092_0155 +#define pci_ss_info_1092_0155 pci_ss_info_104c_3d07_1092_0155 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0156 = + {0x1092, 0x0156, pci_subsys_104c_3d07_1092_0156, 0}; +#undef pci_ss_info_1092_0156 +#define pci_ss_info_1092_0156 pci_ss_info_104c_3d07_1092_0156 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0157 = + {0x1092, 0x0157, pci_subsys_104c_3d07_1092_0157, 0}; +#undef pci_ss_info_1092_0157 +#define pci_ss_info_1092_0157 pci_ss_info_104c_3d07_1092_0157 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1097_3d01 = + {0x1097, 0x3d01, pci_subsys_104c_3d07_1097_3d01, 0}; +#undef pci_ss_info_1097_3d01 +#define pci_ss_info_1097_3d01 pci_ss_info_104c_3d07_1097_3d01 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1102_100f = + {0x1102, 0x100f, pci_subsys_104c_3d07_1102_100f, 0}; +#undef pci_ss_info_1102_100f +#define pci_ss_info_1102_100f pci_ss_info_104c_3d07_1102_100f +static const pciSubsystemInfo pci_ss_info_104c_3d07_3d3d_0100 = + {0x3d3d, 0x0100, pci_subsys_104c_3d07_3d3d_0100, 0}; +#undef pci_ss_info_3d3d_0100 +#define pci_ss_info_3d3d_0100 pci_ss_info_104c_3d07_3d3d_0100 +static const pciSubsystemInfo pci_ss_info_104c_8000_e4bf_1010 = + {0xe4bf, 0x1010, pci_subsys_104c_8000_e4bf_1010, 0}; +#undef pci_ss_info_e4bf_1010 +#define pci_ss_info_e4bf_1010 pci_ss_info_104c_8000_e4bf_1010 +static const pciSubsystemInfo pci_ss_info_104c_8000_e4bf_1020 = + {0xe4bf, 0x1020, pci_subsys_104c_8000_e4bf_1020, 0}; +#undef pci_ss_info_e4bf_1020 +#define pci_ss_info_e4bf_1020 pci_ss_info_104c_8000_e4bf_1020 +static const pciSubsystemInfo pci_ss_info_104c_8009_104d_8032 = + {0x104d, 0x8032, pci_subsys_104c_8009_104d_8032, 0}; +#undef pci_ss_info_104d_8032 +#define pci_ss_info_104d_8032 pci_ss_info_104c_8009_104d_8032 +static const pciSubsystemInfo pci_ss_info_104c_8019_11bd_000a = + {0x11bd, 0x000a, pci_subsys_104c_8019_11bd_000a, 0}; +#undef pci_ss_info_11bd_000a +#define pci_ss_info_11bd_000a pci_ss_info_104c_8019_11bd_000a +static const pciSubsystemInfo pci_ss_info_104c_8019_11bd_000e = + {0x11bd, 0x000e, pci_subsys_104c_8019_11bd_000e, 0}; +#undef pci_ss_info_11bd_000e +#define pci_ss_info_11bd_000e pci_ss_info_104c_8019_11bd_000e +static const pciSubsystemInfo pci_ss_info_104c_8019_e4bf_1010 = + {0xe4bf, 0x1010, pci_subsys_104c_8019_e4bf_1010, 0}; +#undef pci_ss_info_e4bf_1010 +#define pci_ss_info_e4bf_1010 pci_ss_info_104c_8019_e4bf_1010 +static const pciSubsystemInfo pci_ss_info_104c_8021_104d_80df = + {0x104d, 0x80df, pci_subsys_104c_8021_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_104c_8021_104d_80df +static const pciSubsystemInfo pci_ss_info_104c_8021_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_104c_8021_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_104c_8021_104d_80e7 +static const pciSubsystemInfo pci_ss_info_104c_8027_1028_00e6 = + {0x1028, 0x00e6, pci_subsys_104c_8027_1028_00e6, 0}; +#undef pci_ss_info_1028_00e6 +#define pci_ss_info_1028_00e6 pci_ss_info_104c_8027_1028_00e6 +static const pciSubsystemInfo pci_ss_info_104c_ac1b_0e11_b113 = + {0x0e11, 0xb113, pci_subsys_104c_ac1b_0e11_b113, 0}; +#undef pci_ss_info_0e11_b113 +#define pci_ss_info_0e11_b113 pci_ss_info_104c_ac1b_0e11_b113 +static const pciSubsystemInfo pci_ss_info_104c_ac42_1028_00e6 = + {0x1028, 0x00e6, pci_subsys_104c_ac42_1028_00e6, 0}; +#undef pci_ss_info_1028_00e6 +#define pci_ss_info_1028_00e6 pci_ss_info_104c_ac42_1028_00e6 +static const pciSubsystemInfo pci_ss_info_104c_ac51_1014_023b = + {0x1014, 0x023b, pci_subsys_104c_ac51_1014_023b, 0}; +#undef pci_ss_info_1014_023b +#define pci_ss_info_1014_023b pci_ss_info_104c_ac51_1014_023b +static const pciSubsystemInfo pci_ss_info_104c_ac51_10cf_1095 = + {0x10cf, 0x1095, pci_subsys_104c_ac51_10cf_1095, 0}; +#undef pci_ss_info_10cf_1095 +#define pci_ss_info_10cf_1095 pci_ss_info_104c_ac51_10cf_1095 +static const pciSubsystemInfo pci_ss_info_104c_ac51_e4bf_1000 = + {0xe4bf, 0x1000, pci_subsys_104c_ac51_e4bf_1000, 0}; +#undef pci_ss_info_e4bf_1000 +#define pci_ss_info_e4bf_1000 pci_ss_info_104c_ac51_e4bf_1000 +static const pciSubsystemInfo pci_ss_info_104c_ac55_1014_0512 = + {0x1014, 0x0512, pci_subsys_104c_ac55_1014_0512, 0}; +#undef pci_ss_info_1014_0512 +#define pci_ss_info_1014_0512 pci_ss_info_104c_ac55_1014_0512 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1050_0840_1050_0001 = + {0x1050, 0x0001, pci_subsys_1050_0840_1050_0001, 0}; +#undef pci_ss_info_1050_0001 +#define pci_ss_info_1050_0001 pci_ss_info_1050_0840_1050_0001 +static const pciSubsystemInfo pci_ss_info_1050_0840_1050_0840 = + {0x1050, 0x0840, pci_subsys_1050_0840_1050_0840, 0}; +#undef pci_ss_info_1050_0840 +#define pci_ss_info_1050_0840 pci_ss_info_1050_0840_1050_0840 +#endif +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0030 = + {0xecc0, 0x0030, pci_subsys_1057_1801_ecc0_0030, 0}; +#undef pci_ss_info_ecc0_0030 +#define pci_ss_info_ecc0_0030 pci_ss_info_1057_1801_ecc0_0030 +static const pciSubsystemInfo pci_ss_info_1057_5600_1057_0300 = + {0x1057, 0x0300, pci_subsys_1057_5600_1057_0300, 0}; +#undef pci_ss_info_1057_0300 +#define pci_ss_info_1057_0300 pci_ss_info_1057_5600_1057_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_1057_0301 = + {0x1057, 0x0301, pci_subsys_1057_5600_1057_0301, 0}; +#undef pci_ss_info_1057_0301 +#define pci_ss_info_1057_0301 pci_ss_info_1057_5600_1057_0301 +static const pciSubsystemInfo pci_ss_info_1057_5600_1057_0302 = + {0x1057, 0x0302, pci_subsys_1057_5600_1057_0302, 0}; +#undef pci_ss_info_1057_0302 +#define pci_ss_info_1057_0302 pci_ss_info_1057_5600_1057_0302 +static const pciSubsystemInfo pci_ss_info_1057_5600_1057_5600 = + {0x1057, 0x5600, pci_subsys_1057_5600_1057_5600, 0}; +#undef pci_ss_info_1057_5600 +#define pci_ss_info_1057_5600 pci_ss_info_1057_5600_1057_5600 +static const pciSubsystemInfo pci_ss_info_1057_5600_13d2_0300 = + {0x13d2, 0x0300, pci_subsys_1057_5600_13d2_0300, 0}; +#undef pci_ss_info_13d2_0300 +#define pci_ss_info_13d2_0300 pci_ss_info_1057_5600_13d2_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_13d2_0301 = + {0x13d2, 0x0301, pci_subsys_1057_5600_13d2_0301, 0}; +#undef pci_ss_info_13d2_0301 +#define pci_ss_info_13d2_0301 pci_ss_info_1057_5600_13d2_0301 +static const pciSubsystemInfo pci_ss_info_1057_5600_13d2_0302 = + {0x13d2, 0x0302, pci_subsys_1057_5600_13d2_0302, 0}; +#undef pci_ss_info_13d2_0302 +#define pci_ss_info_13d2_0302 pci_ss_info_1057_5600_13d2_0302 +static const pciSubsystemInfo pci_ss_info_1057_5600_1436_0300 = + {0x1436, 0x0300, pci_subsys_1057_5600_1436_0300, 0}; +#undef pci_ss_info_1436_0300 +#define pci_ss_info_1436_0300 pci_ss_info_1057_5600_1436_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_1436_0301 = + {0x1436, 0x0301, pci_subsys_1057_5600_1436_0301, 0}; +#undef pci_ss_info_1436_0301 +#define pci_ss_info_1436_0301 pci_ss_info_1057_5600_1436_0301 +static const pciSubsystemInfo pci_ss_info_1057_5600_1436_0302 = + {0x1436, 0x0302, pci_subsys_1057_5600_1436_0302, 0}; +#undef pci_ss_info_1436_0302 +#define pci_ss_info_1436_0302 pci_ss_info_1057_5600_1436_0302 +static const pciSubsystemInfo pci_ss_info_1057_5600_144f_100c = + {0x144f, 0x100c, pci_subsys_1057_5600_144f_100c, 0}; +#undef pci_ss_info_144f_100c +#define pci_ss_info_144f_100c pci_ss_info_1057_5600_144f_100c +static const pciSubsystemInfo pci_ss_info_1057_5600_1494_0300 = + {0x1494, 0x0300, pci_subsys_1057_5600_1494_0300, 0}; +#undef pci_ss_info_1494_0300 +#define pci_ss_info_1494_0300 pci_ss_info_1057_5600_1494_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_1494_0301 = + {0x1494, 0x0301, pci_subsys_1057_5600_1494_0301, 0}; +#undef pci_ss_info_1494_0301 +#define pci_ss_info_1494_0301 pci_ss_info_1057_5600_1494_0301 +static const pciSubsystemInfo pci_ss_info_1057_5600_14c8_0300 = + {0x14c8, 0x0300, pci_subsys_1057_5600_14c8_0300, 0}; +#undef pci_ss_info_14c8_0300 +#define pci_ss_info_14c8_0300 pci_ss_info_1057_5600_14c8_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_14c8_0302 = + {0x14c8, 0x0302, pci_subsys_1057_5600_14c8_0302, 0}; +#undef pci_ss_info_14c8_0302 +#define pci_ss_info_14c8_0302 pci_ss_info_1057_5600_14c8_0302 +static const pciSubsystemInfo pci_ss_info_1057_5600_1668_0300 = + {0x1668, 0x0300, pci_subsys_1057_5600_1668_0300, 0}; +#undef pci_ss_info_1668_0300 +#define pci_ss_info_1668_0300 pci_ss_info_1057_5600_1668_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_1668_0302 = + {0x1668, 0x0302, pci_subsys_1057_5600_1668_0302, 0}; +#undef pci_ss_info_1668_0302 +#define pci_ss_info_1668_0302 pci_ss_info_1057_5600_1668_0302 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_105a_0d30_105a_4d33 = + {0x105a, 0x4d33, pci_subsys_105a_0d30_105a_4d33, 0}; +#undef pci_ss_info_105a_4d33 +#define pci_ss_info_105a_4d33 pci_ss_info_105a_0d30_105a_4d33 +static const pciSubsystemInfo pci_ss_info_105a_0d38_105a_4d39 = + {0x105a, 0x4d39, pci_subsys_105a_0d38_105a_4d39, 0}; +#undef pci_ss_info_105a_4d39 +#define pci_ss_info_105a_4d39 pci_ss_info_105a_0d38_105a_4d39 +static const pciSubsystemInfo pci_ss_info_105a_4d30_105a_4d33 = + {0x105a, 0x4d33, pci_subsys_105a_4d30_105a_4d33, 0}; +#undef pci_ss_info_105a_4d33 +#define pci_ss_info_105a_4d33 pci_ss_info_105a_4d30_105a_4d33 +static const pciSubsystemInfo pci_ss_info_105a_4d30_105a_4d39 = + {0x105a, 0x4d39, pci_subsys_105a_4d30_105a_4d39, 0}; +#undef pci_ss_info_105a_4d39 +#define pci_ss_info_105a_4d39 pci_ss_info_105a_4d30_105a_4d39 +static const pciSubsystemInfo pci_ss_info_105a_4d33_105a_4d33 = + {0x105a, 0x4d33, pci_subsys_105a_4d33_105a_4d33, 0}; +#undef pci_ss_info_105a_4d33 +#define pci_ss_info_105a_4d33 pci_ss_info_105a_4d33_105a_4d33 +static const pciSubsystemInfo pci_ss_info_105a_4d38_105a_4d30 = + {0x105a, 0x4d30, pci_subsys_105a_4d38_105a_4d30, 0}; +#undef pci_ss_info_105a_4d30 +#define pci_ss_info_105a_4d30 pci_ss_info_105a_4d38_105a_4d30 +static const pciSubsystemInfo pci_ss_info_105a_4d38_105a_4d33 = + {0x105a, 0x4d33, pci_subsys_105a_4d38_105a_4d33, 0}; +#undef pci_ss_info_105a_4d33 +#define pci_ss_info_105a_4d33 pci_ss_info_105a_4d38_105a_4d33 +static const pciSubsystemInfo pci_ss_info_105a_4d38_105a_4d39 = + {0x105a, 0x4d39, pci_subsys_105a_4d38_105a_4d39, 0}; +#undef pci_ss_info_105a_4d39 +#define pci_ss_info_105a_4d39 pci_ss_info_105a_4d38_105a_4d39 +static const pciSubsystemInfo pci_ss_info_105a_4d68_105a_4d68 = + {0x105a, 0x4d68, pci_subsys_105a_4d68_105a_4d68, 0}; +#undef pci_ss_info_105a_4d68 +#define pci_ss_info_105a_4d68 pci_ss_info_105a_4d68_105a_4d68 +static const pciSubsystemInfo pci_ss_info_105a_5275_105a_0275 = + {0x105a, 0x0275, pci_subsys_105a_5275_105a_0275, 0}; +#undef pci_ss_info_105a_0275 +#define pci_ss_info_105a_0275 pci_ss_info_105a_5275_105a_0275 +static const pciSubsystemInfo pci_ss_info_105a_6269_105a_6269 = + {0x105a, 0x6269, pci_subsys_105a_6269_105a_6269, 0}; +#undef pci_ss_info_105a_6269 +#define pci_ss_info_105a_6269 pci_ss_info_105a_6269_105a_6269 +#endif +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0000 = + {0x105d, 0x0000, pci_subsys_105d_2339_105d_0000, 0}; +#undef pci_ss_info_105d_0000 +#define pci_ss_info_105d_0000 pci_ss_info_105d_2339_105d_0000 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0001 = + {0x105d, 0x0001, pci_subsys_105d_2339_105d_0001, 0}; +#undef pci_ss_info_105d_0001 +#define pci_ss_info_105d_0001 pci_ss_info_105d_2339_105d_0001 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0002 = + {0x105d, 0x0002, pci_subsys_105d_2339_105d_0002, 0}; +#undef pci_ss_info_105d_0002 +#define pci_ss_info_105d_0002 pci_ss_info_105d_2339_105d_0002 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0003 = + {0x105d, 0x0003, pci_subsys_105d_2339_105d_0003, 0}; +#undef pci_ss_info_105d_0003 +#define pci_ss_info_105d_0003 pci_ss_info_105d_2339_105d_0003 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0004 = + {0x105d, 0x0004, pci_subsys_105d_2339_105d_0004, 0}; +#undef pci_ss_info_105d_0004 +#define pci_ss_info_105d_0004 pci_ss_info_105d_2339_105d_0004 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0005 = + {0x105d, 0x0005, pci_subsys_105d_2339_105d_0005, 0}; +#undef pci_ss_info_105d_0005 +#define pci_ss_info_105d_0005 pci_ss_info_105d_2339_105d_0005 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0006 = + {0x105d, 0x0006, pci_subsys_105d_2339_105d_0006, 0}; +#undef pci_ss_info_105d_0006 +#define pci_ss_info_105d_0006 pci_ss_info_105d_2339_105d_0006 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0007 = + {0x105d, 0x0007, pci_subsys_105d_2339_105d_0007, 0}; +#undef pci_ss_info_105d_0007 +#define pci_ss_info_105d_0007 pci_ss_info_105d_2339_105d_0007 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0008 = + {0x105d, 0x0008, pci_subsys_105d_2339_105d_0008, 0}; +#undef pci_ss_info_105d_0008 +#define pci_ss_info_105d_0008 pci_ss_info_105d_2339_105d_0008 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0009 = + {0x105d, 0x0009, pci_subsys_105d_2339_105d_0009, 0}; +#undef pci_ss_info_105d_0009 +#define pci_ss_info_105d_0009 pci_ss_info_105d_2339_105d_0009 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_000a = + {0x105d, 0x000a, pci_subsys_105d_2339_105d_000a, 0}; +#undef pci_ss_info_105d_000a +#define pci_ss_info_105d_000a pci_ss_info_105d_2339_105d_000a +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_000b = + {0x105d, 0x000b, pci_subsys_105d_2339_105d_000b, 0}; +#undef pci_ss_info_105d_000b +#define pci_ss_info_105d_000b pci_ss_info_105d_2339_105d_000b +static const pciSubsystemInfo pci_ss_info_105d_2339_11a4_000a = + {0x11a4, 0x000a, pci_subsys_105d_2339_11a4_000a, 0}; +#undef pci_ss_info_11a4_000a +#define pci_ss_info_11a4_000a pci_ss_info_105d_2339_11a4_000a +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0000 = + {0x13cc, 0x0000, pci_subsys_105d_2339_13cc_0000, 0}; +#undef pci_ss_info_13cc_0000 +#define pci_ss_info_13cc_0000 pci_ss_info_105d_2339_13cc_0000 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0004 = + {0x13cc, 0x0004, pci_subsys_105d_2339_13cc_0004, 0}; +#undef pci_ss_info_13cc_0004 +#define pci_ss_info_13cc_0004 pci_ss_info_105d_2339_13cc_0004 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0005 = + {0x13cc, 0x0005, pci_subsys_105d_2339_13cc_0005, 0}; +#undef pci_ss_info_13cc_0005 +#define pci_ss_info_13cc_0005 pci_ss_info_105d_2339_13cc_0005 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0006 = + {0x13cc, 0x0006, pci_subsys_105d_2339_13cc_0006, 0}; +#undef pci_ss_info_13cc_0006 +#define pci_ss_info_13cc_0006 pci_ss_info_105d_2339_13cc_0006 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0008 = + {0x13cc, 0x0008, pci_subsys_105d_2339_13cc_0008, 0}; +#undef pci_ss_info_13cc_0008 +#define pci_ss_info_13cc_0008 pci_ss_info_105d_2339_13cc_0008 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0009 = + {0x13cc, 0x0009, pci_subsys_105d_2339_13cc_0009, 0}; +#undef pci_ss_info_13cc_0009 +#define pci_ss_info_13cc_0009 pci_ss_info_105d_2339_13cc_0009 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_000a = + {0x13cc, 0x000a, pci_subsys_105d_2339_13cc_000a, 0}; +#undef pci_ss_info_13cc_000a +#define pci_ss_info_13cc_000a pci_ss_info_105d_2339_13cc_000a +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_000c = + {0x13cc, 0x000c, pci_subsys_105d_2339_13cc_000c, 0}; +#undef pci_ss_info_13cc_000c +#define pci_ss_info_13cc_000c pci_ss_info_105d_2339_13cc_000c +static const pciSubsystemInfo pci_ss_info_105d_493d_11a4_000a = + {0x11a4, 0x000a, pci_subsys_105d_493d_11a4_000a, 0}; +#undef pci_ss_info_11a4_000a +#define pci_ss_info_11a4_000a pci_ss_info_105d_493d_11a4_000a +static const pciSubsystemInfo pci_ss_info_105d_493d_11a4_000b = + {0x11a4, 0x000b, pci_subsys_105d_493d_11a4_000b, 0}; +#undef pci_ss_info_11a4_000b +#define pci_ss_info_11a4_000b pci_ss_info_105d_493d_11a4_000b +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0002 = + {0x13cc, 0x0002, pci_subsys_105d_493d_13cc_0002, 0}; +#undef pci_ss_info_13cc_0002 +#define pci_ss_info_13cc_0002 pci_ss_info_105d_493d_13cc_0002 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0003 = + {0x13cc, 0x0003, pci_subsys_105d_493d_13cc_0003, 0}; +#undef pci_ss_info_13cc_0003 +#define pci_ss_info_13cc_0003 pci_ss_info_105d_493d_13cc_0003 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0007 = + {0x13cc, 0x0007, pci_subsys_105d_493d_13cc_0007, 0}; +#undef pci_ss_info_13cc_0007 +#define pci_ss_info_13cc_0007 pci_ss_info_105d_493d_13cc_0007 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0008 = + {0x13cc, 0x0008, pci_subsys_105d_493d_13cc_0008, 0}; +#undef pci_ss_info_13cc_0008 +#define pci_ss_info_13cc_0008 pci_ss_info_105d_493d_13cc_0008 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0009 = + {0x13cc, 0x0009, pci_subsys_105d_493d_13cc_0009, 0}; +#undef pci_ss_info_13cc_0009 +#define pci_ss_info_13cc_0009 pci_ss_info_105d_493d_13cc_0009 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_000a = + {0x13cc, 0x000a, pci_subsys_105d_493d_13cc_000a, 0}; +#undef pci_ss_info_13cc_000a +#define pci_ss_info_13cc_000a pci_ss_info_105d_493d_13cc_000a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1073_0004_1073_0004 = + {0x1073, 0x0004, pci_subsys_1073_0004_1073_0004, 0}; +#undef pci_ss_info_1073_0004 +#define pci_ss_info_1073_0004 pci_ss_info_1073_0004_1073_0004 +static const pciSubsystemInfo pci_ss_info_1073_0005_1073_0005 = + {0x1073, 0x0005, pci_subsys_1073_0005_1073_0005, 0}; +#undef pci_ss_info_1073_0005 +#define pci_ss_info_1073_0005 pci_ss_info_1073_0005_1073_0005 +static const pciSubsystemInfo pci_ss_info_1073_0008_1073_0008 = + {0x1073, 0x0008, pci_subsys_1073_0008_1073_0008, 0}; +#undef pci_ss_info_1073_0008 +#define pci_ss_info_1073_0008 pci_ss_info_1073_0008_1073_0008 +static const pciSubsystemInfo pci_ss_info_1073_000a_1073_0004 = + {0x1073, 0x0004, pci_subsys_1073_000a_1073_0004, 0}; +#undef pci_ss_info_1073_0004 +#define pci_ss_info_1073_0004 pci_ss_info_1073_000a_1073_0004 +static const pciSubsystemInfo pci_ss_info_1073_000a_1073_000a = + {0x1073, 0x000a, pci_subsys_1073_000a_1073_000a, 0}; +#undef pci_ss_info_1073_000a +#define pci_ss_info_1073_000a pci_ss_info_1073_000a_1073_000a +static const pciSubsystemInfo pci_ss_info_1073_000c_107a_000c = + {0x107a, 0x000c, pci_subsys_1073_000c_107a_000c, 0}; +#undef pci_ss_info_107a_000c +#define pci_ss_info_107a_000c pci_ss_info_1073_000c_107a_000c +static const pciSubsystemInfo pci_ss_info_1073_000d_1073_000d = + {0x1073, 0x000d, pci_subsys_1073_000d_1073_000d, 0}; +#undef pci_ss_info_1073_000d +#define pci_ss_info_1073_000d pci_ss_info_1073_000d_1073_000d +static const pciSubsystemInfo pci_ss_info_1073_0010_1073_0006 = + {0x1073, 0x0006, pci_subsys_1073_0010_1073_0006, 0}; +#undef pci_ss_info_1073_0006 +#define pci_ss_info_1073_0006 pci_ss_info_1073_0010_1073_0006 +static const pciSubsystemInfo pci_ss_info_1073_0010_1073_0010 = + {0x1073, 0x0010, pci_subsys_1073_0010_1073_0010, 0}; +#undef pci_ss_info_1073_0010 +#define pci_ss_info_1073_0010 pci_ss_info_1073_0010_1073_0010 +static const pciSubsystemInfo pci_ss_info_1073_0012_1073_0012 = + {0x1073, 0x0012, pci_subsys_1073_0012_1073_0012, 0}; +#undef pci_ss_info_1073_0012 +#define pci_ss_info_1073_0012 pci_ss_info_1073_0012_1073_0012 +static const pciSubsystemInfo pci_ss_info_1073_2000_1073_2000 = + {0x1073, 0x2000, pci_subsys_1073_2000_1073_2000, 0}; +#undef pci_ss_info_1073_2000 +#define pci_ss_info_1073_2000 pci_ss_info_1073_2000_1073_2000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1077_1216_101e_8471 = + {0x101e, 0x8471, pci_subsys_1077_1216_101e_8471, 0}; +#undef pci_ss_info_101e_8471 +#define pci_ss_info_101e_8471 pci_ss_info_1077_1216_101e_8471 +static const pciSubsystemInfo pci_ss_info_1077_1216_101e_8493 = + {0x101e, 0x8493, pci_subsys_1077_1216_101e_8493, 0}; +#undef pci_ss_info_101e_8493 +#define pci_ss_info_101e_8493 pci_ss_info_1077_1216_101e_8493 +static const pciSubsystemInfo pci_ss_info_1077_2100_1077_0001 = + {0x1077, 0x0001, pci_subsys_1077_2100_1077_0001, 0}; +#undef pci_ss_info_1077_0001 +#define pci_ss_info_1077_0001 pci_ss_info_1077_2100_1077_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_108d_0004_108d_0004 = + {0x108d, 0x0004, pci_subsys_108d_0004_108d_0004, 0}; +#undef pci_ss_info_108d_0004 +#define pci_ss_info_108d_0004 pci_ss_info_108d_0004_108d_0004 +static const pciSubsystemInfo pci_ss_info_108d_0007_108d_0007 = + {0x108d, 0x0007, pci_subsys_108d_0007_108d_0007, 0}; +#undef pci_ss_info_108d_0007 +#define pci_ss_info_108d_0007 pci_ss_info_108d_0007_108d_0007 +static const pciSubsystemInfo pci_ss_info_108d_0008_108d_0008 = + {0x108d, 0x0008, pci_subsys_108d_0008_108d_0008, 0}; +#undef pci_ss_info_108d_0008 +#define pci_ss_info_108d_0008 pci_ss_info_108d_0008_108d_0008 +static const pciSubsystemInfo pci_ss_info_108d_0019_108d_0016 = + {0x108d, 0x0016, pci_subsys_108d_0019_108d_0016, 0}; +#undef pci_ss_info_108d_0016 +#define pci_ss_info_108d_0016 pci_ss_info_108d_0019_108d_0016 +static const pciSubsystemInfo pci_ss_info_108d_0019_108d_0017 = + {0x108d, 0x0017, pci_subsys_108d_0019_108d_0017, 0}; +#undef pci_ss_info_108d_0017 +#define pci_ss_info_108d_0017 pci_ss_info_108d_0019_108d_0017 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1095_0649_0e11_005d = + {0x0e11, 0x005d, pci_subsys_1095_0649_0e11_005d, 0}; +#undef pci_ss_info_0e11_005d +#define pci_ss_info_0e11_005d pci_ss_info_1095_0649_0e11_005d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1095_0649_0e11_007e = + {0x0e11, 0x007e, pci_subsys_1095_0649_0e11_007e, 0}; +#undef pci_ss_info_0e11_007e +#define pci_ss_info_0e11_007e pci_ss_info_1095_0649_0e11_007e +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1095_0649_101e_0649 = + {0x101e, 0x0649, pci_subsys_1095_0649_101e_0649, 0}; +#undef pci_ss_info_101e_0649 +#define pci_ss_info_101e_0649 pci_ss_info_1095_0649_101e_0649 +static const pciSubsystemInfo pci_ss_info_1095_0670_1095_0670 = + {0x1095, 0x0670, pci_subsys_1095_0670_1095_0670, 0}; +#undef pci_ss_info_1095_0670 +#define pci_ss_info_1095_0670 pci_ss_info_1095_0670_1095_0670 +#endif +static const pciSubsystemInfo pci_ss_info_109e_0369_1002_0001 = + {0x1002, 0x0001, pci_subsys_109e_0369_1002_0001, 0}; +#undef pci_ss_info_1002_0001 +#define pci_ss_info_1002_0001 pci_ss_info_109e_0369_1002_0001 +static const pciSubsystemInfo pci_ss_info_109e_0369_1002_0003 = + {0x1002, 0x0003, pci_subsys_109e_0369_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_109e_0369_1002_0003 +static const pciSubsystemInfo pci_ss_info_109e_036c_13e9_0070 = + {0x13e9, 0x0070, pci_subsys_109e_036c_13e9_0070, 0}; +#undef pci_ss_info_13e9_0070 +#define pci_ss_info_13e9_0070 pci_ss_info_109e_036c_13e9_0070 +static const pciSubsystemInfo pci_ss_info_109e_036e_0070_13eb = + {0x0070, 0x13eb, pci_subsys_109e_036e_0070_13eb, 0}; +#undef pci_ss_info_0070_13eb +#define pci_ss_info_0070_13eb pci_ss_info_109e_036e_0070_13eb +static const pciSubsystemInfo pci_ss_info_109e_036e_0070_ff01 = + {0x0070, 0xff01, pci_subsys_109e_036e_0070_ff01, 0}; +#undef pci_ss_info_0070_ff01 +#define pci_ss_info_0070_ff01 pci_ss_info_109e_036e_0070_ff01 +static const pciSubsystemInfo pci_ss_info_109e_036e_107d_6606 = + {0x107d, 0x6606, pci_subsys_109e_036e_107d_6606, 0}; +#undef pci_ss_info_107d_6606 +#define pci_ss_info_107d_6606 pci_ss_info_109e_036e_107d_6606 +static const pciSubsystemInfo pci_ss_info_109e_036e_11bd_0012 = + {0x11bd, 0x0012, pci_subsys_109e_036e_11bd_0012, 0}; +#undef pci_ss_info_11bd_0012 +#define pci_ss_info_11bd_0012 pci_ss_info_109e_036e_11bd_0012 +static const pciSubsystemInfo pci_ss_info_109e_036e_11bd_001c = + {0x11bd, 0x001c, pci_subsys_109e_036e_11bd_001c, 0}; +#undef pci_ss_info_11bd_001c +#define pci_ss_info_11bd_001c pci_ss_info_109e_036e_11bd_001c +static const pciSubsystemInfo pci_ss_info_109e_036e_127a_0001 = + {0x127a, 0x0001, pci_subsys_109e_036e_127a_0001, 0}; +#undef pci_ss_info_127a_0001 +#define pci_ss_info_127a_0001 pci_ss_info_109e_036e_127a_0001 +static const pciSubsystemInfo pci_ss_info_109e_036e_127a_0002 = + {0x127a, 0x0002, pci_subsys_109e_036e_127a_0002, 0}; +#undef pci_ss_info_127a_0002 +#define pci_ss_info_127a_0002 pci_ss_info_109e_036e_127a_0002 +static const pciSubsystemInfo pci_ss_info_109e_036e_127a_0003 = + {0x127a, 0x0003, pci_subsys_109e_036e_127a_0003, 0}; +#undef pci_ss_info_127a_0003 +#define pci_ss_info_127a_0003 pci_ss_info_109e_036e_127a_0003 +static const pciSubsystemInfo pci_ss_info_109e_036e_127a_0048 = + {0x127a, 0x0048, pci_subsys_109e_036e_127a_0048, 0}; +#undef pci_ss_info_127a_0048 +#define pci_ss_info_127a_0048 pci_ss_info_109e_036e_127a_0048 +static const pciSubsystemInfo pci_ss_info_109e_036e_144f_3000 = + {0x144f, 0x3000, pci_subsys_109e_036e_144f_3000, 0}; +#undef pci_ss_info_144f_3000 +#define pci_ss_info_144f_3000 pci_ss_info_109e_036e_144f_3000 +static const pciSubsystemInfo pci_ss_info_109e_036e_1461_0004 = + {0x1461, 0x0004, pci_subsys_109e_036e_1461_0004, 0}; +#undef pci_ss_info_1461_0004 +#define pci_ss_info_1461_0004 pci_ss_info_109e_036e_1461_0004 +static const pciSubsystemInfo pci_ss_info_109e_036e_14f1_0001 = + {0x14f1, 0x0001, pci_subsys_109e_036e_14f1_0001, 0}; +#undef pci_ss_info_14f1_0001 +#define pci_ss_info_14f1_0001 pci_ss_info_109e_036e_14f1_0001 +static const pciSubsystemInfo pci_ss_info_109e_036e_14f1_0002 = + {0x14f1, 0x0002, pci_subsys_109e_036e_14f1_0002, 0}; +#undef pci_ss_info_14f1_0002 +#define pci_ss_info_14f1_0002 pci_ss_info_109e_036e_14f1_0002 +static const pciSubsystemInfo pci_ss_info_109e_036e_14f1_0003 = + {0x14f1, 0x0003, pci_subsys_109e_036e_14f1_0003, 0}; +#undef pci_ss_info_14f1_0003 +#define pci_ss_info_14f1_0003 pci_ss_info_109e_036e_14f1_0003 +static const pciSubsystemInfo pci_ss_info_109e_036e_14f1_0048 = + {0x14f1, 0x0048, pci_subsys_109e_036e_14f1_0048, 0}; +#undef pci_ss_info_14f1_0048 +#define pci_ss_info_14f1_0048 pci_ss_info_109e_036e_14f1_0048 +static const pciSubsystemInfo pci_ss_info_109e_036e_1851_1850 = + {0x1851, 0x1850, pci_subsys_109e_036e_1851_1850, 0}; +#undef pci_ss_info_1851_1850 +#define pci_ss_info_1851_1850 pci_ss_info_109e_036e_1851_1850 +static const pciSubsystemInfo pci_ss_info_109e_036e_1851_1851 = + {0x1851, 0x1851, pci_subsys_109e_036e_1851_1851, 0}; +#undef pci_ss_info_1851_1851 +#define pci_ss_info_1851_1851 pci_ss_info_109e_036e_1851_1851 +static const pciSubsystemInfo pci_ss_info_109e_036e_1852_1852 = + {0x1852, 0x1852, pci_subsys_109e_036e_1852_1852, 0}; +#undef pci_ss_info_1852_1852 +#define pci_ss_info_1852_1852 pci_ss_info_109e_036e_1852_1852 +static const pciSubsystemInfo pci_ss_info_109e_036e_bd11_1200 = + {0xbd11, 0x1200, pci_subsys_109e_036e_bd11_1200, 0}; +#undef pci_ss_info_bd11_1200 +#define pci_ss_info_bd11_1200 pci_ss_info_109e_036e_bd11_1200 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0044 = + {0x127a, 0x0044, pci_subsys_109e_036f_127a_0044, 0}; +#undef pci_ss_info_127a_0044 +#define pci_ss_info_127a_0044 pci_ss_info_109e_036f_127a_0044 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0122 = + {0x127a, 0x0122, pci_subsys_109e_036f_127a_0122, 0}; +#undef pci_ss_info_127a_0122 +#define pci_ss_info_127a_0122 pci_ss_info_109e_036f_127a_0122 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0144 = + {0x127a, 0x0144, pci_subsys_109e_036f_127a_0144, 0}; +#undef pci_ss_info_127a_0144 +#define pci_ss_info_127a_0144 pci_ss_info_109e_036f_127a_0144 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0222 = + {0x127a, 0x0222, pci_subsys_109e_036f_127a_0222, 0}; +#undef pci_ss_info_127a_0222 +#define pci_ss_info_127a_0222 pci_ss_info_109e_036f_127a_0222 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0244 = + {0x127a, 0x0244, pci_subsys_109e_036f_127a_0244, 0}; +#undef pci_ss_info_127a_0244 +#define pci_ss_info_127a_0244 pci_ss_info_109e_036f_127a_0244 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0322 = + {0x127a, 0x0322, pci_subsys_109e_036f_127a_0322, 0}; +#undef pci_ss_info_127a_0322 +#define pci_ss_info_127a_0322 pci_ss_info_109e_036f_127a_0322 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0422 = + {0x127a, 0x0422, pci_subsys_109e_036f_127a_0422, 0}; +#undef pci_ss_info_127a_0422 +#define pci_ss_info_127a_0422 pci_ss_info_109e_036f_127a_0422 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1122 = + {0x127a, 0x1122, pci_subsys_109e_036f_127a_1122, 0}; +#undef pci_ss_info_127a_1122 +#define pci_ss_info_127a_1122 pci_ss_info_109e_036f_127a_1122 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1222 = + {0x127a, 0x1222, pci_subsys_109e_036f_127a_1222, 0}; +#undef pci_ss_info_127a_1222 +#define pci_ss_info_127a_1222 pci_ss_info_109e_036f_127a_1222 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1322 = + {0x127a, 0x1322, pci_subsys_109e_036f_127a_1322, 0}; +#undef pci_ss_info_127a_1322 +#define pci_ss_info_127a_1322 pci_ss_info_109e_036f_127a_1322 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1522 = + {0x127a, 0x1522, pci_subsys_109e_036f_127a_1522, 0}; +#undef pci_ss_info_127a_1522 +#define pci_ss_info_127a_1522 pci_ss_info_109e_036f_127a_1522 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1622 = + {0x127a, 0x1622, pci_subsys_109e_036f_127a_1622, 0}; +#undef pci_ss_info_127a_1622 +#define pci_ss_info_127a_1622 pci_ss_info_109e_036f_127a_1622 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1722 = + {0x127a, 0x1722, pci_subsys_109e_036f_127a_1722, 0}; +#undef pci_ss_info_127a_1722 +#define pci_ss_info_127a_1722 pci_ss_info_109e_036f_127a_1722 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0044 = + {0x14f1, 0x0044, pci_subsys_109e_036f_14f1_0044, 0}; +#undef pci_ss_info_14f1_0044 +#define pci_ss_info_14f1_0044 pci_ss_info_109e_036f_14f1_0044 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0122 = + {0x14f1, 0x0122, pci_subsys_109e_036f_14f1_0122, 0}; +#undef pci_ss_info_14f1_0122 +#define pci_ss_info_14f1_0122 pci_ss_info_109e_036f_14f1_0122 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0144 = + {0x14f1, 0x0144, pci_subsys_109e_036f_14f1_0144, 0}; +#undef pci_ss_info_14f1_0144 +#define pci_ss_info_14f1_0144 pci_ss_info_109e_036f_14f1_0144 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0222 = + {0x14f1, 0x0222, pci_subsys_109e_036f_14f1_0222, 0}; +#undef pci_ss_info_14f1_0222 +#define pci_ss_info_14f1_0222 pci_ss_info_109e_036f_14f1_0222 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0244 = + {0x14f1, 0x0244, pci_subsys_109e_036f_14f1_0244, 0}; +#undef pci_ss_info_14f1_0244 +#define pci_ss_info_14f1_0244 pci_ss_info_109e_036f_14f1_0244 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0322 = + {0x14f1, 0x0322, pci_subsys_109e_036f_14f1_0322, 0}; +#undef pci_ss_info_14f1_0322 +#define pci_ss_info_14f1_0322 pci_ss_info_109e_036f_14f1_0322 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0422 = + {0x14f1, 0x0422, pci_subsys_109e_036f_14f1_0422, 0}; +#undef pci_ss_info_14f1_0422 +#define pci_ss_info_14f1_0422 pci_ss_info_109e_036f_14f1_0422 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1122 = + {0x14f1, 0x1122, pci_subsys_109e_036f_14f1_1122, 0}; +#undef pci_ss_info_14f1_1122 +#define pci_ss_info_14f1_1122 pci_ss_info_109e_036f_14f1_1122 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1222 = + {0x14f1, 0x1222, pci_subsys_109e_036f_14f1_1222, 0}; +#undef pci_ss_info_14f1_1222 +#define pci_ss_info_14f1_1222 pci_ss_info_109e_036f_14f1_1222 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1322 = + {0x14f1, 0x1322, pci_subsys_109e_036f_14f1_1322, 0}; +#undef pci_ss_info_14f1_1322 +#define pci_ss_info_14f1_1322 pci_ss_info_109e_036f_14f1_1322 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1522 = + {0x14f1, 0x1522, pci_subsys_109e_036f_14f1_1522, 0}; +#undef pci_ss_info_14f1_1522 +#define pci_ss_info_14f1_1522 pci_ss_info_109e_036f_14f1_1522 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1622 = + {0x14f1, 0x1622, pci_subsys_109e_036f_14f1_1622, 0}; +#undef pci_ss_info_14f1_1622 +#define pci_ss_info_14f1_1622 pci_ss_info_109e_036f_14f1_1622 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1722 = + {0x14f1, 0x1722, pci_subsys_109e_036f_14f1_1722, 0}; +#undef pci_ss_info_14f1_1722 +#define pci_ss_info_14f1_1722 pci_ss_info_109e_036f_14f1_1722 +static const pciSubsystemInfo pci_ss_info_109e_036f_1851_1850 = + {0x1851, 0x1850, pci_subsys_109e_036f_1851_1850, 0}; +#undef pci_ss_info_1851_1850 +#define pci_ss_info_1851_1850 pci_ss_info_109e_036f_1851_1850 +static const pciSubsystemInfo pci_ss_info_109e_036f_1851_1851 = + {0x1851, 0x1851, pci_subsys_109e_036f_1851_1851, 0}; +#undef pci_ss_info_1851_1851 +#define pci_ss_info_1851_1851 pci_ss_info_109e_036f_1851_1851 +static const pciSubsystemInfo pci_ss_info_109e_036f_1852_1852 = + {0x1852, 0x1852, pci_subsys_109e_036f_1852_1852, 0}; +#undef pci_ss_info_1852_1852 +#define pci_ss_info_1852_1852 pci_ss_info_109e_036f_1852_1852 +static const pciSubsystemInfo pci_ss_info_109e_0370_1851_1850 = + {0x1851, 0x1850, pci_subsys_109e_0370_1851_1850, 0}; +#undef pci_ss_info_1851_1850 +#define pci_ss_info_1851_1850 pci_ss_info_109e_0370_1851_1850 +static const pciSubsystemInfo pci_ss_info_109e_0370_1851_1851 = + {0x1851, 0x1851, pci_subsys_109e_0370_1851_1851, 0}; +#undef pci_ss_info_1851_1851 +#define pci_ss_info_1851_1851 pci_ss_info_109e_0370_1851_1851 +static const pciSubsystemInfo pci_ss_info_109e_0370_1852_1852 = + {0x1852, 0x1852, pci_subsys_109e_0370_1852_1852, 0}; +#undef pci_ss_info_1852_1852 +#define pci_ss_info_1852_1852 pci_ss_info_109e_0370_1852_1852 +static const pciSubsystemInfo pci_ss_info_109e_0878_0070_13eb = + {0x0070, 0x13eb, pci_subsys_109e_0878_0070_13eb, 0}; +#undef pci_ss_info_0070_13eb +#define pci_ss_info_0070_13eb pci_ss_info_109e_0878_0070_13eb +static const pciSubsystemInfo pci_ss_info_109e_0878_0070_ff01 = + {0x0070, 0xff01, pci_subsys_109e_0878_0070_ff01, 0}; +#undef pci_ss_info_0070_ff01 +#define pci_ss_info_0070_ff01 pci_ss_info_109e_0878_0070_ff01 +static const pciSubsystemInfo pci_ss_info_109e_0878_1002_0001 = + {0x1002, 0x0001, pci_subsys_109e_0878_1002_0001, 0}; +#undef pci_ss_info_1002_0001 +#define pci_ss_info_1002_0001 pci_ss_info_109e_0878_1002_0001 +static const pciSubsystemInfo pci_ss_info_109e_0878_1002_0003 = + {0x1002, 0x0003, pci_subsys_109e_0878_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_109e_0878_1002_0003 +static const pciSubsystemInfo pci_ss_info_109e_0878_11bd_0012 = + {0x11bd, 0x0012, pci_subsys_109e_0878_11bd_0012, 0}; +#undef pci_ss_info_11bd_0012 +#define pci_ss_info_11bd_0012 pci_ss_info_109e_0878_11bd_0012 +static const pciSubsystemInfo pci_ss_info_109e_0878_11bd_001c = + {0x11bd, 0x001c, pci_subsys_109e_0878_11bd_001c, 0}; +#undef pci_ss_info_11bd_001c +#define pci_ss_info_11bd_001c pci_ss_info_109e_0878_11bd_001c +static const pciSubsystemInfo pci_ss_info_109e_0878_127a_0001 = + {0x127a, 0x0001, pci_subsys_109e_0878_127a_0001, 0}; +#undef pci_ss_info_127a_0001 +#define pci_ss_info_127a_0001 pci_ss_info_109e_0878_127a_0001 +static const pciSubsystemInfo pci_ss_info_109e_0878_127a_0002 = + {0x127a, 0x0002, pci_subsys_109e_0878_127a_0002, 0}; +#undef pci_ss_info_127a_0002 +#define pci_ss_info_127a_0002 pci_ss_info_109e_0878_127a_0002 +static const pciSubsystemInfo pci_ss_info_109e_0878_127a_0003 = + {0x127a, 0x0003, pci_subsys_109e_0878_127a_0003, 0}; +#undef pci_ss_info_127a_0003 +#define pci_ss_info_127a_0003 pci_ss_info_109e_0878_127a_0003 +static const pciSubsystemInfo pci_ss_info_109e_0878_127a_0048 = + {0x127a, 0x0048, pci_subsys_109e_0878_127a_0048, 0}; +#undef pci_ss_info_127a_0048 +#define pci_ss_info_127a_0048 pci_ss_info_109e_0878_127a_0048 +static const pciSubsystemInfo pci_ss_info_109e_0878_13e9_0070 = + {0x13e9, 0x0070, pci_subsys_109e_0878_13e9_0070, 0}; +#undef pci_ss_info_13e9_0070 +#define pci_ss_info_13e9_0070 pci_ss_info_109e_0878_13e9_0070 +static const pciSubsystemInfo pci_ss_info_109e_0878_144f_3000 = + {0x144f, 0x3000, pci_subsys_109e_0878_144f_3000, 0}; +#undef pci_ss_info_144f_3000 +#define pci_ss_info_144f_3000 pci_ss_info_109e_0878_144f_3000 +static const pciSubsystemInfo pci_ss_info_109e_0878_1461_0004 = + {0x1461, 0x0004, pci_subsys_109e_0878_1461_0004, 0}; +#undef pci_ss_info_1461_0004 +#define pci_ss_info_1461_0004 pci_ss_info_109e_0878_1461_0004 +static const pciSubsystemInfo pci_ss_info_109e_0878_14f1_0001 = + {0x14f1, 0x0001, pci_subsys_109e_0878_14f1_0001, 0}; +#undef pci_ss_info_14f1_0001 +#define pci_ss_info_14f1_0001 pci_ss_info_109e_0878_14f1_0001 +static const pciSubsystemInfo pci_ss_info_109e_0878_14f1_0002 = + {0x14f1, 0x0002, pci_subsys_109e_0878_14f1_0002, 0}; +#undef pci_ss_info_14f1_0002 +#define pci_ss_info_14f1_0002 pci_ss_info_109e_0878_14f1_0002 +static const pciSubsystemInfo pci_ss_info_109e_0878_14f1_0003 = + {0x14f1, 0x0003, pci_subsys_109e_0878_14f1_0003, 0}; +#undef pci_ss_info_14f1_0003 +#define pci_ss_info_14f1_0003 pci_ss_info_109e_0878_14f1_0003 +static const pciSubsystemInfo pci_ss_info_109e_0878_14f1_0048 = + {0x14f1, 0x0048, pci_subsys_109e_0878_14f1_0048, 0}; +#undef pci_ss_info_14f1_0048 +#define pci_ss_info_14f1_0048 pci_ss_info_109e_0878_14f1_0048 +static const pciSubsystemInfo pci_ss_info_109e_0878_bd11_1200 = + {0xbd11, 0x1200, pci_subsys_109e_0878_bd11_1200, 0}; +#undef pci_ss_info_bd11_1200 +#define pci_ss_info_bd11_1200 pci_ss_info_109e_0878_bd11_1200 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0044 = + {0x127a, 0x0044, pci_subsys_109e_0879_127a_0044, 0}; +#undef pci_ss_info_127a_0044 +#define pci_ss_info_127a_0044 pci_ss_info_109e_0879_127a_0044 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0122 = + {0x127a, 0x0122, pci_subsys_109e_0879_127a_0122, 0}; +#undef pci_ss_info_127a_0122 +#define pci_ss_info_127a_0122 pci_ss_info_109e_0879_127a_0122 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0144 = + {0x127a, 0x0144, pci_subsys_109e_0879_127a_0144, 0}; +#undef pci_ss_info_127a_0144 +#define pci_ss_info_127a_0144 pci_ss_info_109e_0879_127a_0144 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0222 = + {0x127a, 0x0222, pci_subsys_109e_0879_127a_0222, 0}; +#undef pci_ss_info_127a_0222 +#define pci_ss_info_127a_0222 pci_ss_info_109e_0879_127a_0222 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0244 = + {0x127a, 0x0244, pci_subsys_109e_0879_127a_0244, 0}; +#undef pci_ss_info_127a_0244 +#define pci_ss_info_127a_0244 pci_ss_info_109e_0879_127a_0244 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0322 = + {0x127a, 0x0322, pci_subsys_109e_0879_127a_0322, 0}; +#undef pci_ss_info_127a_0322 +#define pci_ss_info_127a_0322 pci_ss_info_109e_0879_127a_0322 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0422 = + {0x127a, 0x0422, pci_subsys_109e_0879_127a_0422, 0}; +#undef pci_ss_info_127a_0422 +#define pci_ss_info_127a_0422 pci_ss_info_109e_0879_127a_0422 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1122 = + {0x127a, 0x1122, pci_subsys_109e_0879_127a_1122, 0}; +#undef pci_ss_info_127a_1122 +#define pci_ss_info_127a_1122 pci_ss_info_109e_0879_127a_1122 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1222 = + {0x127a, 0x1222, pci_subsys_109e_0879_127a_1222, 0}; +#undef pci_ss_info_127a_1222 +#define pci_ss_info_127a_1222 pci_ss_info_109e_0879_127a_1222 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1322 = + {0x127a, 0x1322, pci_subsys_109e_0879_127a_1322, 0}; +#undef pci_ss_info_127a_1322 +#define pci_ss_info_127a_1322 pci_ss_info_109e_0879_127a_1322 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1522 = + {0x127a, 0x1522, pci_subsys_109e_0879_127a_1522, 0}; +#undef pci_ss_info_127a_1522 +#define pci_ss_info_127a_1522 pci_ss_info_109e_0879_127a_1522 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1622 = + {0x127a, 0x1622, pci_subsys_109e_0879_127a_1622, 0}; +#undef pci_ss_info_127a_1622 +#define pci_ss_info_127a_1622 pci_ss_info_109e_0879_127a_1622 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1722 = + {0x127a, 0x1722, pci_subsys_109e_0879_127a_1722, 0}; +#undef pci_ss_info_127a_1722 +#define pci_ss_info_127a_1722 pci_ss_info_109e_0879_127a_1722 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0044 = + {0x14f1, 0x0044, pci_subsys_109e_0879_14f1_0044, 0}; +#undef pci_ss_info_14f1_0044 +#define pci_ss_info_14f1_0044 pci_ss_info_109e_0879_14f1_0044 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0122 = + {0x14f1, 0x0122, pci_subsys_109e_0879_14f1_0122, 0}; +#undef pci_ss_info_14f1_0122 +#define pci_ss_info_14f1_0122 pci_ss_info_109e_0879_14f1_0122 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0144 = + {0x14f1, 0x0144, pci_subsys_109e_0879_14f1_0144, 0}; +#undef pci_ss_info_14f1_0144 +#define pci_ss_info_14f1_0144 pci_ss_info_109e_0879_14f1_0144 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0222 = + {0x14f1, 0x0222, pci_subsys_109e_0879_14f1_0222, 0}; +#undef pci_ss_info_14f1_0222 +#define pci_ss_info_14f1_0222 pci_ss_info_109e_0879_14f1_0222 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0244 = + {0x14f1, 0x0244, pci_subsys_109e_0879_14f1_0244, 0}; +#undef pci_ss_info_14f1_0244 +#define pci_ss_info_14f1_0244 pci_ss_info_109e_0879_14f1_0244 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0322 = + {0x14f1, 0x0322, pci_subsys_109e_0879_14f1_0322, 0}; +#undef pci_ss_info_14f1_0322 +#define pci_ss_info_14f1_0322 pci_ss_info_109e_0879_14f1_0322 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0422 = + {0x14f1, 0x0422, pci_subsys_109e_0879_14f1_0422, 0}; +#undef pci_ss_info_14f1_0422 +#define pci_ss_info_14f1_0422 pci_ss_info_109e_0879_14f1_0422 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1122 = + {0x14f1, 0x1122, pci_subsys_109e_0879_14f1_1122, 0}; +#undef pci_ss_info_14f1_1122 +#define pci_ss_info_14f1_1122 pci_ss_info_109e_0879_14f1_1122 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1222 = + {0x14f1, 0x1222, pci_subsys_109e_0879_14f1_1222, 0}; +#undef pci_ss_info_14f1_1222 +#define pci_ss_info_14f1_1222 pci_ss_info_109e_0879_14f1_1222 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1322 = + {0x14f1, 0x1322, pci_subsys_109e_0879_14f1_1322, 0}; +#undef pci_ss_info_14f1_1322 +#define pci_ss_info_14f1_1322 pci_ss_info_109e_0879_14f1_1322 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1522 = + {0x14f1, 0x1522, pci_subsys_109e_0879_14f1_1522, 0}; +#undef pci_ss_info_14f1_1522 +#define pci_ss_info_14f1_1522 pci_ss_info_109e_0879_14f1_1522 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1622 = + {0x14f1, 0x1622, pci_subsys_109e_0879_14f1_1622, 0}; +#undef pci_ss_info_14f1_1622 +#define pci_ss_info_14f1_1622 pci_ss_info_109e_0879_14f1_1622 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1722 = + {0x14f1, 0x1722, pci_subsys_109e_0879_14f1_1722, 0}; +#undef pci_ss_info_14f1_1722 +#define pci_ss_info_14f1_1722 pci_ss_info_109e_0879_14f1_1722 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b4_1b1d_10b4_237e = + {0x10b4, 0x237e, pci_subsys_10b4_1b1d_10b4_237e, 0}; +#undef pci_ss_info_10b4_237e +#define pci_ss_info_10b4_237e pci_ss_info_10b4_1b1d_10b4_237e +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b5_9030_15ed_1002 = + {0x15ed, 0x1002, pci_subsys_10b5_9030_15ed_1002, 0}; +#undef pci_ss_info_15ed_1002 +#define pci_ss_info_15ed_1002 pci_ss_info_10b5_9030_15ed_1002 +static const pciSubsystemInfo pci_ss_info_10b5_9030_15ed_1003 = + {0x15ed, 0x1003, pci_subsys_10b5_9030_15ed_1003, 0}; +#undef pci_ss_info_15ed_1003 +#define pci_ss_info_15ed_1003 pci_ss_info_10b5_9030_15ed_1003 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_2036 = + {0x10b5, 0x2036, pci_subsys_10b5_9050_10b5_2036, 0}; +#undef pci_ss_info_10b5_2036 +#define pci_ss_info_10b5_2036 pci_ss_info_10b5_9050_10b5_2036 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_2273 = + {0x10b5, 0x2273, pci_subsys_10b5_9050_10b5_2273, 0}; +#undef pci_ss_info_10b5_2273 +#define pci_ss_info_10b5_2273 pci_ss_info_10b5_9050_10b5_2273 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_9050 = + {0x10b5, 0x9050, pci_subsys_10b5_9050_10b5_9050, 0}; +#undef pci_ss_info_10b5_9050 +#define pci_ss_info_10b5_9050 pci_ss_info_10b5_9050_10b5_9050 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0001 = + {0x1522, 0x0001, pci_subsys_10b5_9050_1522_0001, 0}; +#undef pci_ss_info_1522_0001 +#define pci_ss_info_1522_0001 pci_ss_info_10b5_9050_1522_0001 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0002 = + {0x1522, 0x0002, pci_subsys_10b5_9050_1522_0002, 0}; +#undef pci_ss_info_1522_0002 +#define pci_ss_info_1522_0002 pci_ss_info_10b5_9050_1522_0002 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0003 = + {0x1522, 0x0003, pci_subsys_10b5_9050_1522_0003, 0}; +#undef pci_ss_info_1522_0003 +#define pci_ss_info_1522_0003 pci_ss_info_10b5_9050_1522_0003 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0004 = + {0x1522, 0x0004, pci_subsys_10b5_9050_1522_0004, 0}; +#undef pci_ss_info_1522_0004 +#define pci_ss_info_1522_0004 pci_ss_info_10b5_9050_1522_0004 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0010 = + {0x1522, 0x0010, pci_subsys_10b5_9050_1522_0010, 0}; +#undef pci_ss_info_1522_0010 +#define pci_ss_info_1522_0010 pci_ss_info_10b5_9050_1522_0010 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0020 = + {0x1522, 0x0020, pci_subsys_10b5_9050_1522_0020, 0}; +#undef pci_ss_info_1522_0020 +#define pci_ss_info_1522_0020 pci_ss_info_10b5_9050_1522_0020 +static const pciSubsystemInfo pci_ss_info_10b5_9050_15ed_1000 = + {0x15ed, 0x1000, pci_subsys_10b5_9050_15ed_1000, 0}; +#undef pci_ss_info_15ed_1000 +#define pci_ss_info_15ed_1000 pci_ss_info_10b5_9050_15ed_1000 +static const pciSubsystemInfo pci_ss_info_10b5_9050_15ed_1001 = + {0x15ed, 0x1001, pci_subsys_10b5_9050_15ed_1001, 0}; +#undef pci_ss_info_15ed_1001 +#define pci_ss_info_15ed_1001 pci_ss_info_10b5_9050_15ed_1001 +static const pciSubsystemInfo pci_ss_info_10b5_9050_15ed_1002 = + {0x15ed, 0x1002, pci_subsys_10b5_9050_15ed_1002, 0}; +#undef pci_ss_info_15ed_1002 +#define pci_ss_info_15ed_1002 pci_ss_info_10b5_9050_15ed_1002 +static const pciSubsystemInfo pci_ss_info_10b5_9050_15ed_1003 = + {0x15ed, 0x1003, pci_subsys_10b5_9050_15ed_1003, 0}; +#undef pci_ss_info_15ed_1003 +#define pci_ss_info_15ed_1003 pci_ss_info_10b5_9050_15ed_1003 +static const pciSubsystemInfo pci_ss_info_10b5_9050_5654_5634 = + {0x5654, 0x5634, pci_subsys_10b5_9050_5654_5634, 0}; +#undef pci_ss_info_5654_5634 +#define pci_ss_info_5654_5634 pci_ss_info_10b5_9050_5654_5634 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d531_c002 = + {0xd531, 0xc002, pci_subsys_10b5_9050_d531_c002, 0}; +#undef pci_ss_info_d531_c002 +#define pci_ss_info_d531_c002 pci_ss_info_10b5_9050_d531_c002 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4006 = + {0xd84d, 0x4006, pci_subsys_10b5_9050_d84d_4006, 0}; +#undef pci_ss_info_d84d_4006 +#define pci_ss_info_d84d_4006 pci_ss_info_10b5_9050_d84d_4006 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4008 = + {0xd84d, 0x4008, pci_subsys_10b5_9050_d84d_4008, 0}; +#undef pci_ss_info_d84d_4008 +#define pci_ss_info_d84d_4008 pci_ss_info_10b5_9050_d84d_4008 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4014 = + {0xd84d, 0x4014, pci_subsys_10b5_9050_d84d_4014, 0}; +#undef pci_ss_info_d84d_4014 +#define pci_ss_info_d84d_4014 pci_ss_info_10b5_9050_d84d_4014 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4018 = + {0xd84d, 0x4018, pci_subsys_10b5_9050_d84d_4018, 0}; +#undef pci_ss_info_d84d_4018 +#define pci_ss_info_d84d_4018 pci_ss_info_10b5_9050_d84d_4018 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4025 = + {0xd84d, 0x4025, pci_subsys_10b5_9050_d84d_4025, 0}; +#undef pci_ss_info_d84d_4025 +#define pci_ss_info_d84d_4025 pci_ss_info_10b5_9050_d84d_4025 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4027 = + {0xd84d, 0x4027, pci_subsys_10b5_9050_d84d_4027, 0}; +#undef pci_ss_info_d84d_4027 +#define pci_ss_info_d84d_4027 pci_ss_info_10b5_9050_d84d_4027 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4028 = + {0xd84d, 0x4028, pci_subsys_10b5_9050_d84d_4028, 0}; +#undef pci_ss_info_d84d_4028 +#define pci_ss_info_d84d_4028 pci_ss_info_10b5_9050_d84d_4028 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4036 = + {0xd84d, 0x4036, pci_subsys_10b5_9050_d84d_4036, 0}; +#undef pci_ss_info_d84d_4036 +#define pci_ss_info_d84d_4036 pci_ss_info_10b5_9050_d84d_4036 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4037 = + {0xd84d, 0x4037, pci_subsys_10b5_9050_d84d_4037, 0}; +#undef pci_ss_info_d84d_4037 +#define pci_ss_info_d84d_4037 pci_ss_info_10b5_9050_d84d_4037 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4038 = + {0xd84d, 0x4038, pci_subsys_10b5_9050_d84d_4038, 0}; +#undef pci_ss_info_d84d_4038 +#define pci_ss_info_d84d_4038 pci_ss_info_10b5_9050_d84d_4038 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4052 = + {0xd84d, 0x4052, pci_subsys_10b5_9050_d84d_4052, 0}; +#undef pci_ss_info_d84d_4052 +#define pci_ss_info_d84d_4052 pci_ss_info_10b5_9050_d84d_4052 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4053 = + {0xd84d, 0x4053, pci_subsys_10b5_9050_d84d_4053, 0}; +#undef pci_ss_info_d84d_4053 +#define pci_ss_info_d84d_4053 pci_ss_info_10b5_9050_d84d_4053 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4055 = + {0xd84d, 0x4055, pci_subsys_10b5_9050_d84d_4055, 0}; +#undef pci_ss_info_d84d_4055 +#define pci_ss_info_d84d_4055 pci_ss_info_10b5_9050_d84d_4055 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4058 = + {0xd84d, 0x4058, pci_subsys_10b5_9050_d84d_4058, 0}; +#undef pci_ss_info_d84d_4058 +#define pci_ss_info_d84d_4058 pci_ss_info_10b5_9050_d84d_4058 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4065 = + {0xd84d, 0x4065, pci_subsys_10b5_9050_d84d_4065, 0}; +#undef pci_ss_info_d84d_4065 +#define pci_ss_info_d84d_4065 pci_ss_info_10b5_9050_d84d_4065 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4068 = + {0xd84d, 0x4068, pci_subsys_10b5_9050_d84d_4068, 0}; +#undef pci_ss_info_d84d_4068 +#define pci_ss_info_d84d_4068 pci_ss_info_10b5_9050_d84d_4068 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4078 = + {0xd84d, 0x4078, pci_subsys_10b5_9050_d84d_4078, 0}; +#undef pci_ss_info_d84d_4078 +#define pci_ss_info_d84d_4078 pci_ss_info_10b5_9050_d84d_4078 +static const pciSubsystemInfo pci_ss_info_10b5_9054_10b5_2455 = + {0x10b5, 0x2455, pci_subsys_10b5_9054_10b5_2455, 0}; +#undef pci_ss_info_10b5_2455 +#define pci_ss_info_10b5_2455 pci_ss_info_10b5_9054_10b5_2455 +static const pciSubsystemInfo pci_ss_info_10b5_906d_125c_0640 = + {0x125c, 0x0640, pci_subsys_10b5_906d_125c_0640, 0}; +#undef pci_ss_info_125c_0640 +#define pci_ss_info_125c_0640 pci_ss_info_10b5_906d_125c_0640 +static const pciSubsystemInfo pci_ss_info_10b5_9080_10b5_9080 = + {0x10b5, 0x9080, pci_subsys_10b5_9080_10b5_9080, 0}; +#undef pci_ss_info_10b5_9080 +#define pci_ss_info_10b5_9080 pci_ss_info_10b5_9080_10b5_9080 +static const pciSubsystemInfo pci_ss_info_10b5_9080_129d_0002 = + {0x129d, 0x0002, pci_subsys_10b5_9080_129d_0002, 0}; +#undef pci_ss_info_129d_0002 +#define pci_ss_info_129d_0002 pci_ss_info_10b5_9080_129d_0002 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b6_0002_10b6_0002 = + {0x10b6, 0x0002, pci_subsys_10b6_0002_10b6_0002, 0}; +#undef pci_ss_info_10b6_0002 +#define pci_ss_info_10b6_0002 pci_ss_info_10b6_0002_10b6_0002 +static const pciSubsystemInfo pci_ss_info_10b6_0002_10b6_0006 = + {0x10b6, 0x0006, pci_subsys_10b6_0002_10b6_0006, 0}; +#undef pci_ss_info_10b6_0006 +#define pci_ss_info_10b6_0006 pci_ss_info_10b6_0002_10b6_0006 +#endif +static const pciSubsystemInfo pci_ss_info_10b6_0003_0e11_b0fd = + {0x0e11, 0xb0fd, pci_subsys_10b6_0003_0e11_b0fd, 0}; +#undef pci_ss_info_0e11_b0fd +#define pci_ss_info_0e11_b0fd pci_ss_info_10b6_0003_0e11_b0fd +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b6_0003_10b6_0003 = + {0x10b6, 0x0003, pci_subsys_10b6_0003_10b6_0003, 0}; +#undef pci_ss_info_10b6_0003 +#define pci_ss_info_10b6_0003 pci_ss_info_10b6_0003_10b6_0003 +static const pciSubsystemInfo pci_ss_info_10b6_0003_10b6_0007 = + {0x10b6, 0x0007, pci_subsys_10b6_0003_10b6_0007, 0}; +#undef pci_ss_info_10b6_0007 +#define pci_ss_info_10b6_0007 pci_ss_info_10b6_0003_10b6_0007 +static const pciSubsystemInfo pci_ss_info_10b6_0006_10b6_0006 = + {0x10b6, 0x0006, pci_subsys_10b6_0006_10b6_0006, 0}; +#undef pci_ss_info_10b6_0006 +#define pci_ss_info_10b6_0006 pci_ss_info_10b6_0006_10b6_0006 +static const pciSubsystemInfo pci_ss_info_10b6_0007_10b6_0007 = + {0x10b6, 0x0007, pci_subsys_10b6_0007_10b6_0007, 0}; +#undef pci_ss_info_10b6_0007 +#define pci_ss_info_10b6_0007 pci_ss_info_10b6_0007_10b6_0007 +static const pciSubsystemInfo pci_ss_info_10b6_0009_10b6_0009 = + {0x10b6, 0x0009, pci_subsys_10b6_0009_10b6_0009, 0}; +#undef pci_ss_info_10b6_0009 +#define pci_ss_info_10b6_0009 pci_ss_info_10b6_0009_10b6_0009 +static const pciSubsystemInfo pci_ss_info_10b6_000a_10b6_000a = + {0x10b6, 0x000a, pci_subsys_10b6_000a_10b6_000a, 0}; +#undef pci_ss_info_10b6_000a +#define pci_ss_info_10b6_000a pci_ss_info_10b6_000a_10b6_000a +static const pciSubsystemInfo pci_ss_info_10b6_000b_10b6_0008 = + {0x10b6, 0x0008, pci_subsys_10b6_000b_10b6_0008, 0}; +#undef pci_ss_info_10b6_0008 +#define pci_ss_info_10b6_0008 pci_ss_info_10b6_000b_10b6_0008 +static const pciSubsystemInfo pci_ss_info_10b6_000b_10b6_000b = + {0x10b6, 0x000b, pci_subsys_10b6_000b_10b6_000b, 0}; +#undef pci_ss_info_10b6_000b +#define pci_ss_info_10b6_000b pci_ss_info_10b6_000b_10b6_000b +static const pciSubsystemInfo pci_ss_info_10b6_000c_10b6_000c = + {0x10b6, 0x000c, pci_subsys_10b6_000c_10b6_000c, 0}; +#undef pci_ss_info_10b6_000c +#define pci_ss_info_10b6_000c pci_ss_info_10b6_000c_10b6_000c +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b7_1007_10b7_615c = + {0x10b7, 0x615c, pci_subsys_10b7_1007_10b7_615c, 0}; +#undef pci_ss_info_10b7_615c +#define pci_ss_info_10b7_615c pci_ss_info_10b7_1007_10b7_615c +static const pciSubsystemInfo pci_ss_info_10b7_3590_10b7_3590 = + {0x10b7, 0x3590, pci_subsys_10b7_3590_10b7_3590, 0}; +#undef pci_ss_info_10b7_3590 +#define pci_ss_info_10b7_3590 pci_ss_info_10b7_3590_10b7_3590 +static const pciSubsystemInfo pci_ss_info_10b7_5057_10b7_5a57 = + {0x10b7, 0x5a57, pci_subsys_10b7_5057_10b7_5a57, 0}; +#undef pci_ss_info_10b7_5a57 +#define pci_ss_info_10b7_5a57 pci_ss_info_10b7_5057_10b7_5a57 +static const pciSubsystemInfo pci_ss_info_10b7_5157_10b7_5b57 = + {0x10b7, 0x5b57, pci_subsys_10b7_5157_10b7_5b57, 0}; +#undef pci_ss_info_10b7_5b57 +#define pci_ss_info_10b7_5b57 pci_ss_info_10b7_5157_10b7_5b57 +static const pciSubsystemInfo pci_ss_info_10b7_5257_10b7_5c57 = + {0x10b7, 0x5c57, pci_subsys_10b7_5257_10b7_5c57, 0}; +#undef pci_ss_info_10b7_5c57 +#define pci_ss_info_10b7_5c57 pci_ss_info_10b7_5257_10b7_5c57 +static const pciSubsystemInfo pci_ss_info_10b7_5b57_10b7_5b57 = + {0x10b7, 0x5b57, pci_subsys_10b7_5b57_10b7_5b57, 0}; +#undef pci_ss_info_10b7_5b57 +#define pci_ss_info_10b7_5b57 pci_ss_info_10b7_5b57_10b7_5b57 +static const pciSubsystemInfo pci_ss_info_10b7_6056_10b7_6556 = + {0x10b7, 0x6556, pci_subsys_10b7_6056_10b7_6556, 0}; +#undef pci_ss_info_10b7_6556 +#define pci_ss_info_10b7_6556 pci_ss_info_10b7_6056_10b7_6556 +static const pciSubsystemInfo pci_ss_info_10b7_6560_10b7_656a = + {0x10b7, 0x656a, pci_subsys_10b7_6560_10b7_656a, 0}; +#undef pci_ss_info_10b7_656a +#define pci_ss_info_10b7_656a pci_ss_info_10b7_6560_10b7_656a +static const pciSubsystemInfo pci_ss_info_10b7_6561_10b7_656b = + {0x10b7, 0x656b, pci_subsys_10b7_6561_10b7_656b, 0}; +#undef pci_ss_info_10b7_656b +#define pci_ss_info_10b7_656b pci_ss_info_10b7_6561_10b7_656b +static const pciSubsystemInfo pci_ss_info_10b7_6562_10b7_656b = + {0x10b7, 0x656b, pci_subsys_10b7_6562_10b7_656b, 0}; +#undef pci_ss_info_10b7_656b +#define pci_ss_info_10b7_656b pci_ss_info_10b7_6562_10b7_656b +static const pciSubsystemInfo pci_ss_info_10b7_6563_10b7_656b = + {0x10b7, 0x656b, pci_subsys_10b7_6563_10b7_656b, 0}; +#undef pci_ss_info_10b7_656b +#define pci_ss_info_10b7_656b pci_ss_info_10b7_6563_10b7_656b +static const pciSubsystemInfo pci_ss_info_10b7_9004_10b7_9004 = + {0x10b7, 0x9004, pci_subsys_10b7_9004_10b7_9004, 0}; +#undef pci_ss_info_10b7_9004 +#define pci_ss_info_10b7_9004 pci_ss_info_10b7_9004_10b7_9004 +static const pciSubsystemInfo pci_ss_info_10b7_9005_10b7_9005 = + {0x10b7, 0x9005, pci_subsys_10b7_9005_10b7_9005, 0}; +#undef pci_ss_info_10b7_9005 +#define pci_ss_info_10b7_9005 pci_ss_info_10b7_9005_10b7_9005 +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0080 = + {0x1028, 0x0080, pci_subsys_10b7_9055_1028_0080, 0}; +#undef pci_ss_info_1028_0080 +#define pci_ss_info_1028_0080 pci_ss_info_10b7_9055_1028_0080 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0081 = + {0x1028, 0x0081, pci_subsys_10b7_9055_1028_0081, 0}; +#undef pci_ss_info_1028_0081 +#define pci_ss_info_1028_0081 pci_ss_info_10b7_9055_1028_0081 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0082 = + {0x1028, 0x0082, pci_subsys_10b7_9055_1028_0082, 0}; +#undef pci_ss_info_1028_0082 +#define pci_ss_info_1028_0082 pci_ss_info_10b7_9055_1028_0082 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0083 = + {0x1028, 0x0083, pci_subsys_10b7_9055_1028_0083, 0}; +#undef pci_ss_info_1028_0083 +#define pci_ss_info_1028_0083 pci_ss_info_10b7_9055_1028_0083 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0084 = + {0x1028, 0x0084, pci_subsys_10b7_9055_1028_0084, 0}; +#undef pci_ss_info_1028_0084 +#define pci_ss_info_1028_0084 pci_ss_info_10b7_9055_1028_0084 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0085 = + {0x1028, 0x0085, pci_subsys_10b7_9055_1028_0085, 0}; +#undef pci_ss_info_1028_0085 +#define pci_ss_info_1028_0085 pci_ss_info_10b7_9055_1028_0085 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0086 = + {0x1028, 0x0086, pci_subsys_10b7_9055_1028_0086, 0}; +#undef pci_ss_info_1028_0086 +#define pci_ss_info_1028_0086 pci_ss_info_10b7_9055_1028_0086 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0087 = + {0x1028, 0x0087, pci_subsys_10b7_9055_1028_0087, 0}; +#undef pci_ss_info_1028_0087 +#define pci_ss_info_1028_0087 pci_ss_info_10b7_9055_1028_0087 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0088 = + {0x1028, 0x0088, pci_subsys_10b7_9055_1028_0088, 0}; +#undef pci_ss_info_1028_0088 +#define pci_ss_info_1028_0088 pci_ss_info_10b7_9055_1028_0088 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0089 = + {0x1028, 0x0089, pci_subsys_10b7_9055_1028_0089, 0}; +#undef pci_ss_info_1028_0089 +#define pci_ss_info_1028_0089 pci_ss_info_10b7_9055_1028_0089 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0090 = + {0x1028, 0x0090, pci_subsys_10b7_9055_1028_0090, 0}; +#undef pci_ss_info_1028_0090 +#define pci_ss_info_1028_0090 pci_ss_info_10b7_9055_1028_0090 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0091 = + {0x1028, 0x0091, pci_subsys_10b7_9055_1028_0091, 0}; +#undef pci_ss_info_1028_0091 +#define pci_ss_info_1028_0091 pci_ss_info_10b7_9055_1028_0091 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0092 = + {0x1028, 0x0092, pci_subsys_10b7_9055_1028_0092, 0}; +#undef pci_ss_info_1028_0092 +#define pci_ss_info_1028_0092 pci_ss_info_10b7_9055_1028_0092 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0093 = + {0x1028, 0x0093, pci_subsys_10b7_9055_1028_0093, 0}; +#undef pci_ss_info_1028_0093 +#define pci_ss_info_1028_0093 pci_ss_info_10b7_9055_1028_0093 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0094 = + {0x1028, 0x0094, pci_subsys_10b7_9055_1028_0094, 0}; +#undef pci_ss_info_1028_0094 +#define pci_ss_info_1028_0094 pci_ss_info_10b7_9055_1028_0094 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0095 = + {0x1028, 0x0095, pci_subsys_10b7_9055_1028_0095, 0}; +#undef pci_ss_info_1028_0095 +#define pci_ss_info_1028_0095 pci_ss_info_10b7_9055_1028_0095 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0096 = + {0x1028, 0x0096, pci_subsys_10b7_9055_1028_0096, 0}; +#undef pci_ss_info_1028_0096 +#define pci_ss_info_1028_0096 pci_ss_info_10b7_9055_1028_0096 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0097 = + {0x1028, 0x0097, pci_subsys_10b7_9055_1028_0097, 0}; +#undef pci_ss_info_1028_0097 +#define pci_ss_info_1028_0097 pci_ss_info_10b7_9055_1028_0097 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0098 = + {0x1028, 0x0098, pci_subsys_10b7_9055_1028_0098, 0}; +#undef pci_ss_info_1028_0098 +#define pci_ss_info_1028_0098 pci_ss_info_10b7_9055_1028_0098 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0099 = + {0x1028, 0x0099, pci_subsys_10b7_9055_1028_0099, 0}; +#undef pci_ss_info_1028_0099 +#define pci_ss_info_1028_0099 pci_ss_info_10b7_9055_1028_0099 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b7_9055_10b7_9055 = + {0x10b7, 0x9055, pci_subsys_10b7_9055_10b7_9055, 0}; +#undef pci_ss_info_10b7_9055 +#define pci_ss_info_10b7_9055 pci_ss_info_10b7_9055_10b7_9055 +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9200_1028_0095 = + {0x1028, 0x0095, pci_subsys_10b7_9200_1028_0095, 0}; +#undef pci_ss_info_1028_0095 +#define pci_ss_info_1028_0095 pci_ss_info_10b7_9200_1028_0095 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b7_9200_10b7_1000 = + {0x10b7, 0x1000, pci_subsys_10b7_9200_10b7_1000, 0}; +#undef pci_ss_info_10b7_1000 +#define pci_ss_info_10b7_1000 pci_ss_info_10b7_9200_10b7_1000 +static const pciSubsystemInfo pci_ss_info_10b7_9200_10b7_7000 = + {0x10b7, 0x7000, pci_subsys_10b7_9200_10b7_7000, 0}; +#undef pci_ss_info_10b7_7000 +#define pci_ss_info_10b7_7000 pci_ss_info_10b7_9200_10b7_7000 +static const pciSubsystemInfo pci_ss_info_10b7_9800_10b7_9800 = + {0x10b7, 0x9800, pci_subsys_10b7_9800_10b7_9800, 0}; +#undef pci_ss_info_10b7_9800 +#define pci_ss_info_10b7_9800 pci_ss_info_10b7_9800_10b7_9800 +static const pciSubsystemInfo pci_ss_info_10b7_9805_10b7_1201 = + {0x10b7, 0x1201, pci_subsys_10b7_9805_10b7_1201, 0}; +#undef pci_ss_info_10b7_1201 +#define pci_ss_info_10b7_1201 pci_ss_info_10b7_9805_10b7_1201 +static const pciSubsystemInfo pci_ss_info_10b7_9805_10b7_1202 = + {0x10b7, 0x1202, pci_subsys_10b7_9805_10b7_1202, 0}; +#undef pci_ss_info_10b7_1202 +#define pci_ss_info_10b7_1202 pci_ss_info_10b7_9805_10b7_1202 +static const pciSubsystemInfo pci_ss_info_10b7_9805_10b7_9805 = + {0x10b7, 0x9805, pci_subsys_10b7_9805_10b7_9805, 0}; +#undef pci_ss_info_10b7_9805 +#define pci_ss_info_10b7_9805 pci_ss_info_10b7_9805_10b7_9805 +static const pciSubsystemInfo pci_ss_info_10b7_9805_10f1_2462 = + {0x10f1, 0x2462, pci_subsys_10b7_9805_10f1_2462, 0}; +#undef pci_ss_info_10f1_2462 +#define pci_ss_info_10f1_2462 pci_ss_info_10b7_9805_10f1_2462 +static const pciSubsystemInfo pci_ss_info_10b7_9904_10b7_1000 = + {0x10b7, 0x1000, pci_subsys_10b7_9904_10b7_1000, 0}; +#undef pci_ss_info_10b7_1000 +#define pci_ss_info_10b7_1000 pci_ss_info_10b7_9904_10b7_1000 +static const pciSubsystemInfo pci_ss_info_10b7_9904_10b7_2000 = + {0x10b7, 0x2000, pci_subsys_10b7_9904_10b7_2000, 0}; +#undef pci_ss_info_10b7_2000 +#define pci_ss_info_10b7_2000 pci_ss_info_10b7_9904_10b7_2000 +static const pciSubsystemInfo pci_ss_info_10b7_9905_10b7_1101 = + {0x10b7, 0x1101, pci_subsys_10b7_9905_10b7_1101, 0}; +#undef pci_ss_info_10b7_1101 +#define pci_ss_info_10b7_1101 pci_ss_info_10b7_9905_10b7_1101 +static const pciSubsystemInfo pci_ss_info_10b7_9905_10b7_1102 = + {0x10b7, 0x1102, pci_subsys_10b7_9905_10b7_1102, 0}; +#undef pci_ss_info_10b7_1102 +#define pci_ss_info_10b7_1102 pci_ss_info_10b7_9905_10b7_1102 +static const pciSubsystemInfo pci_ss_info_10b7_9905_10b7_2101 = + {0x10b7, 0x2101, pci_subsys_10b7_9905_10b7_2101, 0}; +#undef pci_ss_info_10b7_2101 +#define pci_ss_info_10b7_2101 pci_ss_info_10b7_9905_10b7_2101 +static const pciSubsystemInfo pci_ss_info_10b7_9905_10b7_2102 = + {0x10b7, 0x2102, pci_subsys_10b7_9905_10b7_2102, 0}; +#undef pci_ss_info_10b7_2102 +#define pci_ss_info_10b7_2102 pci_ss_info_10b7_9905_10b7_2102 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b8_0005_1055_e000 = + {0x1055, 0xe000, pci_subsys_10b8_0005_1055_e000, 0}; +#undef pci_ss_info_1055_e000 +#define pci_ss_info_1055_e000 pci_ss_info_10b8_0005_1055_e000 +static const pciSubsystemInfo pci_ss_info_10b8_0005_1055_e002 = + {0x1055, 0xe002, pci_subsys_10b8_0005_1055_e002, 0}; +#undef pci_ss_info_1055_e002 +#define pci_ss_info_1055_e002 pci_ss_info_10b8_0005_1055_e002 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a011 = + {0x10b8, 0xa011, pci_subsys_10b8_0005_10b8_a011, 0}; +#undef pci_ss_info_10b8_a011 +#define pci_ss_info_10b8_a011 pci_ss_info_10b8_0005_10b8_a011 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a014 = + {0x10b8, 0xa014, pci_subsys_10b8_0005_10b8_a014, 0}; +#undef pci_ss_info_10b8_a014 +#define pci_ss_info_10b8_a014 pci_ss_info_10b8_0005_10b8_a014 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a015 = + {0x10b8, 0xa015, pci_subsys_10b8_0005_10b8_a015, 0}; +#undef pci_ss_info_10b8_a015 +#define pci_ss_info_10b8_a015 pci_ss_info_10b8_0005_10b8_a015 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a016 = + {0x10b8, 0xa016, pci_subsys_10b8_0005_10b8_a016, 0}; +#undef pci_ss_info_10b8_a016 +#define pci_ss_info_10b8_a016 pci_ss_info_10b8_0005_10b8_a016 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a017 = + {0x10b8, 0xa017, pci_subsys_10b8_0005_10b8_a017, 0}; +#undef pci_ss_info_10b8_a017 +#define pci_ss_info_10b8_a017 pci_ss_info_10b8_0005_10b8_a017 +static const pciSubsystemInfo pci_ss_info_10b8_0006_1055_e100 = + {0x1055, 0xe100, pci_subsys_10b8_0006_1055_e100, 0}; +#undef pci_ss_info_1055_e100 +#define pci_ss_info_1055_e100 pci_ss_info_10b8_0006_1055_e100 +static const pciSubsystemInfo pci_ss_info_10b8_0006_1055_e102 = + {0x1055, 0xe102, pci_subsys_10b8_0006_1055_e102, 0}; +#undef pci_ss_info_1055_e102 +#define pci_ss_info_1055_e102 pci_ss_info_10b8_0006_1055_e102 +static const pciSubsystemInfo pci_ss_info_10b8_0006_1055_e300 = + {0x1055, 0xe300, pci_subsys_10b8_0006_1055_e300, 0}; +#undef pci_ss_info_1055_e300 +#define pci_ss_info_1055_e300 pci_ss_info_10b8_0006_1055_e300 +static const pciSubsystemInfo pci_ss_info_10b8_0006_1055_e302 = + {0x1055, 0xe302, pci_subsys_10b8_0006_1055_e302, 0}; +#undef pci_ss_info_1055_e302 +#define pci_ss_info_1055_e302 pci_ss_info_10b8_0006_1055_e302 +static const pciSubsystemInfo pci_ss_info_10b8_0006_10b8_a012 = + {0x10b8, 0xa012, pci_subsys_10b8_0006_10b8_a012, 0}; +#undef pci_ss_info_10b8_a012 +#define pci_ss_info_10b8_a012 pci_ss_info_10b8_0006_10b8_a012 +static const pciSubsystemInfo pci_ss_info_10b8_0006_13a2_8002 = + {0x13a2, 0x8002, pci_subsys_10b8_0006_13a2_8002, 0}; +#undef pci_ss_info_13a2_8002 +#define pci_ss_info_13a2_8002 pci_ss_info_10b8_0006_13a2_8002 +static const pciSubsystemInfo pci_ss_info_10b8_0006_13a2_8006 = + {0x13a2, 0x8006, pci_subsys_10b8_0006_13a2_8006, 0}; +#undef pci_ss_info_13a2_8006 +#define pci_ss_info_13a2_8006 pci_ss_info_10b8_0006_13a2_8006 +#endif +static const pciSubsystemInfo pci_ss_info_10b9_0111_10b9_0111 = + {0x10b9, 0x0111, pci_subsys_10b9_0111_10b9_0111, 0}; +#undef pci_ss_info_10b9_0111 +#define pci_ss_info_10b9_0111 pci_ss_info_10b9_0111_10b9_0111 +static const pciSubsystemInfo pci_ss_info_10b9_1521_10b9_1521 = + {0x10b9, 0x1521, pci_subsys_10b9_1521_10b9_1521, 0}; +#undef pci_ss_info_10b9_1521 +#define pci_ss_info_10b9_1521 pci_ss_info_10b9_1521_10b9_1521 +static const pciSubsystemInfo pci_ss_info_10b9_1523_10b9_1523 = + {0x10b9, 0x1523, pci_subsys_10b9_1523_10b9_1523, 0}; +#undef pci_ss_info_10b9_1523 +#define pci_ss_info_10b9_1523 pci_ss_info_10b9_1523_10b9_1523 +static const pciSubsystemInfo pci_ss_info_10b9_1533_10b9_1533 = + {0x10b9, 0x1533, pci_subsys_10b9_1533_10b9_1533, 0}; +#undef pci_ss_info_10b9_1533 +#define pci_ss_info_10b9_1533 pci_ss_info_10b9_1533_10b9_1533 +static const pciSubsystemInfo pci_ss_info_10b9_1541_10b9_1541 = + {0x10b9, 0x1541, pci_subsys_10b9_1541_10b9_1541, 0}; +#undef pci_ss_info_10b9_1541 +#define pci_ss_info_10b9_1541 pci_ss_info_10b9_1541_10b9_1541 +static const pciSubsystemInfo pci_ss_info_10b9_5229_1043_8053 = + {0x1043, 0x8053, pci_subsys_10b9_5229_1043_8053, 0}; +#undef pci_ss_info_1043_8053 +#define pci_ss_info_1043_8053 pci_ss_info_10b9_5229_1043_8053 +static const pciSubsystemInfo pci_ss_info_10b9_5451_1014_0506 = + {0x1014, 0x0506, pci_subsys_10b9_5451_1014_0506, 0}; +#undef pci_ss_info_1014_0506 +#define pci_ss_info_1014_0506 pci_ss_info_10b9_5451_1014_0506 +static const pciSubsystemInfo pci_ss_info_10b9_7101_10b9_7101 = + {0x10b9, 0x7101, pci_subsys_10b9_7101_10b9_7101, 0}; +#undef pci_ss_info_10b9_7101 +#define pci_ss_info_10b9_7101 pci_ss_info_10b9_7101_10b9_7101 +static const pciSubsystemInfo pci_ss_info_10c8_0004_1014_00ba = + {0x1014, 0x00ba, pci_subsys_10c8_0004_1014_00ba, 0}; +#undef pci_ss_info_1014_00ba +#define pci_ss_info_1014_00ba pci_ss_info_10c8_0004_1014_00ba +static const pciSubsystemInfo pci_ss_info_10c8_0004_1025_1007 = + {0x1025, 0x1007, pci_subsys_10c8_0004_1025_1007, 0}; +#undef pci_ss_info_1025_1007 +#define pci_ss_info_1025_1007 pci_ss_info_10c8_0004_1025_1007 +static const pciSubsystemInfo pci_ss_info_10c8_0004_1028_0074 = + {0x1028, 0x0074, pci_subsys_10c8_0004_1028_0074, 0}; +#undef pci_ss_info_1028_0074 +#define pci_ss_info_1028_0074 pci_ss_info_10c8_0004_1028_0074 +static const pciSubsystemInfo pci_ss_info_10c8_0004_1028_0075 = + {0x1028, 0x0075, pci_subsys_10c8_0004_1028_0075, 0}; +#undef pci_ss_info_1028_0075 +#define pci_ss_info_1028_0075 pci_ss_info_10c8_0004_1028_0075 +static const pciSubsystemInfo pci_ss_info_10c8_0004_1028_007d = + {0x1028, 0x007d, pci_subsys_10c8_0004_1028_007d, 0}; +#undef pci_ss_info_1028_007d +#define pci_ss_info_1028_007d pci_ss_info_10c8_0004_1028_007d +static const pciSubsystemInfo pci_ss_info_10c8_0004_1028_007e = + {0x1028, 0x007e, pci_subsys_10c8_0004_1028_007e, 0}; +#undef pci_ss_info_1028_007e +#define pci_ss_info_1028_007e pci_ss_info_10c8_0004_1028_007e +static const pciSubsystemInfo pci_ss_info_10c8_0004_1033_802f = + {0x1033, 0x802f, pci_subsys_10c8_0004_1033_802f, 0}; +#undef pci_ss_info_1033_802f +#define pci_ss_info_1033_802f pci_ss_info_10c8_0004_1033_802f +static const pciSubsystemInfo pci_ss_info_10c8_0004_104d_801b = + {0x104d, 0x801b, pci_subsys_10c8_0004_104d_801b, 0}; +#undef pci_ss_info_104d_801b +#define pci_ss_info_104d_801b pci_ss_info_10c8_0004_104d_801b +static const pciSubsystemInfo pci_ss_info_10c8_0004_104d_802f = + {0x104d, 0x802f, pci_subsys_10c8_0004_104d_802f, 0}; +#undef pci_ss_info_104d_802f +#define pci_ss_info_104d_802f pci_ss_info_10c8_0004_104d_802f +static const pciSubsystemInfo pci_ss_info_10c8_0004_104d_830b = + {0x104d, 0x830b, pci_subsys_10c8_0004_104d_830b, 0}; +#undef pci_ss_info_104d_830b +#define pci_ss_info_104d_830b pci_ss_info_10c8_0004_104d_830b +static const pciSubsystemInfo pci_ss_info_10c8_0004_10ba_0e00 = + {0x10ba, 0x0e00, pci_subsys_10c8_0004_10ba_0e00, 0}; +#undef pci_ss_info_10ba_0e00 +#define pci_ss_info_10ba_0e00 pci_ss_info_10c8_0004_10ba_0e00 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10c8_0004 = + {0x10c8, 0x0004, pci_subsys_10c8_0004_10c8_0004, 0}; +#undef pci_ss_info_10c8_0004 +#define pci_ss_info_10c8_0004 pci_ss_info_10c8_0004_10c8_0004 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10cf_1029 = + {0x10cf, 0x1029, pci_subsys_10c8_0004_10cf_1029, 0}; +#undef pci_ss_info_10cf_1029 +#define pci_ss_info_10cf_1029 pci_ss_info_10c8_0004_10cf_1029 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_8308 = + {0x10f7, 0x8308, pci_subsys_10c8_0004_10f7_8308, 0}; +#undef pci_ss_info_10f7_8308 +#define pci_ss_info_10f7_8308 pci_ss_info_10c8_0004_10f7_8308 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_8309 = + {0x10f7, 0x8309, pci_subsys_10c8_0004_10f7_8309, 0}; +#undef pci_ss_info_10f7_8309 +#define pci_ss_info_10f7_8309 pci_ss_info_10c8_0004_10f7_8309 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_830b = + {0x10f7, 0x830b, pci_subsys_10c8_0004_10f7_830b, 0}; +#undef pci_ss_info_10f7_830b +#define pci_ss_info_10f7_830b pci_ss_info_10c8_0004_10f7_830b +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_830d = + {0x10f7, 0x830d, pci_subsys_10c8_0004_10f7_830d, 0}; +#undef pci_ss_info_10f7_830d +#define pci_ss_info_10f7_830d pci_ss_info_10c8_0004_10f7_830d +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_8312 = + {0x10f7, 0x8312, pci_subsys_10c8_0004_10f7_8312, 0}; +#undef pci_ss_info_10f7_8312 +#define pci_ss_info_10f7_8312 pci_ss_info_10c8_0004_10f7_8312 +static const pciSubsystemInfo pci_ss_info_10c8_0005_1014_00dd = + {0x1014, 0x00dd, pci_subsys_10c8_0005_1014_00dd, 0}; +#undef pci_ss_info_1014_00dd +#define pci_ss_info_1014_00dd pci_ss_info_10c8_0005_1014_00dd +static const pciSubsystemInfo pci_ss_info_10c8_0016_10c8_0016 = + {0x10c8, 0x0016, pci_subsys_10c8_0016_10c8_0016, 0}; +#undef pci_ss_info_10c8_0016 +#define pci_ss_info_10c8_0016 pci_ss_info_10c8_0016_10c8_0016 +static const pciSubsystemInfo pci_ss_info_10c8_8005_0e11_b0d1 = + {0x0e11, 0xb0d1, pci_subsys_10c8_8005_0e11_b0d1, 0}; +#undef pci_ss_info_0e11_b0d1 +#define pci_ss_info_0e11_b0d1 pci_ss_info_10c8_8005_0e11_b0d1 +static const pciSubsystemInfo pci_ss_info_10c8_8005_0e11_b126 = + {0x0e11, 0xb126, pci_subsys_10c8_8005_0e11_b126, 0}; +#undef pci_ss_info_0e11_b126 +#define pci_ss_info_0e11_b126 pci_ss_info_10c8_8005_0e11_b126 +static const pciSubsystemInfo pci_ss_info_10c8_8005_1014_00dd = + {0x1014, 0x00dd, pci_subsys_10c8_8005_1014_00dd, 0}; +#undef pci_ss_info_1014_00dd +#define pci_ss_info_1014_00dd pci_ss_info_10c8_8005_1014_00dd +static const pciSubsystemInfo pci_ss_info_10c8_8005_1025_1003 = + {0x1025, 0x1003, pci_subsys_10c8_8005_1025_1003, 0}; +#undef pci_ss_info_1025_1003 +#define pci_ss_info_1025_1003 pci_ss_info_10c8_8005_1025_1003 +static const pciSubsystemInfo pci_ss_info_10c8_8005_1028_008f = + {0x1028, 0x008f, pci_subsys_10c8_8005_1028_008f, 0}; +#undef pci_ss_info_1028_008f +#define pci_ss_info_1028_008f pci_ss_info_10c8_8005_1028_008f +static const pciSubsystemInfo pci_ss_info_10c8_8005_103c_0007 = + {0x103c, 0x0007, pci_subsys_10c8_8005_103c_0007, 0}; +#undef pci_ss_info_103c_0007 +#define pci_ss_info_103c_0007 pci_ss_info_10c8_8005_103c_0007 +static const pciSubsystemInfo pci_ss_info_10c8_8005_103c_0008 = + {0x103c, 0x0008, pci_subsys_10c8_8005_103c_0008, 0}; +#undef pci_ss_info_103c_0008 +#define pci_ss_info_103c_0008 pci_ss_info_10c8_8005_103c_0008 +static const pciSubsystemInfo pci_ss_info_10c8_8005_103c_000d = + {0x103c, 0x000d, pci_subsys_10c8_8005_103c_000d, 0}; +#undef pci_ss_info_103c_000d +#define pci_ss_info_103c_000d pci_ss_info_10c8_8005_103c_000d +static const pciSubsystemInfo pci_ss_info_10c8_8005_10c8_8005 = + {0x10c8, 0x8005, pci_subsys_10c8_8005_10c8_8005, 0}; +#undef pci_ss_info_10c8_8005 +#define pci_ss_info_10c8_8005 pci_ss_info_10c8_8005_10c8_8005 +static const pciSubsystemInfo pci_ss_info_10c8_8005_110a_8005 = + {0x110a, 0x8005, pci_subsys_10c8_8005_110a_8005, 0}; +#undef pci_ss_info_110a_8005 +#define pci_ss_info_110a_8005 pci_ss_info_10c8_8005_110a_8005 +static const pciSubsystemInfo pci_ss_info_10c8_8005_14c0_0004 = + {0x14c0, 0x0004, pci_subsys_10c8_8005_14c0_0004, 0}; +#undef pci_ss_info_14c0_0004 +#define pci_ss_info_14c0_0004 pci_ss_info_10c8_8005_14c0_0004 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10cd_1300_10cd_1310 = + {0x10cd, 0x1310, pci_subsys_10cd_1300_10cd_1310, 0}; +#undef pci_ss_info_10cd_1310 +#define pci_ss_info_10cd_1310 pci_ss_info_10cd_1300_10cd_1310 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10d9_0531_1186_1200 = + {0x1186, 0x1200, pci_subsys_10d9_0531_1186_1200, 0}; +#undef pci_ss_info_1186_1200 +#define pci_ss_info_1186_1200 pci_ss_info_10d9_0531_1186_1200 +#endif +static const pciSubsystemInfo pci_ss_info_10de_0020_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_0020_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_0020_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_0020_1048_0c18 = + {0x1048, 0x0c18, pci_subsys_10de_0020_1048_0c18, 0}; +#undef pci_ss_info_1048_0c18 +#define pci_ss_info_1048_0c18 pci_ss_info_10de_0020_1048_0c18 +static const pciSubsystemInfo pci_ss_info_10de_0020_1048_0c1b = + {0x1048, 0x0c1b, pci_subsys_10de_0020_1048_0c1b, 0}; +#undef pci_ss_info_1048_0c1b +#define pci_ss_info_1048_0c1b pci_ss_info_10de_0020_1048_0c1b +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_0550 = + {0x1092, 0x0550, pci_subsys_10de_0020_1092_0550, 0}; +#undef pci_ss_info_1092_0550 +#define pci_ss_info_1092_0550 pci_ss_info_10de_0020_1092_0550 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_0552 = + {0x1092, 0x0552, pci_subsys_10de_0020_1092_0552, 0}; +#undef pci_ss_info_1092_0552 +#define pci_ss_info_1092_0552 pci_ss_info_10de_0020_1092_0552 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4804 = + {0x1092, 0x4804, pci_subsys_10de_0020_1092_4804, 0}; +#undef pci_ss_info_1092_4804 +#define pci_ss_info_1092_4804 pci_ss_info_10de_0020_1092_4804 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4808 = + {0x1092, 0x4808, pci_subsys_10de_0020_1092_4808, 0}; +#undef pci_ss_info_1092_4808 +#define pci_ss_info_1092_4808 pci_ss_info_10de_0020_1092_4808 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4810 = + {0x1092, 0x4810, pci_subsys_10de_0020_1092_4810, 0}; +#undef pci_ss_info_1092_4810 +#define pci_ss_info_1092_4810 pci_ss_info_10de_0020_1092_4810 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4812 = + {0x1092, 0x4812, pci_subsys_10de_0020_1092_4812, 0}; +#undef pci_ss_info_1092_4812 +#define pci_ss_info_1092_4812 pci_ss_info_10de_0020_1092_4812 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4815 = + {0x1092, 0x4815, pci_subsys_10de_0020_1092_4815, 0}; +#undef pci_ss_info_1092_4815 +#define pci_ss_info_1092_4815 pci_ss_info_10de_0020_1092_4815 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4820 = + {0x1092, 0x4820, pci_subsys_10de_0020_1092_4820, 0}; +#undef pci_ss_info_1092_4820 +#define pci_ss_info_1092_4820 pci_ss_info_10de_0020_1092_4820 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4822 = + {0x1092, 0x4822, pci_subsys_10de_0020_1092_4822, 0}; +#undef pci_ss_info_1092_4822 +#define pci_ss_info_1092_4822 pci_ss_info_10de_0020_1092_4822 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4904 = + {0x1092, 0x4904, pci_subsys_10de_0020_1092_4904, 0}; +#undef pci_ss_info_1092_4904 +#define pci_ss_info_1092_4904 pci_ss_info_10de_0020_1092_4904 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4914 = + {0x1092, 0x4914, pci_subsys_10de_0020_1092_4914, 0}; +#undef pci_ss_info_1092_4914 +#define pci_ss_info_1092_4914 pci_ss_info_10de_0020_1092_4914 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_8225 = + {0x1092, 0x8225, pci_subsys_10de_0020_1092_8225, 0}; +#undef pci_ss_info_1092_8225 +#define pci_ss_info_1092_8225 pci_ss_info_10de_0020_1092_8225 +static const pciSubsystemInfo pci_ss_info_10de_0020_10b4_273d = + {0x10b4, 0x273d, pci_subsys_10de_0020_10b4_273d, 0}; +#undef pci_ss_info_10b4_273d +#define pci_ss_info_10b4_273d pci_ss_info_10de_0020_10b4_273d +static const pciSubsystemInfo pci_ss_info_10de_0020_10b4_273e = + {0x10b4, 0x273e, pci_subsys_10de_0020_10b4_273e, 0}; +#undef pci_ss_info_10b4_273e +#define pci_ss_info_10b4_273e pci_ss_info_10de_0020_10b4_273e +static const pciSubsystemInfo pci_ss_info_10de_0020_10b4_2740 = + {0x10b4, 0x2740, pci_subsys_10de_0020_10b4_2740, 0}; +#undef pci_ss_info_10b4_2740 +#define pci_ss_info_10b4_2740 pci_ss_info_10de_0020_10b4_2740 +static const pciSubsystemInfo pci_ss_info_10de_0020_10de_0020 = + {0x10de, 0x0020, pci_subsys_10de_0020_10de_0020, 0}; +#undef pci_ss_info_10de_0020 +#define pci_ss_info_10de_0020 pci_ss_info_10de_0020_10de_0020 +static const pciSubsystemInfo pci_ss_info_10de_0020_1102_1015 = + {0x1102, 0x1015, pci_subsys_10de_0020_1102_1015, 0}; +#undef pci_ss_info_1102_1015 +#define pci_ss_info_1102_1015 pci_ss_info_10de_0020_1102_1015 +static const pciSubsystemInfo pci_ss_info_10de_0020_1102_1016 = + {0x1102, 0x1016, pci_subsys_10de_0020_1102_1016, 0}; +#undef pci_ss_info_1102_1016 +#define pci_ss_info_1102_1016 pci_ss_info_10de_0020_1102_1016 +static const pciSubsystemInfo pci_ss_info_10de_0028_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_0028_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_0028_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_0028_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_0028_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_0028_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_0028_1043_0205 = + {0x1043, 0x0205, pci_subsys_10de_0028_1043_0205, 0}; +#undef pci_ss_info_1043_0205 +#define pci_ss_info_1043_0205 pci_ss_info_10de_0028_1043_0205 +static const pciSubsystemInfo pci_ss_info_10de_0028_1043_4000 = + {0x1043, 0x4000, pci_subsys_10de_0028_1043_4000, 0}; +#undef pci_ss_info_1043_4000 +#define pci_ss_info_1043_4000 pci_ss_info_10de_0028_1043_4000 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_4804 = + {0x1092, 0x4804, pci_subsys_10de_0028_1092_4804, 0}; +#undef pci_ss_info_1092_4804 +#define pci_ss_info_1092_4804 pci_ss_info_10de_0028_1092_4804 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_4a00 = + {0x1092, 0x4a00, pci_subsys_10de_0028_1092_4a00, 0}; +#undef pci_ss_info_1092_4a00 +#define pci_ss_info_1092_4a00 pci_ss_info_10de_0028_1092_4a00 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_4a02 = + {0x1092, 0x4a02, pci_subsys_10de_0028_1092_4a02, 0}; +#undef pci_ss_info_1092_4a02 +#define pci_ss_info_1092_4a02 pci_ss_info_10de_0028_1092_4a02 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_5a00 = + {0x1092, 0x5a00, pci_subsys_10de_0028_1092_5a00, 0}; +#undef pci_ss_info_1092_5a00 +#define pci_ss_info_1092_5a00 pci_ss_info_10de_0028_1092_5a00 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_6a02 = + {0x1092, 0x6a02, pci_subsys_10de_0028_1092_6a02, 0}; +#undef pci_ss_info_1092_6a02 +#define pci_ss_info_1092_6a02 pci_ss_info_10de_0028_1092_6a02 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_7a02 = + {0x1092, 0x7a02, pci_subsys_10de_0028_1092_7a02, 0}; +#undef pci_ss_info_1092_7a02 +#define pci_ss_info_1092_7a02 pci_ss_info_10de_0028_1092_7a02 +static const pciSubsystemInfo pci_ss_info_10de_0028_10de_0005 = + {0x10de, 0x0005, pci_subsys_10de_0028_10de_0005, 0}; +#undef pci_ss_info_10de_0005 +#define pci_ss_info_10de_0005 pci_ss_info_10de_0028_10de_0005 +static const pciSubsystemInfo pci_ss_info_10de_0028_10de_000f = + {0x10de, 0x000f, pci_subsys_10de_0028_10de_000f, 0}; +#undef pci_ss_info_10de_000f +#define pci_ss_info_10de_000f pci_ss_info_10de_0028_10de_000f +static const pciSubsystemInfo pci_ss_info_10de_0028_1102_1020 = + {0x1102, 0x1020, pci_subsys_10de_0028_1102_1020, 0}; +#undef pci_ss_info_1102_1020 +#define pci_ss_info_1102_1020 pci_ss_info_10de_0028_1102_1020 +static const pciSubsystemInfo pci_ss_info_10de_0028_1102_1026 = + {0x1102, 0x1026, pci_subsys_10de_0028_1102_1026, 0}; +#undef pci_ss_info_1102_1026 +#define pci_ss_info_1102_1026 pci_ss_info_10de_0028_1102_1026 +static const pciSubsystemInfo pci_ss_info_10de_0028_14af_5810 = + {0x14af, 0x5810, pci_subsys_10de_0028_14af_5810, 0}; +#undef pci_ss_info_14af_5810 +#define pci_ss_info_14af_5810 pci_ss_info_10de_0028_14af_5810 +static const pciSubsystemInfo pci_ss_info_10de_0029_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_0029_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_0029_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_0029_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_0029_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_0029_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_0029_1043_0205 = + {0x1043, 0x0205, pci_subsys_10de_0029_1043_0205, 0}; +#undef pci_ss_info_1043_0205 +#define pci_ss_info_1043_0205 pci_ss_info_10de_0029_1043_0205 +static const pciSubsystemInfo pci_ss_info_10de_0029_1102_1021 = + {0x1102, 0x1021, pci_subsys_10de_0029_1102_1021, 0}; +#undef pci_ss_info_1102_1021 +#define pci_ss_info_1102_1021 pci_ss_info_10de_0029_1102_1021 +static const pciSubsystemInfo pci_ss_info_10de_0029_1102_1029 = + {0x1102, 0x1029, pci_subsys_10de_0029_1102_1029, 0}; +#undef pci_ss_info_1102_1029 +#define pci_ss_info_1102_1029 pci_ss_info_10de_0029_1102_1029 +static const pciSubsystemInfo pci_ss_info_10de_0029_1102_102f = + {0x1102, 0x102f, pci_subsys_10de_0029_1102_102f, 0}; +#undef pci_ss_info_1102_102f +#define pci_ss_info_1102_102f pci_ss_info_10de_0029_1102_102f +static const pciSubsystemInfo pci_ss_info_10de_0029_14af_5820 = + {0x14af, 0x5820, pci_subsys_10de_0029_14af_5820, 0}; +#undef pci_ss_info_14af_5820 +#define pci_ss_info_14af_5820 pci_ss_info_10de_0029_14af_5820 +static const pciSubsystemInfo pci_ss_info_10de_002c_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_002c_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_002c_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_002c_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_002c_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_002c_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_002c_1092_6820 = + {0x1092, 0x6820, pci_subsys_10de_002c_1092_6820, 0}; +#undef pci_ss_info_1092_6820 +#define pci_ss_info_1092_6820 pci_ss_info_10de_002c_1092_6820 +static const pciSubsystemInfo pci_ss_info_10de_002c_1102_1031 = + {0x1102, 0x1031, pci_subsys_10de_002c_1102_1031, 0}; +#undef pci_ss_info_1102_1031 +#define pci_ss_info_1102_1031 pci_ss_info_10de_002c_1102_1031 +static const pciSubsystemInfo pci_ss_info_10de_002c_1102_1034 = + {0x1102, 0x1034, pci_subsys_10de_002c_1102_1034, 0}; +#undef pci_ss_info_1102_1034 +#define pci_ss_info_1102_1034 pci_ss_info_10de_002c_1102_1034 +static const pciSubsystemInfo pci_ss_info_10de_002c_14af_5008 = + {0x14af, 0x5008, pci_subsys_10de_002c_14af_5008, 0}; +#undef pci_ss_info_14af_5008 +#define pci_ss_info_14af_5008 pci_ss_info_10de_002c_14af_5008 +static const pciSubsystemInfo pci_ss_info_10de_002d_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_002d_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_002d_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_002d_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_002d_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_002d_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_002d_1048_0c3a = + {0x1048, 0x0c3a, pci_subsys_10de_002d_1048_0c3a, 0}; +#undef pci_ss_info_1048_0c3a +#define pci_ss_info_1048_0c3a pci_ss_info_10de_002d_1048_0c3a +static const pciSubsystemInfo pci_ss_info_10de_002d_10de_001e = + {0x10de, 0x001e, pci_subsys_10de_002d_10de_001e, 0}; +#undef pci_ss_info_10de_001e +#define pci_ss_info_10de_001e pci_ss_info_10de_002d_10de_001e +static const pciSubsystemInfo pci_ss_info_10de_002d_1102_1023 = + {0x1102, 0x1023, pci_subsys_10de_002d_1102_1023, 0}; +#undef pci_ss_info_1102_1023 +#define pci_ss_info_1102_1023 pci_ss_info_10de_002d_1102_1023 +static const pciSubsystemInfo pci_ss_info_10de_002d_1102_1024 = + {0x1102, 0x1024, pci_subsys_10de_002d_1102_1024, 0}; +#undef pci_ss_info_1102_1024 +#define pci_ss_info_1102_1024 pci_ss_info_10de_002d_1102_1024 +static const pciSubsystemInfo pci_ss_info_10de_002d_1102_102c = + {0x1102, 0x102c, pci_subsys_10de_002d_1102_102c, 0}; +#undef pci_ss_info_1102_102c +#define pci_ss_info_1102_102c pci_ss_info_10de_002d_1102_102c +static const pciSubsystemInfo pci_ss_info_10de_002d_1462_8808 = + {0x1462, 0x8808, pci_subsys_10de_002d_1462_8808, 0}; +#undef pci_ss_info_1462_8808 +#define pci_ss_info_1462_8808 pci_ss_info_10de_002d_1462_8808 +static const pciSubsystemInfo pci_ss_info_10de_002d_1554_1041 = + {0x1554, 0x1041, pci_subsys_10de_002d_1554_1041, 0}; +#undef pci_ss_info_1554_1041 +#define pci_ss_info_1554_1041 pci_ss_info_10de_002d_1554_1041 +static const pciSubsystemInfo pci_ss_info_10de_0060_1043_80ad = + {0x1043, 0x80ad, pci_subsys_10de_0060_1043_80ad, 0}; +#undef pci_ss_info_1043_80ad +#define pci_ss_info_1043_80ad pci_ss_info_10de_0060_1043_80ad +static const pciSubsystemInfo pci_ss_info_10de_0067_1043_0c11 = + {0x1043, 0x0c11, pci_subsys_10de_0067_1043_0c11, 0}; +#undef pci_ss_info_1043_0c11 +#define pci_ss_info_1043_0c11 pci_ss_info_10de_0067_1043_0c11 +static const pciSubsystemInfo pci_ss_info_10de_0068_1043_0c11 = + {0x1043, 0x0c11, pci_subsys_10de_0068_1043_0c11, 0}; +#undef pci_ss_info_1043_0c11 +#define pci_ss_info_1043_0c11 pci_ss_info_10de_0068_1043_0c11 +static const pciSubsystemInfo pci_ss_info_10de_00a0_14af_5810 = + {0x14af, 0x5810, pci_subsys_10de_00a0_14af_5810, 0}; +#undef pci_ss_info_14af_5810 +#define pci_ss_info_14af_5810 pci_ss_info_10de_00a0_14af_5810 +static const pciSubsystemInfo pci_ss_info_10de_0100_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_0100_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_0100_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_0100_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_0100_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_0100_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_0100_1043_4008 = + {0x1043, 0x4008, pci_subsys_10de_0100_1043_4008, 0}; +#undef pci_ss_info_1043_4008 +#define pci_ss_info_1043_4008 pci_ss_info_10de_0100_1043_4008 +static const pciSubsystemInfo pci_ss_info_10de_0100_1043_4009 = + {0x1043, 0x4009, pci_subsys_10de_0100_1043_4009, 0}; +#undef pci_ss_info_1043_4009 +#define pci_ss_info_1043_4009 pci_ss_info_10de_0100_1043_4009 +static const pciSubsystemInfo pci_ss_info_10de_0100_1102_102d = + {0x1102, 0x102d, pci_subsys_10de_0100_1102_102d, 0}; +#undef pci_ss_info_1102_102d +#define pci_ss_info_1102_102d pci_ss_info_10de_0100_1102_102d +static const pciSubsystemInfo pci_ss_info_10de_0100_14af_5022 = + {0x14af, 0x5022, pci_subsys_10de_0100_14af_5022, 0}; +#undef pci_ss_info_14af_5022 +#define pci_ss_info_14af_5022 pci_ss_info_10de_0100_14af_5022 +static const pciSubsystemInfo pci_ss_info_10de_0101_1043_0202 = + {0x1043, 0x0202, pci_subsys_10de_0101_1043_0202, 0}; +#undef pci_ss_info_1043_0202 +#define pci_ss_info_1043_0202 pci_ss_info_10de_0101_1043_0202 +static const pciSubsystemInfo pci_ss_info_10de_0101_1043_400a = + {0x1043, 0x400a, pci_subsys_10de_0101_1043_400a, 0}; +#undef pci_ss_info_1043_400a +#define pci_ss_info_1043_400a pci_ss_info_10de_0101_1043_400a +static const pciSubsystemInfo pci_ss_info_10de_0101_1043_400b = + {0x1043, 0x400b, pci_subsys_10de_0101_1043_400b, 0}; +#undef pci_ss_info_1043_400b +#define pci_ss_info_1043_400b pci_ss_info_10de_0101_1043_400b +static const pciSubsystemInfo pci_ss_info_10de_0101_1102_102e = + {0x1102, 0x102e, pci_subsys_10de_0101_1102_102e, 0}; +#undef pci_ss_info_1102_102e +#define pci_ss_info_1102_102e pci_ss_info_10de_0101_1102_102e +static const pciSubsystemInfo pci_ss_info_10de_0101_14af_5021 = + {0x14af, 0x5021, pci_subsys_10de_0101_14af_5021, 0}; +#undef pci_ss_info_14af_5021 +#define pci_ss_info_14af_5021 pci_ss_info_10de_0101_14af_5021 +static const pciSubsystemInfo pci_ss_info_10de_0110_1043_4015 = + {0x1043, 0x4015, pci_subsys_10de_0110_1043_4015, 0}; +#undef pci_ss_info_1043_4015 +#define pci_ss_info_1043_4015 pci_ss_info_10de_0110_1043_4015 +static const pciSubsystemInfo pci_ss_info_10de_0110_1043_4031 = + {0x1043, 0x4031, pci_subsys_10de_0110_1043_4031, 0}; +#undef pci_ss_info_1043_4031 +#define pci_ss_info_1043_4031 pci_ss_info_10de_0110_1043_4031 +static const pciSubsystemInfo pci_ss_info_10de_0110_1462_8817 = + {0x1462, 0x8817, pci_subsys_10de_0110_1462_8817, 0}; +#undef pci_ss_info_1462_8817 +#define pci_ss_info_1462_8817 pci_ss_info_10de_0110_1462_8817 +static const pciSubsystemInfo pci_ss_info_10de_0110_14af_7102 = + {0x14af, 0x7102, pci_subsys_10de_0110_14af_7102, 0}; +#undef pci_ss_info_14af_7102 +#define pci_ss_info_14af_7102 pci_ss_info_10de_0110_14af_7102 +static const pciSubsystemInfo pci_ss_info_10de_0110_14af_7103 = + {0x14af, 0x7103, pci_subsys_10de_0110_14af_7103, 0}; +#undef pci_ss_info_14af_7103 +#define pci_ss_info_14af_7103 pci_ss_info_10de_0110_14af_7103 +static const pciSubsystemInfo pci_ss_info_10de_0150_1043_4016 = + {0x1043, 0x4016, pci_subsys_10de_0150_1043_4016, 0}; +#undef pci_ss_info_1043_4016 +#define pci_ss_info_1043_4016 pci_ss_info_10de_0150_1043_4016 +static const pciSubsystemInfo pci_ss_info_10de_0150_107d_2840 = + {0x107d, 0x2840, pci_subsys_10de_0150_107d_2840, 0}; +#undef pci_ss_info_107d_2840 +#define pci_ss_info_107d_2840 pci_ss_info_10de_0150_107d_2840 +static const pciSubsystemInfo pci_ss_info_10de_0150_1462_8831 = + {0x1462, 0x8831, pci_subsys_10de_0150_1462_8831, 0}; +#undef pci_ss_info_1462_8831 +#define pci_ss_info_1462_8831 pci_ss_info_10de_0150_1462_8831 +static const pciSubsystemInfo pci_ss_info_10de_0151_1043_405f = + {0x1043, 0x405f, pci_subsys_10de_0151_1043_405f, 0}; +#undef pci_ss_info_1043_405f +#define pci_ss_info_1043_405f pci_ss_info_10de_0151_1043_405f +static const pciSubsystemInfo pci_ss_info_10de_0152_1048_0c56 = + {0x1048, 0x0c56, pci_subsys_10de_0152_1048_0c56, 0}; +#undef pci_ss_info_1048_0c56 +#define pci_ss_info_1048_0c56 pci_ss_info_10de_0152_1048_0c56 +static const pciSubsystemInfo pci_ss_info_10de_0171_1462_8661 = + {0x1462, 0x8661, pci_subsys_10de_0171_1462_8661, 0}; +#undef pci_ss_info_1462_8661 +#define pci_ss_info_1462_8661 pci_ss_info_10de_0171_1462_8661 +static const pciSubsystemInfo pci_ss_info_10de_0171_1462_8730 = + {0x1462, 0x8730, pci_subsys_10de_0171_1462_8730, 0}; +#undef pci_ss_info_1462_8730 +#define pci_ss_info_1462_8730 pci_ss_info_10de_0171_1462_8730 +static const pciSubsystemInfo pci_ss_info_10de_0171_147b_8f00 = + {0x147b, 0x8f00, pci_subsys_10de_0171_147b_8f00, 0}; +#undef pci_ss_info_147b_8f00 +#define pci_ss_info_147b_8f00 pci_ss_info_10de_0171_147b_8f00 +static const pciSubsystemInfo pci_ss_info_10de_0200_1043_402f = + {0x1043, 0x402f, pci_subsys_10de_0200_1043_402f, 0}; +#undef pci_ss_info_1043_402f +#define pci_ss_info_1043_402f pci_ss_info_10de_0200_1043_402f +static const pciSubsystemInfo pci_ss_info_10de_0202_1043_405b = + {0x1043, 0x405b, pci_subsys_10de_0202_1043_405b, 0}; +#undef pci_ss_info_1043_405b +#define pci_ss_info_1043_405b pci_ss_info_10de_0202_1043_405b +static const pciSubsystemInfo pci_ss_info_10de_0202_1545_002f = + {0x1545, 0x002f, pci_subsys_10de_0202_1545_002f, 0}; +#undef pci_ss_info_1545_002f +#define pci_ss_info_1545_002f pci_ss_info_10de_0202_1545_002f +static const pciSubsystemInfo pci_ss_info_10de_0253_107d_2896 = + {0x107d, 0x2896, pci_subsys_10de_0253_107d_2896, 0}; +#undef pci_ss_info_107d_2896 +#define pci_ss_info_107d_2896 pci_ss_info_10de_0253_107d_2896 +static const pciSubsystemInfo pci_ss_info_10de_0253_147b_8f09 = + {0x147b, 0x8f09, pci_subsys_10de_0253_147b_8f09, 0}; +#undef pci_ss_info_147b_8f09 +#define pci_ss_info_147b_8f09 pci_ss_info_10de_0253_147b_8f09 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10e1_0391_10e1_0391 = + {0x10e1, 0x0391, pci_subsys_10e1_0391_10e1_0391, 0}; +#undef pci_ss_info_10e1_0391 +#define pci_ss_info_10e1_0391 pci_ss_info_10e1_0391_10e1_0391 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10ec_8029_10b8_2011 = + {0x10b8, 0x2011, pci_subsys_10ec_8029_10b8_2011, 0}; +#undef pci_ss_info_10b8_2011 +#define pci_ss_info_10b8_2011 pci_ss_info_10ec_8029_10b8_2011 +static const pciSubsystemInfo pci_ss_info_10ec_8029_10ec_8029 = + {0x10ec, 0x8029, pci_subsys_10ec_8029_10ec_8029, 0}; +#undef pci_ss_info_10ec_8029 +#define pci_ss_info_10ec_8029 pci_ss_info_10ec_8029_10ec_8029 +static const pciSubsystemInfo pci_ss_info_10ec_8029_1113_1208 = + {0x1113, 0x1208, pci_subsys_10ec_8029_1113_1208, 0}; +#undef pci_ss_info_1113_1208 +#define pci_ss_info_1113_1208 pci_ss_info_10ec_8029_1113_1208 +static const pciSubsystemInfo pci_ss_info_10ec_8029_1186_0300 = + {0x1186, 0x0300, pci_subsys_10ec_8029_1186_0300, 0}; +#undef pci_ss_info_1186_0300 +#define pci_ss_info_1186_0300 pci_ss_info_10ec_8029_1186_0300 +static const pciSubsystemInfo pci_ss_info_10ec_8029_1259_2400 = + {0x1259, 0x2400, pci_subsys_10ec_8029_1259_2400, 0}; +#undef pci_ss_info_1259_2400 +#define pci_ss_info_1259_2400 pci_ss_info_10ec_8029_1259_2400 +static const pciSubsystemInfo pci_ss_info_10ec_8129_10ec_8129 = + {0x10ec, 0x8129, pci_subsys_10ec_8129_10ec_8129, 0}; +#undef pci_ss_info_10ec_8129 +#define pci_ss_info_10ec_8129 pci_ss_info_10ec_8129_10ec_8129 +static const pciSubsystemInfo pci_ss_info_10ec_8138_10ec_8138 = + {0x10ec, 0x8138, pci_subsys_10ec_8138_10ec_8138, 0}; +#undef pci_ss_info_10ec_8138 +#define pci_ss_info_10ec_8138 pci_ss_info_10ec_8138_10ec_8138 +#endif +static const pciSubsystemInfo pci_ss_info_10ec_8139_1025_8920 = + {0x1025, 0x8920, pci_subsys_10ec_8139_1025_8920, 0}; +#undef pci_ss_info_1025_8920 +#define pci_ss_info_1025_8920 pci_ss_info_10ec_8139_1025_8920 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10ec_8139_1025_8921 = + {0x1025, 0x8921, pci_subsys_10ec_8139_1025_8921, 0}; +#undef pci_ss_info_1025_8921 +#define pci_ss_info_1025_8921 pci_ss_info_10ec_8139_1025_8921 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10ec_8139_10bd_0320 = + {0x10bd, 0x0320, pci_subsys_10ec_8139_10bd_0320, 0}; +#undef pci_ss_info_10bd_0320 +#define pci_ss_info_10bd_0320 pci_ss_info_10ec_8139_10bd_0320 +static const pciSubsystemInfo pci_ss_info_10ec_8139_10ec_8139 = + {0x10ec, 0x8139, pci_subsys_10ec_8139_10ec_8139, 0}; +#undef pci_ss_info_10ec_8139 +#define pci_ss_info_10ec_8139 pci_ss_info_10ec_8139_10ec_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1186_1300 = + {0x1186, 0x1300, pci_subsys_10ec_8139_1186_1300, 0}; +#undef pci_ss_info_1186_1300 +#define pci_ss_info_1186_1300 pci_ss_info_10ec_8139_1186_1300 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1186_1320 = + {0x1186, 0x1320, pci_subsys_10ec_8139_1186_1320, 0}; +#undef pci_ss_info_1186_1320 +#define pci_ss_info_1186_1320 pci_ss_info_10ec_8139_1186_1320 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1186_8139 = + {0x1186, 0x8139, pci_subsys_10ec_8139_1186_8139, 0}; +#undef pci_ss_info_1186_8139 +#define pci_ss_info_1186_8139 pci_ss_info_10ec_8139_1186_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_11f6_8139 = + {0x11f6, 0x8139, pci_subsys_10ec_8139_11f6_8139, 0}; +#undef pci_ss_info_11f6_8139 +#define pci_ss_info_11f6_8139 pci_ss_info_10ec_8139_11f6_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1259_2500 = + {0x1259, 0x2500, pci_subsys_10ec_8139_1259_2500, 0}; +#undef pci_ss_info_1259_2500 +#define pci_ss_info_1259_2500 pci_ss_info_10ec_8139_1259_2500 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1259_2503 = + {0x1259, 0x2503, pci_subsys_10ec_8139_1259_2503, 0}; +#undef pci_ss_info_1259_2503 +#define pci_ss_info_1259_2503 pci_ss_info_10ec_8139_1259_2503 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1429_d010 = + {0x1429, 0xd010, pci_subsys_10ec_8139_1429_d010, 0}; +#undef pci_ss_info_1429_d010 +#define pci_ss_info_1429_d010 pci_ss_info_10ec_8139_1429_d010 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1432_9130 = + {0x1432, 0x9130, pci_subsys_10ec_8139_1432_9130, 0}; +#undef pci_ss_info_1432_9130 +#define pci_ss_info_1432_9130 pci_ss_info_10ec_8139_1432_9130 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1436_8139 = + {0x1436, 0x8139, pci_subsys_10ec_8139_1436_8139, 0}; +#undef pci_ss_info_1436_8139 +#define pci_ss_info_1436_8139 pci_ss_info_10ec_8139_1436_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_146c_1439 = + {0x146c, 0x1439, pci_subsys_10ec_8139_146c_1439, 0}; +#undef pci_ss_info_146c_1439 +#define pci_ss_info_146c_1439 pci_ss_info_10ec_8139_146c_1439 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1489_6001 = + {0x1489, 0x6001, pci_subsys_10ec_8139_1489_6001, 0}; +#undef pci_ss_info_1489_6001 +#define pci_ss_info_1489_6001 pci_ss_info_10ec_8139_1489_6001 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1489_6002 = + {0x1489, 0x6002, pci_subsys_10ec_8139_1489_6002, 0}; +#undef pci_ss_info_1489_6002 +#define pci_ss_info_1489_6002 pci_ss_info_10ec_8139_1489_6002 +static const pciSubsystemInfo pci_ss_info_10ec_8139_149c_139a = + {0x149c, 0x139a, pci_subsys_10ec_8139_149c_139a, 0}; +#undef pci_ss_info_149c_139a +#define pci_ss_info_149c_139a pci_ss_info_10ec_8139_149c_139a +static const pciSubsystemInfo pci_ss_info_10ec_8139_149c_8139 = + {0x149c, 0x8139, pci_subsys_10ec_8139_149c_8139, 0}; +#undef pci_ss_info_149c_8139 +#define pci_ss_info_149c_8139 pci_ss_info_10ec_8139_149c_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_2646_0001 = + {0x2646, 0x0001, pci_subsys_10ec_8139_2646_0001, 0}; +#undef pci_ss_info_2646_0001 +#define pci_ss_info_2646_0001 pci_ss_info_10ec_8139_2646_0001 +static const pciSubsystemInfo pci_ss_info_10ec_8139_8e2e_7000 = + {0x8e2e, 0x7000, pci_subsys_10ec_8139_8e2e_7000, 0}; +#undef pci_ss_info_8e2e_7000 +#define pci_ss_info_8e2e_7000 pci_ss_info_10ec_8139_8e2e_7000 +static const pciSubsystemInfo pci_ss_info_10ec_8139_8e2e_7100 = + {0x8e2e, 0x7100, pci_subsys_10ec_8139_8e2e_7100, 0}; +#undef pci_ss_info_8e2e_7100 +#define pci_ss_info_8e2e_7100 pci_ss_info_10ec_8139_8e2e_7100 +static const pciSubsystemInfo pci_ss_info_10ec_8139_a0a0_0007 = + {0xa0a0, 0x0007, pci_subsys_10ec_8139_a0a0_0007, 0}; +#undef pci_ss_info_a0a0_0007 +#define pci_ss_info_a0a0_0007 pci_ss_info_10ec_8139_a0a0_0007 +static const pciSubsystemInfo pci_ss_info_10ec_8169_1371_434e = + {0x1371, 0x434e, pci_subsys_10ec_8169_1371_434e, 0}; +#undef pci_ss_info_1371_434e +#define pci_ss_info_1371_434e pci_ss_info_10ec_8169_1371_434e +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_0020 = + {0x1102, 0x0020, pci_subsys_1102_0002_1102_0020, 0}; +#undef pci_ss_info_1102_0020 +#define pci_ss_info_1102_0020 pci_ss_info_1102_0002_1102_0020 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_0021 = + {0x1102, 0x0021, pci_subsys_1102_0002_1102_0021, 0}; +#undef pci_ss_info_1102_0021 +#define pci_ss_info_1102_0021 pci_ss_info_1102_0002_1102_0021 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_002f = + {0x1102, 0x002f, pci_subsys_1102_0002_1102_002f, 0}; +#undef pci_ss_info_1102_002f +#define pci_ss_info_1102_002f pci_ss_info_1102_0002_1102_002f +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_4001 = + {0x1102, 0x4001, pci_subsys_1102_0002_1102_4001, 0}; +#undef pci_ss_info_1102_4001 +#define pci_ss_info_1102_4001 pci_ss_info_1102_0002_1102_4001 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8022 = + {0x1102, 0x8022, pci_subsys_1102_0002_1102_8022, 0}; +#undef pci_ss_info_1102_8022 +#define pci_ss_info_1102_8022 pci_ss_info_1102_0002_1102_8022 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8023 = + {0x1102, 0x8023, pci_subsys_1102_0002_1102_8023, 0}; +#undef pci_ss_info_1102_8023 +#define pci_ss_info_1102_8023 pci_ss_info_1102_0002_1102_8023 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8024 = + {0x1102, 0x8024, pci_subsys_1102_0002_1102_8024, 0}; +#undef pci_ss_info_1102_8024 +#define pci_ss_info_1102_8024 pci_ss_info_1102_0002_1102_8024 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8025 = + {0x1102, 0x8025, pci_subsys_1102_0002_1102_8025, 0}; +#undef pci_ss_info_1102_8025 +#define pci_ss_info_1102_8025 pci_ss_info_1102_0002_1102_8025 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8026 = + {0x1102, 0x8026, pci_subsys_1102_0002_1102_8026, 0}; +#undef pci_ss_info_1102_8026 +#define pci_ss_info_1102_8026 pci_ss_info_1102_0002_1102_8026 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8027 = + {0x1102, 0x8027, pci_subsys_1102_0002_1102_8027, 0}; +#undef pci_ss_info_1102_8027 +#define pci_ss_info_1102_8027 pci_ss_info_1102_0002_1102_8027 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8028 = + {0x1102, 0x8028, pci_subsys_1102_0002_1102_8028, 0}; +#undef pci_ss_info_1102_8028 +#define pci_ss_info_1102_8028 pci_ss_info_1102_0002_1102_8028 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8031 = + {0x1102, 0x8031, pci_subsys_1102_0002_1102_8031, 0}; +#undef pci_ss_info_1102_8031 +#define pci_ss_info_1102_8031 pci_ss_info_1102_0002_1102_8031 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8040 = + {0x1102, 0x8040, pci_subsys_1102_0002_1102_8040, 0}; +#undef pci_ss_info_1102_8040 +#define pci_ss_info_1102_8040 pci_ss_info_1102_0002_1102_8040 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8051 = + {0x1102, 0x8051, pci_subsys_1102_0002_1102_8051, 0}; +#undef pci_ss_info_1102_8051 +#define pci_ss_info_1102_8051 pci_ss_info_1102_0002_1102_8051 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8061 = + {0x1102, 0x8061, pci_subsys_1102_0002_1102_8061, 0}; +#undef pci_ss_info_1102_8061 +#define pci_ss_info_1102_8061 pci_ss_info_1102_0002_1102_8061 +static const pciSubsystemInfo pci_ss_info_1102_0004_1102_0051 = + {0x1102, 0x0051, pci_subsys_1102_0004_1102_0051, 0}; +#undef pci_ss_info_1102_0051 +#define pci_ss_info_1102_0051 pci_ss_info_1102_0004_1102_0051 +static const pciSubsystemInfo pci_ss_info_1102_0004_1102_0053 = + {0x1102, 0x0053, pci_subsys_1102_0004_1102_0053, 0}; +#undef pci_ss_info_1102_0053 +#define pci_ss_info_1102_0053 pci_ss_info_1102_0004_1102_0053 +static const pciSubsystemInfo pci_ss_info_1102_4001_1102_0010 = + {0x1102, 0x0010, pci_subsys_1102_4001_1102_0010, 0}; +#undef pci_ss_info_1102_0010 +#define pci_ss_info_1102_0010 pci_ss_info_1102_4001_1102_0010 +static const pciSubsystemInfo pci_ss_info_1102_7002_1102_0020 = + {0x1102, 0x0020, pci_subsys_1102_7002_1102_0020, 0}; +#undef pci_ss_info_1102_0020 +#define pci_ss_info_1102_0020 pci_ss_info_1102_7002_1102_0020 +static const pciSubsystemInfo pci_ss_info_1102_7003_1102_0040 = + {0x1102, 0x0040, pci_subsys_1102_7003_1102_0040, 0}; +#undef pci_ss_info_1102_0040 +#define pci_ss_info_1102_0040 pci_ss_info_1102_7003_1102_0040 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0001 = + {0x1103, 0x0001, pci_subsys_1103_0004_1103_0001, 0}; +#undef pci_ss_info_1103_0001 +#define pci_ss_info_1103_0001 pci_ss_info_1103_0004_1103_0001 +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0005 = + {0x1103, 0x0005, pci_subsys_1103_0004_1103_0005, 0}; +#undef pci_ss_info_1103_0005 +#define pci_ss_info_1103_0005 pci_ss_info_1103_0004_1103_0005 +#endif +static const pciSubsystemInfo pci_ss_info_1106_0305_1043_8033 = + {0x1043, 0x8033, pci_subsys_1106_0305_1043_8033, 0}; +#undef pci_ss_info_1043_8033 +#define pci_ss_info_1043_8033 pci_ss_info_1106_0305_1043_8033 +static const pciSubsystemInfo pci_ss_info_1106_0305_1043_803e = + {0x1043, 0x803e, pci_subsys_1106_0305_1043_803e, 0}; +#undef pci_ss_info_1043_803e +#define pci_ss_info_1043_803e pci_ss_info_1106_0305_1043_803e +static const pciSubsystemInfo pci_ss_info_1106_0305_1043_8042 = + {0x1043, 0x8042, pci_subsys_1106_0305_1043_8042, 0}; +#undef pci_ss_info_1043_8042 +#define pci_ss_info_1043_8042 pci_ss_info_1106_0305_1043_8042 +static const pciSubsystemInfo pci_ss_info_1106_0305_147b_a401 = + {0x147b, 0xa401, pci_subsys_1106_0305_147b_a401, 0}; +#undef pci_ss_info_147b_a401 +#define pci_ss_info_147b_a401 pci_ss_info_1106_0305_147b_a401 +static const pciSubsystemInfo pci_ss_info_1106_0571_1043_8052 = + {0x1043, 0x8052, pci_subsys_1106_0571_1043_8052, 0}; +#undef pci_ss_info_1043_8052 +#define pci_ss_info_1043_8052 pci_ss_info_1106_0571_1043_8052 +static const pciSubsystemInfo pci_ss_info_1106_0571_1106_0571 = + {0x1106, 0x0571, pci_subsys_1106_0571_1106_0571, 0}; +#undef pci_ss_info_1106_0571 +#define pci_ss_info_1106_0571 pci_ss_info_1106_0571_1106_0571 +static const pciSubsystemInfo pci_ss_info_1106_0571_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_0571_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_0571_1179_0001 +static const pciSubsystemInfo pci_ss_info_1106_0571_1458_5002 = + {0x1458, 0x5002, pci_subsys_1106_0571_1458_5002, 0}; +#undef pci_ss_info_1458_5002 +#define pci_ss_info_1458_5002 pci_ss_info_1106_0571_1458_5002 +static const pciSubsystemInfo pci_ss_info_1106_0586_1106_0000 = + {0x1106, 0x0000, pci_subsys_1106_0586_1106_0000, 0}; +#undef pci_ss_info_1106_0000 +#define pci_ss_info_1106_0000 pci_ss_info_1106_0586_1106_0000 +static const pciSubsystemInfo pci_ss_info_1106_0596_1106_0000 = + {0x1106, 0x0000, pci_subsys_1106_0596_1106_0000, 0}; +#undef pci_ss_info_1106_0000 +#define pci_ss_info_1106_0000 pci_ss_info_1106_0596_1106_0000 +static const pciSubsystemInfo pci_ss_info_1106_0596_1458_0596 = + {0x1458, 0x0596, pci_subsys_1106_0596_1458_0596, 0}; +#undef pci_ss_info_1458_0596 +#define pci_ss_info_1458_0596 pci_ss_info_1106_0596_1458_0596 +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_8033 = + {0x1043, 0x8033, pci_subsys_1106_0686_1043_8033, 0}; +#undef pci_ss_info_1043_8033 +#define pci_ss_info_1043_8033 pci_ss_info_1106_0686_1043_8033 +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_803e = + {0x1043, 0x803e, pci_subsys_1106_0686_1043_803e, 0}; +#undef pci_ss_info_1043_803e +#define pci_ss_info_1043_803e pci_ss_info_1106_0686_1043_803e +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_8040 = + {0x1043, 0x8040, pci_subsys_1106_0686_1043_8040, 0}; +#undef pci_ss_info_1043_8040 +#define pci_ss_info_1043_8040 pci_ss_info_1106_0686_1043_8040 +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_8042 = + {0x1043, 0x8042, pci_subsys_1106_0686_1043_8042, 0}; +#undef pci_ss_info_1043_8042 +#define pci_ss_info_1043_8042 pci_ss_info_1106_0686_1043_8042 +static const pciSubsystemInfo pci_ss_info_1106_0686_1106_0000 = + {0x1106, 0x0000, pci_subsys_1106_0686_1106_0000, 0}; +#undef pci_ss_info_1106_0000 +#define pci_ss_info_1106_0000 pci_ss_info_1106_0686_1106_0000 +static const pciSubsystemInfo pci_ss_info_1106_0686_1106_0686 = + {0x1106, 0x0686, pci_subsys_1106_0686_1106_0686, 0}; +#undef pci_ss_info_1106_0686 +#define pci_ss_info_1106_0686 pci_ss_info_1106_0686_1106_0686 +static const pciSubsystemInfo pci_ss_info_1106_0686_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_0686_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_0686_1179_0001 +static const pciSubsystemInfo pci_ss_info_1106_0686_147b_a702 = + {0x147b, 0xa702, pci_subsys_1106_0686_147b_a702, 0}; +#undef pci_ss_info_147b_a702 +#define pci_ss_info_147b_a702 pci_ss_info_1106_0686_147b_a702 +static const pciSubsystemInfo pci_ss_info_1106_0691_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_0691_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_0691_1179_0001 +static const pciSubsystemInfo pci_ss_info_1106_0691_1458_0691 = + {0x1458, 0x0691, pci_subsys_1106_0691_1458_0691, 0}; +#undef pci_ss_info_1458_0691 +#define pci_ss_info_1458_0691 pci_ss_info_1106_0691_1458_0691 +static const pciSubsystemInfo pci_ss_info_1106_3038_0925_1234 = + {0x0925, 0x1234, pci_subsys_1106_3038_0925_1234, 0}; +#undef pci_ss_info_0925_1234 +#define pci_ss_info_0925_1234 pci_ss_info_1106_3038_0925_1234 +static const pciSubsystemInfo pci_ss_info_1106_3038_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_3038_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_3038_1179_0001 +static const pciSubsystemInfo pci_ss_info_1106_3043_10bd_0000 = + {0x10bd, 0x0000, pci_subsys_1106_3043_10bd_0000, 0}; +#undef pci_ss_info_10bd_0000 +#define pci_ss_info_10bd_0000 pci_ss_info_1106_3043_10bd_0000 +static const pciSubsystemInfo pci_ss_info_1106_3043_1106_0100 = + {0x1106, 0x0100, pci_subsys_1106_3043_1106_0100, 0}; +#undef pci_ss_info_1106_0100 +#define pci_ss_info_1106_0100 pci_ss_info_1106_3043_1106_0100 +static const pciSubsystemInfo pci_ss_info_1106_3043_1186_1400 = + {0x1186, 0x1400, pci_subsys_1106_3043_1186_1400, 0}; +#undef pci_ss_info_1186_1400 +#define pci_ss_info_1186_1400 pci_ss_info_1106_3043_1186_1400 +static const pciSubsystemInfo pci_ss_info_1106_3057_1043_8033 = + {0x1043, 0x8033, pci_subsys_1106_3057_1043_8033, 0}; +#undef pci_ss_info_1043_8033 +#define pci_ss_info_1043_8033 pci_ss_info_1106_3057_1043_8033 +static const pciSubsystemInfo pci_ss_info_1106_3057_1043_803e = + {0x1043, 0x803e, pci_subsys_1106_3057_1043_803e, 0}; +#undef pci_ss_info_1043_803e +#define pci_ss_info_1043_803e pci_ss_info_1106_3057_1043_803e +static const pciSubsystemInfo pci_ss_info_1106_3057_1043_8040 = + {0x1043, 0x8040, pci_subsys_1106_3057_1043_8040, 0}; +#undef pci_ss_info_1043_8040 +#define pci_ss_info_1043_8040 pci_ss_info_1106_3057_1043_8040 +static const pciSubsystemInfo pci_ss_info_1106_3057_1043_8042 = + {0x1043, 0x8042, pci_subsys_1106_3057_1043_8042, 0}; +#undef pci_ss_info_1043_8042 +#define pci_ss_info_1043_8042 pci_ss_info_1106_3057_1043_8042 +static const pciSubsystemInfo pci_ss_info_1106_3057_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_3057_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_3057_1179_0001 +static const pciSubsystemInfo pci_ss_info_1106_3058_0e11_b194 = + {0x0e11, 0xb194, pci_subsys_1106_3058_0e11_b194, 0}; +#undef pci_ss_info_0e11_b194 +#define pci_ss_info_0e11_b194 pci_ss_info_1106_3058_0e11_b194 +static const pciSubsystemInfo pci_ss_info_1106_3058_1106_4511 = + {0x1106, 0x4511, pci_subsys_1106_3058_1106_4511, 0}; +#undef pci_ss_info_1106_4511 +#define pci_ss_info_1106_4511 pci_ss_info_1106_3058_1106_4511 +static const pciSubsystemInfo pci_ss_info_1106_3058_1458_7600 = + {0x1458, 0x7600, pci_subsys_1106_3058_1458_7600, 0}; +#undef pci_ss_info_1458_7600 +#define pci_ss_info_1458_7600 pci_ss_info_1106_3058_1458_7600 +static const pciSubsystemInfo pci_ss_info_1106_3058_1462_3091 = + {0x1462, 0x3091, pci_subsys_1106_3058_1462_3091, 0}; +#undef pci_ss_info_1462_3091 +#define pci_ss_info_1462_3091 pci_ss_info_1106_3058_1462_3091 +static const pciSubsystemInfo pci_ss_info_1106_3058_15dd_7609 = + {0x15dd, 0x7609, pci_subsys_1106_3058_15dd_7609, 0}; +#undef pci_ss_info_15dd_7609 +#define pci_ss_info_15dd_7609 pci_ss_info_1106_3058_15dd_7609 +static const pciSubsystemInfo pci_ss_info_1106_3059_1458_a002 = + {0x1458, 0xa002, pci_subsys_1106_3059_1458_a002, 0}; +#undef pci_ss_info_1458_a002 +#define pci_ss_info_1458_a002 pci_ss_info_1106_3059_1458_a002 +static const pciSubsystemInfo pci_ss_info_1106_3065_1106_0102 = + {0x1106, 0x0102, pci_subsys_1106_3065_1106_0102, 0}; +#undef pci_ss_info_1106_0102 +#define pci_ss_info_1106_0102 pci_ss_info_1106_3065_1106_0102 +static const pciSubsystemInfo pci_ss_info_1106_3065_1186_1400 = + {0x1186, 0x1400, pci_subsys_1106_3065_1186_1400, 0}; +#undef pci_ss_info_1186_1400 +#define pci_ss_info_1186_1400 pci_ss_info_1106_3065_1186_1400 +static const pciSubsystemInfo pci_ss_info_1106_3065_1186_1401 = + {0x1186, 0x1401, pci_subsys_1106_3065_1186_1401, 0}; +#undef pci_ss_info_1186_1401 +#define pci_ss_info_1186_1401 pci_ss_info_1106_3065_1186_1401 +static const pciSubsystemInfo pci_ss_info_1106_3074_1043_8052 = + {0x1043, 0x8052, pci_subsys_1106_3074_1043_8052, 0}; +#undef pci_ss_info_1043_8052 +#define pci_ss_info_1043_8052 pci_ss_info_1106_3074_1043_8052 +static const pciSubsystemInfo pci_ss_info_1106_3099_1043_8064 = + {0x1043, 0x8064, pci_subsys_1106_3099_1043_8064, 0}; +#undef pci_ss_info_1043_8064 +#define pci_ss_info_1043_8064 pci_ss_info_1106_3099_1043_8064 +static const pciSubsystemInfo pci_ss_info_1106_3099_1043_807f = + {0x1043, 0x807f, pci_subsys_1106_3099_1043_807f, 0}; +#undef pci_ss_info_1043_807f +#define pci_ss_info_1043_807f pci_ss_info_1106_3099_1043_807f +static const pciSubsystemInfo pci_ss_info_1106_3104_1458_5004 = + {0x1458, 0x5004, pci_subsys_1106_3104_1458_5004, 0}; +#undef pci_ss_info_1458_5004 +#define pci_ss_info_1458_5004 pci_ss_info_1106_3104_1458_5004 +static const pciSubsystemInfo pci_ss_info_1106_3177_1458_5001 = + {0x1458, 0x5001, pci_subsys_1106_3177_1458_5001, 0}; +#undef pci_ss_info_1458_5001 +#define pci_ss_info_1458_5001 pci_ss_info_1106_3177_1458_5001 +static const pciSubsystemInfo pci_ss_info_1106_3189_1458_5000 = + {0x1458, 0x5000, pci_subsys_1106_3189_1458_5000, 0}; +#undef pci_ss_info_1458_5000 +#define pci_ss_info_1458_5000 pci_ss_info_1106_3189_1458_5000 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1113_1211_103c_1207 = + {0x103c, 0x1207, pci_subsys_1113_1211_103c_1207, 0}; +#undef pci_ss_info_103c_1207 +#define pci_ss_info_103c_1207 pci_ss_info_1113_1211_103c_1207 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1113_1211_1113_1211 = + {0x1113, 0x1211, pci_subsys_1113_1211_1113_1211, 0}; +#undef pci_ss_info_1113_1211 +#define pci_ss_info_1113_1211 pci_ss_info_1113_1211_1113_1211 +static const pciSubsystemInfo pci_ss_info_1113_1216_111a_1020 = + {0x111a, 0x1020, pci_subsys_1113_1216_111a_1020, 0}; +#undef pci_ss_info_111a_1020 +#define pci_ss_info_111a_1020 pci_ss_info_1113_1216_111a_1020 +static const pciSubsystemInfo pci_ss_info_1113_9211_1113_9211 = + {0x1113, 0x9211, pci_subsys_1113_9211_1113_9211, 0}; +#undef pci_ss_info_1113_9211 +#define pci_ss_info_1113_9211 pci_ss_info_1113_9211_1113_9211 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_111a_0003_111a_0000 = + {0x111a, 0x0000, pci_subsys_111a_0003_111a_0000, 0}; +#undef pci_ss_info_111a_0000 +#define pci_ss_info_111a_0000 pci_ss_info_111a_0003_111a_0000 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0001 = + {0x111a, 0x0001, pci_subsys_111a_0005_111a_0001, 0}; +#undef pci_ss_info_111a_0001 +#define pci_ss_info_111a_0001 pci_ss_info_111a_0005_111a_0001 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0009 = + {0x111a, 0x0009, pci_subsys_111a_0005_111a_0009, 0}; +#undef pci_ss_info_111a_0009 +#define pci_ss_info_111a_0009 pci_ss_info_111a_0005_111a_0009 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0101 = + {0x111a, 0x0101, pci_subsys_111a_0005_111a_0101, 0}; +#undef pci_ss_info_111a_0101 +#define pci_ss_info_111a_0101 pci_ss_info_111a_0005_111a_0101 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0109 = + {0x111a, 0x0109, pci_subsys_111a_0005_111a_0109, 0}; +#undef pci_ss_info_111a_0109 +#define pci_ss_info_111a_0109 pci_ss_info_111a_0005_111a_0109 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0809 = + {0x111a, 0x0809, pci_subsys_111a_0005_111a_0809, 0}; +#undef pci_ss_info_111a_0809 +#define pci_ss_info_111a_0809 pci_ss_info_111a_0005_111a_0809 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0909 = + {0x111a, 0x0909, pci_subsys_111a_0005_111a_0909, 0}; +#undef pci_ss_info_111a_0909 +#define pci_ss_info_111a_0909 pci_ss_info_111a_0005_111a_0909 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0a09 = + {0x111a, 0x0a09, pci_subsys_111a_0005_111a_0a09, 0}; +#undef pci_ss_info_111a_0a09 +#define pci_ss_info_111a_0a09 pci_ss_info_111a_0005_111a_0a09 +static const pciSubsystemInfo pci_ss_info_111a_0007_111a_1001 = + {0x111a, 0x1001, pci_subsys_111a_0007_111a_1001, 0}; +#undef pci_ss_info_111a_1001 +#define pci_ss_info_111a_1001 pci_ss_info_111a_0007_111a_1001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1127_0400_1127_0400 = + {0x1127, 0x0400, pci_subsys_1127_0400_1127_0400, 0}; +#undef pci_ss_info_1127_0400 +#define pci_ss_info_1127_0400 pci_ss_info_1127_0400_1127_0400 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1131_7146_114b_2003 = + {0x114b, 0x2003, pci_subsys_1131_7146_114b_2003, 0}; +#undef pci_ss_info_114b_2003 +#define pci_ss_info_114b_2003 pci_ss_info_1131_7146_114b_2003 +static const pciSubsystemInfo pci_ss_info_1131_7146_11bd_0006 = + {0x11bd, 0x0006, pci_subsys_1131_7146_11bd_0006, 0}; +#undef pci_ss_info_11bd_0006 +#define pci_ss_info_11bd_0006 pci_ss_info_1131_7146_11bd_0006 +static const pciSubsystemInfo pci_ss_info_1131_7146_11bd_000a = + {0x11bd, 0x000a, pci_subsys_1131_7146_11bd_000a, 0}; +#undef pci_ss_info_11bd_000a +#define pci_ss_info_11bd_000a pci_ss_info_1131_7146_11bd_000a +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1133_e001_1133_e001 = + {0x1133, 0xe001, pci_subsys_1133_e001_1133_e001, 0}; +#undef pci_ss_info_1133_e001 +#define pci_ss_info_1133_e001 pci_ss_info_1133_e001_1133_e001 +static const pciSubsystemInfo pci_ss_info_1133_e002_1133_e002 = + {0x1133, 0xe002, pci_subsys_1133_e002_1133_e002, 0}; +#undef pci_ss_info_1133_e002 +#define pci_ss_info_1133_e002 pci_ss_info_1133_e002_1133_e002 +static const pciSubsystemInfo pci_ss_info_1133_e003_1133_e003 = + {0x1133, 0xe003, pci_subsys_1133_e003_1133_e003, 0}; +#undef pci_ss_info_1133_e003 +#define pci_ss_info_1133_e003 pci_ss_info_1133_e003_1133_e003 +static const pciSubsystemInfo pci_ss_info_1133_e004_1133_e004 = + {0x1133, 0xe004, pci_subsys_1133_e004_1133_e004, 0}; +#undef pci_ss_info_1133_e004 +#define pci_ss_info_1133_e004 pci_ss_info_1133_e004_1133_e004 +static const pciSubsystemInfo pci_ss_info_1133_e005_1133_e005 = + {0x1133, 0xe005, pci_subsys_1133_e005_1133_e005, 0}; +#undef pci_ss_info_1133_e005 +#define pci_ss_info_1133_e005 pci_ss_info_1133_e005_1133_e005 +static const pciSubsystemInfo pci_ss_info_1133_e010_1133_e010 = + {0x1133, 0xe010, pci_subsys_1133_e010_1133_e010, 0}; +#undef pci_ss_info_1133_e010 +#define pci_ss_info_1133_e010 pci_ss_info_1133_e010_1133_e010 +static const pciSubsystemInfo pci_ss_info_1133_e012_1133_e012 = + {0x1133, 0xe012, pci_subsys_1133_e012_1133_e012, 0}; +#undef pci_ss_info_1133_e012 +#define pci_ss_info_1133_e012 pci_ss_info_1133_e012_1133_e012 +static const pciSubsystemInfo pci_ss_info_1133_e014_1133_e014 = + {0x1133, 0xe014, pci_subsys_1133_e014_1133_e014, 0}; +#undef pci_ss_info_1133_e014 +#define pci_ss_info_1133_e014 pci_ss_info_1133_e014_1133_e014 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03b = + {0x0e11, 0xb03b, pci_subsys_1148_4000_0e11_b03b, 0}; +#undef pci_ss_info_0e11_b03b +#define pci_ss_info_0e11_b03b pci_ss_info_1148_4000_0e11_b03b +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03c = + {0x0e11, 0xb03c, pci_subsys_1148_4000_0e11_b03c, 0}; +#undef pci_ss_info_0e11_b03c +#define pci_ss_info_0e11_b03c pci_ss_info_1148_4000_0e11_b03c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03d = + {0x0e11, 0xb03d, pci_subsys_1148_4000_0e11_b03d, 0}; +#undef pci_ss_info_0e11_b03d +#define pci_ss_info_0e11_b03d pci_ss_info_1148_4000_0e11_b03d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03e = + {0x0e11, 0xb03e, pci_subsys_1148_4000_0e11_b03e, 0}; +#undef pci_ss_info_0e11_b03e +#define pci_ss_info_0e11_b03e pci_ss_info_1148_4000_0e11_b03e +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03f = + {0x0e11, 0xb03f, pci_subsys_1148_4000_0e11_b03f, 0}; +#undef pci_ss_info_0e11_b03f +#define pci_ss_info_0e11_b03f pci_ss_info_1148_4000_0e11_b03f +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5521 = + {0x1148, 0x5521, pci_subsys_1148_4000_1148_5521, 0}; +#undef pci_ss_info_1148_5521 +#define pci_ss_info_1148_5521 pci_ss_info_1148_4000_1148_5521 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5522 = + {0x1148, 0x5522, pci_subsys_1148_4000_1148_5522, 0}; +#undef pci_ss_info_1148_5522 +#define pci_ss_info_1148_5522 pci_ss_info_1148_4000_1148_5522 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5541 = + {0x1148, 0x5541, pci_subsys_1148_4000_1148_5541, 0}; +#undef pci_ss_info_1148_5541 +#define pci_ss_info_1148_5541 pci_ss_info_1148_4000_1148_5541 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5543 = + {0x1148, 0x5543, pci_subsys_1148_4000_1148_5543, 0}; +#undef pci_ss_info_1148_5543 +#define pci_ss_info_1148_5543 pci_ss_info_1148_4000_1148_5543 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5544 = + {0x1148, 0x5544, pci_subsys_1148_4000_1148_5544, 0}; +#undef pci_ss_info_1148_5544 +#define pci_ss_info_1148_5544 pci_ss_info_1148_4000_1148_5544 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5821 = + {0x1148, 0x5821, pci_subsys_1148_4000_1148_5821, 0}; +#undef pci_ss_info_1148_5821 +#define pci_ss_info_1148_5821 pci_ss_info_1148_4000_1148_5821 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5822 = + {0x1148, 0x5822, pci_subsys_1148_4000_1148_5822, 0}; +#undef pci_ss_info_1148_5822 +#define pci_ss_info_1148_5822 pci_ss_info_1148_4000_1148_5822 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5841 = + {0x1148, 0x5841, pci_subsys_1148_4000_1148_5841, 0}; +#undef pci_ss_info_1148_5841 +#define pci_ss_info_1148_5841 pci_ss_info_1148_4000_1148_5841 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5843 = + {0x1148, 0x5843, pci_subsys_1148_4000_1148_5843, 0}; +#undef pci_ss_info_1148_5843 +#define pci_ss_info_1148_5843 pci_ss_info_1148_4000_1148_5843 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5844 = + {0x1148, 0x5844, pci_subsys_1148_4000_1148_5844, 0}; +#undef pci_ss_info_1148_5844 +#define pci_ss_info_1148_5844 pci_ss_info_1148_4000_1148_5844 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9821 = + {0x1148, 0x9821, pci_subsys_1148_4300_1148_9821, 0}; +#undef pci_ss_info_1148_9821 +#define pci_ss_info_1148_9821 pci_ss_info_1148_4300_1148_9821 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9822 = + {0x1148, 0x9822, pci_subsys_1148_4300_1148_9822, 0}; +#undef pci_ss_info_1148_9822 +#define pci_ss_info_1148_9822 pci_ss_info_1148_4300_1148_9822 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9841 = + {0x1148, 0x9841, pci_subsys_1148_4300_1148_9841, 0}; +#undef pci_ss_info_1148_9841 +#define pci_ss_info_1148_9841 pci_ss_info_1148_4300_1148_9841 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9842 = + {0x1148, 0x9842, pci_subsys_1148_4300_1148_9842, 0}; +#undef pci_ss_info_1148_9842 +#define pci_ss_info_1148_9842 pci_ss_info_1148_4300_1148_9842 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9843 = + {0x1148, 0x9843, pci_subsys_1148_4300_1148_9843, 0}; +#undef pci_ss_info_1148_9843 +#define pci_ss_info_1148_9843 pci_ss_info_1148_4300_1148_9843 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9844 = + {0x1148, 0x9844, pci_subsys_1148_4300_1148_9844, 0}; +#undef pci_ss_info_1148_9844 +#define pci_ss_info_1148_9844 pci_ss_info_1148_4300_1148_9844 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9861 = + {0x1148, 0x9861, pci_subsys_1148_4300_1148_9861, 0}; +#undef pci_ss_info_1148_9861 +#define pci_ss_info_1148_9861 pci_ss_info_1148_4300_1148_9861 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9862 = + {0x1148, 0x9862, pci_subsys_1148_4300_1148_9862, 0}; +#undef pci_ss_info_1148_9862 +#define pci_ss_info_1148_9862 pci_ss_info_1148_4300_1148_9862 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9871 = + {0x1148, 0x9871, pci_subsys_1148_4300_1148_9871, 0}; +#undef pci_ss_info_1148_9871 +#define pci_ss_info_1148_9871 pci_ss_info_1148_4300_1148_9871 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9872 = + {0x1148, 0x9872, pci_subsys_1148_4300_1148_9872, 0}; +#undef pci_ss_info_1148_9872 +#define pci_ss_info_1148_9872 pci_ss_info_1148_4300_1148_9872 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2970 = + {0x1259, 0x2970, pci_subsys_1148_4300_1259_2970, 0}; +#undef pci_ss_info_1259_2970 +#define pci_ss_info_1259_2970 pci_ss_info_1148_4300_1259_2970 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2972 = + {0x1259, 0x2972, pci_subsys_1148_4300_1259_2972, 0}; +#undef pci_ss_info_1259_2972 +#define pci_ss_info_1259_2972 pci_ss_info_1148_4300_1259_2972 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2975 = + {0x1259, 0x2975, pci_subsys_1148_4300_1259_2975, 0}; +#undef pci_ss_info_1259_2975 +#define pci_ss_info_1259_2975 pci_ss_info_1148_4300_1259_2975 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2977 = + {0x1259, 0x2977, pci_subsys_1148_4300_1259_2977, 0}; +#undef pci_ss_info_1259_2977 +#define pci_ss_info_1259_2977 pci_ss_info_1148_4300_1259_2977 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5021 = + {0x1148, 0x5021, pci_subsys_1148_4320_1148_5021, 0}; +#undef pci_ss_info_1148_5021 +#define pci_ss_info_1148_5021 pci_ss_info_1148_4320_1148_5021 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5041 = + {0x1148, 0x5041, pci_subsys_1148_4320_1148_5041, 0}; +#undef pci_ss_info_1148_5041 +#define pci_ss_info_1148_5041 pci_ss_info_1148_4320_1148_5041 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5043 = + {0x1148, 0x5043, pci_subsys_1148_4320_1148_5043, 0}; +#undef pci_ss_info_1148_5043 +#define pci_ss_info_1148_5043 pci_ss_info_1148_4320_1148_5043 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5051 = + {0x1148, 0x5051, pci_subsys_1148_4320_1148_5051, 0}; +#undef pci_ss_info_1148_5051 +#define pci_ss_info_1148_5051 pci_ss_info_1148_4320_1148_5051 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5061 = + {0x1148, 0x5061, pci_subsys_1148_4320_1148_5061, 0}; +#undef pci_ss_info_1148_5061 +#define pci_ss_info_1148_5061 pci_ss_info_1148_4320_1148_5061 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5071 = + {0x1148, 0x5071, pci_subsys_1148_4320_1148_5071, 0}; +#undef pci_ss_info_1148_5071 +#define pci_ss_info_1148_5071 pci_ss_info_1148_4320_1148_5071 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_9521 = + {0x1148, 0x9521, pci_subsys_1148_4320_1148_9521, 0}; +#undef pci_ss_info_1148_9521 +#define pci_ss_info_1148_9521 pci_ss_info_1148_4320_1148_9521 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_114f_001d_114f_0050 = + {0x114f, 0x0050, pci_subsys_114f_001d_114f_0050, 0}; +#undef pci_ss_info_114f_0050 +#define pci_ss_info_114f_0050 pci_ss_info_114f_001d_114f_0050 +static const pciSubsystemInfo pci_ss_info_114f_001d_114f_0051 = + {0x114f, 0x0051, pci_subsys_114f_001d_114f_0051, 0}; +#undef pci_ss_info_114f_0051 +#define pci_ss_info_114f_0051 pci_ss_info_114f_001d_114f_0051 +static const pciSubsystemInfo pci_ss_info_114f_001d_114f_0052 = + {0x114f, 0x0052, pci_subsys_114f_001d_114f_0052, 0}; +#undef pci_ss_info_114f_0052 +#define pci_ss_info_114f_0052 pci_ss_info_114f_001d_114f_0052 +static const pciSubsystemInfo pci_ss_info_114f_001d_114f_0053 = + {0x114f, 0x0053, pci_subsys_114f_001d_114f_0053, 0}; +#undef pci_ss_info_114f_0053 +#define pci_ss_info_114f_0053 pci_ss_info_114f_001d_114f_0053 +static const pciSubsystemInfo pci_ss_info_114f_0024_114f_0030 = + {0x114f, 0x0030, pci_subsys_114f_0024_114f_0030, 0}; +#undef pci_ss_info_114f_0030 +#define pci_ss_info_114f_0030 pci_ss_info_114f_0024_114f_0030 +static const pciSubsystemInfo pci_ss_info_114f_0024_114f_0031 = + {0x114f, 0x0031, pci_subsys_114f_0024_114f_0031, 0}; +#undef pci_ss_info_114f_0031 +#define pci_ss_info_114f_0031 pci_ss_info_114f_0024_114f_0031 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_115d_0003_1014_0181 = + {0x1014, 0x0181, pci_subsys_115d_0003_1014_0181, 0}; +#undef pci_ss_info_1014_0181 +#define pci_ss_info_1014_0181 pci_ss_info_115d_0003_1014_0181 +static const pciSubsystemInfo pci_ss_info_115d_0003_1014_1181 = + {0x1014, 0x1181, pci_subsys_115d_0003_1014_1181, 0}; +#undef pci_ss_info_1014_1181 +#define pci_ss_info_1014_1181 pci_ss_info_115d_0003_1014_1181 +static const pciSubsystemInfo pci_ss_info_115d_0003_1014_8181 = + {0x1014, 0x8181, pci_subsys_115d_0003_1014_8181, 0}; +#undef pci_ss_info_1014_8181 +#define pci_ss_info_1014_8181 pci_ss_info_115d_0003_1014_8181 +static const pciSubsystemInfo pci_ss_info_115d_0003_1014_9181 = + {0x1014, 0x9181, pci_subsys_115d_0003_1014_9181, 0}; +#undef pci_ss_info_1014_9181 +#define pci_ss_info_1014_9181 pci_ss_info_115d_0003_1014_9181 +static const pciSubsystemInfo pci_ss_info_115d_0003_115d_0181 = + {0x115d, 0x0181, pci_subsys_115d_0003_115d_0181, 0}; +#undef pci_ss_info_115d_0181 +#define pci_ss_info_115d_0181 pci_ss_info_115d_0003_115d_0181 +static const pciSubsystemInfo pci_ss_info_115d_0003_115d_1181 = + {0x115d, 0x1181, pci_subsys_115d_0003_115d_1181, 0}; +#undef pci_ss_info_115d_1181 +#define pci_ss_info_115d_1181 pci_ss_info_115d_0003_115d_1181 +static const pciSubsystemInfo pci_ss_info_115d_0003_1179_0181 = + {0x1179, 0x0181, pci_subsys_115d_0003_1179_0181, 0}; +#undef pci_ss_info_1179_0181 +#define pci_ss_info_1179_0181 pci_ss_info_115d_0003_1179_0181 +#endif +static const pciSubsystemInfo pci_ss_info_115d_0003_8086_8181 = + {0x8086, 0x8181, pci_subsys_115d_0003_8086_8181, 0}; +#undef pci_ss_info_8086_8181 +#define pci_ss_info_8086_8181 pci_ss_info_115d_0003_8086_8181 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_115d_0003_8086_9181 = + {0x8086, 0x9181, pci_subsys_115d_0003_8086_9181, 0}; +#undef pci_ss_info_8086_9181 +#define pci_ss_info_8086_9181 pci_ss_info_115d_0003_8086_9181 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_115d_0005_1014_0182 = + {0x1014, 0x0182, pci_subsys_115d_0005_1014_0182, 0}; +#undef pci_ss_info_1014_0182 +#define pci_ss_info_1014_0182 pci_ss_info_115d_0005_1014_0182 +static const pciSubsystemInfo pci_ss_info_115d_0005_1014_1182 = + {0x1014, 0x1182, pci_subsys_115d_0005_1014_1182, 0}; +#undef pci_ss_info_1014_1182 +#define pci_ss_info_1014_1182 pci_ss_info_115d_0005_1014_1182 +static const pciSubsystemInfo pci_ss_info_115d_0005_115d_0182 = + {0x115d, 0x0182, pci_subsys_115d_0005_115d_0182, 0}; +#undef pci_ss_info_115d_0182 +#define pci_ss_info_115d_0182 pci_ss_info_115d_0005_115d_0182 +static const pciSubsystemInfo pci_ss_info_115d_0005_115d_1182 = + {0x115d, 0x1182, pci_subsys_115d_0005_115d_1182, 0}; +#undef pci_ss_info_115d_1182 +#define pci_ss_info_115d_1182 pci_ss_info_115d_0005_115d_1182 +static const pciSubsystemInfo pci_ss_info_115d_0007_1014_0182 = + {0x1014, 0x0182, pci_subsys_115d_0007_1014_0182, 0}; +#undef pci_ss_info_1014_0182 +#define pci_ss_info_1014_0182 pci_ss_info_115d_0007_1014_0182 +static const pciSubsystemInfo pci_ss_info_115d_0007_1014_1182 = + {0x1014, 0x1182, pci_subsys_115d_0007_1014_1182, 0}; +#undef pci_ss_info_1014_1182 +#define pci_ss_info_1014_1182 pci_ss_info_115d_0007_1014_1182 +static const pciSubsystemInfo pci_ss_info_115d_0007_115d_0182 = + {0x115d, 0x0182, pci_subsys_115d_0007_115d_0182, 0}; +#undef pci_ss_info_115d_0182 +#define pci_ss_info_115d_0182 pci_ss_info_115d_0007_115d_0182 +static const pciSubsystemInfo pci_ss_info_115d_0007_115d_1182 = + {0x115d, 0x1182, pci_subsys_115d_0007_115d_1182, 0}; +#undef pci_ss_info_115d_1182 +#define pci_ss_info_115d_1182 pci_ss_info_115d_0007_115d_1182 +static const pciSubsystemInfo pci_ss_info_115d_000b_1014_0183 = + {0x1014, 0x0183, pci_subsys_115d_000b_1014_0183, 0}; +#undef pci_ss_info_1014_0183 +#define pci_ss_info_1014_0183 pci_ss_info_115d_000b_1014_0183 +static const pciSubsystemInfo pci_ss_info_115d_000b_115d_0183 = + {0x115d, 0x0183, pci_subsys_115d_000b_115d_0183, 0}; +#undef pci_ss_info_115d_0183 +#define pci_ss_info_115d_0183 pci_ss_info_115d_000b_115d_0183 +static const pciSubsystemInfo pci_ss_info_115d_000f_1014_0183 = + {0x1014, 0x0183, pci_subsys_115d_000f_1014_0183, 0}; +#undef pci_ss_info_1014_0183 +#define pci_ss_info_1014_0183 pci_ss_info_115d_000f_1014_0183 +static const pciSubsystemInfo pci_ss_info_115d_000f_115d_0183 = + {0x115d, 0x0183, pci_subsys_115d_000f_115d_0183, 0}; +#undef pci_ss_info_115d_0183 +#define pci_ss_info_115d_0183 pci_ss_info_115d_000f_115d_0183 +static const pciSubsystemInfo pci_ss_info_115d_0101_115d_1081 = + {0x115d, 0x1081, pci_subsys_115d_0101_115d_1081, 0}; +#undef pci_ss_info_115d_1081 +#define pci_ss_info_115d_1081 pci_ss_info_115d_0101_115d_1081 +static const pciSubsystemInfo pci_ss_info_115d_0103_1014_9181 = + {0x1014, 0x9181, pci_subsys_115d_0103_1014_9181, 0}; +#undef pci_ss_info_1014_9181 +#define pci_ss_info_1014_9181 pci_ss_info_115d_0103_1014_9181 +static const pciSubsystemInfo pci_ss_info_115d_0103_1115_1181 = + {0x1115, 0x1181, pci_subsys_115d_0103_1115_1181, 0}; +#undef pci_ss_info_1115_1181 +#define pci_ss_info_1115_1181 pci_ss_info_115d_0103_1115_1181 +static const pciSubsystemInfo pci_ss_info_115d_0103_115d_1181 = + {0x115d, 0x1181, pci_subsys_115d_0103_115d_1181, 0}; +#undef pci_ss_info_115d_1181 +#define pci_ss_info_115d_1181 pci_ss_info_115d_0103_115d_1181 +#endif +static const pciSubsystemInfo pci_ss_info_115d_0103_8086_9181 = + {0x8086, 0x9181, pci_subsys_115d_0103_8086_9181, 0}; +#undef pci_ss_info_8086_9181 +#define pci_ss_info_8086_9181 pci_ss_info_115d_0103_8086_9181 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1163_2000_1092_2000 = + {0x1092, 0x2000, pci_subsys_1163_2000_1092_2000, 0}; +#undef pci_ss_info_1092_2000 +#define pci_ss_info_1092_2000 pci_ss_info_1163_2000_1092_2000 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1179_0d01_1179_0001 = + {0x1179, 0x0001, pci_subsys_1179_0d01_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1179_0d01_1179_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1180_0475_144d_c006 = + {0x144d, 0xc006, pci_subsys_1180_0475_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_1180_0475_144d_c006 +static const pciSubsystemInfo pci_ss_info_1180_0476_1014_0185 = + {0x1014, 0x0185, pci_subsys_1180_0476_1014_0185, 0}; +#undef pci_ss_info_1014_0185 +#define pci_ss_info_1014_0185 pci_ss_info_1180_0476_1014_0185 +#endif +static const pciSubsystemInfo pci_ss_info_1180_0476_104d_80df = + {0x104d, 0x80df, pci_subsys_1180_0476_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_1180_0476_104d_80df +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1180_0476_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_1180_0476_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_1180_0476_104d_80e7 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1180_0478_1014_0184 = + {0x1014, 0x0184, pci_subsys_1180_0478_1014_0184, 0}; +#undef pci_ss_info_1014_0184 +#define pci_ss_info_1014_0184 pci_ss_info_1180_0478_1014_0184 +static const pciSubsystemInfo pci_ss_info_1180_0522_1014_01cf = + {0x1014, 0x01cf, pci_subsys_1180_0522_1014_01cf, 0}; +#undef pci_ss_info_1014_01cf +#define pci_ss_info_1014_01cf pci_ss_info_1180_0522_1014_01cf +static const pciSubsystemInfo pci_ss_info_1180_0551_144d_c006 = + {0x144d, 0xc006, pci_subsys_1180_0551_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_1180_0551_144d_c006 +static const pciSubsystemInfo pci_ss_info_1180_0552_1014_0511 = + {0x1014, 0x0511, pci_subsys_1180_0552_1014_0511, 0}; +#undef pci_ss_info_1014_0511 +#define pci_ss_info_1014_0511 pci_ss_info_1180_0552_1014_0511 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1186_1002_1186_1002 = + {0x1186, 0x1002, pci_subsys_1186_1002_1186_1002, 0}; +#undef pci_ss_info_1186_1002 +#define pci_ss_info_1186_1002 pci_ss_info_1186_1002_1186_1002 +static const pciSubsystemInfo pci_ss_info_1186_1002_1186_1012 = + {0x1186, 0x1012, pci_subsys_1186_1002_1186_1012, 0}; +#undef pci_ss_info_1186_1012 +#define pci_ss_info_1186_1012 pci_ss_info_1186_1002_1186_1012 +static const pciSubsystemInfo pci_ss_info_1186_1300_1186_1300 = + {0x1186, 0x1300, pci_subsys_1186_1300_1186_1300, 0}; +#undef pci_ss_info_1186_1300 +#define pci_ss_info_1186_1300 pci_ss_info_1186_1300_1186_1300 +static const pciSubsystemInfo pci_ss_info_1186_1300_1186_1301 = + {0x1186, 0x1301, pci_subsys_1186_1300_1186_1301, 0}; +#undef pci_ss_info_1186_1301 +#define pci_ss_info_1186_1301 pci_ss_info_1186_1300_1186_1301 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11ad_0002_11ad_0002 = + {0x11ad, 0x0002, pci_subsys_11ad_0002_11ad_0002, 0}; +#undef pci_ss_info_11ad_0002 +#define pci_ss_info_11ad_0002 pci_ss_info_11ad_0002_11ad_0002 +static const pciSubsystemInfo pci_ss_info_11ad_0002_11ad_0003 = + {0x11ad, 0x0003, pci_subsys_11ad_0002_11ad_0003, 0}; +#undef pci_ss_info_11ad_0003 +#define pci_ss_info_11ad_0003 pci_ss_info_11ad_0002_11ad_0003 +static const pciSubsystemInfo pci_ss_info_11ad_0002_11ad_f003 = + {0x11ad, 0xf003, pci_subsys_11ad_0002_11ad_f003, 0}; +#undef pci_ss_info_11ad_f003 +#define pci_ss_info_11ad_f003 pci_ss_info_11ad_0002_11ad_f003 +static const pciSubsystemInfo pci_ss_info_11ad_0002_11ad_ffff = + {0x11ad, 0xffff, pci_subsys_11ad_0002_11ad_ffff, 0}; +#undef pci_ss_info_11ad_ffff +#define pci_ss_info_11ad_ffff pci_ss_info_11ad_0002_11ad_ffff +static const pciSubsystemInfo pci_ss_info_11ad_0002_1385_f004 = + {0x1385, 0xf004, pci_subsys_11ad_0002_1385_f004, 0}; +#undef pci_ss_info_1385_f004 +#define pci_ss_info_1385_f004 pci_ss_info_11ad_0002_1385_f004 +static const pciSubsystemInfo pci_ss_info_11ad_c115_11ad_c001 = + {0x11ad, 0xc001, pci_subsys_11ad_c115_11ad_c001, 0}; +#undef pci_ss_info_11ad_c001 +#define pci_ss_info_11ad_c001 pci_ss_info_11ad_c115_11ad_c001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0440_1033_8015 = + {0x1033, 0x8015, pci_subsys_11c1_0440_1033_8015, 0}; +#undef pci_ss_info_1033_8015 +#define pci_ss_info_1033_8015 pci_ss_info_11c1_0440_1033_8015 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0440_1033_8047 = + {0x1033, 0x8047, pci_subsys_11c1_0440_1033_8047, 0}; +#undef pci_ss_info_1033_8047 +#define pci_ss_info_1033_8047 pci_ss_info_11c1_0440_1033_8047 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0440_1033_804f = + {0x1033, 0x804f, pci_subsys_11c1_0440_1033_804f, 0}; +#undef pci_ss_info_1033_804f +#define pci_ss_info_1033_804f pci_ss_info_11c1_0440_1033_804f +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0440_10cf_102c = + {0x10cf, 0x102c, pci_subsys_11c1_0440_10cf_102c, 0}; +#undef pci_ss_info_10cf_102c +#define pci_ss_info_10cf_102c pci_ss_info_11c1_0440_10cf_102c +static const pciSubsystemInfo pci_ss_info_11c1_0440_10cf_104a = + {0x10cf, 0x104a, pci_subsys_11c1_0440_10cf_104a, 0}; +#undef pci_ss_info_10cf_104a +#define pci_ss_info_10cf_104a pci_ss_info_11c1_0440_10cf_104a +static const pciSubsystemInfo pci_ss_info_11c1_0440_10cf_105f = + {0x10cf, 0x105f, pci_subsys_11c1_0440_10cf_105f, 0}; +#undef pci_ss_info_10cf_105f +#define pci_ss_info_10cf_105f pci_ss_info_11c1_0440_10cf_105f +static const pciSubsystemInfo pci_ss_info_11c1_0440_1179_0001 = + {0x1179, 0x0001, pci_subsys_11c1_0440_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_11c1_0440_1179_0001 +static const pciSubsystemInfo pci_ss_info_11c1_0440_11c1_0440 = + {0x11c1, 0x0440, pci_subsys_11c1_0440_11c1_0440, 0}; +#undef pci_ss_info_11c1_0440 +#define pci_ss_info_11c1_0440 pci_ss_info_11c1_0440_11c1_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0440_122d_4101 = + {0x122d, 0x4101, pci_subsys_11c1_0440_122d_4101, 0}; +#undef pci_ss_info_122d_4101 +#define pci_ss_info_122d_4101 pci_ss_info_11c1_0440_122d_4101 +static const pciSubsystemInfo pci_ss_info_11c1_0440_122d_4102 = + {0x122d, 0x4102, pci_subsys_11c1_0440_122d_4102, 0}; +#undef pci_ss_info_122d_4102 +#define pci_ss_info_122d_4102 pci_ss_info_11c1_0440_122d_4102 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_0040 = + {0x13e0, 0x0040, pci_subsys_11c1_0440_13e0_0040, 0}; +#undef pci_ss_info_13e0_0040 +#define pci_ss_info_13e0_0040 pci_ss_info_11c1_0440_13e0_0040 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_0440 = + {0x13e0, 0x0440, pci_subsys_11c1_0440_13e0_0440, 0}; +#undef pci_ss_info_13e0_0440 +#define pci_ss_info_13e0_0440 pci_ss_info_11c1_0440_13e0_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_0441 = + {0x13e0, 0x0441, pci_subsys_11c1_0440_13e0_0441, 0}; +#undef pci_ss_info_13e0_0441 +#define pci_ss_info_13e0_0441 pci_ss_info_11c1_0440_13e0_0441 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_0450 = + {0x13e0, 0x0450, pci_subsys_11c1_0440_13e0_0450, 0}; +#undef pci_ss_info_13e0_0450 +#define pci_ss_info_13e0_0450 pci_ss_info_11c1_0440_13e0_0450 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_f100 = + {0x13e0, 0xf100, pci_subsys_11c1_0440_13e0_f100, 0}; +#undef pci_ss_info_13e0_f100 +#define pci_ss_info_13e0_f100 pci_ss_info_11c1_0440_13e0_f100 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_f101 = + {0x13e0, 0xf101, pci_subsys_11c1_0440_13e0_f101, 0}; +#undef pci_ss_info_13e0_f101 +#define pci_ss_info_13e0_f101 pci_ss_info_11c1_0440_13e0_f101 +static const pciSubsystemInfo pci_ss_info_11c1_0440_144d_2101 = + {0x144d, 0x2101, pci_subsys_11c1_0440_144d_2101, 0}; +#undef pci_ss_info_144d_2101 +#define pci_ss_info_144d_2101 pci_ss_info_11c1_0440_144d_2101 +static const pciSubsystemInfo pci_ss_info_11c1_0440_149f_0440 = + {0x149f, 0x0440, pci_subsys_11c1_0440_149f_0440, 0}; +#undef pci_ss_info_149f_0440 +#define pci_ss_info_149f_0440 pci_ss_info_11c1_0440_149f_0440 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0441_1033_804d = + {0x1033, 0x804d, pci_subsys_11c1_0441_1033_804d, 0}; +#undef pci_ss_info_1033_804d +#define pci_ss_info_1033_804d pci_ss_info_11c1_0441_1033_804d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0441_1033_8065 = + {0x1033, 0x8065, pci_subsys_11c1_0441_1033_8065, 0}; +#undef pci_ss_info_1033_8065 +#define pci_ss_info_1033_8065 pci_ss_info_11c1_0441_1033_8065 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0441_1092_0440 = + {0x1092, 0x0440, pci_subsys_11c1_0441_1092_0440, 0}; +#undef pci_ss_info_1092_0440 +#define pci_ss_info_1092_0440 pci_ss_info_11c1_0441_1092_0440 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0441_1179_0001 = + {0x1179, 0x0001, pci_subsys_11c1_0441_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_11c1_0441_1179_0001 +static const pciSubsystemInfo pci_ss_info_11c1_0441_11c1_0440 = + {0x11c1, 0x0440, pci_subsys_11c1_0441_11c1_0440, 0}; +#undef pci_ss_info_11c1_0440 +#define pci_ss_info_11c1_0440 pci_ss_info_11c1_0441_11c1_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0441_11c1_0441 = + {0x11c1, 0x0441, pci_subsys_11c1_0441_11c1_0441, 0}; +#undef pci_ss_info_11c1_0441 +#define pci_ss_info_11c1_0441 pci_ss_info_11c1_0441_11c1_0441 +static const pciSubsystemInfo pci_ss_info_11c1_0441_122d_4100 = + {0x122d, 0x4100, pci_subsys_11c1_0441_122d_4100, 0}; +#undef pci_ss_info_122d_4100 +#define pci_ss_info_122d_4100 pci_ss_info_11c1_0441_122d_4100 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0040 = + {0x13e0, 0x0040, pci_subsys_11c1_0441_13e0_0040, 0}; +#undef pci_ss_info_13e0_0040 +#define pci_ss_info_13e0_0040 pci_ss_info_11c1_0441_13e0_0040 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0100 = + {0x13e0, 0x0100, pci_subsys_11c1_0441_13e0_0100, 0}; +#undef pci_ss_info_13e0_0100 +#define pci_ss_info_13e0_0100 pci_ss_info_11c1_0441_13e0_0100 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0410 = + {0x13e0, 0x0410, pci_subsys_11c1_0441_13e0_0410, 0}; +#undef pci_ss_info_13e0_0410 +#define pci_ss_info_13e0_0410 pci_ss_info_11c1_0441_13e0_0410 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0420 = + {0x13e0, 0x0420, pci_subsys_11c1_0441_13e0_0420, 0}; +#undef pci_ss_info_13e0_0420 +#define pci_ss_info_13e0_0420 pci_ss_info_11c1_0441_13e0_0420 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0440 = + {0x13e0, 0x0440, pci_subsys_11c1_0441_13e0_0440, 0}; +#undef pci_ss_info_13e0_0440 +#define pci_ss_info_13e0_0440 pci_ss_info_11c1_0441_13e0_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0443 = + {0x13e0, 0x0443, pci_subsys_11c1_0441_13e0_0443, 0}; +#undef pci_ss_info_13e0_0443 +#define pci_ss_info_13e0_0443 pci_ss_info_11c1_0441_13e0_0443 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_f102 = + {0x13e0, 0xf102, pci_subsys_11c1_0441_13e0_f102, 0}; +#undef pci_ss_info_13e0_f102 +#define pci_ss_info_13e0_f102 pci_ss_info_11c1_0441_13e0_f102 +static const pciSubsystemInfo pci_ss_info_11c1_0441_1416_9804 = + {0x1416, 0x9804, pci_subsys_11c1_0441_1416_9804, 0}; +#undef pci_ss_info_1416_9804 +#define pci_ss_info_1416_9804 pci_ss_info_11c1_0441_1416_9804 +static const pciSubsystemInfo pci_ss_info_11c1_0441_141d_0440 = + {0x141d, 0x0440, pci_subsys_11c1_0441_141d_0440, 0}; +#undef pci_ss_info_141d_0440 +#define pci_ss_info_141d_0440 pci_ss_info_11c1_0441_141d_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0441_144f_0441 = + {0x144f, 0x0441, pci_subsys_11c1_0441_144f_0441, 0}; +#undef pci_ss_info_144f_0441 +#define pci_ss_info_144f_0441 pci_ss_info_11c1_0441_144f_0441 +static const pciSubsystemInfo pci_ss_info_11c1_0441_144f_0449 = + {0x144f, 0x0449, pci_subsys_11c1_0441_144f_0449, 0}; +#undef pci_ss_info_144f_0449 +#define pci_ss_info_144f_0449 pci_ss_info_11c1_0441_144f_0449 +static const pciSubsystemInfo pci_ss_info_11c1_0441_144f_110d = + {0x144f, 0x110d, pci_subsys_11c1_0441_144f_110d, 0}; +#undef pci_ss_info_144f_110d +#define pci_ss_info_144f_110d pci_ss_info_11c1_0441_144f_110d +static const pciSubsystemInfo pci_ss_info_11c1_0441_1468_0441 = + {0x1468, 0x0441, pci_subsys_11c1_0441_1468_0441, 0}; +#undef pci_ss_info_1468_0441 +#define pci_ss_info_1468_0441 pci_ss_info_11c1_0441_1468_0441 +static const pciSubsystemInfo pci_ss_info_11c1_0441_1668_0440 = + {0x1668, 0x0440, pci_subsys_11c1_0441_1668_0440, 0}; +#undef pci_ss_info_1668_0440 +#define pci_ss_info_1668_0440 pci_ss_info_11c1_0441_1668_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0442_11c1_0440 = + {0x11c1, 0x0440, pci_subsys_11c1_0442_11c1_0440, 0}; +#undef pci_ss_info_11c1_0440 +#define pci_ss_info_11c1_0440 pci_ss_info_11c1_0442_11c1_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0442_11c1_0442 = + {0x11c1, 0x0442, pci_subsys_11c1_0442_11c1_0442, 0}; +#undef pci_ss_info_11c1_0442 +#define pci_ss_info_11c1_0442 pci_ss_info_11c1_0442_11c1_0442 +static const pciSubsystemInfo pci_ss_info_11c1_0442_13e0_0412 = + {0x13e0, 0x0412, pci_subsys_11c1_0442_13e0_0412, 0}; +#undef pci_ss_info_13e0_0412 +#define pci_ss_info_13e0_0412 pci_ss_info_11c1_0442_13e0_0412 +static const pciSubsystemInfo pci_ss_info_11c1_0442_13e0_0442 = + {0x13e0, 0x0442, pci_subsys_11c1_0442_13e0_0442, 0}; +#undef pci_ss_info_13e0_0442 +#define pci_ss_info_13e0_0442 pci_ss_info_11c1_0442_13e0_0442 +static const pciSubsystemInfo pci_ss_info_11c1_0442_13fc_2471 = + {0x13fc, 0x2471, pci_subsys_11c1_0442_13fc_2471, 0}; +#undef pci_ss_info_13fc_2471 +#define pci_ss_info_13fc_2471 pci_ss_info_11c1_0442_13fc_2471 +static const pciSubsystemInfo pci_ss_info_11c1_0442_144d_2104 = + {0x144d, 0x2104, pci_subsys_11c1_0442_144d_2104, 0}; +#undef pci_ss_info_144d_2104 +#define pci_ss_info_144d_2104 pci_ss_info_11c1_0442_144d_2104 +static const pciSubsystemInfo pci_ss_info_11c1_0442_144f_1104 = + {0x144f, 0x1104, pci_subsys_11c1_0442_144f_1104, 0}; +#undef pci_ss_info_144f_1104 +#define pci_ss_info_144f_1104 pci_ss_info_11c1_0442_144f_1104 +static const pciSubsystemInfo pci_ss_info_11c1_0442_149f_0440 = + {0x149f, 0x0440, pci_subsys_11c1_0442_149f_0440, 0}; +#undef pci_ss_info_149f_0440 +#define pci_ss_info_149f_0440 pci_ss_info_11c1_0442_149f_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0442_1668_0440 = + {0x1668, 0x0440, pci_subsys_11c1_0442_1668_0440, 0}; +#undef pci_ss_info_1668_0440 +#define pci_ss_info_1668_0440 pci_ss_info_11c1_0442_1668_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0448_1014_0131 = + {0x1014, 0x0131, pci_subsys_11c1_0448_1014_0131, 0}; +#undef pci_ss_info_1014_0131 +#define pci_ss_info_1014_0131 pci_ss_info_11c1_0448_1014_0131 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0448_1033_8066 = + {0x1033, 0x8066, pci_subsys_11c1_0448_1033_8066, 0}; +#undef pci_ss_info_1033_8066 +#define pci_ss_info_1033_8066 pci_ss_info_11c1_0448_1033_8066 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0448_13e0_0030 = + {0x13e0, 0x0030, pci_subsys_11c1_0448_13e0_0030, 0}; +#undef pci_ss_info_13e0_0030 +#define pci_ss_info_13e0_0030 pci_ss_info_11c1_0448_13e0_0030 +static const pciSubsystemInfo pci_ss_info_11c1_0448_13e0_0040 = + {0x13e0, 0x0040, pci_subsys_11c1_0448_13e0_0040, 0}; +#undef pci_ss_info_13e0_0040 +#define pci_ss_info_13e0_0040 pci_ss_info_11c1_0448_13e0_0040 +static const pciSubsystemInfo pci_ss_info_11c1_0448_1668_2400 = + {0x1668, 0x2400, pci_subsys_11c1_0448_1668_2400, 0}; +#undef pci_ss_info_1668_2400 +#define pci_ss_info_1668_2400 pci_ss_info_11c1_0448_1668_2400 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0449_0e11_b14d = + {0x0e11, 0xb14d, pci_subsys_11c1_0449_0e11_b14d, 0}; +#undef pci_ss_info_0e11_b14d +#define pci_ss_info_0e11_b14d pci_ss_info_11c1_0449_0e11_b14d +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0449_13e0_0020 = + {0x13e0, 0x0020, pci_subsys_11c1_0449_13e0_0020, 0}; +#undef pci_ss_info_13e0_0020 +#define pci_ss_info_13e0_0020 pci_ss_info_11c1_0449_13e0_0020 +static const pciSubsystemInfo pci_ss_info_11c1_0449_13e0_0041 = + {0x13e0, 0x0041, pci_subsys_11c1_0449_13e0_0041, 0}; +#undef pci_ss_info_13e0_0041 +#define pci_ss_info_13e0_0041 pci_ss_info_11c1_0449_13e0_0041 +static const pciSubsystemInfo pci_ss_info_11c1_0449_1436_0440 = + {0x1436, 0x0440, pci_subsys_11c1_0449_1436_0440, 0}; +#undef pci_ss_info_1436_0440 +#define pci_ss_info_1436_0440 pci_ss_info_11c1_0449_1436_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0449_144f_0449 = + {0x144f, 0x0449, pci_subsys_11c1_0449_144f_0449, 0}; +#undef pci_ss_info_144f_0449 +#define pci_ss_info_144f_0449 pci_ss_info_11c1_0449_144f_0449 +static const pciSubsystemInfo pci_ss_info_11c1_0449_1468_0410 = + {0x1468, 0x0410, pci_subsys_11c1_0449_1468_0410, 0}; +#undef pci_ss_info_1468_0410 +#define pci_ss_info_1468_0410 pci_ss_info_11c1_0449_1468_0410 +static const pciSubsystemInfo pci_ss_info_11c1_0449_1468_0440 = + {0x1468, 0x0440, pci_subsys_11c1_0449_1468_0440, 0}; +#undef pci_ss_info_1468_0440 +#define pci_ss_info_1468_0440 pci_ss_info_11c1_0449_1468_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0449_1468_0449 = + {0x1468, 0x0449, pci_subsys_11c1_0449_1468_0449, 0}; +#undef pci_ss_info_1468_0449 +#define pci_ss_info_1468_0449 pci_ss_info_11c1_0449_1468_0449 +static const pciSubsystemInfo pci_ss_info_11c1_044a_10cf_1072 = + {0x10cf, 0x1072, pci_subsys_11c1_044a_10cf_1072, 0}; +#undef pci_ss_info_10cf_1072 +#define pci_ss_info_10cf_1072 pci_ss_info_11c1_044a_10cf_1072 +static const pciSubsystemInfo pci_ss_info_11c1_044a_13e0_0012 = + {0x13e0, 0x0012, pci_subsys_11c1_044a_13e0_0012, 0}; +#undef pci_ss_info_13e0_0012 +#define pci_ss_info_13e0_0012 pci_ss_info_11c1_044a_13e0_0012 +static const pciSubsystemInfo pci_ss_info_11c1_044a_13e0_0042 = + {0x13e0, 0x0042, pci_subsys_11c1_044a_13e0_0042, 0}; +#undef pci_ss_info_13e0_0042 +#define pci_ss_info_13e0_0042 pci_ss_info_11c1_044a_13e0_0042 +static const pciSubsystemInfo pci_ss_info_11c1_044a_144f_1005 = + {0x144f, 0x1005, pci_subsys_11c1_044a_144f_1005, 0}; +#undef pci_ss_info_144f_1005 +#define pci_ss_info_144f_1005 pci_ss_info_11c1_044a_144f_1005 +static const pciSubsystemInfo pci_ss_info_11c1_0450_144f_4005 = + {0x144f, 0x4005, pci_subsys_11c1_0450_144f_4005, 0}; +#undef pci_ss_info_144f_4005 +#define pci_ss_info_144f_4005 pci_ss_info_11c1_0450_144f_4005 +static const pciSubsystemInfo pci_ss_info_11c1_5811_dead_0800 = + {0xdead, 0x0800, pci_subsys_11c1_5811_dead_0800, 0}; +#undef pci_ss_info_dead_0800 +#define pci_ss_info_dead_0800 pci_ss_info_11c1_5811_dead_0800 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11cb_2000_11cb_0200 = + {0x11cb, 0x0200, pci_subsys_11cb_2000_11cb_0200, 0}; +#undef pci_ss_info_11cb_0200 +#define pci_ss_info_11cb_0200 pci_ss_info_11cb_2000_11cb_0200 +static const pciSubsystemInfo pci_ss_info_11cb_2000_11cb_b008 = + {0x11cb, 0xb008, pci_subsys_11cb_2000_11cb_b008, 0}; +#undef pci_ss_info_11cb_b008 +#define pci_ss_info_11cb_b008 pci_ss_info_11cb_2000_11cb_b008 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11de_6057_1031_7efe = + {0x1031, 0x7efe, pci_subsys_11de_6057_1031_7efe, 0}; +#undef pci_ss_info_1031_7efe +#define pci_ss_info_1031_7efe pci_ss_info_11de_6057_1031_7efe +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11de_6057_1031_fc00 = + {0x1031, 0xfc00, pci_subsys_11de_6057_1031_fc00, 0}; +#undef pci_ss_info_1031_fc00 +#define pci_ss_info_1031_fc00 pci_ss_info_11de_6057_1031_fc00 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11de_6057_13ca_4231 = + {0x13ca, 0x4231, pci_subsys_11de_6057_13ca_4231, 0}; +#undef pci_ss_info_13ca_4231 +#define pci_ss_info_13ca_4231 pci_ss_info_11de_6057_13ca_4231 +static const pciSubsystemInfo pci_ss_info_11de_6120_1328_f001 = + {0x1328, 0xf001, pci_subsys_11de_6120_1328_f001, 0}; +#undef pci_ss_info_1328_f001 +#define pci_ss_info_1328_f001 pci_ss_info_11de_6120_1328_f001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11f6_2011_11f6_2011 = + {0x11f6, 0x2011, pci_subsys_11f6_2011_11f6_2011, 0}; +#undef pci_ss_info_11f6_2011 +#define pci_ss_info_11f6_2011 pci_ss_info_11f6_2011_11f6_2011 +static const pciSubsystemInfo pci_ss_info_11f6_2201_11f6_2011 = + {0x11f6, 0x2011, pci_subsys_11f6_2201_11f6_2011, 0}; +#undef pci_ss_info_11f6_2011 +#define pci_ss_info_11f6_2011 pci_ss_info_11f6_2201_11f6_2011 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1202_4300_1202_9841 = + {0x1202, 0x9841, pci_subsys_1202_4300_1202_9841, 0}; +#undef pci_ss_info_1202_9841 +#define pci_ss_info_1202_9841 pci_ss_info_1202_4300_1202_9841 +static const pciSubsystemInfo pci_ss_info_1202_4300_1202_9842 = + {0x1202, 0x9842, pci_subsys_1202_4300_1202_9842, 0}; +#undef pci_ss_info_1202_9842 +#define pci_ss_info_1202_9842 pci_ss_info_1202_4300_1202_9842 +static const pciSubsystemInfo pci_ss_info_1202_4300_1202_9843 = + {0x1202, 0x9843, pci_subsys_1202_4300_1202_9843, 0}; +#undef pci_ss_info_1202_9843 +#define pci_ss_info_1202_9843 pci_ss_info_1202_4300_1202_9843 +static const pciSubsystemInfo pci_ss_info_1202_4300_1202_9844 = + {0x1202, 0x9844, pci_subsys_1202_4300_1202_9844, 0}; +#undef pci_ss_info_1202_9844 +#define pci_ss_info_1202_9844 pci_ss_info_1202_4300_1202_9844 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1217_6933_1025_1016 = + {0x1025, 0x1016, pci_subsys_1217_6933_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_1217_6933_1025_1016 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1217_6972_1179_0001 = + {0x1179, 0x0001, pci_subsys_1217_6972_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1217_6972_1179_0001 +#endif +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_0003 = + {0x1092, 0x0003, pci_subsys_121a_0003_1092_0003, 0}; +#undef pci_ss_info_1092_0003 +#define pci_ss_info_1092_0003 pci_ss_info_121a_0003_1092_0003 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_4000 = + {0x1092, 0x4000, pci_subsys_121a_0003_1092_4000, 0}; +#undef pci_ss_info_1092_4000 +#define pci_ss_info_1092_4000 pci_ss_info_121a_0003_1092_4000 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_4002 = + {0x1092, 0x4002, pci_subsys_121a_0003_1092_4002, 0}; +#undef pci_ss_info_1092_4002 +#define pci_ss_info_1092_4002 pci_ss_info_121a_0003_1092_4002 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_4801 = + {0x1092, 0x4801, pci_subsys_121a_0003_1092_4801, 0}; +#undef pci_ss_info_1092_4801 +#define pci_ss_info_1092_4801 pci_ss_info_121a_0003_1092_4801 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_4803 = + {0x1092, 0x4803, pci_subsys_121a_0003_1092_4803, 0}; +#undef pci_ss_info_1092_4803 +#define pci_ss_info_1092_4803 pci_ss_info_121a_0003_1092_4803 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_8030 = + {0x1092, 0x8030, pci_subsys_121a_0003_1092_8030, 0}; +#undef pci_ss_info_1092_8030 +#define pci_ss_info_1092_8030 pci_ss_info_121a_0003_1092_8030 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_8035 = + {0x1092, 0x8035, pci_subsys_121a_0003_1092_8035, 0}; +#undef pci_ss_info_1092_8035 +#define pci_ss_info_1092_8035 pci_ss_info_121a_0003_1092_8035 +static const pciSubsystemInfo pci_ss_info_121a_0003_10b0_0001 = + {0x10b0, 0x0001, pci_subsys_121a_0003_10b0_0001, 0}; +#undef pci_ss_info_10b0_0001 +#define pci_ss_info_10b0_0001 pci_ss_info_121a_0003_10b0_0001 +static const pciSubsystemInfo pci_ss_info_121a_0003_1102_1018 = + {0x1102, 0x1018, pci_subsys_121a_0003_1102_1018, 0}; +#undef pci_ss_info_1102_1018 +#define pci_ss_info_1102_1018 pci_ss_info_121a_0003_1102_1018 +static const pciSubsystemInfo pci_ss_info_121a_0003_121a_0001 = + {0x121a, 0x0001, pci_subsys_121a_0003_121a_0001, 0}; +#undef pci_ss_info_121a_0001 +#define pci_ss_info_121a_0001 pci_ss_info_121a_0003_121a_0001 +static const pciSubsystemInfo pci_ss_info_121a_0003_121a_0003 = + {0x121a, 0x0003, pci_subsys_121a_0003_121a_0003, 0}; +#undef pci_ss_info_121a_0003 +#define pci_ss_info_121a_0003 pci_ss_info_121a_0003_121a_0003 +static const pciSubsystemInfo pci_ss_info_121a_0003_121a_0004 = + {0x121a, 0x0004, pci_subsys_121a_0003_121a_0004, 0}; +#undef pci_ss_info_121a_0004 +#define pci_ss_info_121a_0004 pci_ss_info_121a_0003_121a_0004 +static const pciSubsystemInfo pci_ss_info_121a_0003_139c_0016 = + {0x139c, 0x0016, pci_subsys_121a_0003_139c_0016, 0}; +#undef pci_ss_info_139c_0016 +#define pci_ss_info_139c_0016 pci_ss_info_121a_0003_139c_0016 +static const pciSubsystemInfo pci_ss_info_121a_0003_139c_0017 = + {0x139c, 0x0017, pci_subsys_121a_0003_139c_0017, 0}; +#undef pci_ss_info_139c_0017 +#define pci_ss_info_139c_0017 pci_ss_info_121a_0003_139c_0017 +static const pciSubsystemInfo pci_ss_info_121a_0003_14af_0002 = + {0x14af, 0x0002, pci_subsys_121a_0003_14af_0002, 0}; +#undef pci_ss_info_14af_0002 +#define pci_ss_info_14af_0002 pci_ss_info_121a_0003_14af_0002 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0004 = + {0x121a, 0x0004, pci_subsys_121a_0005_121a_0004, 0}; +#undef pci_ss_info_121a_0004 +#define pci_ss_info_121a_0004 pci_ss_info_121a_0005_121a_0004 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0030 = + {0x121a, 0x0030, pci_subsys_121a_0005_121a_0030, 0}; +#undef pci_ss_info_121a_0030 +#define pci_ss_info_121a_0030 pci_ss_info_121a_0005_121a_0030 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0031 = + {0x121a, 0x0031, pci_subsys_121a_0005_121a_0031, 0}; +#undef pci_ss_info_121a_0031 +#define pci_ss_info_121a_0031 pci_ss_info_121a_0005_121a_0031 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0034 = + {0x121a, 0x0034, pci_subsys_121a_0005_121a_0034, 0}; +#undef pci_ss_info_121a_0034 +#define pci_ss_info_121a_0034 pci_ss_info_121a_0005_121a_0034 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0036 = + {0x121a, 0x0036, pci_subsys_121a_0005_121a_0036, 0}; +#undef pci_ss_info_121a_0036 +#define pci_ss_info_121a_0036 pci_ss_info_121a_0005_121a_0036 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0037 = + {0x121a, 0x0037, pci_subsys_121a_0005_121a_0037, 0}; +#undef pci_ss_info_121a_0037 +#define pci_ss_info_121a_0037 pci_ss_info_121a_0005_121a_0037 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0038 = + {0x121a, 0x0038, pci_subsys_121a_0005_121a_0038, 0}; +#undef pci_ss_info_121a_0038 +#define pci_ss_info_121a_0038 pci_ss_info_121a_0005_121a_0038 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_003a = + {0x121a, 0x003a, pci_subsys_121a_0005_121a_003a, 0}; +#undef pci_ss_info_121a_003a +#define pci_ss_info_121a_003a pci_ss_info_121a_0005_121a_003a +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0044 = + {0x121a, 0x0044, pci_subsys_121a_0005_121a_0044, 0}; +#undef pci_ss_info_121a_0044 +#define pci_ss_info_121a_0044 pci_ss_info_121a_0005_121a_0044 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_004b = + {0x121a, 0x004b, pci_subsys_121a_0005_121a_004b, 0}; +#undef pci_ss_info_121a_004b +#define pci_ss_info_121a_004b pci_ss_info_121a_0005_121a_004b +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_004c = + {0x121a, 0x004c, pci_subsys_121a_0005_121a_004c, 0}; +#undef pci_ss_info_121a_004c +#define pci_ss_info_121a_004c pci_ss_info_121a_0005_121a_004c +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_004d = + {0x121a, 0x004d, pci_subsys_121a_0005_121a_004d, 0}; +#undef pci_ss_info_121a_004d +#define pci_ss_info_121a_004d pci_ss_info_121a_0005_121a_004d +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_004e = + {0x121a, 0x004e, pci_subsys_121a_0005_121a_004e, 0}; +#undef pci_ss_info_121a_004e +#define pci_ss_info_121a_004e pci_ss_info_121a_0005_121a_004e +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0051 = + {0x121a, 0x0051, pci_subsys_121a_0005_121a_0051, 0}; +#undef pci_ss_info_121a_0051 +#define pci_ss_info_121a_0051 pci_ss_info_121a_0005_121a_0051 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0052 = + {0x121a, 0x0052, pci_subsys_121a_0005_121a_0052, 0}; +#undef pci_ss_info_121a_0052 +#define pci_ss_info_121a_0052 pci_ss_info_121a_0005_121a_0052 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0060 = + {0x121a, 0x0060, pci_subsys_121a_0005_121a_0060, 0}; +#undef pci_ss_info_121a_0060 +#define pci_ss_info_121a_0060 pci_ss_info_121a_0005_121a_0060 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0061 = + {0x121a, 0x0061, pci_subsys_121a_0005_121a_0061, 0}; +#undef pci_ss_info_121a_0061 +#define pci_ss_info_121a_0061 pci_ss_info_121a_0005_121a_0061 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0062 = + {0x121a, 0x0062, pci_subsys_121a_0005_121a_0062, 0}; +#undef pci_ss_info_121a_0062 +#define pci_ss_info_121a_0062 pci_ss_info_121a_0005_121a_0062 +static const pciSubsystemInfo pci_ss_info_121a_0009_121a_0009 = + {0x121a, 0x0009, pci_subsys_121a_0009_121a_0009, 0}; +#undef pci_ss_info_121a_0009 +#define pci_ss_info_121a_0009 pci_ss_info_121a_0009_121a_0009 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_122d_50dc_122d_0001 = + {0x122d, 0x0001, pci_subsys_122d_50dc_122d_0001, 0}; +#undef pci_ss_info_122d_0001 +#define pci_ss_info_122d_0001 pci_ss_info_122d_50dc_122d_0001 +static const pciSubsystemInfo pci_ss_info_122d_80da_122d_0001 = + {0x122d, 0x0001, pci_subsys_122d_80da_122d_0001, 0}; +#undef pci_ss_info_122d_0001 +#define pci_ss_info_122d_0001 pci_ss_info_122d_80da_122d_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_123f_8120_11bd_0006 = + {0x11bd, 0x0006, pci_subsys_123f_8120_11bd_0006, 0}; +#undef pci_ss_info_11bd_0006 +#define pci_ss_info_11bd_0006 pci_ss_info_123f_8120_11bd_0006 +static const pciSubsystemInfo pci_ss_info_123f_8120_11bd_000a = + {0x11bd, 0x000a, pci_subsys_123f_8120_11bd_000a, 0}; +#undef pci_ss_info_11bd_000a +#define pci_ss_info_11bd_000a pci_ss_info_123f_8120_11bd_000a +#endif +static const pciSubsystemInfo pci_ss_info_123f_8888_1002_0001 = + {0x1002, 0x0001, pci_subsys_123f_8888_1002_0001, 0}; +#undef pci_ss_info_1002_0001 +#define pci_ss_info_1002_0001 pci_ss_info_123f_8888_1002_0001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_123f_8888_1002_0002 = + {0x1002, 0x0002, pci_subsys_123f_8888_1002_0002, 0}; +#undef pci_ss_info_1002_0002 +#define pci_ss_info_1002_0002 pci_ss_info_123f_8888_1002_0002 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_123f_8888_1328_0001 = + {0x1328, 0x0001, pci_subsys_123f_8888_1328_0001, 0}; +#undef pci_ss_info_1328_0001 +#define pci_ss_info_1328_0001 pci_ss_info_123f_8888_1328_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1242_1560_1242_6562 = + {0x1242, 0x6562, pci_subsys_1242_1560_1242_6562, 0}; +#undef pci_ss_info_1242_6562 +#define pci_ss_info_1242_6562 pci_ss_info_1242_1560_1242_6562 +static const pciSubsystemInfo pci_ss_info_1242_1560_1242_656a = + {0x1242, 0x656a, pci_subsys_1242_1560_1242_656a, 0}; +#undef pci_ss_info_1242_656a +#define pci_ss_info_1242_656a pci_ss_info_1242_1560_1242_656a +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1244_0a00_1244_0a00 = + {0x1244, 0x0a00, pci_subsys_1244_0a00_1244_0a00, 0}; +#undef pci_ss_info_1244_0a00 +#define pci_ss_info_1244_0a00 pci_ss_info_1244_0a00_1244_0a00 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_124b_0040_124b_9080 = + {0x124b, 0x9080, pci_subsys_124b_0040_124b_9080, 0}; +#undef pci_ss_info_124b_9080 +#define pci_ss_info_124b_9080 pci_ss_info_124b_0040_124b_9080 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1968_1028_0085 = + {0x1028, 0x0085, pci_subsys_125d_1968_1028_0085, 0}; +#undef pci_ss_info_1028_0085 +#define pci_ss_info_1028_0085 pci_ss_info_125d_1968_1028_0085 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1968_1033_8051 = + {0x1033, 0x8051, pci_subsys_125d_1968_1033_8051, 0}; +#undef pci_ss_info_1033_8051 +#define pci_ss_info_1033_8051 pci_ss_info_125d_1968_1033_8051 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125d_1969_1014_0166 = + {0x1014, 0x0166, pci_subsys_125d_1969_1014_0166, 0}; +#undef pci_ss_info_1014_0166 +#define pci_ss_info_1014_0166 pci_ss_info_125d_1969_1014_0166 +static const pciSubsystemInfo pci_ss_info_125d_1969_125d_8888 = + {0x125d, 0x8888, pci_subsys_125d_1969_125d_8888, 0}; +#undef pci_ss_info_125d_8888 +#define pci_ss_info_125d_8888 pci_ss_info_125d_1969_125d_8888 +#endif +static const pciSubsystemInfo pci_ss_info_125d_1978_0e11_b112 = + {0x0e11, 0xb112, pci_subsys_125d_1978_0e11_b112, 0}; +#undef pci_ss_info_0e11_b112 +#define pci_ss_info_0e11_b112 pci_ss_info_125d_1978_0e11_b112 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1978_1033_803c = + {0x1033, 0x803c, pci_subsys_125d_1978_1033_803c, 0}; +#undef pci_ss_info_1033_803c +#define pci_ss_info_1033_803c pci_ss_info_125d_1978_1033_803c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1978_1033_8058 = + {0x1033, 0x8058, pci_subsys_125d_1978_1033_8058, 0}; +#undef pci_ss_info_1033_8058 +#define pci_ss_info_1033_8058 pci_ss_info_125d_1978_1033_8058 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1978_1092_4000 = + {0x1092, 0x4000, pci_subsys_125d_1978_1092_4000, 0}; +#undef pci_ss_info_1092_4000 +#define pci_ss_info_1092_4000 pci_ss_info_125d_1978_1092_4000 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125d_1978_1179_0001 = + {0x1179, 0x0001, pci_subsys_125d_1978_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_125d_1978_1179_0001 +#endif +static const pciSubsystemInfo pci_ss_info_125d_1988_1092_4100 = + {0x1092, 0x4100, pci_subsys_125d_1988_1092_4100, 0}; +#undef pci_ss_info_1092_4100 +#define pci_ss_info_1092_4100 pci_ss_info_125d_1988_1092_4100 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125d_1988_125d_1988 = + {0x125d, 0x1988, pci_subsys_125d_1988_125d_1988, 0}; +#undef pci_ss_info_125d_1988 +#define pci_ss_info_125d_1988 pci_ss_info_125d_1988_125d_1988 +static const pciSubsystemInfo pci_ss_info_125d_1989_125d_1989 = + {0x125d, 0x1989, pci_subsys_125d_1989_125d_1989, 0}; +#undef pci_ss_info_125d_1989 +#define pci_ss_info_125d_1989 pci_ss_info_125d_1989_125d_1989 +#endif +static const pciSubsystemInfo pci_ss_info_125d_1998_1028_00e6 = + {0x1028, 0x00e6, pci_subsys_125d_1998_1028_00e6, 0}; +#undef pci_ss_info_1028_00e6 +#define pci_ss_info_1028_00e6 pci_ss_info_125d_1998_1028_00e6 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0424 = + {0x125d, 0x0424, pci_subsys_125d_2898_125d_0424, 0}; +#undef pci_ss_info_125d_0424 +#define pci_ss_info_125d_0424 pci_ss_info_125d_2898_125d_0424 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0425 = + {0x125d, 0x0425, pci_subsys_125d_2898_125d_0425, 0}; +#undef pci_ss_info_125d_0425 +#define pci_ss_info_125d_0425 pci_ss_info_125d_2898_125d_0425 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0426 = + {0x125d, 0x0426, pci_subsys_125d_2898_125d_0426, 0}; +#undef pci_ss_info_125d_0426 +#define pci_ss_info_125d_0426 pci_ss_info_125d_2898_125d_0426 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0427 = + {0x125d, 0x0427, pci_subsys_125d_2898_125d_0427, 0}; +#undef pci_ss_info_125d_0427 +#define pci_ss_info_125d_0427 pci_ss_info_125d_2898_125d_0427 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0428 = + {0x125d, 0x0428, pci_subsys_125d_2898_125d_0428, 0}; +#undef pci_ss_info_125d_0428 +#define pci_ss_info_125d_0428 pci_ss_info_125d_2898_125d_0428 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0429 = + {0x125d, 0x0429, pci_subsys_125d_2898_125d_0429, 0}; +#undef pci_ss_info_125d_0429 +#define pci_ss_info_125d_0429 pci_ss_info_125d_2898_125d_0429 +static const pciSubsystemInfo pci_ss_info_125d_2898_147a_c001 = + {0x147a, 0xc001, pci_subsys_125d_2898_147a_c001, 0}; +#undef pci_ss_info_147a_c001 +#define pci_ss_info_147a_c001 pci_ss_info_125d_2898_147a_c001 +static const pciSubsystemInfo pci_ss_info_125d_2898_14fe_0428 = + {0x14fe, 0x0428, pci_subsys_125d_2898_14fe_0428, 0}; +#undef pci_ss_info_14fe_0428 +#define pci_ss_info_14fe_0428 pci_ss_info_125d_2898_14fe_0428 +static const pciSubsystemInfo pci_ss_info_125d_2898_14fe_0429 = + {0x14fe, 0x0429, pci_subsys_125d_2898_14fe_0429, 0}; +#undef pci_ss_info_14fe_0429 +#define pci_ss_info_14fe_0429 pci_ss_info_125d_2898_14fe_0429 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1260_3873_1186_3501 = + {0x1186, 0x3501, pci_subsys_1260_3873_1186_3501, 0}; +#undef pci_ss_info_1186_3501 +#define pci_ss_info_1186_3501 pci_ss_info_1260_3873_1186_3501 +static const pciSubsystemInfo pci_ss_info_1260_3873_1668_0414 = + {0x1668, 0x0414, pci_subsys_1260_3873_1668_0414, 0}; +#undef pci_ss_info_1668_0414 +#define pci_ss_info_1668_0414 pci_ss_info_1260_3873_1668_0414 +static const pciSubsystemInfo pci_ss_info_1260_3873_1737_3874 = + {0x1737, 0x3874, pci_subsys_1260_3873_1737_3874, 0}; +#undef pci_ss_info_1737_3874 +#define pci_ss_info_1737_3874 pci_ss_info_1260_3873_1737_3874 +#endif +static const pciSubsystemInfo pci_ss_info_1260_3873_8086_2513 = + {0x8086, 0x2513, pci_subsys_1260_3873_8086_2513, 0}; +#undef pci_ss_info_8086_2513 +#define pci_ss_info_8086_2513 pci_ss_info_1260_3873_8086_2513 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1266_1910_1266_1910 = + {0x1266, 0x1910, pci_subsys_1266_1910_1266_1910, 0}; +#undef pci_ss_info_1266_1910 +#define pci_ss_info_1266_1910 pci_ss_info_1266_1910_1266_1910 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_0e11_0024 = + {0x0e11, 0x0024, pci_subsys_1274_1371_0e11_0024, 0}; +#undef pci_ss_info_0e11_0024 +#define pci_ss_info_0e11_0024 pci_ss_info_1274_1371_0e11_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_0e11_b1a7 = + {0x0e11, 0xb1a7, pci_subsys_1274_1371_0e11_b1a7, 0}; +#undef pci_ss_info_0e11_b1a7 +#define pci_ss_info_0e11_b1a7 pci_ss_info_1274_1371_0e11_b1a7 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_1033_80ac = + {0x1033, 0x80ac, pci_subsys_1274_1371_1033_80ac, 0}; +#undef pci_ss_info_1033_80ac +#define pci_ss_info_1033_80ac pci_ss_info_1274_1371_1033_80ac +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1274_1371_1042_1854 = + {0x1042, 0x1854, pci_subsys_1274_1371_1042_1854, 0}; +#undef pci_ss_info_1042_1854 +#define pci_ss_info_1042_1854 pci_ss_info_1274_1371_1042_1854 +static const pciSubsystemInfo pci_ss_info_1274_1371_107b_8054 = + {0x107b, 0x8054, pci_subsys_1274_1371_107b_8054, 0}; +#undef pci_ss_info_107b_8054 +#define pci_ss_info_107b_8054 pci_ss_info_1274_1371_107b_8054 +static const pciSubsystemInfo pci_ss_info_1274_1371_1274_1371 = + {0x1274, 0x1371, pci_subsys_1274_1371_1274_1371, 0}; +#undef pci_ss_info_1274_1371 +#define pci_ss_info_1274_1371 pci_ss_info_1274_1371_1274_1371 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6470 = + {0x1462, 0x6470, pci_subsys_1274_1371_1462_6470, 0}; +#undef pci_ss_info_1462_6470 +#define pci_ss_info_1462_6470 pci_ss_info_1274_1371_1462_6470 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6560 = + {0x1462, 0x6560, pci_subsys_1274_1371_1462_6560, 0}; +#undef pci_ss_info_1462_6560 +#define pci_ss_info_1462_6560 pci_ss_info_1274_1371_1462_6560 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6630 = + {0x1462, 0x6630, pci_subsys_1274_1371_1462_6630, 0}; +#undef pci_ss_info_1462_6630 +#define pci_ss_info_1462_6630 pci_ss_info_1274_1371_1462_6630 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6631 = + {0x1462, 0x6631, pci_subsys_1274_1371_1462_6631, 0}; +#undef pci_ss_info_1462_6631 +#define pci_ss_info_1462_6631 pci_ss_info_1274_1371_1462_6631 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6632 = + {0x1462, 0x6632, pci_subsys_1274_1371_1462_6632, 0}; +#undef pci_ss_info_1462_6632 +#define pci_ss_info_1462_6632 pci_ss_info_1274_1371_1462_6632 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6633 = + {0x1462, 0x6633, pci_subsys_1274_1371_1462_6633, 0}; +#undef pci_ss_info_1462_6633 +#define pci_ss_info_1462_6633 pci_ss_info_1274_1371_1462_6633 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6820 = + {0x1462, 0x6820, pci_subsys_1274_1371_1462_6820, 0}; +#undef pci_ss_info_1462_6820 +#define pci_ss_info_1462_6820 pci_ss_info_1274_1371_1462_6820 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6822 = + {0x1462, 0x6822, pci_subsys_1274_1371_1462_6822, 0}; +#undef pci_ss_info_1462_6822 +#define pci_ss_info_1462_6822 pci_ss_info_1274_1371_1462_6822 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6830 = + {0x1462, 0x6830, pci_subsys_1274_1371_1462_6830, 0}; +#undef pci_ss_info_1462_6830 +#define pci_ss_info_1462_6830 pci_ss_info_1274_1371_1462_6830 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6880 = + {0x1462, 0x6880, pci_subsys_1274_1371_1462_6880, 0}; +#undef pci_ss_info_1462_6880 +#define pci_ss_info_1462_6880 pci_ss_info_1274_1371_1462_6880 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6900 = + {0x1462, 0x6900, pci_subsys_1274_1371_1462_6900, 0}; +#undef pci_ss_info_1462_6900 +#define pci_ss_info_1462_6900 pci_ss_info_1274_1371_1462_6900 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6910 = + {0x1462, 0x6910, pci_subsys_1274_1371_1462_6910, 0}; +#undef pci_ss_info_1462_6910 +#define pci_ss_info_1462_6910 pci_ss_info_1274_1371_1462_6910 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6930 = + {0x1462, 0x6930, pci_subsys_1274_1371_1462_6930, 0}; +#undef pci_ss_info_1462_6930 +#define pci_ss_info_1462_6930 pci_ss_info_1274_1371_1462_6930 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6990 = + {0x1462, 0x6990, pci_subsys_1274_1371_1462_6990, 0}; +#undef pci_ss_info_1462_6990 +#define pci_ss_info_1462_6990 pci_ss_info_1274_1371_1462_6990 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6991 = + {0x1462, 0x6991, pci_subsys_1274_1371_1462_6991, 0}; +#undef pci_ss_info_1462_6991 +#define pci_ss_info_1462_6991 pci_ss_info_1274_1371_1462_6991 +static const pciSubsystemInfo pci_ss_info_1274_1371_14a4_2077 = + {0x14a4, 0x2077, pci_subsys_1274_1371_14a4_2077, 0}; +#undef pci_ss_info_14a4_2077 +#define pci_ss_info_14a4_2077 pci_ss_info_1274_1371_14a4_2077 +static const pciSubsystemInfo pci_ss_info_1274_1371_14a4_2105 = + {0x14a4, 0x2105, pci_subsys_1274_1371_14a4_2105, 0}; +#undef pci_ss_info_14a4_2105 +#define pci_ss_info_14a4_2105 pci_ss_info_1274_1371_14a4_2105 +static const pciSubsystemInfo pci_ss_info_1274_1371_14a4_2107 = + {0x14a4, 0x2107, pci_subsys_1274_1371_14a4_2107, 0}; +#undef pci_ss_info_14a4_2107 +#define pci_ss_info_14a4_2107 pci_ss_info_1274_1371_14a4_2107 +static const pciSubsystemInfo pci_ss_info_1274_1371_14a4_2172 = + {0x14a4, 0x2172, pci_subsys_1274_1371_14a4_2172, 0}; +#undef pci_ss_info_14a4_2172 +#define pci_ss_info_14a4_2172 pci_ss_info_1274_1371_14a4_2172 +static const pciSubsystemInfo pci_ss_info_1274_1371_1509_9902 = + {0x1509, 0x9902, pci_subsys_1274_1371_1509_9902, 0}; +#undef pci_ss_info_1509_9902 +#define pci_ss_info_1509_9902 pci_ss_info_1274_1371_1509_9902 +static const pciSubsystemInfo pci_ss_info_1274_1371_1509_9903 = + {0x1509, 0x9903, pci_subsys_1274_1371_1509_9903, 0}; +#undef pci_ss_info_1509_9903 +#define pci_ss_info_1509_9903 pci_ss_info_1274_1371_1509_9903 +static const pciSubsystemInfo pci_ss_info_1274_1371_1509_9904 = + {0x1509, 0x9904, pci_subsys_1274_1371_1509_9904, 0}; +#undef pci_ss_info_1509_9904 +#define pci_ss_info_1509_9904 pci_ss_info_1274_1371_1509_9904 +static const pciSubsystemInfo pci_ss_info_1274_1371_1509_9905 = + {0x1509, 0x9905, pci_subsys_1274_1371_1509_9905, 0}; +#undef pci_ss_info_1509_9905 +#define pci_ss_info_1509_9905 pci_ss_info_1274_1371_1509_9905 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8801 = + {0x152d, 0x8801, pci_subsys_1274_1371_152d_8801, 0}; +#undef pci_ss_info_152d_8801 +#define pci_ss_info_152d_8801 pci_ss_info_1274_1371_152d_8801 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8802 = + {0x152d, 0x8802, pci_subsys_1274_1371_152d_8802, 0}; +#undef pci_ss_info_152d_8802 +#define pci_ss_info_152d_8802 pci_ss_info_1274_1371_152d_8802 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8803 = + {0x152d, 0x8803, pci_subsys_1274_1371_152d_8803, 0}; +#undef pci_ss_info_152d_8803 +#define pci_ss_info_152d_8803 pci_ss_info_1274_1371_152d_8803 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8804 = + {0x152d, 0x8804, pci_subsys_1274_1371_152d_8804, 0}; +#undef pci_ss_info_152d_8804 +#define pci_ss_info_152d_8804 pci_ss_info_1274_1371_152d_8804 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8805 = + {0x152d, 0x8805, pci_subsys_1274_1371_152d_8805, 0}; +#undef pci_ss_info_152d_8805 +#define pci_ss_info_152d_8805 pci_ss_info_1274_1371_152d_8805 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_2001 = + {0x270f, 0x2001, pci_subsys_1274_1371_270f_2001, 0}; +#undef pci_ss_info_270f_2001 +#define pci_ss_info_270f_2001 pci_ss_info_1274_1371_270f_2001 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_2200 = + {0x270f, 0x2200, pci_subsys_1274_1371_270f_2200, 0}; +#undef pci_ss_info_270f_2200 +#define pci_ss_info_270f_2200 pci_ss_info_1274_1371_270f_2200 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_3000 = + {0x270f, 0x3000, pci_subsys_1274_1371_270f_3000, 0}; +#undef pci_ss_info_270f_3000 +#define pci_ss_info_270f_3000 pci_ss_info_1274_1371_270f_3000 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_3100 = + {0x270f, 0x3100, pci_subsys_1274_1371_270f_3100, 0}; +#undef pci_ss_info_270f_3100 +#define pci_ss_info_270f_3100 pci_ss_info_1274_1371_270f_3100 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_3102 = + {0x270f, 0x3102, pci_subsys_1274_1371_270f_3102, 0}; +#undef pci_ss_info_270f_3102 +#define pci_ss_info_270f_3102 pci_ss_info_1274_1371_270f_3102 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_7060 = + {0x270f, 0x7060, pci_subsys_1274_1371_270f_7060, 0}; +#undef pci_ss_info_270f_7060 +#define pci_ss_info_270f_7060 pci_ss_info_1274_1371_270f_7060 +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4249 = + {0x8086, 0x4249, pci_subsys_1274_1371_8086_4249, 0}; +#undef pci_ss_info_8086_4249 +#define pci_ss_info_8086_4249 pci_ss_info_1274_1371_8086_4249 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_424c = + {0x8086, 0x424c, pci_subsys_1274_1371_8086_424c, 0}; +#undef pci_ss_info_8086_424c +#define pci_ss_info_8086_424c pci_ss_info_1274_1371_8086_424c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_425a = + {0x8086, 0x425a, pci_subsys_1274_1371_8086_425a, 0}; +#undef pci_ss_info_8086_425a +#define pci_ss_info_8086_425a pci_ss_info_1274_1371_8086_425a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4341 = + {0x8086, 0x4341, pci_subsys_1274_1371_8086_4341, 0}; +#undef pci_ss_info_8086_4341 +#define pci_ss_info_8086_4341 pci_ss_info_1274_1371_8086_4341 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4343 = + {0x8086, 0x4343, pci_subsys_1274_1371_8086_4343, 0}; +#undef pci_ss_info_8086_4343 +#define pci_ss_info_8086_4343 pci_ss_info_1274_1371_8086_4343 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4649 = + {0x8086, 0x4649, pci_subsys_1274_1371_8086_4649, 0}; +#undef pci_ss_info_8086_4649 +#define pci_ss_info_8086_4649 pci_ss_info_1274_1371_8086_4649 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_464a = + {0x8086, 0x464a, pci_subsys_1274_1371_8086_464a, 0}; +#undef pci_ss_info_8086_464a +#define pci_ss_info_8086_464a pci_ss_info_1274_1371_8086_464a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4d4f = + {0x8086, 0x4d4f, pci_subsys_1274_1371_8086_4d4f, 0}; +#undef pci_ss_info_8086_4d4f +#define pci_ss_info_8086_4d4f pci_ss_info_1274_1371_8086_4d4f +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4f43 = + {0x8086, 0x4f43, pci_subsys_1274_1371_8086_4f43, 0}; +#undef pci_ss_info_8086_4f43 +#define pci_ss_info_8086_4f43 pci_ss_info_1274_1371_8086_4f43 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_5243 = + {0x8086, 0x5243, pci_subsys_1274_1371_8086_5243, 0}; +#undef pci_ss_info_8086_5243 +#define pci_ss_info_8086_5243 pci_ss_info_1274_1371_8086_5243 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_5352 = + {0x8086, 0x5352, pci_subsys_1274_1371_8086_5352, 0}; +#undef pci_ss_info_8086_5352 +#define pci_ss_info_8086_5352 pci_ss_info_1274_1371_8086_5352 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_5643 = + {0x8086, 0x5643, pci_subsys_1274_1371_8086_5643, 0}; +#undef pci_ss_info_8086_5643 +#define pci_ss_info_8086_5643 pci_ss_info_1274_1371_8086_5643 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_5753 = + {0x8086, 0x5753, pci_subsys_1274_1371_8086_5753, 0}; +#undef pci_ss_info_8086_5753 +#define pci_ss_info_8086_5753 pci_ss_info_1274_1371_8086_5753 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1274_5880_1274_2000 = + {0x1274, 0x2000, pci_subsys_1274_5880_1274_2000, 0}; +#undef pci_ss_info_1274_2000 +#define pci_ss_info_1274_2000 pci_ss_info_1274_5880_1274_2000 +static const pciSubsystemInfo pci_ss_info_1274_5880_1274_2003 = + {0x1274, 0x2003, pci_subsys_1274_5880_1274_2003, 0}; +#undef pci_ss_info_1274_2003 +#define pci_ss_info_1274_2003 pci_ss_info_1274_5880_1274_2003 +static const pciSubsystemInfo pci_ss_info_1274_5880_1274_5880 = + {0x1274, 0x5880, pci_subsys_1274_5880_1274_5880, 0}; +#undef pci_ss_info_1274_5880 +#define pci_ss_info_1274_5880 pci_ss_info_1274_5880_1274_5880 +static const pciSubsystemInfo pci_ss_info_1274_5880_1458_a000 = + {0x1458, 0xa000, pci_subsys_1274_5880_1458_a000, 0}; +#undef pci_ss_info_1458_a000 +#define pci_ss_info_1458_a000 pci_ss_info_1274_5880_1458_a000 +static const pciSubsystemInfo pci_ss_info_1274_5880_1462_6880 = + {0x1462, 0x6880, pci_subsys_1274_5880_1462_6880, 0}; +#undef pci_ss_info_1462_6880 +#define pci_ss_info_1462_6880 pci_ss_info_1274_5880_1462_6880 +static const pciSubsystemInfo pci_ss_info_1274_5880_270f_2001 = + {0x270f, 0x2001, pci_subsys_1274_5880_270f_2001, 0}; +#undef pci_ss_info_270f_2001 +#define pci_ss_info_270f_2001 pci_ss_info_1274_5880_270f_2001 +static const pciSubsystemInfo pci_ss_info_1274_5880_270f_2200 = + {0x270f, 0x2200, pci_subsys_1274_5880_270f_2200, 0}; +#undef pci_ss_info_270f_2200 +#define pci_ss_info_270f_2200 pci_ss_info_1274_5880_270f_2200 +static const pciSubsystemInfo pci_ss_info_1274_5880_270f_7040 = + {0x270f, 0x7040, pci_subsys_1274_5880_270f_7040, 0}; +#undef pci_ss_info_270f_7040 +#define pci_ss_info_270f_7040 pci_ss_info_1274_5880_270f_7040 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1002_1092_094c = + {0x1092, 0x094c, pci_subsys_127a_1002_1092_094c, 0}; +#undef pci_ss_info_1092_094c +#define pci_ss_info_1092_094c pci_ss_info_127a_1002_1092_094c +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4002 = + {0x122d, 0x4002, pci_subsys_127a_1002_122d_4002, 0}; +#undef pci_ss_info_122d_4002 +#define pci_ss_info_122d_4002 pci_ss_info_127a_1002_122d_4002 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4005 = + {0x122d, 0x4005, pci_subsys_127a_1002_122d_4005, 0}; +#undef pci_ss_info_122d_4005 +#define pci_ss_info_122d_4005 pci_ss_info_127a_1002_122d_4005 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4007 = + {0x122d, 0x4007, pci_subsys_127a_1002_122d_4007, 0}; +#undef pci_ss_info_122d_4007 +#define pci_ss_info_122d_4007 pci_ss_info_127a_1002_122d_4007 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4012 = + {0x122d, 0x4012, pci_subsys_127a_1002_122d_4012, 0}; +#undef pci_ss_info_122d_4012 +#define pci_ss_info_122d_4012 pci_ss_info_127a_1002_122d_4012 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4017 = + {0x122d, 0x4017, pci_subsys_127a_1002_122d_4017, 0}; +#undef pci_ss_info_122d_4017 +#define pci_ss_info_122d_4017 pci_ss_info_127a_1002_122d_4017 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4018 = + {0x122d, 0x4018, pci_subsys_127a_1002_122d_4018, 0}; +#undef pci_ss_info_122d_4018 +#define pci_ss_info_122d_4018 pci_ss_info_127a_1002_122d_4018 +static const pciSubsystemInfo pci_ss_info_127a_1002_127a_1002 = + {0x127a, 0x1002, pci_subsys_127a_1002_127a_1002, 0}; +#undef pci_ss_info_127a_1002 +#define pci_ss_info_127a_1002 pci_ss_info_127a_1002_127a_1002 +#endif +static const pciSubsystemInfo pci_ss_info_127a_1003_0e11_b0bc = + {0x0e11, 0xb0bc, pci_subsys_127a_1003_0e11_b0bc, 0}; +#undef pci_ss_info_0e11_b0bc +#define pci_ss_info_0e11_b0bc pci_ss_info_127a_1003_0e11_b0bc +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1003_0e11_b114 = + {0x0e11, 0xb114, pci_subsys_127a_1003_0e11_b114, 0}; +#undef pci_ss_info_0e11_b114 +#define pci_ss_info_0e11_b114 pci_ss_info_127a_1003_0e11_b114 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1003_1033_802b = + {0x1033, 0x802b, pci_subsys_127a_1003_1033_802b, 0}; +#undef pci_ss_info_1033_802b +#define pci_ss_info_1033_802b pci_ss_info_127a_1003_1033_802b +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_127a_1003_13df_1003 = + {0x13df, 0x1003, pci_subsys_127a_1003_13df_1003, 0}; +#undef pci_ss_info_13df_1003 +#define pci_ss_info_13df_1003 pci_ss_info_127a_1003_13df_1003 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_0117 = + {0x13e0, 0x0117, pci_subsys_127a_1003_13e0_0117, 0}; +#undef pci_ss_info_13e0_0117 +#define pci_ss_info_13e0_0117 pci_ss_info_127a_1003_13e0_0117 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_0147 = + {0x13e0, 0x0147, pci_subsys_127a_1003_13e0_0147, 0}; +#undef pci_ss_info_13e0_0147 +#define pci_ss_info_13e0_0147 pci_ss_info_127a_1003_13e0_0147 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_0197 = + {0x13e0, 0x0197, pci_subsys_127a_1003_13e0_0197, 0}; +#undef pci_ss_info_13e0_0197 +#define pci_ss_info_13e0_0197 pci_ss_info_127a_1003_13e0_0197 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_01c7 = + {0x13e0, 0x01c7, pci_subsys_127a_1003_13e0_01c7, 0}; +#undef pci_ss_info_13e0_01c7 +#define pci_ss_info_13e0_01c7 pci_ss_info_127a_1003_13e0_01c7 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_01f7 = + {0x13e0, 0x01f7, pci_subsys_127a_1003_13e0_01f7, 0}; +#undef pci_ss_info_13e0_01f7 +#define pci_ss_info_13e0_01f7 pci_ss_info_127a_1003_13e0_01f7 +static const pciSubsystemInfo pci_ss_info_127a_1003_1436_1003 = + {0x1436, 0x1003, pci_subsys_127a_1003_1436_1003, 0}; +#undef pci_ss_info_1436_1003 +#define pci_ss_info_1436_1003 pci_ss_info_127a_1003_1436_1003 +static const pciSubsystemInfo pci_ss_info_127a_1003_1436_1103 = + {0x1436, 0x1103, pci_subsys_127a_1003_1436_1103, 0}; +#undef pci_ss_info_1436_1103 +#define pci_ss_info_1436_1103 pci_ss_info_127a_1003_1436_1103 +static const pciSubsystemInfo pci_ss_info_127a_1003_1436_1602 = + {0x1436, 0x1602, pci_subsys_127a_1003_1436_1602, 0}; +#undef pci_ss_info_1436_1602 +#define pci_ss_info_1436_1602 pci_ss_info_127a_1003_1436_1602 +static const pciSubsystemInfo pci_ss_info_127a_1004_1048_1500 = + {0x1048, 0x1500, pci_subsys_127a_1004_1048_1500, 0}; +#undef pci_ss_info_1048_1500 +#define pci_ss_info_1048_1500 pci_ss_info_127a_1004_1048_1500 +static const pciSubsystemInfo pci_ss_info_127a_1004_10cf_1059 = + {0x10cf, 0x1059, pci_subsys_127a_1004_10cf_1059, 0}; +#undef pci_ss_info_10cf_1059 +#define pci_ss_info_10cf_1059 pci_ss_info_127a_1004_10cf_1059 +#endif +static const pciSubsystemInfo pci_ss_info_127a_1005_1033_8029 = + {0x1033, 0x8029, pci_subsys_127a_1005_1033_8029, 0}; +#undef pci_ss_info_1033_8029 +#define pci_ss_info_1033_8029 pci_ss_info_127a_1005_1033_8029 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1005_1033_8054 = + {0x1033, 0x8054, pci_subsys_127a_1005_1033_8054, 0}; +#undef pci_ss_info_1033_8054 +#define pci_ss_info_1033_8054 pci_ss_info_127a_1005_1033_8054 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_127a_1005_10cf_103c = + {0x10cf, 0x103c, pci_subsys_127a_1005_10cf_103c, 0}; +#undef pci_ss_info_10cf_103c +#define pci_ss_info_10cf_103c pci_ss_info_127a_1005_10cf_103c +static const pciSubsystemInfo pci_ss_info_127a_1005_10cf_1055 = + {0x10cf, 0x1055, pci_subsys_127a_1005_10cf_1055, 0}; +#undef pci_ss_info_10cf_1055 +#define pci_ss_info_10cf_1055 pci_ss_info_127a_1005_10cf_1055 +static const pciSubsystemInfo pci_ss_info_127a_1005_10cf_1056 = + {0x10cf, 0x1056, pci_subsys_127a_1005_10cf_1056, 0}; +#undef pci_ss_info_10cf_1056 +#define pci_ss_info_10cf_1056 pci_ss_info_127a_1005_10cf_1056 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4003 = + {0x122d, 0x4003, pci_subsys_127a_1005_122d_4003, 0}; +#undef pci_ss_info_122d_4003 +#define pci_ss_info_122d_4003 pci_ss_info_127a_1005_122d_4003 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4006 = + {0x122d, 0x4006, pci_subsys_127a_1005_122d_4006, 0}; +#undef pci_ss_info_122d_4006 +#define pci_ss_info_122d_4006 pci_ss_info_127a_1005_122d_4006 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4008 = + {0x122d, 0x4008, pci_subsys_127a_1005_122d_4008, 0}; +#undef pci_ss_info_122d_4008 +#define pci_ss_info_122d_4008 pci_ss_info_127a_1005_122d_4008 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4009 = + {0x122d, 0x4009, pci_subsys_127a_1005_122d_4009, 0}; +#undef pci_ss_info_122d_4009 +#define pci_ss_info_122d_4009 pci_ss_info_127a_1005_122d_4009 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4010 = + {0x122d, 0x4010, pci_subsys_127a_1005_122d_4010, 0}; +#undef pci_ss_info_122d_4010 +#define pci_ss_info_122d_4010 pci_ss_info_127a_1005_122d_4010 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4011 = + {0x122d, 0x4011, pci_subsys_127a_1005_122d_4011, 0}; +#undef pci_ss_info_122d_4011 +#define pci_ss_info_122d_4011 pci_ss_info_127a_1005_122d_4011 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4013 = + {0x122d, 0x4013, pci_subsys_127a_1005_122d_4013, 0}; +#undef pci_ss_info_122d_4013 +#define pci_ss_info_122d_4013 pci_ss_info_127a_1005_122d_4013 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4015 = + {0x122d, 0x4015, pci_subsys_127a_1005_122d_4015, 0}; +#undef pci_ss_info_122d_4015 +#define pci_ss_info_122d_4015 pci_ss_info_127a_1005_122d_4015 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4016 = + {0x122d, 0x4016, pci_subsys_127a_1005_122d_4016, 0}; +#undef pci_ss_info_122d_4016 +#define pci_ss_info_122d_4016 pci_ss_info_127a_1005_122d_4016 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4019 = + {0x122d, 0x4019, pci_subsys_127a_1005_122d_4019, 0}; +#undef pci_ss_info_122d_4019 +#define pci_ss_info_122d_4019 pci_ss_info_127a_1005_122d_4019 +static const pciSubsystemInfo pci_ss_info_127a_1005_13df_1005 = + {0x13df, 0x1005, pci_subsys_127a_1005_13df_1005, 0}; +#undef pci_ss_info_13df_1005 +#define pci_ss_info_13df_1005 pci_ss_info_127a_1005_13df_1005 +static const pciSubsystemInfo pci_ss_info_127a_1005_13e0_0187 = + {0x13e0, 0x0187, pci_subsys_127a_1005_13e0_0187, 0}; +#undef pci_ss_info_13e0_0187 +#define pci_ss_info_13e0_0187 pci_ss_info_127a_1005_13e0_0187 +static const pciSubsystemInfo pci_ss_info_127a_1005_13e0_01a7 = + {0x13e0, 0x01a7, pci_subsys_127a_1005_13e0_01a7, 0}; +#undef pci_ss_info_13e0_01a7 +#define pci_ss_info_13e0_01a7 pci_ss_info_127a_1005_13e0_01a7 +static const pciSubsystemInfo pci_ss_info_127a_1005_13e0_01b7 = + {0x13e0, 0x01b7, pci_subsys_127a_1005_13e0_01b7, 0}; +#undef pci_ss_info_13e0_01b7 +#define pci_ss_info_13e0_01b7 pci_ss_info_127a_1005_13e0_01b7 +static const pciSubsystemInfo pci_ss_info_127a_1005_13e0_01d7 = + {0x13e0, 0x01d7, pci_subsys_127a_1005_13e0_01d7, 0}; +#undef pci_ss_info_13e0_01d7 +#define pci_ss_info_13e0_01d7 pci_ss_info_127a_1005_13e0_01d7 +static const pciSubsystemInfo pci_ss_info_127a_1005_1436_1005 = + {0x1436, 0x1005, pci_subsys_127a_1005_1436_1005, 0}; +#undef pci_ss_info_1436_1005 +#define pci_ss_info_1436_1005 pci_ss_info_127a_1005_1436_1005 +static const pciSubsystemInfo pci_ss_info_127a_1005_1436_1105 = + {0x1436, 0x1105, pci_subsys_127a_1005_1436_1105, 0}; +#undef pci_ss_info_1436_1105 +#define pci_ss_info_1436_1105 pci_ss_info_127a_1005_1436_1105 +static const pciSubsystemInfo pci_ss_info_127a_1005_1437_1105 = + {0x1437, 0x1105, pci_subsys_127a_1005_1437_1105, 0}; +#undef pci_ss_info_1437_1105 +#define pci_ss_info_1437_1105 pci_ss_info_127a_1005_1437_1105 +static const pciSubsystemInfo pci_ss_info_127a_1022_1436_1303 = + {0x1436, 0x1303, pci_subsys_127a_1022_1436_1303, 0}; +#undef pci_ss_info_1436_1303 +#define pci_ss_info_1436_1303 pci_ss_info_127a_1022_1436_1303 +static const pciSubsystemInfo pci_ss_info_127a_1023_122d_4020 = + {0x122d, 0x4020, pci_subsys_127a_1023_122d_4020, 0}; +#undef pci_ss_info_122d_4020 +#define pci_ss_info_122d_4020 pci_ss_info_127a_1023_122d_4020 +static const pciSubsystemInfo pci_ss_info_127a_1023_122d_4023 = + {0x122d, 0x4023, pci_subsys_127a_1023_122d_4023, 0}; +#undef pci_ss_info_122d_4023 +#define pci_ss_info_122d_4023 pci_ss_info_127a_1023_122d_4023 +static const pciSubsystemInfo pci_ss_info_127a_1023_13e0_0247 = + {0x13e0, 0x0247, pci_subsys_127a_1023_13e0_0247, 0}; +#undef pci_ss_info_13e0_0247 +#define pci_ss_info_13e0_0247 pci_ss_info_127a_1023_13e0_0247 +static const pciSubsystemInfo pci_ss_info_127a_1023_13e0_0297 = + {0x13e0, 0x0297, pci_subsys_127a_1023_13e0_0297, 0}; +#undef pci_ss_info_13e0_0297 +#define pci_ss_info_13e0_0297 pci_ss_info_127a_1023_13e0_0297 +static const pciSubsystemInfo pci_ss_info_127a_1023_13e0_02c7 = + {0x13e0, 0x02c7, pci_subsys_127a_1023_13e0_02c7, 0}; +#undef pci_ss_info_13e0_02c7 +#define pci_ss_info_13e0_02c7 pci_ss_info_127a_1023_13e0_02c7 +static const pciSubsystemInfo pci_ss_info_127a_1023_1436_1203 = + {0x1436, 0x1203, pci_subsys_127a_1023_1436_1203, 0}; +#undef pci_ss_info_1436_1203 +#define pci_ss_info_1436_1203 pci_ss_info_127a_1023_1436_1203 +static const pciSubsystemInfo pci_ss_info_127a_1023_1436_1303 = + {0x1436, 0x1303, pci_subsys_127a_1023_1436_1303, 0}; +#undef pci_ss_info_1436_1303 +#define pci_ss_info_1436_1303 pci_ss_info_127a_1023_1436_1303 +static const pciSubsystemInfo pci_ss_info_127a_1025_10cf_106a = + {0x10cf, 0x106a, pci_subsys_127a_1025_10cf_106a, 0}; +#undef pci_ss_info_10cf_106a +#define pci_ss_info_10cf_106a pci_ss_info_127a_1025_10cf_106a +static const pciSubsystemInfo pci_ss_info_127a_1025_122d_4021 = + {0x122d, 0x4021, pci_subsys_127a_1025_122d_4021, 0}; +#undef pci_ss_info_122d_4021 +#define pci_ss_info_122d_4021 pci_ss_info_127a_1025_122d_4021 +static const pciSubsystemInfo pci_ss_info_127a_1025_122d_4022 = + {0x122d, 0x4022, pci_subsys_127a_1025_122d_4022, 0}; +#undef pci_ss_info_122d_4022 +#define pci_ss_info_122d_4022 pci_ss_info_127a_1025_122d_4022 +static const pciSubsystemInfo pci_ss_info_127a_1025_122d_4024 = + {0x122d, 0x4024, pci_subsys_127a_1025_122d_4024, 0}; +#undef pci_ss_info_122d_4024 +#define pci_ss_info_122d_4024 pci_ss_info_127a_1025_122d_4024 +static const pciSubsystemInfo pci_ss_info_127a_1025_122d_4025 = + {0x122d, 0x4025, pci_subsys_127a_1025_122d_4025, 0}; +#undef pci_ss_info_122d_4025 +#define pci_ss_info_122d_4025 pci_ss_info_127a_1025_122d_4025 +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8044 = + {0x104d, 0x8044, pci_subsys_127a_2005_104d_8044, 0}; +#undef pci_ss_info_104d_8044 +#define pci_ss_info_104d_8044 pci_ss_info_127a_2005_104d_8044 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8045 = + {0x104d, 0x8045, pci_subsys_127a_2005_104d_8045, 0}; +#undef pci_ss_info_104d_8045 +#define pci_ss_info_104d_8045 pci_ss_info_127a_2005_104d_8045 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8055 = + {0x104d, 0x8055, pci_subsys_127a_2005_104d_8055, 0}; +#undef pci_ss_info_104d_8055 +#define pci_ss_info_104d_8055 pci_ss_info_127a_2005_104d_8055 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8056 = + {0x104d, 0x8056, pci_subsys_127a_2005_104d_8056, 0}; +#undef pci_ss_info_104d_8056 +#define pci_ss_info_104d_8056 pci_ss_info_127a_2005_104d_8056 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_805a = + {0x104d, 0x805a, pci_subsys_127a_2005_104d_805a, 0}; +#undef pci_ss_info_104d_805a +#define pci_ss_info_104d_805a pci_ss_info_127a_2005_104d_805a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_805f = + {0x104d, 0x805f, pci_subsys_127a_2005_104d_805f, 0}; +#undef pci_ss_info_104d_805f +#define pci_ss_info_104d_805f pci_ss_info_127a_2005_104d_805f +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8074 = + {0x104d, 0x8074, pci_subsys_127a_2005_104d_8074, 0}; +#undef pci_ss_info_104d_8074 +#define pci_ss_info_104d_8074 pci_ss_info_127a_2005_104d_8074 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_127a_2013_1179_0001 = + {0x1179, 0x0001, pci_subsys_127a_2013_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_127a_2013_1179_0001 +static const pciSubsystemInfo pci_ss_info_127a_2013_1179_ff00 = + {0x1179, 0xff00, pci_subsys_127a_2013_1179_ff00, 0}; +#undef pci_ss_info_1179_ff00 +#define pci_ss_info_1179_ff00 pci_ss_info_127a_2013_1179_ff00 +static const pciSubsystemInfo pci_ss_info_127a_2014_10cf_1057 = + {0x10cf, 0x1057, pci_subsys_127a_2014_10cf_1057, 0}; +#undef pci_ss_info_10cf_1057 +#define pci_ss_info_10cf_1057 pci_ss_info_127a_2014_10cf_1057 +static const pciSubsystemInfo pci_ss_info_127a_2014_122d_4050 = + {0x122d, 0x4050, pci_subsys_127a_2014_122d_4050, 0}; +#undef pci_ss_info_122d_4050 +#define pci_ss_info_122d_4050 pci_ss_info_127a_2014_122d_4050 +static const pciSubsystemInfo pci_ss_info_127a_2014_122d_4055 = + {0x122d, 0x4055, pci_subsys_127a_2014_122d_4055, 0}; +#undef pci_ss_info_122d_4055 +#define pci_ss_info_122d_4055 pci_ss_info_127a_2014_122d_4055 +static const pciSubsystemInfo pci_ss_info_127a_2015_10cf_1063 = + {0x10cf, 0x1063, pci_subsys_127a_2015_10cf_1063, 0}; +#undef pci_ss_info_10cf_1063 +#define pci_ss_info_10cf_1063 pci_ss_info_127a_2015_10cf_1063 +static const pciSubsystemInfo pci_ss_info_127a_2015_10cf_1064 = + {0x10cf, 0x1064, pci_subsys_127a_2015_10cf_1064, 0}; +#undef pci_ss_info_10cf_1064 +#define pci_ss_info_10cf_1064 pci_ss_info_127a_2015_10cf_1064 +static const pciSubsystemInfo pci_ss_info_127a_2015_1468_2015 = + {0x1468, 0x2015, pci_subsys_127a_2015_1468_2015, 0}; +#undef pci_ss_info_1468_2015 +#define pci_ss_info_1468_2015 pci_ss_info_127a_2015_1468_2015 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4051 = + {0x122d, 0x4051, pci_subsys_127a_2016_122d_4051, 0}; +#undef pci_ss_info_122d_4051 +#define pci_ss_info_122d_4051 pci_ss_info_127a_2016_122d_4051 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4052 = + {0x122d, 0x4052, pci_subsys_127a_2016_122d_4052, 0}; +#undef pci_ss_info_122d_4052 +#define pci_ss_info_122d_4052 pci_ss_info_127a_2016_122d_4052 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4054 = + {0x122d, 0x4054, pci_subsys_127a_2016_122d_4054, 0}; +#undef pci_ss_info_122d_4054 +#define pci_ss_info_122d_4054 pci_ss_info_127a_2016_122d_4054 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4056 = + {0x122d, 0x4056, pci_subsys_127a_2016_122d_4056, 0}; +#undef pci_ss_info_122d_4056 +#define pci_ss_info_122d_4056 pci_ss_info_127a_2016_122d_4056 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4057 = + {0x122d, 0x4057, pci_subsys_127a_2016_122d_4057, 0}; +#undef pci_ss_info_122d_4057 +#define pci_ss_info_122d_4057 pci_ss_info_127a_2016_122d_4057 +static const pciSubsystemInfo pci_ss_info_127a_4311_127a_4311 = + {0x127a, 0x4311, pci_subsys_127a_4311_127a_4311, 0}; +#undef pci_ss_info_127a_4311 +#define pci_ss_info_127a_4311 pci_ss_info_127a_4311_127a_4311 +static const pciSubsystemInfo pci_ss_info_127a_4311_13e0_0210 = + {0x13e0, 0x0210, pci_subsys_127a_4311_13e0_0210, 0}; +#undef pci_ss_info_13e0_0210 +#define pci_ss_info_13e0_0210 pci_ss_info_127a_4311_13e0_0210 +static const pciSubsystemInfo pci_ss_info_127a_4320_1235_4320 = + {0x1235, 0x4320, pci_subsys_127a_4320_1235_4320, 0}; +#undef pci_ss_info_1235_4320 +#define pci_ss_info_1235_4320 pci_ss_info_127a_4320_1235_4320 +static const pciSubsystemInfo pci_ss_info_127a_4321_1235_4321 = + {0x1235, 0x4321, pci_subsys_127a_4321_1235_4321, 0}; +#undef pci_ss_info_1235_4321 +#define pci_ss_info_1235_4321 pci_ss_info_127a_4321_1235_4321 +static const pciSubsystemInfo pci_ss_info_127a_4321_1235_4324 = + {0x1235, 0x4324, pci_subsys_127a_4321_1235_4324, 0}; +#undef pci_ss_info_1235_4324 +#define pci_ss_info_1235_4324 pci_ss_info_127a_4321_1235_4324 +static const pciSubsystemInfo pci_ss_info_127a_4321_13e0_0210 = + {0x13e0, 0x0210, pci_subsys_127a_4321_13e0_0210, 0}; +#undef pci_ss_info_13e0_0210 +#define pci_ss_info_13e0_0210 pci_ss_info_127a_4321_13e0_0210 +static const pciSubsystemInfo pci_ss_info_127a_4321_144d_2321 = + {0x144d, 0x2321, pci_subsys_127a_4321_144d_2321, 0}; +#undef pci_ss_info_144d_2321 +#define pci_ss_info_144d_2321 pci_ss_info_127a_4321_144d_2321 +static const pciSubsystemInfo pci_ss_info_127a_4322_1235_4322 = + {0x1235, 0x4322, pci_subsys_127a_4322_1235_4322, 0}; +#undef pci_ss_info_1235_4322 +#define pci_ss_info_1235_4322 pci_ss_info_127a_4322_1235_4322 +static const pciSubsystemInfo pci_ss_info_127a_8234_108d_0022 = + {0x108d, 0x0022, pci_subsys_127a_8234_108d_0022, 0}; +#undef pci_ss_info_108d_0022 +#define pci_ss_info_108d_0022 pci_ss_info_127a_8234_108d_0022 +static const pciSubsystemInfo pci_ss_info_127a_8234_108d_0027 = + {0x108d, 0x0027, pci_subsys_127a_8234_108d_0027, 0}; +#undef pci_ss_info_108d_0027 +#define pci_ss_info_108d_0027 pci_ss_info_127a_8234_108d_0027 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12ae_0001_12ae_0001 = + {0x12ae, 0x0001, pci_subsys_12ae_0001_12ae_0001, 0}; +#undef pci_ss_info_12ae_0001 +#define pci_ss_info_12ae_0001 pci_ss_info_12ae_0001_12ae_0001 +static const pciSubsystemInfo pci_ss_info_12ae_0001_1410_0104 = + {0x1410, 0x0104, pci_subsys_12ae_0001_1410_0104, 0}; +#undef pci_ss_info_1410_0104 +#define pci_ss_info_1410_0104 pci_ss_info_12ae_0001_1410_0104 +static const pciSubsystemInfo pci_ss_info_12ae_0002_12ae_0002 = + {0x12ae, 0x0002, pci_subsys_12ae_0002_12ae_0002, 0}; +#undef pci_ss_info_12ae_0002 +#define pci_ss_info_12ae_0002 pci_ss_info_12ae_0002_12ae_0002 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_005c = + {0x12b9, 0x005c, pci_subsys_12b9_1006_12b9_005c, 0}; +#undef pci_ss_info_12b9_005c +#define pci_ss_info_12b9_005c pci_ss_info_12b9_1006_12b9_005c +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_005e = + {0x12b9, 0x005e, pci_subsys_12b9_1006_12b9_005e, 0}; +#undef pci_ss_info_12b9_005e +#define pci_ss_info_12b9_005e pci_ss_info_12b9_1006_12b9_005e +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0062 = + {0x12b9, 0x0062, pci_subsys_12b9_1006_12b9_0062, 0}; +#undef pci_ss_info_12b9_0062 +#define pci_ss_info_12b9_0062 pci_ss_info_12b9_1006_12b9_0062 +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0068 = + {0x12b9, 0x0068, pci_subsys_12b9_1006_12b9_0068, 0}; +#undef pci_ss_info_12b9_0068 +#define pci_ss_info_12b9_0068 pci_ss_info_12b9_1006_12b9_0068 +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_007a = + {0x12b9, 0x007a, pci_subsys_12b9_1006_12b9_007a, 0}; +#undef pci_ss_info_12b9_007a +#define pci_ss_info_12b9_007a pci_ss_info_12b9_1006_12b9_007a +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_007f = + {0x12b9, 0x007f, pci_subsys_12b9_1006_12b9_007f, 0}; +#undef pci_ss_info_12b9_007f +#define pci_ss_info_12b9_007f pci_ss_info_12b9_1006_12b9_007f +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0080 = + {0x12b9, 0x0080, pci_subsys_12b9_1006_12b9_0080, 0}; +#undef pci_ss_info_12b9_0080 +#define pci_ss_info_12b9_0080 pci_ss_info_12b9_1006_12b9_0080 +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0081 = + {0x12b9, 0x0081, pci_subsys_12b9_1006_12b9_0081, 0}; +#undef pci_ss_info_12b9_0081 +#define pci_ss_info_12b9_0081 pci_ss_info_12b9_1006_12b9_0081 +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0091 = + {0x12b9, 0x0091, pci_subsys_12b9_1006_12b9_0091, 0}; +#undef pci_ss_info_12b9_0091 +#define pci_ss_info_12b9_0091 pci_ss_info_12b9_1006_12b9_0091 +static const pciSubsystemInfo pci_ss_info_12b9_1007_12b9_00a3 = + {0x12b9, 0x00a3, pci_subsys_12b9_1007_12b9_00a3, 0}; +#undef pci_ss_info_12b9_00a3 +#define pci_ss_info_12b9_00a3 pci_ss_info_12b9_1007_12b9_00a3 +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00a2 = + {0x12b9, 0x00a2, pci_subsys_12b9_1008_12b9_00a2, 0}; +#undef pci_ss_info_12b9_00a2 +#define pci_ss_info_12b9_00a2 pci_ss_info_12b9_1008_12b9_00a2 +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00aa = + {0x12b9, 0x00aa, pci_subsys_12b9_1008_12b9_00aa, 0}; +#undef pci_ss_info_12b9_00aa +#define pci_ss_info_12b9_00aa pci_ss_info_12b9_1008_12b9_00aa +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00ab = + {0x12b9, 0x00ab, pci_subsys_12b9_1008_12b9_00ab, 0}; +#undef pci_ss_info_12b9_00ab +#define pci_ss_info_12b9_00ab pci_ss_info_12b9_1008_12b9_00ab +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00ac = + {0x12b9, 0x00ac, pci_subsys_12b9_1008_12b9_00ac, 0}; +#undef pci_ss_info_12b9_00ac +#define pci_ss_info_12b9_00ac pci_ss_info_12b9_1008_12b9_00ac +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00ad = + {0x12b9, 0x00ad, pci_subsys_12b9_1008_12b9_00ad, 0}; +#undef pci_ss_info_12b9_00ad +#define pci_ss_info_12b9_00ad pci_ss_info_12b9_1008_12b9_00ad +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12be_3042_12be_3042 = + {0x12be, 0x3042, pci_subsys_12be_3042_12be_3042, 0}; +#undef pci_ss_info_12be_3042 +#define pci_ss_info_12be_3042 pci_ss_info_12be_3042_12be_3042 +#endif +static const pciSubsystemInfo pci_ss_info_12d2_0018_1048_0c10 = + {0x1048, 0x0c10, pci_subsys_12d2_0018_1048_0c10, 0}; +#undef pci_ss_info_1048_0c10 +#define pci_ss_info_1048_0c10 pci_ss_info_12d2_0018_1048_0c10 +static const pciSubsystemInfo pci_ss_info_12d2_0018_107b_8030 = + {0x107b, 0x8030, pci_subsys_12d2_0018_107b_8030, 0}; +#undef pci_ss_info_107b_8030 +#define pci_ss_info_107b_8030 pci_ss_info_12d2_0018_107b_8030 +static const pciSubsystemInfo pci_ss_info_12d2_0018_1092_0350 = + {0x1092, 0x0350, pci_subsys_12d2_0018_1092_0350, 0}; +#undef pci_ss_info_1092_0350 +#define pci_ss_info_1092_0350 pci_ss_info_12d2_0018_1092_0350 +static const pciSubsystemInfo pci_ss_info_12d2_0018_1092_1092 = + {0x1092, 0x1092, pci_subsys_12d2_0018_1092_1092, 0}; +#undef pci_ss_info_1092_1092 +#define pci_ss_info_1092_1092 pci_ss_info_12d2_0018_1092_1092 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b1b = + {0x10b4, 0x1b1b, pci_subsys_12d2_0018_10b4_1b1b, 0}; +#undef pci_ss_info_10b4_1b1b +#define pci_ss_info_10b4_1b1b pci_ss_info_12d2_0018_10b4_1b1b +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b1d = + {0x10b4, 0x1b1d, pci_subsys_12d2_0018_10b4_1b1d, 0}; +#undef pci_ss_info_10b4_1b1d +#define pci_ss_info_10b4_1b1d pci_ss_info_12d2_0018_10b4_1b1d +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b1e = + {0x10b4, 0x1b1e, pci_subsys_12d2_0018_10b4_1b1e, 0}; +#undef pci_ss_info_10b4_1b1e +#define pci_ss_info_10b4_1b1e pci_ss_info_12d2_0018_10b4_1b1e +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b20 = + {0x10b4, 0x1b20, pci_subsys_12d2_0018_10b4_1b20, 0}; +#undef pci_ss_info_10b4_1b20 +#define pci_ss_info_10b4_1b20 pci_ss_info_12d2_0018_10b4_1b20 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b21 = + {0x10b4, 0x1b21, pci_subsys_12d2_0018_10b4_1b21, 0}; +#undef pci_ss_info_10b4_1b21 +#define pci_ss_info_10b4_1b21 pci_ss_info_12d2_0018_10b4_1b21 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b22 = + {0x10b4, 0x1b22, pci_subsys_12d2_0018_10b4_1b22, 0}; +#undef pci_ss_info_10b4_1b22 +#define pci_ss_info_10b4_1b22 pci_ss_info_12d2_0018_10b4_1b22 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b23 = + {0x10b4, 0x1b23, pci_subsys_12d2_0018_10b4_1b23, 0}; +#undef pci_ss_info_10b4_1b23 +#define pci_ss_info_10b4_1b23 pci_ss_info_12d2_0018_10b4_1b23 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b27 = + {0x10b4, 0x1b27, pci_subsys_12d2_0018_10b4_1b27, 0}; +#undef pci_ss_info_10b4_1b27 +#define pci_ss_info_10b4_1b27 pci_ss_info_12d2_0018_10b4_1b27 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b88 = + {0x10b4, 0x1b88, pci_subsys_12d2_0018_10b4_1b88, 0}; +#undef pci_ss_info_10b4_1b88 +#define pci_ss_info_10b4_1b88 pci_ss_info_12d2_0018_10b4_1b88 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_222a = + {0x10b4, 0x222a, pci_subsys_12d2_0018_10b4_222a, 0}; +#undef pci_ss_info_10b4_222a +#define pci_ss_info_10b4_222a pci_ss_info_12d2_0018_10b4_222a +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_2230 = + {0x10b4, 0x2230, pci_subsys_12d2_0018_10b4_2230, 0}; +#undef pci_ss_info_10b4_2230 +#define pci_ss_info_10b4_2230 pci_ss_info_12d2_0018_10b4_2230 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_2232 = + {0x10b4, 0x2232, pci_subsys_12d2_0018_10b4_2232, 0}; +#undef pci_ss_info_10b4_2232 +#define pci_ss_info_10b4_2232 pci_ss_info_12d2_0018_10b4_2232 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_2235 = + {0x10b4, 0x2235, pci_subsys_12d2_0018_10b4_2235, 0}; +#undef pci_ss_info_10b4_2235 +#define pci_ss_info_10b4_2235 pci_ss_info_12d2_0018_10b4_2235 +static const pciSubsystemInfo pci_ss_info_12d2_0018_2a15_54a3 = + {0x2a15, 0x54a3, pci_subsys_12d2_0018_2a15_54a3, 0}; +#undef pci_ss_info_2a15_54a3 +#define pci_ss_info_2a15_54a3 pci_ss_info_12d2_0018_2a15_54a3 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_104d_8036 = + {0x104d, 0x8036, pci_subsys_12eb_0001_104d_8036, 0}; +#undef pci_ss_info_104d_8036 +#define pci_ss_info_104d_8036 pci_ss_info_12eb_0001_104d_8036 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_1092_2000 = + {0x1092, 0x2000, pci_subsys_12eb_0001_1092_2000, 0}; +#undef pci_ss_info_1092_2000 +#define pci_ss_info_1092_2000 pci_ss_info_12eb_0001_1092_2000 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_1092_2100 = + {0x1092, 0x2100, pci_subsys_12eb_0001_1092_2100, 0}; +#undef pci_ss_info_1092_2100 +#define pci_ss_info_1092_2100 pci_ss_info_12eb_0001_1092_2100 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_1092_2110 = + {0x1092, 0x2110, pci_subsys_12eb_0001_1092_2110, 0}; +#undef pci_ss_info_1092_2110 +#define pci_ss_info_1092_2110 pci_ss_info_12eb_0001_1092_2110 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_1092_2200 = + {0x1092, 0x2200, pci_subsys_12eb_0001_1092_2200, 0}; +#undef pci_ss_info_1092_2200 +#define pci_ss_info_1092_2200 pci_ss_info_12eb_0001_1092_2200 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12eb_0001_122d_1002 = + {0x122d, 0x1002, pci_subsys_12eb_0001_122d_1002, 0}; +#undef pci_ss_info_122d_1002 +#define pci_ss_info_122d_1002 pci_ss_info_12eb_0001_122d_1002 +static const pciSubsystemInfo pci_ss_info_12eb_0001_12eb_0001 = + {0x12eb, 0x0001, pci_subsys_12eb_0001_12eb_0001, 0}; +#undef pci_ss_info_12eb_0001 +#define pci_ss_info_12eb_0001 pci_ss_info_12eb_0001_12eb_0001 +static const pciSubsystemInfo pci_ss_info_12eb_0001_5053_3355 = + {0x5053, 0x3355, pci_subsys_12eb_0001_5053_3355, 0}; +#undef pci_ss_info_5053_3355 +#define pci_ss_info_5053_3355 pci_ss_info_12eb_0001_5053_3355 +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_104d_8049 = + {0x104d, 0x8049, pci_subsys_12eb_0002_104d_8049, 0}; +#undef pci_ss_info_104d_8049 +#define pci_ss_info_104d_8049 pci_ss_info_12eb_0002_104d_8049 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_104d_807b = + {0x104d, 0x807b, pci_subsys_12eb_0002_104d_807b, 0}; +#undef pci_ss_info_104d_807b +#define pci_ss_info_104d_807b pci_ss_info_12eb_0002_104d_807b +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3000 = + {0x1092, 0x3000, pci_subsys_12eb_0002_1092_3000, 0}; +#undef pci_ss_info_1092_3000 +#define pci_ss_info_1092_3000 pci_ss_info_12eb_0002_1092_3000 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3001 = + {0x1092, 0x3001, pci_subsys_12eb_0002_1092_3001, 0}; +#undef pci_ss_info_1092_3001 +#define pci_ss_info_1092_3001 pci_ss_info_12eb_0002_1092_3001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3002 = + {0x1092, 0x3002, pci_subsys_12eb_0002_1092_3002, 0}; +#undef pci_ss_info_1092_3002 +#define pci_ss_info_1092_3002 pci_ss_info_12eb_0002_1092_3002 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3003 = + {0x1092, 0x3003, pci_subsys_12eb_0002_1092_3003, 0}; +#undef pci_ss_info_1092_3003 +#define pci_ss_info_1092_3003 pci_ss_info_12eb_0002_1092_3003 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3004 = + {0x1092, 0x3004, pci_subsys_12eb_0002_1092_3004, 0}; +#undef pci_ss_info_1092_3004 +#define pci_ss_info_1092_3004 pci_ss_info_12eb_0002_1092_3004 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12eb_0002_12eb_0001 = + {0x12eb, 0x0001, pci_subsys_12eb_0002_12eb_0001, 0}; +#undef pci_ss_info_12eb_0001 +#define pci_ss_info_12eb_0001 pci_ss_info_12eb_0002_12eb_0001 +static const pciSubsystemInfo pci_ss_info_12eb_0002_12eb_0002 = + {0x12eb, 0x0002, pci_subsys_12eb_0002_12eb_0002, 0}; +#undef pci_ss_info_12eb_0002 +#define pci_ss_info_12eb_0002 pci_ss_info_12eb_0002_12eb_0002 +static const pciSubsystemInfo pci_ss_info_12eb_0002_12eb_0088 = + {0x12eb, 0x0088, pci_subsys_12eb_0002_12eb_0088, 0}; +#undef pci_ss_info_12eb_0088 +#define pci_ss_info_12eb_0088 pci_ss_info_12eb_0002_12eb_0088 +static const pciSubsystemInfo pci_ss_info_12eb_0002_144d_3510 = + {0x144d, 0x3510, pci_subsys_12eb_0002_144d_3510, 0}; +#undef pci_ss_info_144d_3510 +#define pci_ss_info_144d_3510 pci_ss_info_12eb_0002_144d_3510 +static const pciSubsystemInfo pci_ss_info_12eb_0002_5053_3356 = + {0x5053, 0x3356, pci_subsys_12eb_0002_5053_3356, 0}; +#undef pci_ss_info_5053_3356 +#define pci_ss_info_5053_3356 pci_ss_info_12eb_0002_5053_3356 +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0003_104d_8049 = + {0x104d, 0x8049, pci_subsys_12eb_0003_104d_8049, 0}; +#undef pci_ss_info_104d_8049 +#define pci_ss_info_104d_8049 pci_ss_info_12eb_0003_104d_8049 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0003_104d_8077 = + {0x104d, 0x8077, pci_subsys_12eb_0003_104d_8077, 0}; +#undef pci_ss_info_104d_8077 +#define pci_ss_info_104d_8077 pci_ss_info_12eb_0003_104d_8077 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12eb_0003_109f_1000 = + {0x109f, 0x1000, pci_subsys_12eb_0003_109f_1000, 0}; +#undef pci_ss_info_109f_1000 +#define pci_ss_info_109f_1000 pci_ss_info_12eb_0003_109f_1000 +static const pciSubsystemInfo pci_ss_info_12eb_0003_12eb_0003 = + {0x12eb, 0x0003, pci_subsys_12eb_0003_12eb_0003, 0}; +#undef pci_ss_info_12eb_0003 +#define pci_ss_info_12eb_0003 pci_ss_info_12eb_0003_12eb_0003 +static const pciSubsystemInfo pci_ss_info_12eb_0003_1462_6780 = + {0x1462, 0x6780, pci_subsys_12eb_0003_1462_6780, 0}; +#undef pci_ss_info_1462_6780 +#define pci_ss_info_1462_6780 pci_ss_info_12eb_0003_1462_6780 +static const pciSubsystemInfo pci_ss_info_12eb_0003_14a4_2073 = + {0x14a4, 0x2073, pci_subsys_12eb_0003_14a4_2073, 0}; +#undef pci_ss_info_14a4_2073 +#define pci_ss_info_14a4_2073 pci_ss_info_12eb_0003_14a4_2073 +static const pciSubsystemInfo pci_ss_info_12eb_0003_14a4_2091 = + {0x14a4, 0x2091, pci_subsys_12eb_0003_14a4_2091, 0}; +#undef pci_ss_info_14a4_2091 +#define pci_ss_info_14a4_2091 pci_ss_info_12eb_0003_14a4_2091 +static const pciSubsystemInfo pci_ss_info_12eb_0003_14a4_2104 = + {0x14a4, 0x2104, pci_subsys_12eb_0003_14a4_2104, 0}; +#undef pci_ss_info_14a4_2104 +#define pci_ss_info_14a4_2104 pci_ss_info_12eb_0003_14a4_2104 +static const pciSubsystemInfo pci_ss_info_12eb_0003_14a4_2106 = + {0x14a4, 0x2106, pci_subsys_12eb_0003_14a4_2106, 0}; +#undef pci_ss_info_14a4_2106 +#define pci_ss_info_14a4_2106 pci_ss_info_12eb_0003_14a4_2106 +static const pciSubsystemInfo pci_ss_info_12eb_8803_12eb_8803 = + {0x12eb, 0x8803, pci_subsys_12eb_8803_12eb_8803, 0}; +#undef pci_ss_info_12eb_8803 +#define pci_ss_info_12eb_8803 pci_ss_info_12eb_8803_12eb_8803 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1308_0001_1308_0001 = + {0x1308, 0x0001, pci_subsys_1308_0001_1308_0001, 0}; +#undef pci_ss_info_1308_0001 +#define pci_ss_info_1308_0001 pci_ss_info_1308_0001_1308_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_131f_2030_131f_2030 = + {0x131f, 0x2030, pci_subsys_131f_2030_131f_2030, 0}; +#undef pci_ss_info_131f_2030 +#define pci_ss_info_131f_2030 pci_ss_info_131f_2030_131f_2030 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_134d_7891_134d_0001 = + {0x134d, 0x0001, pci_subsys_134d_7891_134d_0001, 0}; +#undef pci_ss_info_134d_0001 +#define pci_ss_info_134d_0001 pci_ss_info_134d_7891_134d_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1394_0001_1394_0001 = + {0x1394, 0x0001, pci_subsys_1394_0001_1394_0001, 0}; +#undef pci_ss_info_1394_0001 +#define pci_ss_info_1394_0001 pci_ss_info_1394_0001_1394_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1397_2bd0_1397_2bd0 = + {0x1397, 0x2bd0, pci_subsys_1397_2bd0_1397_2bd0, 0}; +#undef pci_ss_info_1397_2bd0 +#define pci_ss_info_1397_2bd0 pci_ss_info_1397_2bd0_1397_2bd0 +static const pciSubsystemInfo pci_ss_info_1397_2bd0_e4bf_1000 = + {0xe4bf, 0x1000, pci_subsys_1397_2bd0_e4bf_1000, 0}; +#undef pci_ss_info_e4bf_1000 +#define pci_ss_info_e4bf_1000 pci_ss_info_1397_2bd0_e4bf_1000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_13df_0001_13df_0001 = + {0x13df, 0x0001, pci_subsys_13df_0001_13df_0001, 0}; +#undef pci_ss_info_13df_0001 +#define pci_ss_info_13df_0001 pci_ss_info_13df_0001_13df_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_13f6_0100_13f6_ffff = + {0x13f6, 0xffff, pci_subsys_13f6_0100_13f6_ffff, 0}; +#undef pci_ss_info_13f6_ffff +#define pci_ss_info_13f6_ffff pci_ss_info_13f6_0100_13f6_ffff +static const pciSubsystemInfo pci_ss_info_13f6_0101_13f6_0101 = + {0x13f6, 0x0101, pci_subsys_13f6_0101_13f6_0101, 0}; +#undef pci_ss_info_13f6_0101 +#define pci_ss_info_13f6_0101 pci_ss_info_13f6_0101_13f6_0101 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1019_0970 = + {0x1019, 0x0970, pci_subsys_13f6_0111_1019_0970, 0}; +#undef pci_ss_info_1019_0970 +#define pci_ss_info_1019_0970 pci_ss_info_13f6_0111_1019_0970 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1043_8077 = + {0x1043, 0x8077, pci_subsys_13f6_0111_1043_8077, 0}; +#undef pci_ss_info_1043_8077 +#define pci_ss_info_1043_8077 pci_ss_info_13f6_0111_1043_8077 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1043_80e2 = + {0x1043, 0x80e2, pci_subsys_13f6_0111_1043_80e2, 0}; +#undef pci_ss_info_1043_80e2 +#define pci_ss_info_1043_80e2 pci_ss_info_13f6_0111_1043_80e2 +static const pciSubsystemInfo pci_ss_info_13f6_0111_13f6_0111 = + {0x13f6, 0x0111, pci_subsys_13f6_0111_13f6_0111, 0}; +#undef pci_ss_info_13f6_0111 +#define pci_ss_info_13f6_0111 pci_ss_info_13f6_0111_13f6_0111 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1415_9501_15ed_2000 = + {0x15ed, 0x2000, pci_subsys_1415_9501_15ed_2000, 0}; +#undef pci_ss_info_15ed_2000 +#define pci_ss_info_15ed_2000 pci_ss_info_1415_9501_15ed_2000 +static const pciSubsystemInfo pci_ss_info_1415_9501_15ed_2001 = + {0x15ed, 0x2001, pci_subsys_1415_9501_15ed_2001, 0}; +#undef pci_ss_info_15ed_2001 +#define pci_ss_info_15ed_2001 pci_ss_info_1415_9501_15ed_2001 +static const pciSubsystemInfo pci_ss_info_1415_9511_15ed_2000 = + {0x15ed, 0x2000, pci_subsys_1415_9511_15ed_2000, 0}; +#undef pci_ss_info_15ed_2000 +#define pci_ss_info_15ed_2000 pci_ss_info_1415_9511_15ed_2000 +static const pciSubsystemInfo pci_ss_info_1415_9511_15ed_2001 = + {0x15ed, 0x2001, pci_subsys_1415_9511_15ed_2001, 0}; +#undef pci_ss_info_15ed_2001 +#define pci_ss_info_15ed_2001 pci_ss_info_1415_9511_15ed_2001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1644_1014_0277 = + {0x1014, 0x0277, pci_subsys_14e4_1644_1014_0277, 0}; +#undef pci_ss_info_1014_0277 +#define pci_ss_info_1014_0277 pci_ss_info_14e4_1644_1014_0277 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1644_1028_00d1 = + {0x1028, 0x00d1, pci_subsys_14e4_1644_1028_00d1, 0}; +#undef pci_ss_info_1028_00d1 +#define pci_ss_info_1028_00d1 pci_ss_info_14e4_1644_1028_00d1 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1644_1028_0106 = + {0x1028, 0x0106, pci_subsys_14e4_1644_1028_0106, 0}; +#undef pci_ss_info_1028_0106 +#define pci_ss_info_1028_0106 pci_ss_info_14e4_1644_1028_0106 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1644_1028_0109 = + {0x1028, 0x0109, pci_subsys_14e4_1644_1028_0109, 0}; +#undef pci_ss_info_1028_0109 +#define pci_ss_info_1028_0109 pci_ss_info_14e4_1644_1028_0109 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1644_1028_010a = + {0x1028, 0x010a, pci_subsys_14e4_1644_1028_010a, 0}; +#undef pci_ss_info_1028_010a +#define pci_ss_info_1028_010a pci_ss_info_14e4_1644_1028_010a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1000 = + {0x10b7, 0x1000, pci_subsys_14e4_1644_10b7_1000, 0}; +#undef pci_ss_info_10b7_1000 +#define pci_ss_info_10b7_1000 pci_ss_info_14e4_1644_10b7_1000 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1001 = + {0x10b7, 0x1001, pci_subsys_14e4_1644_10b7_1001, 0}; +#undef pci_ss_info_10b7_1001 +#define pci_ss_info_10b7_1001 pci_ss_info_14e4_1644_10b7_1001 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1002 = + {0x10b7, 0x1002, pci_subsys_14e4_1644_10b7_1002, 0}; +#undef pci_ss_info_10b7_1002 +#define pci_ss_info_10b7_1002 pci_ss_info_14e4_1644_10b7_1002 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1003 = + {0x10b7, 0x1003, pci_subsys_14e4_1644_10b7_1003, 0}; +#undef pci_ss_info_10b7_1003 +#define pci_ss_info_10b7_1003 pci_ss_info_14e4_1644_10b7_1003 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1004 = + {0x10b7, 0x1004, pci_subsys_14e4_1644_10b7_1004, 0}; +#undef pci_ss_info_10b7_1004 +#define pci_ss_info_10b7_1004 pci_ss_info_14e4_1644_10b7_1004 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1005 = + {0x10b7, 0x1005, pci_subsys_14e4_1644_10b7_1005, 0}; +#undef pci_ss_info_10b7_1005 +#define pci_ss_info_10b7_1005 pci_ss_info_14e4_1644_10b7_1005 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1008 = + {0x10b7, 0x1008, pci_subsys_14e4_1644_10b7_1008, 0}; +#undef pci_ss_info_10b7_1008 +#define pci_ss_info_10b7_1008 pci_ss_info_14e4_1644_10b7_1008 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_0002 = + {0x14e4, 0x0002, pci_subsys_14e4_1644_14e4_0002, 0}; +#undef pci_ss_info_14e4_0002 +#define pci_ss_info_14e4_0002 pci_ss_info_14e4_1644_14e4_0002 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_0003 = + {0x14e4, 0x0003, pci_subsys_14e4_1644_14e4_0003, 0}; +#undef pci_ss_info_14e4_0003 +#define pci_ss_info_14e4_0003 pci_ss_info_14e4_1644_14e4_0003 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_0004 = + {0x14e4, 0x0004, pci_subsys_14e4_1644_14e4_0004, 0}; +#undef pci_ss_info_14e4_0004 +#define pci_ss_info_14e4_0004 pci_ss_info_14e4_1644_14e4_0004 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_1028 = + {0x14e4, 0x1028, pci_subsys_14e4_1644_14e4_1028, 0}; +#undef pci_ss_info_14e4_1028 +#define pci_ss_info_14e4_1028 pci_ss_info_14e4_1644_14e4_1028 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_1644 = + {0x14e4, 0x1644, pci_subsys_14e4_1644_14e4_1644, 0}; +#undef pci_ss_info_14e4_1644 +#define pci_ss_info_14e4_1644 pci_ss_info_14e4_1644_14e4_1644 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_007c = + {0x0e11, 0x007c, pci_subsys_14e4_1645_0e11_007c, 0}; +#undef pci_ss_info_0e11_007c +#define pci_ss_info_0e11_007c pci_ss_info_14e4_1645_0e11_007c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_007d = + {0x0e11, 0x007d, pci_subsys_14e4_1645_0e11_007d, 0}; +#undef pci_ss_info_0e11_007d +#define pci_ss_info_0e11_007d pci_ss_info_14e4_1645_0e11_007d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_0085 = + {0x0e11, 0x0085, pci_subsys_14e4_1645_0e11_0085, 0}; +#undef pci_ss_info_0e11_0085 +#define pci_ss_info_0e11_0085 pci_ss_info_14e4_1645_0e11_0085 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_0099 = + {0x0e11, 0x0099, pci_subsys_14e4_1645_0e11_0099, 0}; +#undef pci_ss_info_0e11_0099 +#define pci_ss_info_0e11_0099 pci_ss_info_14e4_1645_0e11_0099 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_009a = + {0x0e11, 0x009a, pci_subsys_14e4_1645_0e11_009a, 0}; +#undef pci_ss_info_0e11_009a +#define pci_ss_info_0e11_009a pci_ss_info_14e4_1645_0e11_009a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_00c1 = + {0x0e11, 0x00c1, pci_subsys_14e4_1645_0e11_00c1, 0}; +#undef pci_ss_info_0e11_00c1 +#define pci_ss_info_0e11_00c1 pci_ss_info_14e4_1645_0e11_00c1 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_1028_0121 = + {0x1028, 0x0121, pci_subsys_14e4_1645_1028_0121, 0}; +#undef pci_ss_info_1028_0121 +#define pci_ss_info_1028_0121 pci_ss_info_14e4_1645_1028_0121 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1645_10b7_1004 = + {0x10b7, 0x1004, pci_subsys_14e4_1645_10b7_1004, 0}; +#undef pci_ss_info_10b7_1004 +#define pci_ss_info_10b7_1004 pci_ss_info_14e4_1645_10b7_1004 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10b7_1006 = + {0x10b7, 0x1006, pci_subsys_14e4_1645_10b7_1006, 0}; +#undef pci_ss_info_10b7_1006 +#define pci_ss_info_10b7_1006 pci_ss_info_14e4_1645_10b7_1006 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10b7_1007 = + {0x10b7, 0x1007, pci_subsys_14e4_1645_10b7_1007, 0}; +#undef pci_ss_info_10b7_1007 +#define pci_ss_info_10b7_1007 pci_ss_info_14e4_1645_10b7_1007 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10b7_1008 = + {0x10b7, 0x1008, pci_subsys_14e4_1645_10b7_1008, 0}; +#undef pci_ss_info_10b7_1008 +#define pci_ss_info_10b7_1008 pci_ss_info_14e4_1645_10b7_1008 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0001 = + {0x14e4, 0x0001, pci_subsys_14e4_1645_14e4_0001, 0}; +#undef pci_ss_info_14e4_0001 +#define pci_ss_info_14e4_0001 pci_ss_info_14e4_1645_14e4_0001 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0005 = + {0x14e4, 0x0005, pci_subsys_14e4_1645_14e4_0005, 0}; +#undef pci_ss_info_14e4_0005 +#define pci_ss_info_14e4_0005 pci_ss_info_14e4_1645_14e4_0005 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0006 = + {0x14e4, 0x0006, pci_subsys_14e4_1645_14e4_0006, 0}; +#undef pci_ss_info_14e4_0006 +#define pci_ss_info_14e4_0006 pci_ss_info_14e4_1645_14e4_0006 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0007 = + {0x14e4, 0x0007, pci_subsys_14e4_1645_14e4_0007, 0}; +#undef pci_ss_info_14e4_0007 +#define pci_ss_info_14e4_0007 pci_ss_info_14e4_1645_14e4_0007 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0008 = + {0x14e4, 0x0008, pci_subsys_14e4_1645_14e4_0008, 0}; +#undef pci_ss_info_14e4_0008 +#define pci_ss_info_14e4_0008 pci_ss_info_14e4_1645_14e4_0008 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_8008 = + {0x14e4, 0x8008, pci_subsys_14e4_1645_14e4_8008, 0}; +#undef pci_ss_info_14e4_8008 +#define pci_ss_info_14e4_8008 pci_ss_info_14e4_1645_14e4_8008 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1646_0e11_00bb = + {0x0e11, 0x00bb, pci_subsys_14e4_1646_0e11_00bb, 0}; +#undef pci_ss_info_0e11_00bb +#define pci_ss_info_0e11_00bb pci_ss_info_14e4_1646_0e11_00bb +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1646_1028_0126 = + {0x1028, 0x0126, pci_subsys_14e4_1646_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_14e4_1646_1028_0126 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1646_14e4_8009 = + {0x14e4, 0x8009, pci_subsys_14e4_1646_14e4_8009, 0}; +#undef pci_ss_info_14e4_8009 +#define pci_ss_info_14e4_8009 pci_ss_info_14e4_1646_14e4_8009 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1647_0e11_0099 = + {0x0e11, 0x0099, pci_subsys_14e4_1647_0e11_0099, 0}; +#undef pci_ss_info_0e11_0099 +#define pci_ss_info_0e11_0099 pci_ss_info_14e4_1647_0e11_0099 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1647_0e11_009a = + {0x0e11, 0x009a, pci_subsys_14e4_1647_0e11_009a, 0}; +#undef pci_ss_info_0e11_009a +#define pci_ss_info_0e11_009a pci_ss_info_14e4_1647_0e11_009a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_0009 = + {0x14e4, 0x0009, pci_subsys_14e4_1647_14e4_0009, 0}; +#undef pci_ss_info_14e4_0009 +#define pci_ss_info_14e4_0009 pci_ss_info_14e4_1647_14e4_0009 +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_000a = + {0x14e4, 0x000a, pci_subsys_14e4_1647_14e4_000a, 0}; +#undef pci_ss_info_14e4_000a +#define pci_ss_info_14e4_000a pci_ss_info_14e4_1647_14e4_000a +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_000b = + {0x14e4, 0x000b, pci_subsys_14e4_1647_14e4_000b, 0}; +#undef pci_ss_info_14e4_000b +#define pci_ss_info_14e4_000b pci_ss_info_14e4_1647_14e4_000b +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_8009 = + {0x14e4, 0x8009, pci_subsys_14e4_1647_14e4_8009, 0}; +#undef pci_ss_info_14e4_8009 +#define pci_ss_info_14e4_8009 pci_ss_info_14e4_1647_14e4_8009 +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_800a = + {0x14e4, 0x800a, pci_subsys_14e4_1647_14e4_800a, 0}; +#undef pci_ss_info_14e4_800a +#define pci_ss_info_14e4_800a pci_ss_info_14e4_1647_14e4_800a +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1648_0e11_00cf = + {0x0e11, 0x00cf, pci_subsys_14e4_1648_0e11_00cf, 0}; +#undef pci_ss_info_0e11_00cf +#define pci_ss_info_0e11_00cf pci_ss_info_14e4_1648_0e11_00cf +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1648_0e11_00d0 = + {0x0e11, 0x00d0, pci_subsys_14e4_1648_0e11_00d0, 0}; +#undef pci_ss_info_0e11_00d0 +#define pci_ss_info_0e11_00d0 pci_ss_info_14e4_1648_0e11_00d0 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1648_0e11_00d1 = + {0x0e11, 0x00d1, pci_subsys_14e4_1648_0e11_00d1, 0}; +#undef pci_ss_info_0e11_00d1 +#define pci_ss_info_0e11_00d1 pci_ss_info_14e4_1648_0e11_00d1 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1648_10b7_2000 = + {0x10b7, 0x2000, pci_subsys_14e4_1648_10b7_2000, 0}; +#undef pci_ss_info_10b7_2000 +#define pci_ss_info_10b7_2000 pci_ss_info_14e4_1648_10b7_2000 +static const pciSubsystemInfo pci_ss_info_14e4_1648_10b7_3000 = + {0x10b7, 0x3000, pci_subsys_14e4_1648_10b7_3000, 0}; +#undef pci_ss_info_10b7_3000 +#define pci_ss_info_10b7_3000 pci_ss_info_14e4_1648_10b7_3000 +static const pciSubsystemInfo pci_ss_info_14e4_1648_1166_1648 = + {0x1166, 0x1648, pci_subsys_14e4_1648_1166_1648, 0}; +#undef pci_ss_info_1166_1648 +#define pci_ss_info_1166_1648 pci_ss_info_14e4_1648_1166_1648 +static const pciSubsystemInfo pci_ss_info_14e4_1696_14e4_000d = + {0x14e4, 0x000d, pci_subsys_14e4_1696_14e4_000d, 0}; +#undef pci_ss_info_14e4_000d +#define pci_ss_info_14e4_000d pci_ss_info_14e4_1696_14e4_000d +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16a6_0e11_00bb = + {0x0e11, 0x00bb, pci_subsys_14e4_16a6_0e11_00bb, 0}; +#undef pci_ss_info_0e11_00bb +#define pci_ss_info_0e11_00bb pci_ss_info_14e4_16a6_0e11_00bb +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16a6_1028_0126 = + {0x1028, 0x0126, pci_subsys_14e4_16a6_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_14e4_16a6_1028_0126 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_16a6_14e4_000c = + {0x14e4, 0x000c, pci_subsys_14e4_16a6_14e4_000c, 0}; +#undef pci_ss_info_14e4_000c +#define pci_ss_info_14e4_000c pci_ss_info_14e4_16a6_14e4_000c +static const pciSubsystemInfo pci_ss_info_14e4_16a6_14e4_8009 = + {0x14e4, 0x8009, pci_subsys_14e4_16a6_14e4_8009, 0}; +#undef pci_ss_info_14e4_8009 +#define pci_ss_info_14e4_8009 pci_ss_info_14e4_16a6_14e4_8009 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16a7_0e11_00ca = + {0x0e11, 0x00ca, pci_subsys_14e4_16a7_0e11_00ca, 0}; +#undef pci_ss_info_0e11_00ca +#define pci_ss_info_0e11_00ca pci_ss_info_14e4_16a7_0e11_00ca +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16a7_0e11_00cb = + {0x0e11, 0x00cb, pci_subsys_14e4_16a7_0e11_00cb, 0}; +#undef pci_ss_info_0e11_00cb +#define pci_ss_info_0e11_00cb pci_ss_info_14e4_16a7_0e11_00cb +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_16a7_14e4_0009 = + {0x14e4, 0x0009, pci_subsys_14e4_16a7_14e4_0009, 0}; +#undef pci_ss_info_14e4_0009 +#define pci_ss_info_14e4_0009 pci_ss_info_14e4_16a7_14e4_0009 +static const pciSubsystemInfo pci_ss_info_14e4_16a7_14e4_000a = + {0x14e4, 0x000a, pci_subsys_14e4_16a7_14e4_000a, 0}; +#undef pci_ss_info_14e4_000a +#define pci_ss_info_14e4_000a pci_ss_info_14e4_16a7_14e4_000a +static const pciSubsystemInfo pci_ss_info_14e4_16a7_14e4_000b = + {0x14e4, 0x000b, pci_subsys_14e4_16a7_14e4_000b, 0}; +#undef pci_ss_info_14e4_000b +#define pci_ss_info_14e4_000b pci_ss_info_14e4_16a7_14e4_000b +static const pciSubsystemInfo pci_ss_info_14e4_16a7_14e4_800a = + {0x14e4, 0x800a, pci_subsys_14e4_16a7_14e4_800a, 0}; +#undef pci_ss_info_14e4_800a +#define pci_ss_info_14e4_800a pci_ss_info_14e4_16a7_14e4_800a +static const pciSubsystemInfo pci_ss_info_14e4_16a8_10b7_2001 = + {0x10b7, 0x2001, pci_subsys_14e4_16a8_10b7_2001, 0}; +#undef pci_ss_info_10b7_2001 +#define pci_ss_info_10b7_2001 pci_ss_info_14e4_16a8_10b7_2001 +static const pciSubsystemInfo pci_ss_info_14e4_16c6_10b7_1100 = + {0x10b7, 0x1100, pci_subsys_14e4_16c6_10b7_1100, 0}; +#undef pci_ss_info_10b7_1100 +#define pci_ss_info_10b7_1100 pci_ss_info_14e4_16c6_10b7_1100 +static const pciSubsystemInfo pci_ss_info_14e4_16c6_14e4_000c = + {0x14e4, 0x000c, pci_subsys_14e4_16c6_14e4_000c, 0}; +#undef pci_ss_info_14e4_000c +#define pci_ss_info_14e4_000c pci_ss_info_14e4_16c6_14e4_000c +static const pciSubsystemInfo pci_ss_info_14e4_16c6_14e4_8009 = + {0x14e4, 0x8009, pci_subsys_14e4_16c6_14e4_8009, 0}; +#undef pci_ss_info_14e4_8009 +#define pci_ss_info_14e4_8009 pci_ss_info_14e4_16c6_14e4_8009 +static const pciSubsystemInfo pci_ss_info_14e4_16c7_14e4_0009 = + {0x14e4, 0x0009, pci_subsys_14e4_16c7_14e4_0009, 0}; +#undef pci_ss_info_14e4_0009 +#define pci_ss_info_14e4_0009 pci_ss_info_14e4_16c7_14e4_0009 +static const pciSubsystemInfo pci_ss_info_14e4_16c7_14e4_000a = + {0x14e4, 0x000a, pci_subsys_14e4_16c7_14e4_000a, 0}; +#undef pci_ss_info_14e4_000a +#define pci_ss_info_14e4_000a pci_ss_info_14e4_16c7_14e4_000a +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1033_1033_8077 = + {0x1033, 0x8077, pci_subsys_14f1_1033_1033_8077, 0}; +#undef pci_ss_info_1033_8077 +#define pci_ss_info_1033_8077 pci_ss_info_14f1_1033_1033_8077 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_1033_122d_4027 = + {0x122d, 0x4027, pci_subsys_14f1_1033_122d_4027, 0}; +#undef pci_ss_info_122d_4027 +#define pci_ss_info_122d_4027 pci_ss_info_14f1_1033_122d_4027 +static const pciSubsystemInfo pci_ss_info_14f1_1033_122d_4030 = + {0x122d, 0x4030, pci_subsys_14f1_1033_122d_4030, 0}; +#undef pci_ss_info_122d_4030 +#define pci_ss_info_122d_4030 pci_ss_info_14f1_1033_122d_4030 +static const pciSubsystemInfo pci_ss_info_14f1_1033_122d_4034 = + {0x122d, 0x4034, pci_subsys_14f1_1033_122d_4034, 0}; +#undef pci_ss_info_122d_4034 +#define pci_ss_info_122d_4034 pci_ss_info_14f1_1033_122d_4034 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_020d = + {0x13e0, 0x020d, pci_subsys_14f1_1033_13e0_020d, 0}; +#undef pci_ss_info_13e0_020d +#define pci_ss_info_13e0_020d pci_ss_info_14f1_1033_13e0_020d +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_020e = + {0x13e0, 0x020e, pci_subsys_14f1_1033_13e0_020e, 0}; +#undef pci_ss_info_13e0_020e +#define pci_ss_info_13e0_020e pci_ss_info_14f1_1033_13e0_020e +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_0261 = + {0x13e0, 0x0261, pci_subsys_14f1_1033_13e0_0261, 0}; +#undef pci_ss_info_13e0_0261 +#define pci_ss_info_13e0_0261 pci_ss_info_14f1_1033_13e0_0261 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_0290 = + {0x13e0, 0x0290, pci_subsys_14f1_1033_13e0_0290, 0}; +#undef pci_ss_info_13e0_0290 +#define pci_ss_info_13e0_0290 pci_ss_info_14f1_1033_13e0_0290 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_02a0 = + {0x13e0, 0x02a0, pci_subsys_14f1_1033_13e0_02a0, 0}; +#undef pci_ss_info_13e0_02a0 +#define pci_ss_info_13e0_02a0 pci_ss_info_14f1_1033_13e0_02a0 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_02b0 = + {0x13e0, 0x02b0, pci_subsys_14f1_1033_13e0_02b0, 0}; +#undef pci_ss_info_13e0_02b0 +#define pci_ss_info_13e0_02b0 pci_ss_info_14f1_1033_13e0_02b0 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_02c0 = + {0x13e0, 0x02c0, pci_subsys_14f1_1033_13e0_02c0, 0}; +#undef pci_ss_info_13e0_02c0 +#define pci_ss_info_13e0_02c0 pci_ss_info_14f1_1033_13e0_02c0 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_02d0 = + {0x13e0, 0x02d0, pci_subsys_14f1_1033_13e0_02d0, 0}; +#undef pci_ss_info_13e0_02d0 +#define pci_ss_info_13e0_02d0 pci_ss_info_14f1_1033_13e0_02d0 +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_1500 = + {0x144f, 0x1500, pci_subsys_14f1_1033_144f_1500, 0}; +#undef pci_ss_info_144f_1500 +#define pci_ss_info_144f_1500 pci_ss_info_14f1_1033_144f_1500 +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_1501 = + {0x144f, 0x1501, pci_subsys_14f1_1033_144f_1501, 0}; +#undef pci_ss_info_144f_1501 +#define pci_ss_info_144f_1501 pci_ss_info_14f1_1033_144f_1501 +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_150a = + {0x144f, 0x150a, pci_subsys_14f1_1033_144f_150a, 0}; +#undef pci_ss_info_144f_150a +#define pci_ss_info_144f_150a pci_ss_info_14f1_1033_144f_150a +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_150b = + {0x144f, 0x150b, pci_subsys_14f1_1033_144f_150b, 0}; +#undef pci_ss_info_144f_150b +#define pci_ss_info_144f_150b pci_ss_info_14f1_1033_144f_150b +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_1510 = + {0x144f, 0x1510, pci_subsys_14f1_1033_144f_1510, 0}; +#undef pci_ss_info_144f_1510 +#define pci_ss_info_144f_1510 pci_ss_info_14f1_1033_144f_1510 +static const pciSubsystemInfo pci_ss_info_14f1_1035_10cf_1098 = + {0x10cf, 0x1098, pci_subsys_14f1_1035_10cf_1098, 0}; +#undef pci_ss_info_10cf_1098 +#define pci_ss_info_10cf_1098 pci_ss_info_14f1_1035_10cf_1098 +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1036_104d_8067 = + {0x104d, 0x8067, pci_subsys_14f1_1036_104d_8067, 0}; +#undef pci_ss_info_104d_8067 +#define pci_ss_info_104d_8067 pci_ss_info_14f1_1036_104d_8067 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_1036_122d_4029 = + {0x122d, 0x4029, pci_subsys_14f1_1036_122d_4029, 0}; +#undef pci_ss_info_122d_4029 +#define pci_ss_info_122d_4029 pci_ss_info_14f1_1036_122d_4029 +static const pciSubsystemInfo pci_ss_info_14f1_1036_122d_4031 = + {0x122d, 0x4031, pci_subsys_14f1_1036_122d_4031, 0}; +#undef pci_ss_info_122d_4031 +#define pci_ss_info_122d_4031 pci_ss_info_14f1_1036_122d_4031 +static const pciSubsystemInfo pci_ss_info_14f1_1036_13e0_0209 = + {0x13e0, 0x0209, pci_subsys_14f1_1036_13e0_0209, 0}; +#undef pci_ss_info_13e0_0209 +#define pci_ss_info_13e0_0209 pci_ss_info_14f1_1036_13e0_0209 +static const pciSubsystemInfo pci_ss_info_14f1_1036_13e0_020a = + {0x13e0, 0x020a, pci_subsys_14f1_1036_13e0_020a, 0}; +#undef pci_ss_info_13e0_020a +#define pci_ss_info_13e0_020a pci_ss_info_14f1_1036_13e0_020a +static const pciSubsystemInfo pci_ss_info_14f1_1036_13e0_0260 = + {0x13e0, 0x0260, pci_subsys_14f1_1036_13e0_0260, 0}; +#undef pci_ss_info_13e0_0260 +#define pci_ss_info_13e0_0260 pci_ss_info_14f1_1036_13e0_0260 +static const pciSubsystemInfo pci_ss_info_14f1_1036_13e0_0270 = + {0x13e0, 0x0270, pci_subsys_14f1_1036_13e0_0270, 0}; +#undef pci_ss_info_13e0_0270 +#define pci_ss_info_13e0_0270 pci_ss_info_14f1_1036_13e0_0270 +static const pciSubsystemInfo pci_ss_info_14f1_1066_122d_4033 = + {0x122d, 0x4033, pci_subsys_14f1_1066_122d_4033, 0}; +#undef pci_ss_info_122d_4033 +#define pci_ss_info_122d_4033 pci_ss_info_14f1_1066_122d_4033 +static const pciSubsystemInfo pci_ss_info_14f1_1453_13e0_0240 = + {0x13e0, 0x0240, pci_subsys_14f1_1453_13e0_0240, 0}; +#undef pci_ss_info_13e0_0240 +#define pci_ss_info_13e0_0240 pci_ss_info_14f1_1453_13e0_0240 +static const pciSubsystemInfo pci_ss_info_14f1_1453_13e0_0250 = + {0x13e0, 0x0250, pci_subsys_14f1_1453_13e0_0250, 0}; +#undef pci_ss_info_13e0_0250 +#define pci_ss_info_13e0_0250 pci_ss_info_14f1_1453_13e0_0250 +static const pciSubsystemInfo pci_ss_info_14f1_1453_144f_1502 = + {0x144f, 0x1502, pci_subsys_14f1_1453_144f_1502, 0}; +#undef pci_ss_info_144f_1502 +#define pci_ss_info_144f_1502 pci_ss_info_14f1_1453_144f_1502 +static const pciSubsystemInfo pci_ss_info_14f1_1453_144f_1503 = + {0x144f, 0x1503, pci_subsys_14f1_1453_144f_1503, 0}; +#undef pci_ss_info_144f_1503 +#define pci_ss_info_144f_1503 pci_ss_info_14f1_1453_144f_1503 +static const pciSubsystemInfo pci_ss_info_14f1_1456_122d_4035 = + {0x122d, 0x4035, pci_subsys_14f1_1456_122d_4035, 0}; +#undef pci_ss_info_122d_4035 +#define pci_ss_info_122d_4035 pci_ss_info_14f1_1456_122d_4035 +static const pciSubsystemInfo pci_ss_info_14f1_1456_122d_4302 = + {0x122d, 0x4302, pci_subsys_14f1_1456_122d_4302, 0}; +#undef pci_ss_info_122d_4302 +#define pci_ss_info_122d_4302 pci_ss_info_14f1_1456_122d_4302 +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1803_0e11_0023 = + {0x0e11, 0x0023, pci_subsys_14f1_1803_0e11_0023, 0}; +#undef pci_ss_info_0e11_0023 +#define pci_ss_info_0e11_0023 pci_ss_info_14f1_1803_0e11_0023 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1803_0e11_0043 = + {0x0e11, 0x0043, pci_subsys_14f1_1803_0e11_0043, 0}; +#undef pci_ss_info_0e11_0043 +#define pci_ss_info_0e11_0043 pci_ss_info_14f1_1803_0e11_0043 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1815_0e11_0022 = + {0x0e11, 0x0022, pci_subsys_14f1_1815_0e11_0022, 0}; +#undef pci_ss_info_0e11_0022 +#define pci_ss_info_0e11_0022 pci_ss_info_14f1_1815_0e11_0022 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1815_0e11_0042 = + {0x0e11, 0x0042, pci_subsys_14f1_1815_0e11_0042, 0}; +#undef pci_ss_info_0e11_0042 +#define pci_ss_info_0e11_0042 pci_ss_info_14f1_1815_0e11_0042 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_0e11_b195 = + {0x0e11, 0xb195, pci_subsys_14f1_2013_0e11_b195, 0}; +#undef pci_ss_info_0e11_b195 +#define pci_ss_info_0e11_b195 pci_ss_info_14f1_2013_0e11_b195 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_0e11_b196 = + {0x0e11, 0xb196, pci_subsys_14f1_2013_0e11_b196, 0}; +#undef pci_ss_info_0e11_b196 +#define pci_ss_info_0e11_b196 pci_ss_info_14f1_2013_0e11_b196 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_0e11_b1be = + {0x0e11, 0xb1be, pci_subsys_14f1_2013_0e11_b1be, 0}; +#undef pci_ss_info_0e11_b1be +#define pci_ss_info_0e11_b1be pci_ss_info_14f1_2013_0e11_b1be +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_1025_8013 = + {0x1025, 0x8013, pci_subsys_14f1_2013_1025_8013, 0}; +#undef pci_ss_info_1025_8013 +#define pci_ss_info_1025_8013 pci_ss_info_14f1_2013_1025_8013 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_1033_809d = + {0x1033, 0x809d, pci_subsys_14f1_2013_1033_809d, 0}; +#undef pci_ss_info_1033_809d +#define pci_ss_info_1033_809d pci_ss_info_14f1_2013_1033_809d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_1033_80bc = + {0x1033, 0x80bc, pci_subsys_14f1_2013_1033_80bc, 0}; +#undef pci_ss_info_1033_80bc +#define pci_ss_info_1033_80bc pci_ss_info_14f1_2013_1033_80bc +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_2013_155d_6793 = + {0x155d, 0x6793, pci_subsys_14f1_2013_155d_6793, 0}; +#undef pci_ss_info_155d_6793 +#define pci_ss_info_155d_6793 pci_ss_info_14f1_2013_155d_6793 +static const pciSubsystemInfo pci_ss_info_14f1_2013_155d_8850 = + {0x155d, 0x8850, pci_subsys_14f1_2013_155d_8850, 0}; +#undef pci_ss_info_155d_8850 +#define pci_ss_info_155d_8850 pci_ss_info_14f1_2013_155d_8850 +static const pciSubsystemInfo pci_ss_info_14f1_2093_155d_2f07 = + {0x155d, 0x2f07, pci_subsys_14f1_2093_155d_2f07, 0}; +#undef pci_ss_info_155d_2f07 +#define pci_ss_info_155d_2f07 pci_ss_info_14f1_2093_155d_2f07 +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2443_104d_8075 = + {0x104d, 0x8075, pci_subsys_14f1_2443_104d_8075, 0}; +#undef pci_ss_info_104d_8075 +#define pci_ss_info_104d_8075 pci_ss_info_14f1_2443_104d_8075 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2443_104d_8083 = + {0x104d, 0x8083, pci_subsys_14f1_2443_104d_8083, 0}; +#undef pci_ss_info_104d_8083 +#define pci_ss_info_104d_8083 pci_ss_info_14f1_2443_104d_8083 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2443_104d_8097 = + {0x104d, 0x8097, pci_subsys_14f1_2443_104d_8097, 0}; +#undef pci_ss_info_104d_8097 +#define pci_ss_info_104d_8097 pci_ss_info_14f1_2443_104d_8097 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_2f00_13e0_8d84 = + {0x13e0, 0x8d84, pci_subsys_14f1_2f00_13e0_8d84, 0}; +#undef pci_ss_info_13e0_8d84 +#define pci_ss_info_13e0_8d84 pci_ss_info_14f1_2f00_13e0_8d84 +static const pciSubsystemInfo pci_ss_info_14f1_2f00_13e0_8d85 = + {0x13e0, 0x8d85, pci_subsys_14f1_2f00_13e0_8d85, 0}; +#undef pci_ss_info_13e0_8d85 +#define pci_ss_info_13e0_8d85 pci_ss_info_14f1_2f00_13e0_8d85 +static const pciSubsystemInfo pci_ss_info_14f1_2f00_14f1_2004 = + {0x14f1, 0x2004, pci_subsys_14f1_2f00_14f1_2004, 0}; +#undef pci_ss_info_14f1_2004 +#define pci_ss_info_14f1_2004 pci_ss_info_14f1_2f00_14f1_2004 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1516_0803_1320_10bd = + {0x1320, 0x10bd, pci_subsys_1516_0803_1320_10bd, 0}; +#undef pci_ss_info_1320_10bd +#define pci_ss_info_1320_10bd pci_ss_info_1516_0803_1320_10bd +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0200 = + {0x1522, 0x0200, pci_subsys_1522_0100_1522_0200, 0}; +#undef pci_ss_info_1522_0200 +#define pci_ss_info_1522_0200 pci_ss_info_1522_0100_1522_0200 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0300 = + {0x1522, 0x0300, pci_subsys_1522_0100_1522_0300, 0}; +#undef pci_ss_info_1522_0300 +#define pci_ss_info_1522_0300 pci_ss_info_1522_0100_1522_0300 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0400 = + {0x1522, 0x0400, pci_subsys_1522_0100_1522_0400, 0}; +#undef pci_ss_info_1522_0400 +#define pci_ss_info_1522_0400 pci_ss_info_1522_0100_1522_0400 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0500 = + {0x1522, 0x0500, pci_subsys_1522_0100_1522_0500, 0}; +#undef pci_ss_info_1522_0500 +#define pci_ss_info_1522_0500 pci_ss_info_1522_0100_1522_0500 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0600 = + {0x1522, 0x0600, pci_subsys_1522_0100_1522_0600, 0}; +#undef pci_ss_info_1522_0600 +#define pci_ss_info_1522_0600 pci_ss_info_1522_0100_1522_0600 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0700 = + {0x1522, 0x0700, pci_subsys_1522_0100_1522_0700, 0}; +#undef pci_ss_info_1522_0700 +#define pci_ss_info_1522_0700 pci_ss_info_1522_0100_1522_0700 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0800 = + {0x1522, 0x0800, pci_subsys_1522_0100_1522_0800, 0}; +#undef pci_ss_info_1522_0800 +#define pci_ss_info_1522_0800 pci_ss_info_1522_0100_1522_0800 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_173b_03ea_173b_0001 = + {0x173b, 0x0001, pci_subsys_173b_03ea_173b_0001, 0}; +#undef pci_ss_info_173b_0001 +#define pci_ss_info_173b_0001 pci_ss_info_173b_03ea_173b_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1813_4000_16be_0001 = + {0x16be, 0x0001, pci_subsys_1813_4000_16be_0001, 0}; +#undef pci_ss_info_16be_0001 +#define pci_ss_info_16be_0001 pci_ss_info_1813_4000_16be_0001 +static const pciSubsystemInfo pci_ss_info_1813_4100_16be_0002 = + {0x16be, 0x0002, pci_subsys_1813_4100_16be_0002, 0}; +#undef pci_ss_info_16be_0002 +#define pci_ss_info_16be_0002 pci_ss_info_1813_4100_16be_0002 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_3388_8011_3388_8011 = + {0x3388, 0x8011, pci_subsys_3388_8011_3388_8011, 0}; +#undef pci_ss_info_3388_8011 +#define pci_ss_info_3388_8011 pci_ss_info_3388_8011_3388_8011 +static const pciSubsystemInfo pci_ss_info_3388_8012_3388_8012 = + {0x3388, 0x8012, pci_subsys_3388_8012_3388_8012, 0}; +#undef pci_ss_info_3388_8012 +#define pci_ss_info_3388_8012 pci_ss_info_3388_8012_3388_8012 +static const pciSubsystemInfo pci_ss_info_3388_8013_3388_8013 = + {0x3388, 0x8013, pci_subsys_3388_8013_3388_8013, 0}; +#undef pci_ss_info_3388_8013 +#define pci_ss_info_3388_8013 pci_ss_info_3388_8013_3388_8013 +#endif +static const pciSubsystemInfo pci_ss_info_3d3d_0009_1040_0011 = + {0x1040, 0x0011, pci_subsys_3d3d_0009_1040_0011, 0}; +#undef pci_ss_info_1040_0011 +#define pci_ss_info_1040_0011 pci_ss_info_3d3d_0009_1040_0011 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0100 = + {0x3d3d, 0x0100, pci_subsys_3d3d_0009_3d3d_0100, 0}; +#undef pci_ss_info_3d3d_0100 +#define pci_ss_info_3d3d_0100 pci_ss_info_3d3d_0009_3d3d_0100 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0111 = + {0x3d3d, 0x0111, pci_subsys_3d3d_0009_3d3d_0111, 0}; +#undef pci_ss_info_3d3d_0111 +#define pci_ss_info_3d3d_0111 pci_ss_info_3d3d_0009_3d3d_0111 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0114 = + {0x3d3d, 0x0114, pci_subsys_3d3d_0009_3d3d_0114, 0}; +#undef pci_ss_info_3d3d_0114 +#define pci_ss_info_3d3d_0114 pci_ss_info_3d3d_0009_3d3d_0114 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0116 = + {0x3d3d, 0x0116, pci_subsys_3d3d_0009_3d3d_0116, 0}; +#undef pci_ss_info_3d3d_0116 +#define pci_ss_info_3d3d_0116 pci_ss_info_3d3d_0009_3d3d_0116 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0119 = + {0x3d3d, 0x0119, pci_subsys_3d3d_0009_3d3d_0119, 0}; +#undef pci_ss_info_3d3d_0119 +#define pci_ss_info_3d3d_0119 pci_ss_info_3d3d_0009_3d3d_0119 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0120 = + {0x3d3d, 0x0120, pci_subsys_3d3d_0009_3d3d_0120, 0}; +#undef pci_ss_info_3d3d_0120 +#define pci_ss_info_3d3d_0120 pci_ss_info_3d3d_0009_3d3d_0120 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0125 = + {0x3d3d, 0x0125, pci_subsys_3d3d_0009_3d3d_0125, 0}; +#undef pci_ss_info_3d3d_0125 +#define pci_ss_info_3d3d_0125 pci_ss_info_3d3d_0009_3d3d_0125 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0127 = + {0x3d3d, 0x0127, pci_subsys_3d3d_0009_3d3d_0127, 0}; +#undef pci_ss_info_3d3d_0127 +#define pci_ss_info_3d3d_0127 pci_ss_info_3d3d_0009_3d3d_0127 +static const pciSubsystemInfo pci_ss_info_3d3d_000a_3d3d_0121 = + {0x3d3d, 0x0121, pci_subsys_3d3d_000a_3d3d_0121, 0}; +#undef pci_ss_info_3d3d_0121 +#define pci_ss_info_3d3d_0121 pci_ss_info_3d3d_000a_3d3d_0121 +static const pciSubsystemInfo pci_ss_info_3d3d_000c_3d3d_0144 = + {0x3d3d, 0x0144, pci_subsys_3d3d_000c_3d3d_0144, 0}; +#undef pci_ss_info_3d3d_0144 +#define pci_ss_info_3d3d_0144 pci_ss_info_3d3d_000c_3d3d_0144 +static const pciSubsystemInfo pci_ss_info_4005_4000_4005_4000 = + {0x4005, 0x4000, pci_subsys_4005_4000_4005_4000, 0}; +#undef pci_ss_info_4005_4000 +#define pci_ss_info_4005_4000 pci_ss_info_4005_4000_4005_4000 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_4a14_5000_4a14_5000 = + {0x4a14, 0x5000, pci_subsys_4a14_5000_4a14_5000, 0}; +#undef pci_ss_info_4a14_5000 +#define pci_ss_info_4a14_5000 pci_ss_info_4a14_5000_4a14_5000 +#endif +static const pciSubsystemInfo pci_ss_info_5333_8900_5333_8900 = + {0x5333, 0x8900, pci_subsys_5333_8900_5333_8900, 0}; +#undef pci_ss_info_5333_8900 +#define pci_ss_info_5333_8900 pci_ss_info_5333_8900_5333_8900 +static const pciSubsystemInfo pci_ss_info_5333_8901_5333_8901 = + {0x5333, 0x8901, pci_subsys_5333_8901_5333_8901, 0}; +#undef pci_ss_info_5333_8901 +#define pci_ss_info_5333_8901 pci_ss_info_5333_8901_5333_8901 +static const pciSubsystemInfo pci_ss_info_5333_8904_1014_00db = + {0x1014, 0x00db, pci_subsys_5333_8904_1014_00db, 0}; +#undef pci_ss_info_1014_00db +#define pci_ss_info_1014_00db pci_ss_info_5333_8904_1014_00db +static const pciSubsystemInfo pci_ss_info_5333_8904_5333_8904 = + {0x5333, 0x8904, pci_subsys_5333_8904_5333_8904, 0}; +#undef pci_ss_info_5333_8904 +#define pci_ss_info_5333_8904 pci_ss_info_5333_8904_5333_8904 +static const pciSubsystemInfo pci_ss_info_5333_8a01_0e11_b032 = + {0x0e11, 0xb032, pci_subsys_5333_8a01_0e11_b032, 0}; +#undef pci_ss_info_0e11_b032 +#define pci_ss_info_0e11_b032 pci_ss_info_5333_8a01_0e11_b032 +static const pciSubsystemInfo pci_ss_info_5333_8a01_10b4_1617 = + {0x10b4, 0x1617, pci_subsys_5333_8a01_10b4_1617, 0}; +#undef pci_ss_info_10b4_1617 +#define pci_ss_info_10b4_1617 pci_ss_info_5333_8a01_10b4_1617 +static const pciSubsystemInfo pci_ss_info_5333_8a01_10b4_1717 = + {0x10b4, 0x1717, pci_subsys_5333_8a01_10b4_1717, 0}; +#undef pci_ss_info_10b4_1717 +#define pci_ss_info_10b4_1717 pci_ss_info_5333_8a01_10b4_1717 +static const pciSubsystemInfo pci_ss_info_5333_8a01_5333_8a01 = + {0x5333, 0x8a01, pci_subsys_5333_8a01_5333_8a01, 0}; +#undef pci_ss_info_5333_8a01 +#define pci_ss_info_5333_8a01 pci_ss_info_5333_8a01_5333_8a01 +static const pciSubsystemInfo pci_ss_info_5333_8a10_1092_8a10 = + {0x1092, 0x8a10, pci_subsys_5333_8a10_1092_8a10, 0}; +#undef pci_ss_info_1092_8a10 +#define pci_ss_info_1092_8a10 pci_ss_info_5333_8a10_1092_8a10 +static const pciSubsystemInfo pci_ss_info_5333_8a13_5333_8a13 = + {0x5333, 0x8a13, pci_subsys_5333_8a13_5333_8a13, 0}; +#undef pci_ss_info_5333_8a13 +#define pci_ss_info_5333_8a13 pci_ss_info_5333_8a13_5333_8a13 +static const pciSubsystemInfo pci_ss_info_5333_8a20_5333_8a20 = + {0x5333, 0x8a20, pci_subsys_5333_8a20_5333_8a20, 0}; +#undef pci_ss_info_5333_8a20 +#define pci_ss_info_5333_8a20 pci_ss_info_5333_8a20_5333_8a20 +static const pciSubsystemInfo pci_ss_info_5333_8a21_5333_8a21 = + {0x5333, 0x8a21, pci_subsys_5333_8a21_5333_8a21, 0}; +#undef pci_ss_info_5333_8a21 +#define pci_ss_info_5333_8a21 pci_ss_info_5333_8a21_5333_8a21 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1033_8068 = + {0x1033, 0x8068, pci_subsys_5333_8a22_1033_8068, 0}; +#undef pci_ss_info_1033_8068 +#define pci_ss_info_1033_8068 pci_ss_info_5333_8a22_1033_8068 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1033_8069 = + {0x1033, 0x8069, pci_subsys_5333_8a22_1033_8069, 0}; +#undef pci_ss_info_1033_8069 +#define pci_ss_info_1033_8069 pci_ss_info_5333_8a22_1033_8069 +static const pciSubsystemInfo pci_ss_info_5333_8a22_105d_0018 = + {0x105d, 0x0018, pci_subsys_5333_8a22_105d_0018, 0}; +#undef pci_ss_info_105d_0018 +#define pci_ss_info_105d_0018 pci_ss_info_5333_8a22_105d_0018 +static const pciSubsystemInfo pci_ss_info_5333_8a22_105d_002a = + {0x105d, 0x002a, pci_subsys_5333_8a22_105d_002a, 0}; +#undef pci_ss_info_105d_002a +#define pci_ss_info_105d_002a pci_ss_info_5333_8a22_105d_002a +static const pciSubsystemInfo pci_ss_info_5333_8a22_105d_003a = + {0x105d, 0x003a, pci_subsys_5333_8a22_105d_003a, 0}; +#undef pci_ss_info_105d_003a +#define pci_ss_info_105d_003a pci_ss_info_5333_8a22_105d_003a +static const pciSubsystemInfo pci_ss_info_5333_8a22_105d_092f = + {0x105d, 0x092f, pci_subsys_5333_8a22_105d_092f, 0}; +#undef pci_ss_info_105d_092f +#define pci_ss_info_105d_092f pci_ss_info_5333_8a22_105d_092f +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4207 = + {0x1092, 0x4207, pci_subsys_5333_8a22_1092_4207, 0}; +#undef pci_ss_info_1092_4207 +#define pci_ss_info_1092_4207 pci_ss_info_5333_8a22_1092_4207 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4800 = + {0x1092, 0x4800, pci_subsys_5333_8a22_1092_4800, 0}; +#undef pci_ss_info_1092_4800 +#define pci_ss_info_1092_4800 pci_ss_info_5333_8a22_1092_4800 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4807 = + {0x1092, 0x4807, pci_subsys_5333_8a22_1092_4807, 0}; +#undef pci_ss_info_1092_4807 +#define pci_ss_info_1092_4807 pci_ss_info_5333_8a22_1092_4807 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4808 = + {0x1092, 0x4808, pci_subsys_5333_8a22_1092_4808, 0}; +#undef pci_ss_info_1092_4808 +#define pci_ss_info_1092_4808 pci_ss_info_5333_8a22_1092_4808 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4809 = + {0x1092, 0x4809, pci_subsys_5333_8a22_1092_4809, 0}; +#undef pci_ss_info_1092_4809 +#define pci_ss_info_1092_4809 pci_ss_info_5333_8a22_1092_4809 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_480e = + {0x1092, 0x480e, pci_subsys_5333_8a22_1092_480e, 0}; +#undef pci_ss_info_1092_480e +#define pci_ss_info_1092_480e pci_ss_info_5333_8a22_1092_480e +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4904 = + {0x1092, 0x4904, pci_subsys_5333_8a22_1092_4904, 0}; +#undef pci_ss_info_1092_4904 +#define pci_ss_info_1092_4904 pci_ss_info_5333_8a22_1092_4904 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4905 = + {0x1092, 0x4905, pci_subsys_5333_8a22_1092_4905, 0}; +#undef pci_ss_info_1092_4905 +#define pci_ss_info_1092_4905 pci_ss_info_5333_8a22_1092_4905 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4a09 = + {0x1092, 0x4a09, pci_subsys_5333_8a22_1092_4a09, 0}; +#undef pci_ss_info_1092_4a09 +#define pci_ss_info_1092_4a09 pci_ss_info_5333_8a22_1092_4a09 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4a0b = + {0x1092, 0x4a0b, pci_subsys_5333_8a22_1092_4a0b, 0}; +#undef pci_ss_info_1092_4a0b +#define pci_ss_info_1092_4a0b pci_ss_info_5333_8a22_1092_4a0b +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4a0f = + {0x1092, 0x4a0f, pci_subsys_5333_8a22_1092_4a0f, 0}; +#undef pci_ss_info_1092_4a0f +#define pci_ss_info_1092_4a0f pci_ss_info_5333_8a22_1092_4a0f +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4e01 = + {0x1092, 0x4e01, pci_subsys_5333_8a22_1092_4e01, 0}; +#undef pci_ss_info_1092_4e01 +#define pci_ss_info_1092_4e01 pci_ss_info_5333_8a22_1092_4e01 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1102_101d = + {0x1102, 0x101d, pci_subsys_5333_8a22_1102_101d, 0}; +#undef pci_ss_info_1102_101d +#define pci_ss_info_1102_101d pci_ss_info_5333_8a22_1102_101d +static const pciSubsystemInfo pci_ss_info_5333_8a22_1102_101e = + {0x1102, 0x101e, pci_subsys_5333_8a22_1102_101e, 0}; +#undef pci_ss_info_1102_101e +#define pci_ss_info_1102_101e pci_ss_info_5333_8a22_1102_101e +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8100 = + {0x5333, 0x8100, pci_subsys_5333_8a22_5333_8100, 0}; +#undef pci_ss_info_5333_8100 +#define pci_ss_info_5333_8100 pci_ss_info_5333_8a22_5333_8100 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8110 = + {0x5333, 0x8110, pci_subsys_5333_8a22_5333_8110, 0}; +#undef pci_ss_info_5333_8110 +#define pci_ss_info_5333_8110 pci_ss_info_5333_8a22_5333_8110 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8125 = + {0x5333, 0x8125, pci_subsys_5333_8a22_5333_8125, 0}; +#undef pci_ss_info_5333_8125 +#define pci_ss_info_5333_8125 pci_ss_info_5333_8a22_5333_8125 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8143 = + {0x5333, 0x8143, pci_subsys_5333_8a22_5333_8143, 0}; +#undef pci_ss_info_5333_8143 +#define pci_ss_info_5333_8143 pci_ss_info_5333_8a22_5333_8143 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8a22 = + {0x5333, 0x8a22, pci_subsys_5333_8a22_5333_8a22, 0}; +#undef pci_ss_info_5333_8a22 +#define pci_ss_info_5333_8a22 pci_ss_info_5333_8a22_5333_8a22 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8a2e = + {0x5333, 0x8a2e, pci_subsys_5333_8a22_5333_8a2e, 0}; +#undef pci_ss_info_5333_8a2e +#define pci_ss_info_5333_8a2e pci_ss_info_5333_8a22_5333_8a2e +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_9125 = + {0x5333, 0x9125, pci_subsys_5333_8a22_5333_9125, 0}; +#undef pci_ss_info_5333_9125 +#define pci_ss_info_5333_9125 pci_ss_info_5333_8a22_5333_9125 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_9143 = + {0x5333, 0x9143, pci_subsys_5333_8a22_5333_9143, 0}; +#undef pci_ss_info_5333_9143 +#define pci_ss_info_5333_9143 pci_ss_info_5333_8a22_5333_9143 +static const pciSubsystemInfo pci_ss_info_5333_8c01_1179_0001 = + {0x1179, 0x0001, pci_subsys_5333_8c01_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_5333_8c01_1179_0001 +static const pciSubsystemInfo pci_ss_info_5333_8c12_1014_017f = + {0x1014, 0x017f, pci_subsys_5333_8c12_1014_017f, 0}; +#undef pci_ss_info_1014_017f +#define pci_ss_info_1014_017f pci_ss_info_5333_8c12_1014_017f +static const pciSubsystemInfo pci_ss_info_5333_8c13_1179_0001 = + {0x1179, 0x0001, pci_subsys_5333_8c13_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_5333_8c13_1179_0001 +static const pciSubsystemInfo pci_ss_info_5333_8c2e_1014_01fc = + {0x1014, 0x01fc, pci_subsys_5333_8c2e_1014_01fc, 0}; +#undef pci_ss_info_1014_01fc +#define pci_ss_info_1014_01fc pci_ss_info_5333_8c2e_1014_01fc +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5932 = + {0x1092, 0x5932, pci_subsys_5333_9102_1092_5932, 0}; +#undef pci_ss_info_1092_5932 +#define pci_ss_info_1092_5932 pci_ss_info_5333_9102_1092_5932 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5934 = + {0x1092, 0x5934, pci_subsys_5333_9102_1092_5934, 0}; +#undef pci_ss_info_1092_5934 +#define pci_ss_info_1092_5934 pci_ss_info_5333_9102_1092_5934 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5952 = + {0x1092, 0x5952, pci_subsys_5333_9102_1092_5952, 0}; +#undef pci_ss_info_1092_5952 +#define pci_ss_info_1092_5952 pci_ss_info_5333_9102_1092_5952 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5954 = + {0x1092, 0x5954, pci_subsys_5333_9102_1092_5954, 0}; +#undef pci_ss_info_1092_5954 +#define pci_ss_info_1092_5954 pci_ss_info_5333_9102_1092_5954 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5a35 = + {0x1092, 0x5a35, pci_subsys_5333_9102_1092_5a35, 0}; +#undef pci_ss_info_1092_5a35 +#define pci_ss_info_1092_5a35 pci_ss_info_5333_9102_1092_5a35 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5a37 = + {0x1092, 0x5a37, pci_subsys_5333_9102_1092_5a37, 0}; +#undef pci_ss_info_1092_5a37 +#define pci_ss_info_1092_5a37 pci_ss_info_5333_9102_1092_5a37 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5a55 = + {0x1092, 0x5a55, pci_subsys_5333_9102_1092_5a55, 0}; +#undef pci_ss_info_1092_5a55 +#define pci_ss_info_1092_5a55 pci_ss_info_5333_9102_1092_5a55 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5a57 = + {0x1092, 0x5a57, pci_subsys_5333_9102_1092_5a57, 0}; +#undef pci_ss_info_1092_5a57 +#define pci_ss_info_1092_5a57 pci_ss_info_5333_9102_1092_5a57 +static const pciSubsystemInfo pci_ss_info_8086_1000_0e11_b0df = + {0x0e11, 0xb0df, pci_subsys_8086_1000_0e11_b0df, 0}; +#undef pci_ss_info_0e11_b0df +#define pci_ss_info_0e11_b0df pci_ss_info_8086_1000_0e11_b0df +static const pciSubsystemInfo pci_ss_info_8086_1000_0e11_b0e0 = + {0x0e11, 0xb0e0, pci_subsys_8086_1000_0e11_b0e0, 0}; +#undef pci_ss_info_0e11_b0e0 +#define pci_ss_info_0e11_b0e0 pci_ss_info_8086_1000_0e11_b0e0 +static const pciSubsystemInfo pci_ss_info_8086_1000_0e11_b123 = + {0x0e11, 0xb123, pci_subsys_8086_1000_0e11_b123, 0}; +#undef pci_ss_info_0e11_b123 +#define pci_ss_info_0e11_b123 pci_ss_info_8086_1000_0e11_b123 +static const pciSubsystemInfo pci_ss_info_8086_1000_1014_0119 = + {0x1014, 0x0119, pci_subsys_8086_1000_1014_0119, 0}; +#undef pci_ss_info_1014_0119 +#define pci_ss_info_1014_0119 pci_ss_info_8086_1000_1014_0119 +static const pciSubsystemInfo pci_ss_info_8086_1000_8086_1000 = + {0x8086, 0x1000, pci_subsys_8086_1000_8086_1000, 0}; +#undef pci_ss_info_8086_1000 +#define pci_ss_info_8086_1000 pci_ss_info_8086_1000_8086_1000 +static const pciSubsystemInfo pci_ss_info_8086_1001_0e11_004a = + {0x0e11, 0x004a, pci_subsys_8086_1001_0e11_004a, 0}; +#undef pci_ss_info_0e11_004a +#define pci_ss_info_0e11_004a pci_ss_info_8086_1001_0e11_004a +static const pciSubsystemInfo pci_ss_info_8086_1001_1014_01ea = + {0x1014, 0x01ea, pci_subsys_8086_1001_1014_01ea, 0}; +#undef pci_ss_info_1014_01ea +#define pci_ss_info_1014_01ea pci_ss_info_8086_1001_1014_01ea +static const pciSubsystemInfo pci_ss_info_8086_1001_8086_1003 = + {0x8086, 0x1003, pci_subsys_8086_1001_8086_1003, 0}; +#undef pci_ss_info_8086_1003 +#define pci_ss_info_8086_1003 pci_ss_info_8086_1001_8086_1003 +static const pciSubsystemInfo pci_ss_info_8086_1002_8086_200e = + {0x8086, 0x200e, pci_subsys_8086_1002_8086_200e, 0}; +#undef pci_ss_info_8086_200e +#define pci_ss_info_8086_200e pci_ss_info_8086_1002_8086_200e +static const pciSubsystemInfo pci_ss_info_8086_1002_8086_2013 = + {0x8086, 0x2013, pci_subsys_8086_1002_8086_2013, 0}; +#undef pci_ss_info_8086_2013 +#define pci_ss_info_8086_2013 pci_ss_info_8086_1002_8086_2013 +static const pciSubsystemInfo pci_ss_info_8086_1002_8086_2017 = + {0x8086, 0x2017, pci_subsys_8086_1002_8086_2017, 0}; +#undef pci_ss_info_8086_2017 +#define pci_ss_info_8086_2017 pci_ss_info_8086_1002_8086_2017 +static const pciSubsystemInfo pci_ss_info_8086_1004_0e11_0049 = + {0x0e11, 0x0049, pci_subsys_8086_1004_0e11_0049, 0}; +#undef pci_ss_info_0e11_0049 +#define pci_ss_info_0e11_0049 pci_ss_info_8086_1004_0e11_0049 +static const pciSubsystemInfo pci_ss_info_8086_1004_0e11_b1a4 = + {0x0e11, 0xb1a4, pci_subsys_8086_1004_0e11_b1a4, 0}; +#undef pci_ss_info_0e11_b1a4 +#define pci_ss_info_0e11_b1a4 pci_ss_info_8086_1004_0e11_b1a4 +static const pciSubsystemInfo pci_ss_info_8086_1004_1014_10f2 = + {0x1014, 0x10f2, pci_subsys_8086_1004_1014_10f2, 0}; +#undef pci_ss_info_1014_10f2 +#define pci_ss_info_1014_10f2 pci_ss_info_8086_1004_1014_10f2 +static const pciSubsystemInfo pci_ss_info_8086_1004_8086_1004 = + {0x8086, 0x1004, pci_subsys_8086_1004_8086_1004, 0}; +#undef pci_ss_info_8086_1004 +#define pci_ss_info_8086_1004 pci_ss_info_8086_1004_8086_1004 +static const pciSubsystemInfo pci_ss_info_8086_1004_8086_2004 = + {0x8086, 0x2004, pci_subsys_8086_1004_8086_2004, 0}; +#undef pci_ss_info_8086_2004 +#define pci_ss_info_8086_2004 pci_ss_info_8086_1004_8086_2004 +static const pciSubsystemInfo pci_ss_info_8086_1008_8086_1107 = + {0x8086, 0x1107, pci_subsys_8086_1008_8086_1107, 0}; +#undef pci_ss_info_8086_1107 +#define pci_ss_info_8086_1107 pci_ss_info_8086_1008_8086_1107 +static const pciSubsystemInfo pci_ss_info_8086_1008_8086_2107 = + {0x8086, 0x2107, pci_subsys_8086_1008_8086_2107, 0}; +#undef pci_ss_info_8086_2107 +#define pci_ss_info_8086_2107 pci_ss_info_8086_1008_8086_2107 +static const pciSubsystemInfo pci_ss_info_8086_1008_8086_2110 = + {0x8086, 0x2110, pci_subsys_8086_1008_8086_2110, 0}; +#undef pci_ss_info_8086_2110 +#define pci_ss_info_8086_2110 pci_ss_info_8086_1008_8086_2110 +static const pciSubsystemInfo pci_ss_info_8086_1009_8086_1109 = + {0x8086, 0x1109, pci_subsys_8086_1009_8086_1109, 0}; +#undef pci_ss_info_8086_1109 +#define pci_ss_info_8086_1109 pci_ss_info_8086_1009_8086_1109 +static const pciSubsystemInfo pci_ss_info_8086_1009_8086_2109 = + {0x8086, 0x2109, pci_subsys_8086_1009_8086_2109, 0}; +#undef pci_ss_info_8086_2109 +#define pci_ss_info_8086_2109 pci_ss_info_8086_1009_8086_2109 +static const pciSubsystemInfo pci_ss_info_8086_100c_8086_1112 = + {0x8086, 0x1112, pci_subsys_8086_100c_8086_1112, 0}; +#undef pci_ss_info_8086_1112 +#define pci_ss_info_8086_1112 pci_ss_info_8086_100c_8086_1112 +static const pciSubsystemInfo pci_ss_info_8086_100c_8086_2112 = + {0x8086, 0x2112, pci_subsys_8086_100c_8086_2112, 0}; +#undef pci_ss_info_8086_2112 +#define pci_ss_info_8086_2112 pci_ss_info_8086_100c_8086_2112 +static const pciSubsystemInfo pci_ss_info_8086_100e_8086_001e = + {0x8086, 0x001e, pci_subsys_8086_100e_8086_001e, 0}; +#undef pci_ss_info_8086_001e +#define pci_ss_info_8086_001e pci_ss_info_8086_100e_8086_001e +static const pciSubsystemInfo pci_ss_info_8086_100e_8086_002e = + {0x8086, 0x002e, pci_subsys_8086_100e_8086_002e, 0}; +#undef pci_ss_info_8086_002e +#define pci_ss_info_8086_002e pci_ss_info_8086_100e_8086_002e +static const pciSubsystemInfo pci_ss_info_8086_100f_8086_1001 = + {0x8086, 0x1001, pci_subsys_8086_100f_8086_1001, 0}; +#undef pci_ss_info_8086_1001 +#define pci_ss_info_8086_1001 pci_ss_info_8086_100f_8086_1001 +static const pciSubsystemInfo pci_ss_info_8086_1010_8086_1011 = + {0x8086, 0x1011, pci_subsys_8086_1010_8086_1011, 0}; +#undef pci_ss_info_8086_1011 +#define pci_ss_info_8086_1011 pci_ss_info_8086_1010_8086_1011 +static const pciSubsystemInfo pci_ss_info_8086_1011_8086_1002 = + {0x8086, 0x1002, pci_subsys_8086_1011_8086_1002, 0}; +#undef pci_ss_info_8086_1002 +#define pci_ss_info_8086_1002 pci_ss_info_8086_1011_8086_1002 +static const pciSubsystemInfo pci_ss_info_8086_1012_8086_1012 = + {0x8086, 0x1012, pci_subsys_8086_1012_8086_1012, 0}; +#undef pci_ss_info_8086_1012 +#define pci_ss_info_8086_1012 pci_ss_info_8086_1012_8086_1012 +static const pciSubsystemInfo pci_ss_info_8086_1031_1014_0209 = + {0x1014, 0x0209, pci_subsys_8086_1031_1014_0209, 0}; +#undef pci_ss_info_1014_0209 +#define pci_ss_info_1014_0209 pci_ss_info_8086_1031_1014_0209 +static const pciSubsystemInfo pci_ss_info_8086_1031_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_1031_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_1031_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_1031_107b_5350 = + {0x107b, 0x5350, pci_subsys_8086_1031_107b_5350, 0}; +#undef pci_ss_info_107b_5350 +#define pci_ss_info_107b_5350 pci_ss_info_8086_1031_107b_5350 +static const pciSubsystemInfo pci_ss_info_8086_1031_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_1031_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_1031_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_1031_144d_c000 = + {0x144d, 0xc000, pci_subsys_8086_1031_144d_c000, 0}; +#undef pci_ss_info_144d_c000 +#define pci_ss_info_144d_c000 pci_ss_info_8086_1031_144d_c000 +static const pciSubsystemInfo pci_ss_info_8086_1031_144d_c001 = + {0x144d, 0xc001, pci_subsys_8086_1031_144d_c001, 0}; +#undef pci_ss_info_144d_c001 +#define pci_ss_info_144d_c001 pci_ss_info_8086_1031_144d_c001 +static const pciSubsystemInfo pci_ss_info_8086_1031_144d_c003 = + {0x144d, 0xc003, pci_subsys_8086_1031_144d_c003, 0}; +#undef pci_ss_info_144d_c003 +#define pci_ss_info_144d_c003 pci_ss_info_8086_1031_144d_c003 +static const pciSubsystemInfo pci_ss_info_8086_1031_144d_c006 = + {0x144d, 0xc006, pci_subsys_8086_1031_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_8086_1031_144d_c006 +static const pciSubsystemInfo pci_ss_info_8086_1040_16be_1040 = + {0x16be, 0x1040, pci_subsys_8086_1040_16be_1040, 0}; +#undef pci_ss_info_16be_1040 +#define pci_ss_info_16be_1040 pci_ss_info_8086_1040_16be_1040 +static const pciSubsystemInfo pci_ss_info_8086_1130_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_1130_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_1130_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_1130_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_1130_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_1130_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_1130_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_1130_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_1130_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_1132_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_1132_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_1132_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_1132_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_1132_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_1132_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_1161_8086_1161 = + {0x8086, 0x1161, pci_subsys_8086_1161_8086_1161, 0}; +#undef pci_ss_info_8086_1161 +#define pci_ss_info_8086_1161 pci_ss_info_8086_1161_8086_1161 +static const pciSubsystemInfo pci_ss_info_8086_1200_172a_0000 = + {0x172a, 0x0000, pci_subsys_8086_1200_172a_0000, 0}; +#undef pci_ss_info_172a_0000 +#define pci_ss_info_172a_0000 pci_ss_info_8086_1200_172a_0000 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3001 = + {0x0e11, 0x3001, pci_subsys_8086_1229_0e11_3001, 0}; +#undef pci_ss_info_0e11_3001 +#define pci_ss_info_0e11_3001 pci_ss_info_8086_1229_0e11_3001 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3002 = + {0x0e11, 0x3002, pci_subsys_8086_1229_0e11_3002, 0}; +#undef pci_ss_info_0e11_3002 +#define pci_ss_info_0e11_3002 pci_ss_info_8086_1229_0e11_3002 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3003 = + {0x0e11, 0x3003, pci_subsys_8086_1229_0e11_3003, 0}; +#undef pci_ss_info_0e11_3003 +#define pci_ss_info_0e11_3003 pci_ss_info_8086_1229_0e11_3003 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3004 = + {0x0e11, 0x3004, pci_subsys_8086_1229_0e11_3004, 0}; +#undef pci_ss_info_0e11_3004 +#define pci_ss_info_0e11_3004 pci_ss_info_8086_1229_0e11_3004 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3005 = + {0x0e11, 0x3005, pci_subsys_8086_1229_0e11_3005, 0}; +#undef pci_ss_info_0e11_3005 +#define pci_ss_info_0e11_3005 pci_ss_info_8086_1229_0e11_3005 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3006 = + {0x0e11, 0x3006, pci_subsys_8086_1229_0e11_3006, 0}; +#undef pci_ss_info_0e11_3006 +#define pci_ss_info_0e11_3006 pci_ss_info_8086_1229_0e11_3006 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3007 = + {0x0e11, 0x3007, pci_subsys_8086_1229_0e11_3007, 0}; +#undef pci_ss_info_0e11_3007 +#define pci_ss_info_0e11_3007 pci_ss_info_8086_1229_0e11_3007 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b01e = + {0x0e11, 0xb01e, pci_subsys_8086_1229_0e11_b01e, 0}; +#undef pci_ss_info_0e11_b01e +#define pci_ss_info_0e11_b01e pci_ss_info_8086_1229_0e11_b01e +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b01f = + {0x0e11, 0xb01f, pci_subsys_8086_1229_0e11_b01f, 0}; +#undef pci_ss_info_0e11_b01f +#define pci_ss_info_0e11_b01f pci_ss_info_8086_1229_0e11_b01f +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b02f = + {0x0e11, 0xb02f, pci_subsys_8086_1229_0e11_b02f, 0}; +#undef pci_ss_info_0e11_b02f +#define pci_ss_info_0e11_b02f pci_ss_info_8086_1229_0e11_b02f +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b04a = + {0x0e11, 0xb04a, pci_subsys_8086_1229_0e11_b04a, 0}; +#undef pci_ss_info_0e11_b04a +#define pci_ss_info_0e11_b04a pci_ss_info_8086_1229_0e11_b04a +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0c6 = + {0x0e11, 0xb0c6, pci_subsys_8086_1229_0e11_b0c6, 0}; +#undef pci_ss_info_0e11_b0c6 +#define pci_ss_info_0e11_b0c6 pci_ss_info_8086_1229_0e11_b0c6 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0c7 = + {0x0e11, 0xb0c7, pci_subsys_8086_1229_0e11_b0c7, 0}; +#undef pci_ss_info_0e11_b0c7 +#define pci_ss_info_0e11_b0c7 pci_ss_info_8086_1229_0e11_b0c7 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0d7 = + {0x0e11, 0xb0d7, pci_subsys_8086_1229_0e11_b0d7, 0}; +#undef pci_ss_info_0e11_b0d7 +#define pci_ss_info_0e11_b0d7 pci_ss_info_8086_1229_0e11_b0d7 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0dd = + {0x0e11, 0xb0dd, pci_subsys_8086_1229_0e11_b0dd, 0}; +#undef pci_ss_info_0e11_b0dd +#define pci_ss_info_0e11_b0dd pci_ss_info_8086_1229_0e11_b0dd +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0de = + {0x0e11, 0xb0de, pci_subsys_8086_1229_0e11_b0de, 0}; +#undef pci_ss_info_0e11_b0de +#define pci_ss_info_0e11_b0de pci_ss_info_8086_1229_0e11_b0de +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0e1 = + {0x0e11, 0xb0e1, pci_subsys_8086_1229_0e11_b0e1, 0}; +#undef pci_ss_info_0e11_b0e1 +#define pci_ss_info_0e11_b0e1 pci_ss_info_8086_1229_0e11_b0e1 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b134 = + {0x0e11, 0xb134, pci_subsys_8086_1229_0e11_b134, 0}; +#undef pci_ss_info_0e11_b134 +#define pci_ss_info_0e11_b134 pci_ss_info_8086_1229_0e11_b134 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b13c = + {0x0e11, 0xb13c, pci_subsys_8086_1229_0e11_b13c, 0}; +#undef pci_ss_info_0e11_b13c +#define pci_ss_info_0e11_b13c pci_ss_info_8086_1229_0e11_b13c +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b144 = + {0x0e11, 0xb144, pci_subsys_8086_1229_0e11_b144, 0}; +#undef pci_ss_info_0e11_b144 +#define pci_ss_info_0e11_b144 pci_ss_info_8086_1229_0e11_b144 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b163 = + {0x0e11, 0xb163, pci_subsys_8086_1229_0e11_b163, 0}; +#undef pci_ss_info_0e11_b163 +#define pci_ss_info_0e11_b163 pci_ss_info_8086_1229_0e11_b163 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b164 = + {0x0e11, 0xb164, pci_subsys_8086_1229_0e11_b164, 0}; +#undef pci_ss_info_0e11_b164 +#define pci_ss_info_0e11_b164 pci_ss_info_8086_1229_0e11_b164 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b1a4 = + {0x0e11, 0xb1a4, pci_subsys_8086_1229_0e11_b1a4, 0}; +#undef pci_ss_info_0e11_b1a4 +#define pci_ss_info_0e11_b1a4 pci_ss_info_8086_1229_0e11_b1a4 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_005c = + {0x1014, 0x005c, pci_subsys_8086_1229_1014_005c, 0}; +#undef pci_ss_info_1014_005c +#define pci_ss_info_1014_005c pci_ss_info_8086_1229_1014_005c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_01bc = + {0x1014, 0x01bc, pci_subsys_8086_1229_1014_01bc, 0}; +#undef pci_ss_info_1014_01bc +#define pci_ss_info_1014_01bc pci_ss_info_8086_1229_1014_01bc +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_01f1 = + {0x1014, 0x01f1, pci_subsys_8086_1229_1014_01f1, 0}; +#undef pci_ss_info_1014_01f1 +#define pci_ss_info_1014_01f1 pci_ss_info_8086_1229_1014_01f1 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_01f2 = + {0x1014, 0x01f2, pci_subsys_8086_1229_1014_01f2, 0}; +#undef pci_ss_info_1014_01f2 +#define pci_ss_info_1014_01f2 pci_ss_info_8086_1229_1014_01f2 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_0207 = + {0x1014, 0x0207, pci_subsys_8086_1229_1014_0207, 0}; +#undef pci_ss_info_1014_0207 +#define pci_ss_info_1014_0207 pci_ss_info_8086_1229_1014_0207 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_0232 = + {0x1014, 0x0232, pci_subsys_8086_1229_1014_0232, 0}; +#undef pci_ss_info_1014_0232 +#define pci_ss_info_1014_0232 pci_ss_info_8086_1229_1014_0232 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_023a = + {0x1014, 0x023a, pci_subsys_8086_1229_1014_023a, 0}; +#undef pci_ss_info_1014_023a +#define pci_ss_info_1014_023a pci_ss_info_8086_1229_1014_023a +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_105c = + {0x1014, 0x105c, pci_subsys_8086_1229_1014_105c, 0}; +#undef pci_ss_info_1014_105c +#define pci_ss_info_1014_105c pci_ss_info_8086_1229_1014_105c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_2205 = + {0x1014, 0x2205, pci_subsys_8086_1229_1014_2205, 0}; +#undef pci_ss_info_1014_2205 +#define pci_ss_info_1014_2205 pci_ss_info_8086_1229_1014_2205 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_305c = + {0x1014, 0x305c, pci_subsys_8086_1229_1014_305c, 0}; +#undef pci_ss_info_1014_305c +#define pci_ss_info_1014_305c pci_ss_info_8086_1229_1014_305c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_405c = + {0x1014, 0x405c, pci_subsys_8086_1229_1014_405c, 0}; +#undef pci_ss_info_1014_405c +#define pci_ss_info_1014_405c pci_ss_info_8086_1229_1014_405c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_505c = + {0x1014, 0x505c, pci_subsys_8086_1229_1014_505c, 0}; +#undef pci_ss_info_1014_505c +#define pci_ss_info_1014_505c pci_ss_info_8086_1229_1014_505c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_605c = + {0x1014, 0x605c, pci_subsys_8086_1229_1014_605c, 0}; +#undef pci_ss_info_1014_605c +#define pci_ss_info_1014_605c pci_ss_info_8086_1229_1014_605c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_705c = + {0x1014, 0x705c, pci_subsys_8086_1229_1014_705c, 0}; +#undef pci_ss_info_1014_705c +#define pci_ss_info_1014_705c pci_ss_info_8086_1229_1014_705c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_805c = + {0x1014, 0x805c, pci_subsys_8086_1229_1014_805c, 0}; +#undef pci_ss_info_1014_805c +#define pci_ss_info_1014_805c pci_ss_info_8086_1229_1014_805c +static const pciSubsystemInfo pci_ss_info_8086_1229_1028_009b = + {0x1028, 0x009b, pci_subsys_8086_1229_1028_009b, 0}; +#undef pci_ss_info_1028_009b +#define pci_ss_info_1028_009b pci_ss_info_8086_1229_1028_009b +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8000 = + {0x1033, 0x8000, pci_subsys_8086_1229_1033_8000, 0}; +#undef pci_ss_info_1033_8000 +#define pci_ss_info_1033_8000 pci_ss_info_8086_1229_1033_8000 +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8016 = + {0x1033, 0x8016, pci_subsys_8086_1229_1033_8016, 0}; +#undef pci_ss_info_1033_8016 +#define pci_ss_info_1033_8016 pci_ss_info_8086_1229_1033_8016 +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_801f = + {0x1033, 0x801f, pci_subsys_8086_1229_1033_801f, 0}; +#undef pci_ss_info_1033_801f +#define pci_ss_info_1033_801f pci_ss_info_8086_1229_1033_801f +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8026 = + {0x1033, 0x8026, pci_subsys_8086_1229_1033_8026, 0}; +#undef pci_ss_info_1033_8026 +#define pci_ss_info_1033_8026 pci_ss_info_8086_1229_1033_8026 +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8063 = + {0x1033, 0x8063, pci_subsys_8086_1229_1033_8063, 0}; +#undef pci_ss_info_1033_8063 +#define pci_ss_info_1033_8063 pci_ss_info_8086_1229_1033_8063 +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8064 = + {0x1033, 0x8064, pci_subsys_8086_1229_1033_8064, 0}; +#undef pci_ss_info_1033_8064 +#define pci_ss_info_1033_8064 pci_ss_info_8086_1229_1033_8064 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10c0 = + {0x103c, 0x10c0, pci_subsys_8086_1229_103c_10c0, 0}; +#undef pci_ss_info_103c_10c0 +#define pci_ss_info_103c_10c0 pci_ss_info_8086_1229_103c_10c0 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10c3 = + {0x103c, 0x10c3, pci_subsys_8086_1229_103c_10c3, 0}; +#undef pci_ss_info_103c_10c3 +#define pci_ss_info_103c_10c3 pci_ss_info_8086_1229_103c_10c3 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10ca = + {0x103c, 0x10ca, pci_subsys_8086_1229_103c_10ca, 0}; +#undef pci_ss_info_103c_10ca +#define pci_ss_info_103c_10ca pci_ss_info_8086_1229_103c_10ca +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10cb = + {0x103c, 0x10cb, pci_subsys_8086_1229_103c_10cb, 0}; +#undef pci_ss_info_103c_10cb +#define pci_ss_info_103c_10cb pci_ss_info_8086_1229_103c_10cb +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10e3 = + {0x103c, 0x10e3, pci_subsys_8086_1229_103c_10e3, 0}; +#undef pci_ss_info_103c_10e3 +#define pci_ss_info_103c_10e3 pci_ss_info_8086_1229_103c_10e3 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10e4 = + {0x103c, 0x10e4, pci_subsys_8086_1229_103c_10e4, 0}; +#undef pci_ss_info_103c_10e4 +#define pci_ss_info_103c_10e4 pci_ss_info_8086_1229_103c_10e4 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_1200 = + {0x103c, 0x1200, pci_subsys_8086_1229_103c_1200, 0}; +#undef pci_ss_info_103c_1200 +#define pci_ss_info_103c_1200 pci_ss_info_8086_1229_103c_1200 +static const pciSubsystemInfo pci_ss_info_8086_1229_10c3_1100 = + {0x10c3, 0x1100, pci_subsys_8086_1229_10c3_1100, 0}; +#undef pci_ss_info_10c3_1100 +#define pci_ss_info_10c3_1100 pci_ss_info_8086_1229_10c3_1100 +static const pciSubsystemInfo pci_ss_info_8086_1229_10cf_1115 = + {0x10cf, 0x1115, pci_subsys_8086_1229_10cf_1115, 0}; +#undef pci_ss_info_10cf_1115 +#define pci_ss_info_10cf_1115 pci_ss_info_8086_1229_10cf_1115 +static const pciSubsystemInfo pci_ss_info_8086_1229_10cf_1143 = + {0x10cf, 0x1143, pci_subsys_8086_1229_10cf_1143, 0}; +#undef pci_ss_info_10cf_1143 +#define pci_ss_info_10cf_1143 pci_ss_info_8086_1229_10cf_1143 +static const pciSubsystemInfo pci_ss_info_8086_1229_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_1229_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_1229_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_1229_1179_0002 = + {0x1179, 0x0002, pci_subsys_8086_1229_1179_0002, 0}; +#undef pci_ss_info_1179_0002 +#define pci_ss_info_1179_0002 pci_ss_info_8086_1229_1179_0002 +static const pciSubsystemInfo pci_ss_info_8086_1229_1179_0003 = + {0x1179, 0x0003, pci_subsys_8086_1229_1179_0003, 0}; +#undef pci_ss_info_1179_0003 +#define pci_ss_info_1179_0003 pci_ss_info_8086_1229_1179_0003 +static const pciSubsystemInfo pci_ss_info_8086_1229_1259_2560 = + {0x1259, 0x2560, pci_subsys_8086_1229_1259_2560, 0}; +#undef pci_ss_info_1259_2560 +#define pci_ss_info_1259_2560 pci_ss_info_8086_1229_1259_2560 +static const pciSubsystemInfo pci_ss_info_8086_1229_1259_2561 = + {0x1259, 0x2561, pci_subsys_8086_1229_1259_2561, 0}; +#undef pci_ss_info_1259_2561 +#define pci_ss_info_1259_2561 pci_ss_info_8086_1229_1259_2561 +static const pciSubsystemInfo pci_ss_info_8086_1229_1266_0001 = + {0x1266, 0x0001, pci_subsys_8086_1229_1266_0001, 0}; +#undef pci_ss_info_1266_0001 +#define pci_ss_info_1266_0001 pci_ss_info_8086_1229_1266_0001 +static const pciSubsystemInfo pci_ss_info_8086_1229_144d_2501 = + {0x144d, 0x2501, pci_subsys_8086_1229_144d_2501, 0}; +#undef pci_ss_info_144d_2501 +#define pci_ss_info_144d_2501 pci_ss_info_8086_1229_144d_2501 +static const pciSubsystemInfo pci_ss_info_8086_1229_144d_2502 = + {0x144d, 0x2502, pci_subsys_8086_1229_144d_2502, 0}; +#undef pci_ss_info_144d_2502 +#define pci_ss_info_144d_2502 pci_ss_info_8086_1229_144d_2502 +static const pciSubsystemInfo pci_ss_info_8086_1229_1668_1100 = + {0x1668, 0x1100, pci_subsys_8086_1229_1668_1100, 0}; +#undef pci_ss_info_1668_1100 +#define pci_ss_info_1668_1100 pci_ss_info_8086_1229_1668_1100 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0001 = + {0x8086, 0x0001, pci_subsys_8086_1229_8086_0001, 0}; +#undef pci_ss_info_8086_0001 +#define pci_ss_info_8086_0001 pci_ss_info_8086_1229_8086_0001 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0002 = + {0x8086, 0x0002, pci_subsys_8086_1229_8086_0002, 0}; +#undef pci_ss_info_8086_0002 +#define pci_ss_info_8086_0002 pci_ss_info_8086_1229_8086_0002 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0003 = + {0x8086, 0x0003, pci_subsys_8086_1229_8086_0003, 0}; +#undef pci_ss_info_8086_0003 +#define pci_ss_info_8086_0003 pci_ss_info_8086_1229_8086_0003 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0004 = + {0x8086, 0x0004, pci_subsys_8086_1229_8086_0004, 0}; +#undef pci_ss_info_8086_0004 +#define pci_ss_info_8086_0004 pci_ss_info_8086_1229_8086_0004 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0005 = + {0x8086, 0x0005, pci_subsys_8086_1229_8086_0005, 0}; +#undef pci_ss_info_8086_0005 +#define pci_ss_info_8086_0005 pci_ss_info_8086_1229_8086_0005 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0006 = + {0x8086, 0x0006, pci_subsys_8086_1229_8086_0006, 0}; +#undef pci_ss_info_8086_0006 +#define pci_ss_info_8086_0006 pci_ss_info_8086_1229_8086_0006 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0007 = + {0x8086, 0x0007, pci_subsys_8086_1229_8086_0007, 0}; +#undef pci_ss_info_8086_0007 +#define pci_ss_info_8086_0007 pci_ss_info_8086_1229_8086_0007 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0008 = + {0x8086, 0x0008, pci_subsys_8086_1229_8086_0008, 0}; +#undef pci_ss_info_8086_0008 +#define pci_ss_info_8086_0008 pci_ss_info_8086_1229_8086_0008 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0009 = + {0x8086, 0x0009, pci_subsys_8086_1229_8086_0009, 0}; +#undef pci_ss_info_8086_0009 +#define pci_ss_info_8086_0009 pci_ss_info_8086_1229_8086_0009 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000a = + {0x8086, 0x000a, pci_subsys_8086_1229_8086_000a, 0}; +#undef pci_ss_info_8086_000a +#define pci_ss_info_8086_000a pci_ss_info_8086_1229_8086_000a +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000b = + {0x8086, 0x000b, pci_subsys_8086_1229_8086_000b, 0}; +#undef pci_ss_info_8086_000b +#define pci_ss_info_8086_000b pci_ss_info_8086_1229_8086_000b +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000c = + {0x8086, 0x000c, pci_subsys_8086_1229_8086_000c, 0}; +#undef pci_ss_info_8086_000c +#define pci_ss_info_8086_000c pci_ss_info_8086_1229_8086_000c +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000d = + {0x8086, 0x000d, pci_subsys_8086_1229_8086_000d, 0}; +#undef pci_ss_info_8086_000d +#define pci_ss_info_8086_000d pci_ss_info_8086_1229_8086_000d +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000e = + {0x8086, 0x000e, pci_subsys_8086_1229_8086_000e, 0}; +#undef pci_ss_info_8086_000e +#define pci_ss_info_8086_000e pci_ss_info_8086_1229_8086_000e +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000f = + {0x8086, 0x000f, pci_subsys_8086_1229_8086_000f, 0}; +#undef pci_ss_info_8086_000f +#define pci_ss_info_8086_000f pci_ss_info_8086_1229_8086_000f +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0010 = + {0x8086, 0x0010, pci_subsys_8086_1229_8086_0010, 0}; +#undef pci_ss_info_8086_0010 +#define pci_ss_info_8086_0010 pci_ss_info_8086_1229_8086_0010 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0011 = + {0x8086, 0x0011, pci_subsys_8086_1229_8086_0011, 0}; +#undef pci_ss_info_8086_0011 +#define pci_ss_info_8086_0011 pci_ss_info_8086_1229_8086_0011 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0012 = + {0x8086, 0x0012, pci_subsys_8086_1229_8086_0012, 0}; +#undef pci_ss_info_8086_0012 +#define pci_ss_info_8086_0012 pci_ss_info_8086_1229_8086_0012 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0013 = + {0x8086, 0x0013, pci_subsys_8086_1229_8086_0013, 0}; +#undef pci_ss_info_8086_0013 +#define pci_ss_info_8086_0013 pci_ss_info_8086_1229_8086_0013 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0030 = + {0x8086, 0x0030, pci_subsys_8086_1229_8086_0030, 0}; +#undef pci_ss_info_8086_0030 +#define pci_ss_info_8086_0030 pci_ss_info_8086_1229_8086_0030 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0031 = + {0x8086, 0x0031, pci_subsys_8086_1229_8086_0031, 0}; +#undef pci_ss_info_8086_0031 +#define pci_ss_info_8086_0031 pci_ss_info_8086_1229_8086_0031 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0040 = + {0x8086, 0x0040, pci_subsys_8086_1229_8086_0040, 0}; +#undef pci_ss_info_8086_0040 +#define pci_ss_info_8086_0040 pci_ss_info_8086_1229_8086_0040 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0041 = + {0x8086, 0x0041, pci_subsys_8086_1229_8086_0041, 0}; +#undef pci_ss_info_8086_0041 +#define pci_ss_info_8086_0041 pci_ss_info_8086_1229_8086_0041 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0042 = + {0x8086, 0x0042, pci_subsys_8086_1229_8086_0042, 0}; +#undef pci_ss_info_8086_0042 +#define pci_ss_info_8086_0042 pci_ss_info_8086_1229_8086_0042 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0050 = + {0x8086, 0x0050, pci_subsys_8086_1229_8086_0050, 0}; +#undef pci_ss_info_8086_0050 +#define pci_ss_info_8086_0050 pci_ss_info_8086_1229_8086_0050 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1009 = + {0x8086, 0x1009, pci_subsys_8086_1229_8086_1009, 0}; +#undef pci_ss_info_8086_1009 +#define pci_ss_info_8086_1009 pci_ss_info_8086_1229_8086_1009 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_100c = + {0x8086, 0x100c, pci_subsys_8086_1229_8086_100c, 0}; +#undef pci_ss_info_8086_100c +#define pci_ss_info_8086_100c pci_ss_info_8086_1229_8086_100c +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1012 = + {0x8086, 0x1012, pci_subsys_8086_1229_8086_1012, 0}; +#undef pci_ss_info_8086_1012 +#define pci_ss_info_8086_1012 pci_ss_info_8086_1229_8086_1012 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1013 = + {0x8086, 0x1013, pci_subsys_8086_1229_8086_1013, 0}; +#undef pci_ss_info_8086_1013 +#define pci_ss_info_8086_1013 pci_ss_info_8086_1229_8086_1013 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1015 = + {0x8086, 0x1015, pci_subsys_8086_1229_8086_1015, 0}; +#undef pci_ss_info_8086_1015 +#define pci_ss_info_8086_1015 pci_ss_info_8086_1229_8086_1015 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1017 = + {0x8086, 0x1017, pci_subsys_8086_1229_8086_1017, 0}; +#undef pci_ss_info_8086_1017 +#define pci_ss_info_8086_1017 pci_ss_info_8086_1229_8086_1017 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1030 = + {0x8086, 0x1030, pci_subsys_8086_1229_8086_1030, 0}; +#undef pci_ss_info_8086_1030 +#define pci_ss_info_8086_1030 pci_ss_info_8086_1229_8086_1030 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1040 = + {0x8086, 0x1040, pci_subsys_8086_1229_8086_1040, 0}; +#undef pci_ss_info_8086_1040 +#define pci_ss_info_8086_1040 pci_ss_info_8086_1229_8086_1040 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1041 = + {0x8086, 0x1041, pci_subsys_8086_1229_8086_1041, 0}; +#undef pci_ss_info_8086_1041 +#define pci_ss_info_8086_1041 pci_ss_info_8086_1229_8086_1041 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1042 = + {0x8086, 0x1042, pci_subsys_8086_1229_8086_1042, 0}; +#undef pci_ss_info_8086_1042 +#define pci_ss_info_8086_1042 pci_ss_info_8086_1229_8086_1042 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1050 = + {0x8086, 0x1050, pci_subsys_8086_1229_8086_1050, 0}; +#undef pci_ss_info_8086_1050 +#define pci_ss_info_8086_1050 pci_ss_info_8086_1229_8086_1050 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1051 = + {0x8086, 0x1051, pci_subsys_8086_1229_8086_1051, 0}; +#undef pci_ss_info_8086_1051 +#define pci_ss_info_8086_1051 pci_ss_info_8086_1229_8086_1051 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1052 = + {0x8086, 0x1052, pci_subsys_8086_1229_8086_1052, 0}; +#undef pci_ss_info_8086_1052 +#define pci_ss_info_8086_1052 pci_ss_info_8086_1229_8086_1052 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_10f0 = + {0x8086, 0x10f0, pci_subsys_8086_1229_8086_10f0, 0}; +#undef pci_ss_info_8086_10f0 +#define pci_ss_info_8086_10f0 pci_ss_info_8086_1229_8086_10f0 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2009 = + {0x8086, 0x2009, pci_subsys_8086_1229_8086_2009, 0}; +#undef pci_ss_info_8086_2009 +#define pci_ss_info_8086_2009 pci_ss_info_8086_1229_8086_2009 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_200d = + {0x8086, 0x200d, pci_subsys_8086_1229_8086_200d, 0}; +#undef pci_ss_info_8086_200d +#define pci_ss_info_8086_200d pci_ss_info_8086_1229_8086_200d +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_200e = + {0x8086, 0x200e, pci_subsys_8086_1229_8086_200e, 0}; +#undef pci_ss_info_8086_200e +#define pci_ss_info_8086_200e pci_ss_info_8086_1229_8086_200e +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_200f = + {0x8086, 0x200f, pci_subsys_8086_1229_8086_200f, 0}; +#undef pci_ss_info_8086_200f +#define pci_ss_info_8086_200f pci_ss_info_8086_1229_8086_200f +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2010 = + {0x8086, 0x2010, pci_subsys_8086_1229_8086_2010, 0}; +#undef pci_ss_info_8086_2010 +#define pci_ss_info_8086_2010 pci_ss_info_8086_1229_8086_2010 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2013 = + {0x8086, 0x2013, pci_subsys_8086_1229_8086_2013, 0}; +#undef pci_ss_info_8086_2013 +#define pci_ss_info_8086_2013 pci_ss_info_8086_1229_8086_2013 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2016 = + {0x8086, 0x2016, pci_subsys_8086_1229_8086_2016, 0}; +#undef pci_ss_info_8086_2016 +#define pci_ss_info_8086_2016 pci_ss_info_8086_1229_8086_2016 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2017 = + {0x8086, 0x2017, pci_subsys_8086_1229_8086_2017, 0}; +#undef pci_ss_info_8086_2017 +#define pci_ss_info_8086_2017 pci_ss_info_8086_1229_8086_2017 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2018 = + {0x8086, 0x2018, pci_subsys_8086_1229_8086_2018, 0}; +#undef pci_ss_info_8086_2018 +#define pci_ss_info_8086_2018 pci_ss_info_8086_1229_8086_2018 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2019 = + {0x8086, 0x2019, pci_subsys_8086_1229_8086_2019, 0}; +#undef pci_ss_info_8086_2019 +#define pci_ss_info_8086_2019 pci_ss_info_8086_1229_8086_2019 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2101 = + {0x8086, 0x2101, pci_subsys_8086_1229_8086_2101, 0}; +#undef pci_ss_info_8086_2101 +#define pci_ss_info_8086_2101 pci_ss_info_8086_1229_8086_2101 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2102 = + {0x8086, 0x2102, pci_subsys_8086_1229_8086_2102, 0}; +#undef pci_ss_info_8086_2102 +#define pci_ss_info_8086_2102 pci_ss_info_8086_1229_8086_2102 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2103 = + {0x8086, 0x2103, pci_subsys_8086_1229_8086_2103, 0}; +#undef pci_ss_info_8086_2103 +#define pci_ss_info_8086_2103 pci_ss_info_8086_1229_8086_2103 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2104 = + {0x8086, 0x2104, pci_subsys_8086_1229_8086_2104, 0}; +#undef pci_ss_info_8086_2104 +#define pci_ss_info_8086_2104 pci_ss_info_8086_1229_8086_2104 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2105 = + {0x8086, 0x2105, pci_subsys_8086_1229_8086_2105, 0}; +#undef pci_ss_info_8086_2105 +#define pci_ss_info_8086_2105 pci_ss_info_8086_1229_8086_2105 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2106 = + {0x8086, 0x2106, pci_subsys_8086_1229_8086_2106, 0}; +#undef pci_ss_info_8086_2106 +#define pci_ss_info_8086_2106 pci_ss_info_8086_1229_8086_2106 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2107 = + {0x8086, 0x2107, pci_subsys_8086_1229_8086_2107, 0}; +#undef pci_ss_info_8086_2107 +#define pci_ss_info_8086_2107 pci_ss_info_8086_1229_8086_2107 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2108 = + {0x8086, 0x2108, pci_subsys_8086_1229_8086_2108, 0}; +#undef pci_ss_info_8086_2108 +#define pci_ss_info_8086_2108 pci_ss_info_8086_1229_8086_2108 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2200 = + {0x8086, 0x2200, pci_subsys_8086_1229_8086_2200, 0}; +#undef pci_ss_info_8086_2200 +#define pci_ss_info_8086_2200 pci_ss_info_8086_1229_8086_2200 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2201 = + {0x8086, 0x2201, pci_subsys_8086_1229_8086_2201, 0}; +#undef pci_ss_info_8086_2201 +#define pci_ss_info_8086_2201 pci_ss_info_8086_1229_8086_2201 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2202 = + {0x8086, 0x2202, pci_subsys_8086_1229_8086_2202, 0}; +#undef pci_ss_info_8086_2202 +#define pci_ss_info_8086_2202 pci_ss_info_8086_1229_8086_2202 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2203 = + {0x8086, 0x2203, pci_subsys_8086_1229_8086_2203, 0}; +#undef pci_ss_info_8086_2203 +#define pci_ss_info_8086_2203 pci_ss_info_8086_1229_8086_2203 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2204 = + {0x8086, 0x2204, pci_subsys_8086_1229_8086_2204, 0}; +#undef pci_ss_info_8086_2204 +#define pci_ss_info_8086_2204 pci_ss_info_8086_1229_8086_2204 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2205 = + {0x8086, 0x2205, pci_subsys_8086_1229_8086_2205, 0}; +#undef pci_ss_info_8086_2205 +#define pci_ss_info_8086_2205 pci_ss_info_8086_1229_8086_2205 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2206 = + {0x8086, 0x2206, pci_subsys_8086_1229_8086_2206, 0}; +#undef pci_ss_info_8086_2206 +#define pci_ss_info_8086_2206 pci_ss_info_8086_1229_8086_2206 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2207 = + {0x8086, 0x2207, pci_subsys_8086_1229_8086_2207, 0}; +#undef pci_ss_info_8086_2207 +#define pci_ss_info_8086_2207 pci_ss_info_8086_1229_8086_2207 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2208 = + {0x8086, 0x2208, pci_subsys_8086_1229_8086_2208, 0}; +#undef pci_ss_info_8086_2208 +#define pci_ss_info_8086_2208 pci_ss_info_8086_1229_8086_2208 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2402 = + {0x8086, 0x2402, pci_subsys_8086_1229_8086_2402, 0}; +#undef pci_ss_info_8086_2402 +#define pci_ss_info_8086_2402 pci_ss_info_8086_1229_8086_2402 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2407 = + {0x8086, 0x2407, pci_subsys_8086_1229_8086_2407, 0}; +#undef pci_ss_info_8086_2407 +#define pci_ss_info_8086_2407 pci_ss_info_8086_1229_8086_2407 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2408 = + {0x8086, 0x2408, pci_subsys_8086_1229_8086_2408, 0}; +#undef pci_ss_info_8086_2408 +#define pci_ss_info_8086_2408 pci_ss_info_8086_1229_8086_2408 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2409 = + {0x8086, 0x2409, pci_subsys_8086_1229_8086_2409, 0}; +#undef pci_ss_info_8086_2409 +#define pci_ss_info_8086_2409 pci_ss_info_8086_1229_8086_2409 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_240f = + {0x8086, 0x240f, pci_subsys_8086_1229_8086_240f, 0}; +#undef pci_ss_info_8086_240f +#define pci_ss_info_8086_240f pci_ss_info_8086_1229_8086_240f +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2410 = + {0x8086, 0x2410, pci_subsys_8086_1229_8086_2410, 0}; +#undef pci_ss_info_8086_2410 +#define pci_ss_info_8086_2410 pci_ss_info_8086_1229_8086_2410 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2411 = + {0x8086, 0x2411, pci_subsys_8086_1229_8086_2411, 0}; +#undef pci_ss_info_8086_2411 +#define pci_ss_info_8086_2411 pci_ss_info_8086_1229_8086_2411 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2412 = + {0x8086, 0x2412, pci_subsys_8086_1229_8086_2412, 0}; +#undef pci_ss_info_8086_2412 +#define pci_ss_info_8086_2412 pci_ss_info_8086_1229_8086_2412 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2413 = + {0x8086, 0x2413, pci_subsys_8086_1229_8086_2413, 0}; +#undef pci_ss_info_8086_2413 +#define pci_ss_info_8086_2413 pci_ss_info_8086_1229_8086_2413 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3000 = + {0x8086, 0x3000, pci_subsys_8086_1229_8086_3000, 0}; +#undef pci_ss_info_8086_3000 +#define pci_ss_info_8086_3000 pci_ss_info_8086_1229_8086_3000 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3001 = + {0x8086, 0x3001, pci_subsys_8086_1229_8086_3001, 0}; +#undef pci_ss_info_8086_3001 +#define pci_ss_info_8086_3001 pci_ss_info_8086_1229_8086_3001 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3002 = + {0x8086, 0x3002, pci_subsys_8086_1229_8086_3002, 0}; +#undef pci_ss_info_8086_3002 +#define pci_ss_info_8086_3002 pci_ss_info_8086_1229_8086_3002 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3006 = + {0x8086, 0x3006, pci_subsys_8086_1229_8086_3006, 0}; +#undef pci_ss_info_8086_3006 +#define pci_ss_info_8086_3006 pci_ss_info_8086_1229_8086_3006 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3007 = + {0x8086, 0x3007, pci_subsys_8086_1229_8086_3007, 0}; +#undef pci_ss_info_8086_3007 +#define pci_ss_info_8086_3007 pci_ss_info_8086_1229_8086_3007 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3008 = + {0x8086, 0x3008, pci_subsys_8086_1229_8086_3008, 0}; +#undef pci_ss_info_8086_3008 +#define pci_ss_info_8086_3008 pci_ss_info_8086_1229_8086_3008 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3010 = + {0x8086, 0x3010, pci_subsys_8086_1229_8086_3010, 0}; +#undef pci_ss_info_8086_3010 +#define pci_ss_info_8086_3010 pci_ss_info_8086_1229_8086_3010 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3011 = + {0x8086, 0x3011, pci_subsys_8086_1229_8086_3011, 0}; +#undef pci_ss_info_8086_3011 +#define pci_ss_info_8086_3011 pci_ss_info_8086_1229_8086_3011 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3012 = + {0x8086, 0x3012, pci_subsys_8086_1229_8086_3012, 0}; +#undef pci_ss_info_8086_3012 +#define pci_ss_info_8086_3012 pci_ss_info_8086_1229_8086_3012 +static const pciSubsystemInfo pci_ss_info_8086_1361_8086_1361 = + {0x8086, 0x1361, pci_subsys_8086_1361_8086_1361, 0}; +#undef pci_ss_info_8086_1361 +#define pci_ss_info_8086_1361 pci_ss_info_8086_1361_8086_1361 +static const pciSubsystemInfo pci_ss_info_8086_1361_8086_8000 = + {0x8086, 0x8000, pci_subsys_8086_1361_8086_8000, 0}; +#undef pci_ss_info_8086_8000 +#define pci_ss_info_8086_8000 pci_ss_info_8086_1361_8086_8000 +static const pciSubsystemInfo pci_ss_info_8086_1461_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_1461_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_1461_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0431 = + {0x101e, 0x0431, pci_subsys_8086_1960_101e_0431, 0}; +#undef pci_ss_info_101e_0431 +#define pci_ss_info_101e_0431 pci_ss_info_8086_1960_101e_0431 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0438 = + {0x101e, 0x0438, pci_subsys_8086_1960_101e_0438, 0}; +#undef pci_ss_info_101e_0438 +#define pci_ss_info_101e_0438 pci_ss_info_8086_1960_101e_0438 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0466 = + {0x101e, 0x0466, pci_subsys_8086_1960_101e_0466, 0}; +#undef pci_ss_info_101e_0466 +#define pci_ss_info_101e_0466 pci_ss_info_8086_1960_101e_0466 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0467 = + {0x101e, 0x0467, pci_subsys_8086_1960_101e_0467, 0}; +#undef pci_ss_info_101e_0467 +#define pci_ss_info_101e_0467 pci_ss_info_8086_1960_101e_0467 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0490 = + {0x101e, 0x0490, pci_subsys_8086_1960_101e_0490, 0}; +#undef pci_ss_info_101e_0490 +#define pci_ss_info_101e_0490 pci_ss_info_8086_1960_101e_0490 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0762 = + {0x101e, 0x0762, pci_subsys_8086_1960_101e_0762, 0}; +#undef pci_ss_info_101e_0762 +#define pci_ss_info_101e_0762 pci_ss_info_8086_1960_101e_0762 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_09a0 = + {0x101e, 0x09a0, pci_subsys_8086_1960_101e_09a0, 0}; +#undef pci_ss_info_101e_09a0 +#define pci_ss_info_101e_09a0 pci_ss_info_8086_1960_101e_09a0 +static const pciSubsystemInfo pci_ss_info_8086_1960_1028_0467 = + {0x1028, 0x0467, pci_subsys_8086_1960_1028_0467, 0}; +#undef pci_ss_info_1028_0467 +#define pci_ss_info_1028_0467 pci_ss_info_8086_1960_1028_0467 +static const pciSubsystemInfo pci_ss_info_8086_1960_1028_1111 = + {0x1028, 0x1111, pci_subsys_8086_1960_1028_1111, 0}; +#undef pci_ss_info_1028_1111 +#define pci_ss_info_1028_1111 pci_ss_info_8086_1960_1028_1111 +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_03a2 = + {0x103c, 0x03a2, pci_subsys_8086_1960_103c_03a2, 0}; +#undef pci_ss_info_103c_03a2 +#define pci_ss_info_103c_03a2 pci_ss_info_8086_1960_103c_03a2 +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_10c6 = + {0x103c, 0x10c6, pci_subsys_8086_1960_103c_10c6, 0}; +#undef pci_ss_info_103c_10c6 +#define pci_ss_info_103c_10c6 pci_ss_info_8086_1960_103c_10c6 +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_10c7 = + {0x103c, 0x10c7, pci_subsys_8086_1960_103c_10c7, 0}; +#undef pci_ss_info_103c_10c7 +#define pci_ss_info_103c_10c7 pci_ss_info_8086_1960_103c_10c7 +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_10cc = + {0x103c, 0x10cc, pci_subsys_8086_1960_103c_10cc, 0}; +#undef pci_ss_info_103c_10cc +#define pci_ss_info_103c_10cc pci_ss_info_8086_1960_103c_10cc +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_10cd = + {0x103c, 0x10cd, pci_subsys_8086_1960_103c_10cd, 0}; +#undef pci_ss_info_103c_10cd +#define pci_ss_info_103c_10cd pci_ss_info_8086_1960_103c_10cd +static const pciSubsystemInfo pci_ss_info_8086_1960_105a_0000 = + {0x105a, 0x0000, pci_subsys_8086_1960_105a_0000, 0}; +#undef pci_ss_info_105a_0000 +#define pci_ss_info_105a_0000 pci_ss_info_8086_1960_105a_0000 +static const pciSubsystemInfo pci_ss_info_8086_1960_105a_2168 = + {0x105a, 0x2168, pci_subsys_8086_1960_105a_2168, 0}; +#undef pci_ss_info_105a_2168 +#define pci_ss_info_105a_2168 pci_ss_info_8086_1960_105a_2168 +static const pciSubsystemInfo pci_ss_info_8086_1960_105a_5168 = + {0x105a, 0x5168, pci_subsys_8086_1960_105a_5168, 0}; +#undef pci_ss_info_105a_5168 +#define pci_ss_info_105a_5168 pci_ss_info_8086_1960_105a_5168 +static const pciSubsystemInfo pci_ss_info_8086_1960_1111_1111 = + {0x1111, 0x1111, pci_subsys_8086_1960_1111_1111, 0}; +#undef pci_ss_info_1111_1111 +#define pci_ss_info_1111_1111 pci_ss_info_8086_1960_1111_1111 +static const pciSubsystemInfo pci_ss_info_8086_1960_1111_1112 = + {0x1111, 0x1112, pci_subsys_8086_1960_1111_1112, 0}; +#undef pci_ss_info_1111_1112 +#define pci_ss_info_1111_1112 pci_ss_info_8086_1960_1111_1112 +static const pciSubsystemInfo pci_ss_info_8086_1960_113c_03a2 = + {0x113c, 0x03a2, pci_subsys_8086_1960_113c_03a2, 0}; +#undef pci_ss_info_113c_03a2 +#define pci_ss_info_113c_03a2 pci_ss_info_8086_1960_113c_03a2 +static const pciSubsystemInfo pci_ss_info_8086_1962_105a_0000 = + {0x105a, 0x0000, pci_subsys_8086_1962_105a_0000, 0}; +#undef pci_ss_info_105a_0000 +#define pci_ss_info_105a_0000 pci_ss_info_8086_1962_105a_0000 +static const pciSubsystemInfo pci_ss_info_8086_2415_1028_0095 = + {0x1028, 0x0095, pci_subsys_8086_2415_1028_0095, 0}; +#undef pci_ss_info_1028_0095 +#define pci_ss_info_1028_0095 pci_ss_info_8086_2415_1028_0095 +static const pciSubsystemInfo pci_ss_info_8086_2415_11d4_0040 = + {0x11d4, 0x0040, pci_subsys_8086_2415_11d4_0040, 0}; +#undef pci_ss_info_11d4_0040 +#define pci_ss_info_11d4_0040 pci_ss_info_8086_2415_11d4_0040 +static const pciSubsystemInfo pci_ss_info_8086_2415_11d4_0048 = + {0x11d4, 0x0048, pci_subsys_8086_2415_11d4_0048, 0}; +#undef pci_ss_info_11d4_0048 +#define pci_ss_info_11d4_0048 pci_ss_info_8086_2415_11d4_0048 +static const pciSubsystemInfo pci_ss_info_8086_2415_11d4_5340 = + {0x11d4, 0x5340, pci_subsys_8086_2415_11d4_5340, 0}; +#undef pci_ss_info_11d4_5340 +#define pci_ss_info_11d4_5340 pci_ss_info_8086_2415_11d4_5340 +static const pciSubsystemInfo pci_ss_info_8086_2425_11d4_0040 = + {0x11d4, 0x0040, pci_subsys_8086_2425_11d4_0040, 0}; +#undef pci_ss_info_11d4_0040 +#define pci_ss_info_11d4_0040 pci_ss_info_8086_2425_11d4_0040 +static const pciSubsystemInfo pci_ss_info_8086_2425_11d4_0048 = + {0x11d4, 0x0048, pci_subsys_8086_2425_11d4_0048, 0}; +#undef pci_ss_info_11d4_0048 +#define pci_ss_info_11d4_0048 pci_ss_info_8086_2425_11d4_0048 +static const pciSubsystemInfo pci_ss_info_8086_2442_1014_01c6 = + {0x1014, 0x01c6, pci_subsys_8086_2442_1014_01c6, 0}; +#undef pci_ss_info_1014_01c6 +#define pci_ss_info_1014_01c6 pci_ss_info_8086_2442_1014_01c6 +static const pciSubsystemInfo pci_ss_info_8086_2442_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2442_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2442_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2442_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2442_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2442_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2442_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2442_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2442_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2443_1014_01c6 = + {0x1014, 0x01c6, pci_subsys_8086_2443_1014_01c6, 0}; +#undef pci_ss_info_1014_01c6 +#define pci_ss_info_1014_01c6 pci_ss_info_8086_2443_1014_01c6 +static const pciSubsystemInfo pci_ss_info_8086_2443_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2443_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2443_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2443_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_2443_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_2443_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_2443_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2443_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2443_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2443_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2443_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2443_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2444_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2444_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2444_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2444_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2444_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2444_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2444_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2444_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2444_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2445_1014_01c6 = + {0x1014, 0x01c6, pci_subsys_8086_2445_1014_01c6, 0}; +#undef pci_ss_info_1014_01c6 +#define pci_ss_info_1014_01c6 pci_ss_info_8086_2445_1014_01c6 +static const pciSubsystemInfo pci_ss_info_8086_2445_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2445_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2445_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2445_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2445_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2445_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2445_1462_3370 = + {0x1462, 0x3370, pci_subsys_8086_2445_1462_3370, 0}; +#undef pci_ss_info_1462_3370 +#define pci_ss_info_1462_3370 pci_ss_info_8086_2445_1462_3370 +static const pciSubsystemInfo pci_ss_info_8086_2445_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2445_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2445_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2446_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2446_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2446_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2446_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2446_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2446_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2449_0e11_0012 = + {0x0e11, 0x0012, pci_subsys_8086_2449_0e11_0012, 0}; +#undef pci_ss_info_0e11_0012 +#define pci_ss_info_0e11_0012 pci_ss_info_8086_2449_0e11_0012 +static const pciSubsystemInfo pci_ss_info_8086_2449_0e11_0091 = + {0x0e11, 0x0091, pci_subsys_8086_2449_0e11_0091, 0}; +#undef pci_ss_info_0e11_0091 +#define pci_ss_info_0e11_0091 pci_ss_info_8086_2449_0e11_0091 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_01ce = + {0x1014, 0x01ce, pci_subsys_8086_2449_1014_01ce, 0}; +#undef pci_ss_info_1014_01ce +#define pci_ss_info_1014_01ce pci_ss_info_8086_2449_1014_01ce +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_01dc = + {0x1014, 0x01dc, pci_subsys_8086_2449_1014_01dc, 0}; +#undef pci_ss_info_1014_01dc +#define pci_ss_info_1014_01dc pci_ss_info_8086_2449_1014_01dc +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_01eb = + {0x1014, 0x01eb, pci_subsys_8086_2449_1014_01eb, 0}; +#undef pci_ss_info_1014_01eb +#define pci_ss_info_1014_01eb pci_ss_info_8086_2449_1014_01eb +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_01ec = + {0x1014, 0x01ec, pci_subsys_8086_2449_1014_01ec, 0}; +#undef pci_ss_info_1014_01ec +#define pci_ss_info_1014_01ec pci_ss_info_8086_2449_1014_01ec +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0202 = + {0x1014, 0x0202, pci_subsys_8086_2449_1014_0202, 0}; +#undef pci_ss_info_1014_0202 +#define pci_ss_info_1014_0202 pci_ss_info_8086_2449_1014_0202 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0205 = + {0x1014, 0x0205, pci_subsys_8086_2449_1014_0205, 0}; +#undef pci_ss_info_1014_0205 +#define pci_ss_info_1014_0205 pci_ss_info_8086_2449_1014_0205 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0217 = + {0x1014, 0x0217, pci_subsys_8086_2449_1014_0217, 0}; +#undef pci_ss_info_1014_0217 +#define pci_ss_info_1014_0217 pci_ss_info_8086_2449_1014_0217 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0234 = + {0x1014, 0x0234, pci_subsys_8086_2449_1014_0234, 0}; +#undef pci_ss_info_1014_0234 +#define pci_ss_info_1014_0234 pci_ss_info_8086_2449_1014_0234 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_023d = + {0x1014, 0x023d, pci_subsys_8086_2449_1014_023d, 0}; +#undef pci_ss_info_1014_023d +#define pci_ss_info_1014_023d pci_ss_info_8086_2449_1014_023d +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0244 = + {0x1014, 0x0244, pci_subsys_8086_2449_1014_0244, 0}; +#undef pci_ss_info_1014_0244 +#define pci_ss_info_1014_0244 pci_ss_info_8086_2449_1014_0244 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0245 = + {0x1014, 0x0245, pci_subsys_8086_2449_1014_0245, 0}; +#undef pci_ss_info_1014_0245 +#define pci_ss_info_1014_0245 pci_ss_info_8086_2449_1014_0245 +static const pciSubsystemInfo pci_ss_info_8086_2449_109f_315d = + {0x109f, 0x315d, pci_subsys_8086_2449_109f_315d, 0}; +#undef pci_ss_info_109f_315d +#define pci_ss_info_109f_315d pci_ss_info_8086_2449_109f_315d +static const pciSubsystemInfo pci_ss_info_8086_2449_109f_3181 = + {0x109f, 0x3181, pci_subsys_8086_2449_109f_3181, 0}; +#undef pci_ss_info_109f_3181 +#define pci_ss_info_109f_3181 pci_ss_info_8086_2449_109f_3181 +static const pciSubsystemInfo pci_ss_info_8086_2449_1186_7801 = + {0x1186, 0x7801, pci_subsys_8086_2449_1186_7801, 0}; +#undef pci_ss_info_1186_7801 +#define pci_ss_info_1186_7801 pci_ss_info_8086_2449_1186_7801 +static const pciSubsystemInfo pci_ss_info_8086_2449_144d_2602 = + {0x144d, 0x2602, pci_subsys_8086_2449_144d_2602, 0}; +#undef pci_ss_info_144d_2602 +#define pci_ss_info_144d_2602 pci_ss_info_8086_2449_144d_2602 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3010 = + {0x8086, 0x3010, pci_subsys_8086_2449_8086_3010, 0}; +#undef pci_ss_info_8086_3010 +#define pci_ss_info_8086_3010 pci_ss_info_8086_2449_8086_3010 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3011 = + {0x8086, 0x3011, pci_subsys_8086_2449_8086_3011, 0}; +#undef pci_ss_info_8086_3011 +#define pci_ss_info_8086_3011 pci_ss_info_8086_2449_8086_3011 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3012 = + {0x8086, 0x3012, pci_subsys_8086_2449_8086_3012, 0}; +#undef pci_ss_info_8086_3012 +#define pci_ss_info_8086_3012 pci_ss_info_8086_2449_8086_3012 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3013 = + {0x8086, 0x3013, pci_subsys_8086_2449_8086_3013, 0}; +#undef pci_ss_info_8086_3013 +#define pci_ss_info_8086_3013 pci_ss_info_8086_2449_8086_3013 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3014 = + {0x8086, 0x3014, pci_subsys_8086_2449_8086_3014, 0}; +#undef pci_ss_info_8086_3014 +#define pci_ss_info_8086_3014 pci_ss_info_8086_2449_8086_3014 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3015 = + {0x8086, 0x3015, pci_subsys_8086_2449_8086_3015, 0}; +#undef pci_ss_info_8086_3015 +#define pci_ss_info_8086_3015 pci_ss_info_8086_2449_8086_3015 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3016 = + {0x8086, 0x3016, pci_subsys_8086_2449_8086_3016, 0}; +#undef pci_ss_info_8086_3016 +#define pci_ss_info_8086_3016 pci_ss_info_8086_2449_8086_3016 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3017 = + {0x8086, 0x3017, pci_subsys_8086_2449_8086_3017, 0}; +#undef pci_ss_info_8086_3017 +#define pci_ss_info_8086_3017 pci_ss_info_8086_2449_8086_3017 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3018 = + {0x8086, 0x3018, pci_subsys_8086_2449_8086_3018, 0}; +#undef pci_ss_info_8086_3018 +#define pci_ss_info_8086_3018 pci_ss_info_8086_2449_8086_3018 +static const pciSubsystemInfo pci_ss_info_8086_244a_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_244a_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_244a_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_244a_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_244a_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_244a_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_244b_1014_01c6 = + {0x1014, 0x01c6, pci_subsys_8086_244b_1014_01c6, 0}; +#undef pci_ss_info_1014_01c6 +#define pci_ss_info_1014_01c6 pci_ss_info_8086_244b_1014_01c6 +static const pciSubsystemInfo pci_ss_info_8086_244b_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_244b_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_244b_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_244b_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_244b_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_244b_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2482_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_2482_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_2482_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_2482_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2482_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2482_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2482_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2482_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2482_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2482_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_2482_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_2482_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_2483_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_2483_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_2483_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_2483_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2483_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2483_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2483_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2483_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2483_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2483_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_2483_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_2483_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_2484_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_2484_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_2484_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_2484_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2484_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2484_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2484_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2484_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2484_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2484_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_2484_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_2484_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_2485_1014_0222 = + {0x1014, 0x0222, pci_subsys_8086_2485_1014_0222, 0}; +#undef pci_ss_info_1014_0222 +#define pci_ss_info_1014_0222 pci_ss_info_8086_2485_1014_0222 +static const pciSubsystemInfo pci_ss_info_8086_2485_1014_0508 = + {0x1014, 0x0508, pci_subsys_8086_2485_1014_0508, 0}; +#undef pci_ss_info_1014_0508 +#define pci_ss_info_1014_0508 pci_ss_info_8086_2485_1014_0508 +static const pciSubsystemInfo pci_ss_info_8086_2485_1014_051c = + {0x1014, 0x051c, pci_subsys_8086_2485_1014_051c, 0}; +#undef pci_ss_info_1014_051c +#define pci_ss_info_1014_051c pci_ss_info_8086_2485_1014_051c +static const pciSubsystemInfo pci_ss_info_8086_2485_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2485_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2485_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2485_144d_c006 = + {0x144d, 0xc006, pci_subsys_8086_2485_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_8086_2485_144d_c006 +static const pciSubsystemInfo pci_ss_info_8086_2486_1014_0223 = + {0x1014, 0x0223, pci_subsys_8086_2486_1014_0223, 0}; +#undef pci_ss_info_1014_0223 +#define pci_ss_info_1014_0223 pci_ss_info_8086_2486_1014_0223 +static const pciSubsystemInfo pci_ss_info_8086_2486_1014_0503 = + {0x1014, 0x0503, pci_subsys_8086_2486_1014_0503, 0}; +#undef pci_ss_info_1014_0503 +#define pci_ss_info_1014_0503 pci_ss_info_8086_2486_1014_0503 +static const pciSubsystemInfo pci_ss_info_8086_2486_1014_051a = + {0x1014, 0x051a, pci_subsys_8086_2486_1014_051a, 0}; +#undef pci_ss_info_1014_051a +#define pci_ss_info_1014_051a pci_ss_info_8086_2486_1014_051a +static const pciSubsystemInfo pci_ss_info_8086_2486_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2486_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2486_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2486_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_2486_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_2486_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_2486_134d_4c21 = + {0x134d, 0x4c21, pci_subsys_8086_2486_134d_4c21, 0}; +#undef pci_ss_info_134d_4c21 +#define pci_ss_info_134d_4c21 pci_ss_info_8086_2486_134d_4c21 +static const pciSubsystemInfo pci_ss_info_8086_2486_144d_2115 = + {0x144d, 0x2115, pci_subsys_8086_2486_144d_2115, 0}; +#undef pci_ss_info_144d_2115 +#define pci_ss_info_144d_2115 pci_ss_info_8086_2486_144d_2115 +static const pciSubsystemInfo pci_ss_info_8086_2486_14f1_5421 = + {0x14f1, 0x5421, pci_subsys_8086_2486_14f1_5421, 0}; +#undef pci_ss_info_14f1_5421 +#define pci_ss_info_14f1_5421 pci_ss_info_8086_2486_14f1_5421 +static const pciSubsystemInfo pci_ss_info_8086_2487_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_2487_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_2487_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_2487_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2487_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2487_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2487_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2487_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2487_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2487_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_2487_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_2487_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_248a_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_248a_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_248a_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_248a_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_248a_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_248a_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_248a_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_248a_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_248a_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_248b_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_248b_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_248b_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_24c0_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c0_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c0_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c2_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c2_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c3_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c3_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c4_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c4_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c5_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c5_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c7_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c7_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24cb_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24cb_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24cb_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1462_3981 = + {0x1462, 0x3981, pci_subsys_8086_24cd_1462_3981, 0}; +#undef pci_ss_info_1462_3981 +#define pci_ss_info_1462_3981 pci_ss_info_8086_24cd_1462_3981 +static const pciSubsystemInfo pci_ss_info_8086_2500_1028_0095 = + {0x1028, 0x0095, pci_subsys_8086_2500_1028_0095, 0}; +#undef pci_ss_info_1028_0095 +#define pci_ss_info_1028_0095 pci_ss_info_8086_2500_1028_0095 +static const pciSubsystemInfo pci_ss_info_8086_2500_1043_801c = + {0x1043, 0x801c, pci_subsys_8086_2500_1043_801c, 0}; +#undef pci_ss_info_1043_801c +#define pci_ss_info_1043_801c pci_ss_info_8086_2500_1043_801c +static const pciSubsystemInfo pci_ss_info_8086_2501_1043_801c = + {0x1043, 0x801c, pci_subsys_8086_2501_1043_801c, 0}; +#undef pci_ss_info_1043_801c +#define pci_ss_info_1043_801c pci_ss_info_8086_2501_1043_801c +static const pciSubsystemInfo pci_ss_info_8086_2530_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2530_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2530_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2540_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2540_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2540_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2541_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2541_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2541_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2560_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_2560_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_2560_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_3575_1014_021d = + {0x1014, 0x021d, pci_subsys_8086_3575_1014_021d, 0}; +#undef pci_ss_info_1014_021d +#define pci_ss_info_1014_021d pci_ss_info_8086_3575_1014_021d +static const pciSubsystemInfo pci_ss_info_8086_3575_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_3575_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_3575_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_3577_1014_0513 = + {0x1014, 0x0513, pci_subsys_8086_3577_1014_0513, 0}; +#undef pci_ss_info_1014_0513 +#define pci_ss_info_1014_0513 pci_ss_info_8086_3577_1014_0513 +static const pciSubsystemInfo pci_ss_info_8086_5201_8086_0001 = + {0x8086, 0x0001, pci_subsys_8086_5201_8086_0001, 0}; +#undef pci_ss_info_8086_0001 +#define pci_ss_info_8086_0001 pci_ss_info_8086_5201_8086_0001 +static const pciSubsystemInfo pci_ss_info_8086_7190_0e11_0500 = + {0x0e11, 0x0500, pci_subsys_8086_7190_0e11_0500, 0}; +#undef pci_ss_info_0e11_0500 +#define pci_ss_info_0e11_0500 pci_ss_info_8086_7190_0e11_0500 +static const pciSubsystemInfo pci_ss_info_8086_7190_0e11_b110 = + {0x0e11, 0xb110, pci_subsys_8086_7190_0e11_b110, 0}; +#undef pci_ss_info_0e11_b110 +#define pci_ss_info_0e11_b110 pci_ss_info_8086_7190_0e11_b110 +static const pciSubsystemInfo pci_ss_info_8086_7190_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_7190_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_7190_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_7192_0e11_0460 = + {0x0e11, 0x0460, pci_subsys_8086_7192_0e11_0460, 0}; +#undef pci_ss_info_0e11_0460 +#define pci_ss_info_0e11_0460 pci_ss_info_8086_7192_0e11_0460 +static const pciSubsystemInfo pci_ss_info_8086_7195_10cf_1099 = + {0x10cf, 0x1099, pci_subsys_8086_7195_10cf_1099, 0}; +#undef pci_ss_info_10cf_1099 +#define pci_ss_info_10cf_1099 pci_ss_info_8086_7195_10cf_1099 +static const pciSubsystemInfo pci_ss_info_8086_7195_11d4_0040 = + {0x11d4, 0x0040, pci_subsys_8086_7195_11d4_0040, 0}; +#undef pci_ss_info_11d4_0040 +#define pci_ss_info_11d4_0040 pci_ss_info_8086_7195_11d4_0040 +static const pciSubsystemInfo pci_ss_info_8086_7195_11d4_0048 = + {0x11d4, 0x0048, pci_subsys_8086_7195_11d4_0048, 0}; +#undef pci_ss_info_11d4_0048 +#define pci_ss_info_11d4_0048 pci_ss_info_8086_7195_11d4_0048 +static const pciSubsystemInfo pci_ss_info_8086_7800_003d_0008 = + {0x003d, 0x0008, pci_subsys_8086_7800_003d_0008, 0}; +#undef pci_ss_info_003d_0008 +#define pci_ss_info_003d_0008 pci_ss_info_8086_7800_003d_0008 +static const pciSubsystemInfo pci_ss_info_8086_7800_003d_000b = + {0x003d, 0x000b, pci_subsys_8086_7800_003d_000b, 0}; +#undef pci_ss_info_003d_000b +#define pci_ss_info_003d_000b pci_ss_info_8086_7800_003d_000b +static const pciSubsystemInfo pci_ss_info_8086_7800_1092_0100 = + {0x1092, 0x0100, pci_subsys_8086_7800_1092_0100, 0}; +#undef pci_ss_info_1092_0100 +#define pci_ss_info_1092_0100 pci_ss_info_8086_7800_1092_0100 +static const pciSubsystemInfo pci_ss_info_8086_7800_10b4_201a = + {0x10b4, 0x201a, pci_subsys_8086_7800_10b4_201a, 0}; +#undef pci_ss_info_10b4_201a +#define pci_ss_info_10b4_201a pci_ss_info_8086_7800_10b4_201a +static const pciSubsystemInfo pci_ss_info_8086_7800_10b4_202f = + {0x10b4, 0x202f, pci_subsys_8086_7800_10b4_202f, 0}; +#undef pci_ss_info_10b4_202f +#define pci_ss_info_10b4_202f pci_ss_info_8086_7800_10b4_202f +static const pciSubsystemInfo pci_ss_info_8086_7800_8086_0000 = + {0x8086, 0x0000, pci_subsys_8086_7800_8086_0000, 0}; +#undef pci_ss_info_8086_0000 +#define pci_ss_info_8086_0000 pci_ss_info_8086_7800_8086_0000 +static const pciSubsystemInfo pci_ss_info_8086_7800_8086_0100 = + {0x8086, 0x0100, pci_subsys_8086_7800_8086_0100, 0}; +#undef pci_ss_info_8086_0100 +#define pci_ss_info_8086_0100 pci_ss_info_8086_7800_8086_0100 +static const pciSubsystemInfo pci_ss_info_8086_b555_e4bf_1000 = + {0xe4bf, 0x1000, pci_subsys_8086_b555_e4bf_1000, 0}; +#undef pci_ss_info_e4bf_1000 +#define pci_ss_info_e4bf_1000 pci_ss_info_8086_b555_e4bf_1000 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9004_5078_9004_7850 = + {0x9004, 0x7850, pci_subsys_9004_5078_9004_7850, 0}; +#undef pci_ss_info_9004_7850 +#define pci_ss_info_9004_7850 pci_ss_info_9004_5078_9004_7850 +static const pciSubsystemInfo pci_ss_info_9004_5647_9004_7710 = + {0x9004, 0x7710, pci_subsys_9004_5647_9004_7710, 0}; +#undef pci_ss_info_9004_7710 +#define pci_ss_info_9004_7710 pci_ss_info_9004_5647_9004_7710 +static const pciSubsystemInfo pci_ss_info_9004_5647_9004_7711 = + {0x9004, 0x7711, pci_subsys_9004_5647_9004_7711, 0}; +#undef pci_ss_info_9004_7711 +#define pci_ss_info_9004_7711 pci_ss_info_9004_5647_9004_7711 +static const pciSubsystemInfo pci_ss_info_9004_6075_9004_7560 = + {0x9004, 0x7560, pci_subsys_9004_6075_9004_7560, 0}; +#undef pci_ss_info_9004_7560 +#define pci_ss_info_9004_7560 pci_ss_info_9004_6075_9004_7560 +static const pciSubsystemInfo pci_ss_info_9004_6178_9004_7861 = + {0x9004, 0x7861, pci_subsys_9004_6178_9004_7861, 0}; +#undef pci_ss_info_9004_7861 +#define pci_ss_info_9004_7861 pci_ss_info_9004_6178_9004_7861 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0008 = + {0x9004, 0x0008, pci_subsys_9004_6915_9004_0008, 0}; +#undef pci_ss_info_9004_0008 +#define pci_ss_info_9004_0008 pci_ss_info_9004_6915_9004_0008 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0009 = + {0x9004, 0x0009, pci_subsys_9004_6915_9004_0009, 0}; +#undef pci_ss_info_9004_0009 +#define pci_ss_info_9004_0009 pci_ss_info_9004_6915_9004_0009 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0010 = + {0x9004, 0x0010, pci_subsys_9004_6915_9004_0010, 0}; +#undef pci_ss_info_9004_0010 +#define pci_ss_info_9004_0010 pci_ss_info_9004_6915_9004_0010 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0018 = + {0x9004, 0x0018, pci_subsys_9004_6915_9004_0018, 0}; +#undef pci_ss_info_9004_0018 +#define pci_ss_info_9004_0018 pci_ss_info_9004_6915_9004_0018 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0019 = + {0x9004, 0x0019, pci_subsys_9004_6915_9004_0019, 0}; +#undef pci_ss_info_9004_0019 +#define pci_ss_info_9004_0019 pci_ss_info_9004_6915_9004_0019 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0020 = + {0x9004, 0x0020, pci_subsys_9004_6915_9004_0020, 0}; +#undef pci_ss_info_9004_0020 +#define pci_ss_info_9004_0020 pci_ss_info_9004_6915_9004_0020 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0028 = + {0x9004, 0x0028, pci_subsys_9004_6915_9004_0028, 0}; +#undef pci_ss_info_9004_0028 +#define pci_ss_info_9004_0028 pci_ss_info_9004_6915_9004_0028 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8008 = + {0x9004, 0x8008, pci_subsys_9004_6915_9004_8008, 0}; +#undef pci_ss_info_9004_8008 +#define pci_ss_info_9004_8008 pci_ss_info_9004_6915_9004_8008 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8009 = + {0x9004, 0x8009, pci_subsys_9004_6915_9004_8009, 0}; +#undef pci_ss_info_9004_8009 +#define pci_ss_info_9004_8009 pci_ss_info_9004_6915_9004_8009 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8010 = + {0x9004, 0x8010, pci_subsys_9004_6915_9004_8010, 0}; +#undef pci_ss_info_9004_8010 +#define pci_ss_info_9004_8010 pci_ss_info_9004_6915_9004_8010 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8018 = + {0x9004, 0x8018, pci_subsys_9004_6915_9004_8018, 0}; +#undef pci_ss_info_9004_8018 +#define pci_ss_info_9004_8018 pci_ss_info_9004_6915_9004_8018 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8019 = + {0x9004, 0x8019, pci_subsys_9004_6915_9004_8019, 0}; +#undef pci_ss_info_9004_8019 +#define pci_ss_info_9004_8019 pci_ss_info_9004_6915_9004_8019 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8020 = + {0x9004, 0x8020, pci_subsys_9004_6915_9004_8020, 0}; +#undef pci_ss_info_9004_8020 +#define pci_ss_info_9004_8020 pci_ss_info_9004_6915_9004_8020 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8028 = + {0x9004, 0x8028, pci_subsys_9004_6915_9004_8028, 0}; +#undef pci_ss_info_9004_8028 +#define pci_ss_info_9004_8028 pci_ss_info_9004_6915_9004_8028 +static const pciSubsystemInfo pci_ss_info_9004_7815_9004_7815 = + {0x9004, 0x7815, pci_subsys_9004_7815_9004_7815, 0}; +#undef pci_ss_info_9004_7815 +#define pci_ss_info_9004_7815 pci_ss_info_9004_7815_9004_7815 +static const pciSubsystemInfo pci_ss_info_9004_7815_9004_7840 = + {0x9004, 0x7840, pci_subsys_9004_7815_9004_7840, 0}; +#undef pci_ss_info_9004_7840 +#define pci_ss_info_9004_7840 pci_ss_info_9004_7815_9004_7840 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7890 = + {0x9004, 0x7890, pci_subsys_9004_7895_9004_7890, 0}; +#undef pci_ss_info_9004_7890 +#define pci_ss_info_9004_7890 pci_ss_info_9004_7895_9004_7890 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7891 = + {0x9004, 0x7891, pci_subsys_9004_7895_9004_7891, 0}; +#undef pci_ss_info_9004_7891 +#define pci_ss_info_9004_7891 pci_ss_info_9004_7895_9004_7891 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7892 = + {0x9004, 0x7892, pci_subsys_9004_7895_9004_7892, 0}; +#undef pci_ss_info_9004_7892 +#define pci_ss_info_9004_7892 pci_ss_info_9004_7895_9004_7892 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7894 = + {0x9004, 0x7894, pci_subsys_9004_7895_9004_7894, 0}; +#undef pci_ss_info_9004_7894 +#define pci_ss_info_9004_7894 pci_ss_info_9004_7895_9004_7894 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7895 = + {0x9004, 0x7895, pci_subsys_9004_7895_9004_7895, 0}; +#undef pci_ss_info_9004_7895 +#define pci_ss_info_9004_7895 pci_ss_info_9004_7895_9004_7895 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7896 = + {0x9004, 0x7896, pci_subsys_9004_7895_9004_7896, 0}; +#undef pci_ss_info_9004_7896 +#define pci_ss_info_9004_7896 pci_ss_info_9004_7895_9004_7896 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7897 = + {0x9004, 0x7897, pci_subsys_9004_7895_9004_7897, 0}; +#undef pci_ss_info_9004_7897 +#define pci_ss_info_9004_7897 pci_ss_info_9004_7895_9004_7897 +static const pciSubsystemInfo pci_ss_info_9004_8078_9004_7880 = + {0x9004, 0x7880, pci_subsys_9004_8078_9004_7880, 0}; +#undef pci_ss_info_9004_7880 +#define pci_ss_info_9004_7880 pci_ss_info_9004_8078_9004_7880 +static const pciSubsystemInfo pci_ss_info_9004_8178_9004_7881 = + {0x9004, 0x7881, pci_subsys_9004_8178_9004_7881, 0}; +#undef pci_ss_info_9004_7881 +#define pci_ss_info_9004_7881 pci_ss_info_9004_8178_9004_7881 +static const pciSubsystemInfo pci_ss_info_9004_8778_9004_7887 = + {0x9004, 0x7887, pci_subsys_9004_8778_9004_7887, 0}; +#undef pci_ss_info_9004_7887 +#define pci_ss_info_9004_7887 pci_ss_info_9004_8778_9004_7887 +static const pciSubsystemInfo pci_ss_info_9004_8878_9004_7888 = + {0x9004, 0x7888, pci_subsys_9004_8878_9004_7888, 0}; +#undef pci_ss_info_9004_7888 +#define pci_ss_info_9004_7888 pci_ss_info_9004_8878_9004_7888 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_0010_9005_2180 = + {0x9005, 0x2180, pci_subsys_9005_0010_9005_2180, 0}; +#undef pci_ss_info_9005_2180 +#define pci_ss_info_9005_2180 pci_ss_info_9005_0010_9005_2180 +static const pciSubsystemInfo pci_ss_info_9005_0010_9005_8100 = + {0x9005, 0x8100, pci_subsys_9005_0010_9005_8100, 0}; +#undef pci_ss_info_9005_8100 +#define pci_ss_info_9005_8100 pci_ss_info_9005_0010_9005_8100 +static const pciSubsystemInfo pci_ss_info_9005_0010_9005_a180 = + {0x9005, 0xa180, pci_subsys_9005_0010_9005_a180, 0}; +#undef pci_ss_info_9005_a180 +#define pci_ss_info_9005_a180 pci_ss_info_9005_0010_9005_a180 +static const pciSubsystemInfo pci_ss_info_9005_0010_9005_e100 = + {0x9005, 0xe100, pci_subsys_9005_0010_9005_e100, 0}; +#undef pci_ss_info_9005_e100 +#define pci_ss_info_9005_e100 pci_ss_info_9005_0010_9005_e100 +static const pciSubsystemInfo pci_ss_info_9005_0013_9005_0003 = + {0x9005, 0x0003, pci_subsys_9005_0013_9005_0003, 0}; +#undef pci_ss_info_9005_0003 +#define pci_ss_info_9005_0003 pci_ss_info_9005_0013_9005_0003 +static const pciSubsystemInfo pci_ss_info_9005_001f_9005_000f = + {0x9005, 0x000f, pci_subsys_9005_001f_9005_000f, 0}; +#undef pci_ss_info_9005_000f +#define pci_ss_info_9005_000f pci_ss_info_9005_001f_9005_000f +static const pciSubsystemInfo pci_ss_info_9005_001f_9005_a180 = + {0x9005, 0xa180, pci_subsys_9005_001f_9005_a180, 0}; +#undef pci_ss_info_9005_a180 +#define pci_ss_info_9005_a180 pci_ss_info_9005_001f_9005_a180 +static const pciSubsystemInfo pci_ss_info_9005_0050_9005_f500 = + {0x9005, 0xf500, pci_subsys_9005_0050_9005_f500, 0}; +#undef pci_ss_info_9005_f500 +#define pci_ss_info_9005_f500 pci_ss_info_9005_0050_9005_f500 +static const pciSubsystemInfo pci_ss_info_9005_0051_9005_b500 = + {0x9005, 0xb500, pci_subsys_9005_0051_9005_b500, 0}; +#undef pci_ss_info_9005_b500 +#define pci_ss_info_9005_b500 pci_ss_info_9005_0051_9005_b500 +static const pciSubsystemInfo pci_ss_info_9005_0053_9005_ffff = + {0x9005, 0xffff, pci_subsys_9005_0053_9005_ffff, 0}; +#undef pci_ss_info_9005_ffff +#define pci_ss_info_9005_ffff pci_ss_info_9005_0053_9005_ffff +#endif +static const pciSubsystemInfo pci_ss_info_9005_0080_0e11_e2a0 = + {0x0e11, 0xe2a0, pci_subsys_9005_0080_0e11_e2a0, 0}; +#undef pci_ss_info_0e11_e2a0 +#define pci_ss_info_0e11_e2a0 pci_ss_info_9005_0080_0e11_e2a0 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_0080_9005_62a0 = + {0x9005, 0x62a0, pci_subsys_9005_0080_9005_62a0, 0}; +#undef pci_ss_info_9005_62a0 +#define pci_ss_info_9005_62a0 pci_ss_info_9005_0080_9005_62a0 +static const pciSubsystemInfo pci_ss_info_9005_0080_9005_e220 = + {0x9005, 0xe220, pci_subsys_9005_0080_9005_e220, 0}; +#undef pci_ss_info_9005_e220 +#define pci_ss_info_9005_e220 pci_ss_info_9005_0080_9005_e220 +static const pciSubsystemInfo pci_ss_info_9005_0080_9005_e2a0 = + {0x9005, 0xe2a0, pci_subsys_9005_0080_9005_e2a0, 0}; +#undef pci_ss_info_9005_e2a0 +#define pci_ss_info_9005_e2a0 pci_ss_info_9005_0080_9005_e2a0 +static const pciSubsystemInfo pci_ss_info_9005_0081_9005_62a1 = + {0x9005, 0x62a1, pci_subsys_9005_0081_9005_62a1, 0}; +#undef pci_ss_info_9005_62a1 +#define pci_ss_info_9005_62a1 pci_ss_info_9005_0081_9005_62a1 +static const pciSubsystemInfo pci_ss_info_9005_008f_1179_0001 = + {0x1179, 0x0001, pci_subsys_9005_008f_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_9005_008f_1179_0001 +static const pciSubsystemInfo pci_ss_info_9005_008f_15d9_9005 = + {0x15d9, 0x9005, pci_subsys_9005_008f_15d9_9005, 0}; +#undef pci_ss_info_15d9_9005 +#define pci_ss_info_15d9_9005 pci_ss_info_9005_008f_15d9_9005 +#endif +static const pciSubsystemInfo pci_ss_info_9005_00c0_0e11_f620 = + {0x0e11, 0xf620, pci_subsys_9005_00c0_0e11_f620, 0}; +#undef pci_ss_info_0e11_f620 +#define pci_ss_info_0e11_f620 pci_ss_info_9005_00c0_0e11_f620 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_00c0_9005_f620 = + {0x9005, 0xf620, pci_subsys_9005_00c0_9005_f620, 0}; +#undef pci_ss_info_9005_f620 +#define pci_ss_info_9005_f620 pci_ss_info_9005_00c0_9005_f620 +#endif +static const pciSubsystemInfo pci_ss_info_9005_00c5_1028_00c5 = + {0x1028, 0x00c5, pci_subsys_9005_00c5_1028_00c5, 0}; +#undef pci_ss_info_1028_00c5 +#define pci_ss_info_1028_00c5 pci_ss_info_9005_00c5_1028_00c5 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_9005_00cf_1028_00d1 = + {0x1028, 0x00d1, pci_subsys_9005_00cf_1028_00d1, 0}; +#undef pci_ss_info_1028_00d1 +#define pci_ss_info_1028_00d1 pci_ss_info_9005_00cf_1028_00d1 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_00cf_10f1_2462 = + {0x10f1, 0x2462, pci_subsys_9005_00cf_10f1_2462, 0}; +#undef pci_ss_info_10f1_2462 +#define pci_ss_info_10f1_2462 pci_ss_info_9005_00cf_10f1_2462 +static const pciSubsystemInfo pci_ss_info_9005_00cf_15d9_9005 = + {0x15d9, 0x9005, pci_subsys_9005_00cf_15d9_9005, 0}; +#undef pci_ss_info_15d9_9005 +#define pci_ss_info_15d9_9005 pci_ss_info_9005_00cf_15d9_9005 +static const pciSubsystemInfo pci_ss_info_9005_0250_1014_0279 = + {0x1014, 0x0279, pci_subsys_9005_0250_1014_0279, 0}; +#undef pci_ss_info_1014_0279 +#define pci_ss_info_1014_0279 pci_ss_info_9005_0250_1014_0279 +static const pciSubsystemInfo pci_ss_info_9005_0250_1014_028c = + {0x1014, 0x028c, pci_subsys_9005_0250_1014_028c, 0}; +#undef pci_ss_info_1014_028c +#define pci_ss_info_1014_028c pci_ss_info_9005_0250_1014_028c +#endif +static const pciSubsystemInfo pci_ss_info_9005_0285_1028_0287 = + {0x1028, 0x0287, pci_subsys_9005_0285_1028_0287, 0}; +#undef pci_ss_info_1028_0287 +#define pci_ss_info_1028_0287 pci_ss_info_9005_0285_1028_0287 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_9005_8011_0e11_00ac = + {0x0e11, 0x00ac, pci_subsys_9005_8011_0e11_00ac, 0}; +#undef pci_ss_info_0e11_00ac +#define pci_ss_info_0e11_00ac pci_ss_info_9005_8011_0e11_00ac +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_8011_9005_0041 = + {0x9005, 0x0041, pci_subsys_9005_8011_9005_0041, 0}; +#undef pci_ss_info_9005_0041 +#define pci_ss_info_9005_0041 pci_ss_info_9005_8011_9005_0041 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_e159_0001_0059_0001 = + {0x0059, 0x0001, pci_subsys_e159_0001_0059_0001, 0}; +#undef pci_ss_info_0059_0001 +#define pci_ss_info_0059_0001 pci_ss_info_e159_0001_0059_0001 +static const pciSubsystemInfo pci_ss_info_e159_0001_0059_0003 = + {0x0059, 0x0003, pci_subsys_e159_0001_0059_0003, 0}; +#undef pci_ss_info_0059_0003 +#define pci_ss_info_0059_0003 pci_ss_info_e159_0001_0059_0003 +#endif +#define pci_ss_list_0675_1700 NULL +#define pci_ss_list_0675_1702 NULL +#define pci_ss_list_09c1_0704 NULL +#define pci_ss_list_0e11_0001 NULL +#define pci_ss_list_0e11_0002 NULL +#define pci_ss_list_0e11_0049 NULL +#define pci_ss_list_0e11_004a NULL +#define pci_ss_list_0e11_0508 NULL +#define pci_ss_list_0e11_1000 NULL +#define pci_ss_list_0e11_2000 NULL +#define pci_ss_list_0e11_3032 NULL +#define pci_ss_list_0e11_3033 NULL +#define pci_ss_list_0e11_3034 NULL +#define pci_ss_list_0e11_4000 NULL +#define pci_ss_list_0e11_6010 NULL +#define pci_ss_list_0e11_7020 NULL +#define pci_ss_list_0e11_a0ec NULL +#define pci_ss_list_0e11_a0f0 NULL +#define pci_ss_list_0e11_a0f3 NULL +static const pciSubsystemInfo *pci_ss_list_0e11_a0f7[] = { + &pci_ss_info_0e11_a0f7_8086_002a, + &pci_ss_info_0e11_a0f7_8086_002b, + NULL +}; +#define pci_ss_list_0e11_a0f8 NULL +#define pci_ss_list_0e11_a0fc NULL +static const pciSubsystemInfo *pci_ss_list_0e11_ae10[] = { + &pci_ss_info_0e11_ae10_0e11_4030, + &pci_ss_info_0e11_ae10_0e11_4031, + &pci_ss_info_0e11_ae10_0e11_4032, + &pci_ss_info_0e11_ae10_0e11_4033, + NULL +}; +#define pci_ss_list_0e11_ae29 NULL +#define pci_ss_list_0e11_ae2a NULL +#define pci_ss_list_0e11_ae2b NULL +#define pci_ss_list_0e11_ae31 NULL +#define pci_ss_list_0e11_ae32 NULL +#define pci_ss_list_0e11_ae33 NULL +#define pci_ss_list_0e11_ae34 NULL +#define pci_ss_list_0e11_ae35 NULL +#define pci_ss_list_0e11_ae40 NULL +#define pci_ss_list_0e11_ae43 NULL +#define pci_ss_list_0e11_ae69 NULL +#define pci_ss_list_0e11_ae6c NULL +#define pci_ss_list_0e11_ae6d NULL +#define pci_ss_list_0e11_b011 NULL +#define pci_ss_list_0e11_b012 NULL +#define pci_ss_list_0e11_b01e NULL +#define pci_ss_list_0e11_b01f NULL +#define pci_ss_list_0e11_b02f NULL +#define pci_ss_list_0e11_b030 NULL +#define pci_ss_list_0e11_b04a NULL +#define pci_ss_list_0e11_b060 NULL +#define pci_ss_list_0e11_b0c6 NULL +#define pci_ss_list_0e11_b0c7 NULL +#define pci_ss_list_0e11_b0d7 NULL +#define pci_ss_list_0e11_b0dd NULL +#define pci_ss_list_0e11_b0de NULL +#define pci_ss_list_0e11_b0df NULL +#define pci_ss_list_0e11_b0e0 NULL +#define pci_ss_list_0e11_b0e1 NULL +#define pci_ss_list_0e11_b123 NULL +#define pci_ss_list_0e11_b134 NULL +#define pci_ss_list_0e11_b13c NULL +#define pci_ss_list_0e11_b144 NULL +#define pci_ss_list_0e11_b163 NULL +#define pci_ss_list_0e11_b164 NULL +#define pci_ss_list_0e11_b178 NULL +#define pci_ss_list_0e11_b1a4 NULL +#define pci_ss_list_0e11_f130 NULL +#define pci_ss_list_0e11_f150 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1000_0001[] = { + &pci_ss_info_1000_0001_1000_1000, + NULL +}; +#define pci_ss_list_1000_0002 NULL +#define pci_ss_list_1000_0003 NULL +#define pci_ss_list_1000_0004 NULL +#define pci_ss_list_1000_0005 NULL +#define pci_ss_list_1000_0006 NULL +#define pci_ss_list_1000_000a NULL +#define pci_ss_list_1000_000b NULL +static const pciSubsystemInfo *pci_ss_list_1000_000c[] = { + &pci_ss_info_1000_000c_1de1_3907, + NULL +}; +#define pci_ss_list_1000_000d NULL +static const pciSubsystemInfo *pci_ss_list_1000_000f[] = { + &pci_ss_info_1000_000f_0e11_7004, + &pci_ss_info_1000_000f_1092_8760, + &pci_ss_info_1000_000f_1de1_3904, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0010[] = { + &pci_ss_info_1000_0010_0e11_4040, + &pci_ss_info_1000_0010_0e11_4048, + NULL +}; +#define pci_ss_list_1000_0012 NULL +#define pci_ss_list_1000_0013 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0020[] = { + &pci_ss_info_1000_0020_1de1_1020, + NULL +}; +#define pci_ss_list_1000_0021 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0030[] = { + &pci_ss_info_1000_0030_1028_1010, + NULL +}; +#define pci_ss_list_1000_0040 NULL +static const pciSubsystemInfo *pci_ss_list_1000_008f[] = { + &pci_ss_info_1000_008f_1092_8000, + &pci_ss_info_1000_008f_1092_8760, + NULL +}; +#define pci_ss_list_1000_0621 NULL +#define pci_ss_list_1000_0622 NULL +#define pci_ss_list_1000_0623 NULL +#define pci_ss_list_1000_0624 NULL +#define pci_ss_list_1000_0625 NULL +#define pci_ss_list_1000_0626 NULL +#define pci_ss_list_1000_0627 NULL +#define pci_ss_list_1000_0628 NULL +#define pci_ss_list_1000_0629 NULL +#define pci_ss_list_1000_0701 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0702[] = { + &pci_ss_info_1000_0702_1318_0000, + NULL +}; +#define pci_ss_list_1000_0901 NULL +#define pci_ss_list_1000_1000 NULL +static const pciSubsystemInfo *pci_ss_list_1000_1960[] = { + &pci_ss_info_1000_1960_1028_0518, + &pci_ss_info_1000_1960_1028_0520, + &pci_ss_info_1000_1960_1028_0531, + NULL +}; +#endif +#define pci_ss_list_1001_0010 NULL +#define pci_ss_list_1001_0011 NULL +#define pci_ss_list_1001_0012 NULL +#define pci_ss_list_1001_0013 NULL +#define pci_ss_list_1001_0014 NULL +#define pci_ss_list_1001_0015 NULL +#define pci_ss_list_1001_0016 NULL +#define pci_ss_list_1001_0017 NULL +#define pci_ss_list_1001_9100 NULL +#define pci_ss_list_1002_4144 NULL +#define pci_ss_list_1002_4145 NULL +#define pci_ss_list_1002_4146 NULL +#define pci_ss_list_1002_4147 NULL +#define pci_ss_list_1002_4158 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4242[] = { + &pci_ss_info_1002_4242_1002_02aa, + NULL +}; +#define pci_ss_list_1002_4336 NULL +#define pci_ss_list_1002_4337 NULL +#define pci_ss_list_1002_4354 NULL +#define pci_ss_list_1002_4358 NULL +#define pci_ss_list_1002_4554 NULL +#define pci_ss_list_1002_4654 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4742[] = { + &pci_ss_info_1002_4742_1002_0040, + &pci_ss_info_1002_4742_1002_0044, + &pci_ss_info_1002_4742_1002_0061, + &pci_ss_info_1002_4742_1002_0062, + &pci_ss_info_1002_4742_1002_0063, + &pci_ss_info_1002_4742_1002_0080, + &pci_ss_info_1002_4742_1002_0084, + &pci_ss_info_1002_4742_1002_4742, + &pci_ss_info_1002_4742_1002_8001, + &pci_ss_info_1002_4742_1028_0082, + &pci_ss_info_1002_4742_1028_4082, + &pci_ss_info_1002_4742_1028_8082, + &pci_ss_info_1002_4742_1028_c082, + &pci_ss_info_1002_4742_8086_4152, + &pci_ss_info_1002_4742_8086_464a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4744[] = { + &pci_ss_info_1002_4744_1002_4744, + NULL +}; +#define pci_ss_list_1002_4747 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4749[] = { + &pci_ss_info_1002_4749_1002_0061, + &pci_ss_info_1002_4749_1002_0062, + NULL +}; +#define pci_ss_list_1002_474c NULL +static const pciSubsystemInfo *pci_ss_list_1002_474d[] = { + &pci_ss_info_1002_474d_1002_0004, + &pci_ss_info_1002_474d_1002_0008, + &pci_ss_info_1002_474d_1002_0080, + &pci_ss_info_1002_474d_1002_0084, + &pci_ss_info_1002_474d_1002_474d, + &pci_ss_info_1002_474d_1033_806a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_474e[] = { + &pci_ss_info_1002_474e_1002_474e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_474f[] = { + &pci_ss_info_1002_474f_1002_0008, + &pci_ss_info_1002_474f_1002_474f, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4750[] = { + &pci_ss_info_1002_4750_1002_0040, + &pci_ss_info_1002_4750_1002_0044, + &pci_ss_info_1002_4750_1002_0080, + &pci_ss_info_1002_4750_1002_0084, + &pci_ss_info_1002_4750_1002_4750, + NULL +}; +#define pci_ss_list_1002_4751 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4752[] = { + &pci_ss_info_1002_4752_1002_0008, + &pci_ss_info_1002_4752_1002_4752, + &pci_ss_info_1002_4752_1002_8008, + &pci_ss_info_1002_4752_1028_00d1, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4753[] = { + &pci_ss_info_1002_4753_1002_4753, + NULL +}; +#define pci_ss_list_1002_4754 NULL +#define pci_ss_list_1002_4755 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4756[] = { + &pci_ss_info_1002_4756_1002_4756, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4757[] = { + &pci_ss_info_1002_4757_1002_4757, + &pci_ss_info_1002_4757_1028_0089, + &pci_ss_info_1002_4757_1028_4082, + &pci_ss_info_1002_4757_1028_8082, + &pci_ss_info_1002_4757_1028_c082, + NULL +}; +#define pci_ss_list_1002_4758 NULL +#define pci_ss_list_1002_4759 NULL +static const pciSubsystemInfo *pci_ss_list_1002_475a[] = { + &pci_ss_info_1002_475a_1002_0087, + &pci_ss_info_1002_475a_1002_475a, + NULL +}; +#define pci_ss_list_1002_4964 NULL +#define pci_ss_list_1002_4965 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4966[] = { + &pci_ss_info_1002_4966_10f1_0002, + &pci_ss_info_1002_4966_148c_2039, + &pci_ss_info_1002_4966_1509_9a00, + &pci_ss_info_1002_4966_1681_0040, + &pci_ss_info_1002_4966_174b_7176, + &pci_ss_info_1002_4966_174b_7192, + &pci_ss_info_1002_4966_17af_2005, + &pci_ss_info_1002_4966_17af_2006, + NULL +}; +#define pci_ss_list_1002_4967 NULL +#define pci_ss_list_1002_496e NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c42[] = { + &pci_ss_info_1002_4c42_0e11_b0e8, + &pci_ss_info_1002_4c42_0e11_b10e, + &pci_ss_info_1002_4c42_1002_0040, + &pci_ss_info_1002_4c42_1002_0044, + &pci_ss_info_1002_4c42_1002_4c42, + &pci_ss_info_1002_4c42_1002_8001, + &pci_ss_info_1002_4c42_1028_0085, + NULL +}; +#define pci_ss_list_1002_4c44 NULL +#define pci_ss_list_1002_4c45 NULL +#define pci_ss_list_1002_4c46 NULL +#define pci_ss_list_1002_4c47 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c49[] = { + &pci_ss_info_1002_4c49_1002_0004, + &pci_ss_info_1002_4c49_1002_0040, + &pci_ss_info_1002_4c49_1002_0044, + &pci_ss_info_1002_4c49_1002_4c49, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4c4d[] = { + &pci_ss_info_1002_4c4d_0e11_b111, + &pci_ss_info_1002_4c4d_1002_0084, + &pci_ss_info_1002_4c4d_1014_0154, + NULL +}; +#define pci_ss_list_1002_4c4e NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c50[] = { + &pci_ss_info_1002_4c50_1002_4c50, + NULL +}; +#define pci_ss_list_1002_4c51 NULL +#define pci_ss_list_1002_4c52 NULL +#define pci_ss_list_1002_4c53 NULL +#define pci_ss_list_1002_4c54 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c57[] = { + &pci_ss_info_1002_4c57_1014_0517, + &pci_ss_info_1002_4c57_1028_00e6, + &pci_ss_info_1002_4c57_144d_c006, + NULL +}; +#define pci_ss_list_1002_4c58 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c59[] = { + &pci_ss_info_1002_4c59_1014_0235, + &pci_ss_info_1002_4c59_1014_0239, + &pci_ss_info_1002_4c59_104d_80e7, + NULL +}; +#define pci_ss_list_1002_4c5a NULL +#define pci_ss_list_1002_4c64 NULL +#define pci_ss_list_1002_4c65 NULL +#define pci_ss_list_1002_4c66 NULL +#define pci_ss_list_1002_4c67 NULL +#define pci_ss_list_1002_4d46 NULL +#define pci_ss_list_1002_4d4c NULL +#define pci_ss_list_1002_4e44 NULL +#define pci_ss_list_1002_4e45 NULL +#define pci_ss_list_1002_4e46 NULL +#define pci_ss_list_1002_4e47 NULL +#define pci_ss_list_1002_4e64 NULL +#define pci_ss_list_1002_4e65 NULL +#define pci_ss_list_1002_4e66 NULL +#define pci_ss_list_1002_4e67 NULL +#define pci_ss_list_1002_5041 NULL +#define pci_ss_list_1002_5042 NULL +#define pci_ss_list_1002_5043 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5044[] = { + &pci_ss_info_1002_5044_1002_0028, + &pci_ss_info_1002_5044_1002_0029, + NULL +}; +#define pci_ss_list_1002_5045 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5046[] = { + &pci_ss_info_1002_5046_1002_0004, + &pci_ss_info_1002_5046_1002_0008, + &pci_ss_info_1002_5046_1002_0014, + &pci_ss_info_1002_5046_1002_0018, + &pci_ss_info_1002_5046_1002_0028, + &pci_ss_info_1002_5046_1002_002a, + &pci_ss_info_1002_5046_1002_0048, + &pci_ss_info_1002_5046_1002_2000, + &pci_ss_info_1002_5046_1002_2001, + NULL +}; +#define pci_ss_list_1002_5047 NULL +#define pci_ss_list_1002_5048 NULL +#define pci_ss_list_1002_5049 NULL +#define pci_ss_list_1002_504a NULL +#define pci_ss_list_1002_504b NULL +#define pci_ss_list_1002_504c NULL +#define pci_ss_list_1002_504d NULL +#define pci_ss_list_1002_504e NULL +#define pci_ss_list_1002_504f NULL +static const pciSubsystemInfo *pci_ss_list_1002_5050[] = { + &pci_ss_info_1002_5050_1002_0008, + NULL +}; +#define pci_ss_list_1002_5051 NULL +#define pci_ss_list_1002_5052 NULL +#define pci_ss_list_1002_5053 NULL +#define pci_ss_list_1002_5054 NULL +#define pci_ss_list_1002_5055 NULL +#define pci_ss_list_1002_5056 NULL +#define pci_ss_list_1002_5057 NULL +#define pci_ss_list_1002_5058 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5144[] = { + &pci_ss_info_1002_5144_1002_0008, + &pci_ss_info_1002_5144_1002_0009, + &pci_ss_info_1002_5144_1002_000a, + &pci_ss_info_1002_5144_1002_001a, + &pci_ss_info_1002_5144_1002_0029, + &pci_ss_info_1002_5144_1002_0038, + &pci_ss_info_1002_5144_1002_0039, + &pci_ss_info_1002_5144_1002_008a, + &pci_ss_info_1002_5144_1002_00ba, + &pci_ss_info_1002_5144_1002_0139, + &pci_ss_info_1002_5144_1002_028a, + &pci_ss_info_1002_5144_1002_02aa, + &pci_ss_info_1002_5144_1002_053a, + NULL +}; +#define pci_ss_list_1002_5145 NULL +#define pci_ss_list_1002_5146 NULL +#define pci_ss_list_1002_5147 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5148[] = { + &pci_ss_info_1002_5148_1002_010a, + &pci_ss_info_1002_5148_1002_0152, + &pci_ss_info_1002_5148_1002_0162, + &pci_ss_info_1002_5148_1002_0172, + NULL +}; +#define pci_ss_list_1002_5149 NULL +#define pci_ss_list_1002_514a NULL +#define pci_ss_list_1002_514b NULL +static const pciSubsystemInfo *pci_ss_list_1002_514c[] = { + &pci_ss_info_1002_514c_1002_003a, + &pci_ss_info_1002_514c_1002_013a, + &pci_ss_info_1002_514c_148c_2026, + &pci_ss_info_1002_514c_174b_7149, + NULL +}; +#define pci_ss_list_1002_514d NULL +#define pci_ss_list_1002_514e NULL +#define pci_ss_list_1002_514f NULL +static const pciSubsystemInfo *pci_ss_list_1002_5157[] = { + &pci_ss_info_1002_5157_1002_013a, + &pci_ss_info_1002_5157_1458_4000, + &pci_ss_info_1002_5157_148c_2024, + &pci_ss_info_1002_5157_148c_2025, + &pci_ss_info_1002_5157_148c_2036, + &pci_ss_info_1002_5157_174b_7147, + &pci_ss_info_1002_5157_174b_7161, + &pci_ss_info_1002_5157_17af_0202, + NULL +}; +#define pci_ss_list_1002_5158 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5159[] = { + &pci_ss_info_1002_5159_1002_000a, + &pci_ss_info_1002_5159_1002_000b, + &pci_ss_info_1002_5159_1002_0038, + &pci_ss_info_1002_5159_1002_003a, + &pci_ss_info_1002_5159_1002_00ba, + &pci_ss_info_1002_5159_1002_013a, + &pci_ss_info_1002_5159_1458_4002, + &pci_ss_info_1002_5159_148c_2003, + &pci_ss_info_1002_5159_148c_2023, + &pci_ss_info_1002_5159_174b_7112, + &pci_ss_info_1002_5159_1787_0202, + NULL +}; +#define pci_ss_list_1002_515a NULL +#define pci_ss_list_1002_5168 NULL +#define pci_ss_list_1002_5169 NULL +#define pci_ss_list_1002_516a NULL +#define pci_ss_list_1002_516b NULL +#define pci_ss_list_1002_516c NULL +static const pciSubsystemInfo *pci_ss_list_1002_5245[] = { + &pci_ss_info_1002_5245_1002_0008, + &pci_ss_info_1002_5245_1002_0028, + &pci_ss_info_1002_5245_1002_0029, + &pci_ss_info_1002_5245_1002_0068, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_5246[] = { + &pci_ss_info_1002_5246_1002_0004, + &pci_ss_info_1002_5246_1002_0008, + &pci_ss_info_1002_5246_1002_0028, + &pci_ss_info_1002_5246_1002_0044, + &pci_ss_info_1002_5246_1002_0068, + &pci_ss_info_1002_5246_1002_0448, + NULL +}; +#define pci_ss_list_1002_5247 NULL +#define pci_ss_list_1002_524b NULL +static const pciSubsystemInfo *pci_ss_list_1002_524c[] = { + &pci_ss_info_1002_524c_1002_0008, + &pci_ss_info_1002_524c_1002_0088, + NULL +}; +#define pci_ss_list_1002_5345 NULL +#define pci_ss_list_1002_5346 NULL +#define pci_ss_list_1002_5347 NULL +#define pci_ss_list_1002_5348 NULL +#define pci_ss_list_1002_534b NULL +#define pci_ss_list_1002_534c NULL +static const pciSubsystemInfo *pci_ss_list_1002_534d[] = { + &pci_ss_info_1002_534d_1002_0008, + &pci_ss_info_1002_534d_1002_0018, + NULL +}; +#define pci_ss_list_1002_534e NULL +static const pciSubsystemInfo *pci_ss_list_1002_5354[] = { + &pci_ss_info_1002_5354_1002_5654, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_5446[] = { + &pci_ss_info_1002_5446_1002_0004, + &pci_ss_info_1002_5446_1002_0008, + &pci_ss_info_1002_5446_1002_0018, + &pci_ss_info_1002_5446_1002_0028, + &pci_ss_info_1002_5446_1002_0029, + &pci_ss_info_1002_5446_1002_002a, + &pci_ss_info_1002_5446_1002_002b, + &pci_ss_info_1002_5446_1002_0048, + NULL +}; +#define pci_ss_list_1002_544c NULL +static const pciSubsystemInfo *pci_ss_list_1002_5452[] = { + &pci_ss_info_1002_5452_1002_001c, + &pci_ss_info_1002_5452_103c_1279, + NULL +}; +#define pci_ss_list_1002_5453 NULL +#define pci_ss_list_1002_5454 NULL +#define pci_ss_list_1002_5455 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5654[] = { + &pci_ss_info_1002_5654_1002_5654, + NULL +}; +#define pci_ss_list_1002_5655 NULL +#define pci_ss_list_1002_5656 NULL +#define pci_ss_list_1002_700f NULL +#define pci_ss_list_1003_0201 NULL +#define pci_ss_list_1004_0005 NULL +#define pci_ss_list_1004_0006 NULL +#define pci_ss_list_1004_0007 NULL +#define pci_ss_list_1004_0008 NULL +#define pci_ss_list_1004_0009 NULL +#define pci_ss_list_1004_000c NULL +#define pci_ss_list_1004_000d NULL +#define pci_ss_list_1004_0101 NULL +#define pci_ss_list_1004_0102 NULL +#define pci_ss_list_1004_0103 NULL +#define pci_ss_list_1004_0104 NULL +#define pci_ss_list_1004_0105 NULL +#define pci_ss_list_1004_0200 NULL +#define pci_ss_list_1004_0280 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1004_0304[] = { + &pci_ss_info_1004_0304_1004_0304, + &pci_ss_info_1004_0304_122d_1206, + &pci_ss_info_1004_0304_1483_5020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1004_0305[] = { + &pci_ss_info_1004_0305_1004_0305, + &pci_ss_info_1004_0305_122d_1207, + &pci_ss_info_1004_0305_1483_5021, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1004_0306[] = { + &pci_ss_info_1004_0306_1004_0306, + &pci_ss_info_1004_0306_122d_1208, + &pci_ss_info_1004_0306_1483_5022, + NULL +}; +#define pci_ss_list_1004_0307 NULL +#define pci_ss_list_1004_0308 NULL +#define pci_ss_list_1004_0702 NULL +#define pci_ss_list_1004_0703 NULL +#endif +#define pci_ss_list_1005_2064 NULL +#define pci_ss_list_1005_2128 NULL +#define pci_ss_list_1005_2301 NULL +#define pci_ss_list_1005_2302 NULL +#define pci_ss_list_1005_2364 NULL +#define pci_ss_list_1005_2464 NULL +#define pci_ss_list_1005_2501 NULL +#define pci_ss_list_100b_0001 NULL +#define pci_ss_list_100b_0002 NULL +#define pci_ss_list_100b_000e NULL +#define pci_ss_list_100b_000f NULL +#define pci_ss_list_100b_0011 NULL +#define pci_ss_list_100b_0012 NULL +#define pci_ss_list_100b_0020 NULL +#define pci_ss_list_100b_0022 NULL +#define pci_ss_list_100b_0500 NULL +#define pci_ss_list_100b_0501 NULL +#define pci_ss_list_100b_0502 NULL +#define pci_ss_list_100b_0503 NULL +#define pci_ss_list_100b_0504 NULL +#define pci_ss_list_100b_0505 NULL +#define pci_ss_list_100b_d001 NULL +#define pci_ss_list_100c_3202 NULL +#define pci_ss_list_100c_3205 NULL +#define pci_ss_list_100c_3206 NULL +#define pci_ss_list_100c_3207 NULL +#define pci_ss_list_100c_3208 NULL +#define pci_ss_list_100c_4702 NULL +#define pci_ss_list_100e_9000 NULL +#define pci_ss_list_100e_9001 NULL +#define pci_ss_list_100e_9002 NULL +#define pci_ss_list_100e_9100 NULL +#define pci_ss_list_1011_0001 NULL +#define pci_ss_list_1011_0002 NULL +#define pci_ss_list_1011_0004 NULL +#define pci_ss_list_1011_0007 NULL +#define pci_ss_list_1011_0008 NULL +static const pciSubsystemInfo *pci_ss_list_1011_0009[] = { + &pci_ss_info_1011_0009_1025_0310, + &pci_ss_info_1011_0009_10b8_2001, + &pci_ss_info_1011_0009_10b8_2002, + &pci_ss_info_1011_0009_10b8_2003, + &pci_ss_info_1011_0009_1109_2400, + &pci_ss_info_1011_0009_1112_2300, + &pci_ss_info_1011_0009_1112_2320, + &pci_ss_info_1011_0009_1112_2340, + &pci_ss_info_1011_0009_1113_1207, + &pci_ss_info_1011_0009_1186_1100, + &pci_ss_info_1011_0009_1186_1112, + &pci_ss_info_1011_0009_1186_1140, + &pci_ss_info_1011_0009_1186_1142, + &pci_ss_info_1011_0009_11f6_0503, + &pci_ss_info_1011_0009_1282_9100, + &pci_ss_info_1011_0009_1385_1100, + &pci_ss_info_1011_0009_2646_0001, + NULL +}; +#define pci_ss_list_1011_000a NULL +#define pci_ss_list_1011_000d NULL +#define pci_ss_list_1011_000f NULL +static const pciSubsystemInfo *pci_ss_list_1011_0014[] = { + &pci_ss_info_1011_0014_1186_0100, + NULL +}; +#define pci_ss_list_1011_0016 NULL +static const pciSubsystemInfo *pci_ss_list_1011_0019[] = { + &pci_ss_info_1011_0019_1011_500a, + &pci_ss_info_1011_0019_1011_500b, + &pci_ss_info_1011_0019_1014_0001, + &pci_ss_info_1011_0019_1025_0315, + &pci_ss_info_1011_0019_1033_800c, + &pci_ss_info_1011_0019_1033_800d, + &pci_ss_info_1011_0019_108d_0016, + &pci_ss_info_1011_0019_108d_0017, + &pci_ss_info_1011_0019_10b8_2005, + &pci_ss_info_1011_0019_10b8_8034, + &pci_ss_info_1011_0019_10ef_8169, + &pci_ss_info_1011_0019_1109_2a00, + &pci_ss_info_1011_0019_1109_2b00, + &pci_ss_info_1011_0019_1109_3000, + &pci_ss_info_1011_0019_1113_1207, + &pci_ss_info_1011_0019_1113_2220, + &pci_ss_info_1011_0019_115d_0002, + &pci_ss_info_1011_0019_1179_0203, + &pci_ss_info_1011_0019_1179_0204, + &pci_ss_info_1011_0019_1186_1100, + &pci_ss_info_1011_0019_1186_1101, + &pci_ss_info_1011_0019_1186_1102, + &pci_ss_info_1011_0019_1259_2800, + &pci_ss_info_1011_0019_1266_0004, + &pci_ss_info_1011_0019_12af_0019, + &pci_ss_info_1011_0019_1374_0001, + &pci_ss_info_1011_0019_1374_0002, + &pci_ss_info_1011_0019_1374_0007, + &pci_ss_info_1011_0019_1374_0008, + &pci_ss_info_1011_0019_1385_2100, + &pci_ss_info_1011_0019_1395_0001, + &pci_ss_info_1011_0019_13d1_ab01, + &pci_ss_info_1011_0019_8086_0001, + NULL +}; +#define pci_ss_list_1011_001a NULL +#define pci_ss_list_1011_0021 NULL +#define pci_ss_list_1011_0022 NULL +#define pci_ss_list_1011_0023 NULL +#define pci_ss_list_1011_0024 NULL +#define pci_ss_list_1011_0025 NULL +#define pci_ss_list_1011_0026 NULL +static const pciSubsystemInfo *pci_ss_list_1011_0034[] = { + &pci_ss_info_1011_0034_1374_0003, + NULL +}; +#define pci_ss_list_1011_0045 NULL +static const pciSubsystemInfo *pci_ss_list_1011_0046[] = { + &pci_ss_info_1011_0046_0e11_4050, + &pci_ss_info_1011_0046_0e11_4051, + &pci_ss_info_1011_0046_0e11_4058, + &pci_ss_info_1011_0046_103c_10c2, + &pci_ss_info_1011_0046_12d9_000a, + &pci_ss_info_1011_0046_9005_0365, + &pci_ss_info_1011_0046_9005_1364, + &pci_ss_info_1011_0046_9005_1365, + &pci_ss_info_1011_0046_e4bf_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1011_1065[] = { + &pci_ss_info_1011_1065_1069_0020, + NULL +}; +#define pci_ss_list_1013_0038 NULL +#define pci_ss_list_1013_0040 NULL +#define pci_ss_list_1013_004c NULL +#define pci_ss_list_1013_00a0 NULL +#define pci_ss_list_1013_00a2 NULL +#define pci_ss_list_1013_00a4 NULL +#define pci_ss_list_1013_00a8 NULL +#define pci_ss_list_1013_00ac NULL +#define pci_ss_list_1013_00b0 NULL +#define pci_ss_list_1013_00b8 NULL +static const pciSubsystemInfo *pci_ss_list_1013_00bc[] = { + &pci_ss_info_1013_00bc_1013_00bc, + NULL +}; +#define pci_ss_list_1013_00d0 NULL +#define pci_ss_list_1013_00d2 NULL +#define pci_ss_list_1013_00d4 NULL +#define pci_ss_list_1013_00d5 NULL +static const pciSubsystemInfo *pci_ss_list_1013_00d6[] = { + &pci_ss_info_1013_00d6_13ce_8031, + &pci_ss_info_1013_00d6_13cf_8031, + NULL +}; +#define pci_ss_list_1013_00e8 NULL +#define pci_ss_list_1013_1100 NULL +#define pci_ss_list_1013_1110 NULL +#define pci_ss_list_1013_1112 NULL +#define pci_ss_list_1013_1113 NULL +#define pci_ss_list_1013_1200 NULL +#define pci_ss_list_1013_1202 NULL +#define pci_ss_list_1013_1204 NULL +#define pci_ss_list_1013_4400 NULL +static const pciSubsystemInfo *pci_ss_list_1013_6001[] = { + &pci_ss_info_1013_6001_1014_1010, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1013_6003[] = { + &pci_ss_info_1013_6003_1013_4280, + &pci_ss_info_1013_6003_1681_0050, + &pci_ss_info_1013_6003_1681_a011, + NULL +}; +#define pci_ss_list_1013_6004 NULL +static const pciSubsystemInfo *pci_ss_list_1013_6005[] = { + &pci_ss_info_1013_6005_1013_4281, + &pci_ss_info_1013_6005_10cf_10a8, + &pci_ss_info_1013_6005_10cf_10a9, + &pci_ss_info_1013_6005_10cf_10aa, + &pci_ss_info_1013_6005_10cf_10ab, + &pci_ss_info_1013_6005_10cf_10ac, + &pci_ss_info_1013_6005_10cf_10ad, + &pci_ss_info_1013_6005_10cf_10b4, + &pci_ss_info_1013_6005_1179_0001, + &pci_ss_info_1013_6005_14c0_000c, + NULL +}; +#define pci_ss_list_1014_0002 NULL +#define pci_ss_list_1014_0005 NULL +#define pci_ss_list_1014_0007 NULL +#define pci_ss_list_1014_000a NULL +#define pci_ss_list_1014_0017 NULL +#define pci_ss_list_1014_0018 NULL +#define pci_ss_list_1014_001b NULL +#define pci_ss_list_1014_001c NULL +#define pci_ss_list_1014_001d NULL +#define pci_ss_list_1014_0020 NULL +#define pci_ss_list_1014_0022 NULL +#define pci_ss_list_1014_002d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1014_002e[] = { + &pci_ss_info_1014_002e_1014_002e, + &pci_ss_info_1014_002e_1014_022e, + NULL +}; +#define pci_ss_list_1014_0036 NULL +#define pci_ss_list_1014_003a NULL +static const pciSubsystemInfo *pci_ss_list_1014_003e[] = { + &pci_ss_info_1014_003e_1014_003e, + &pci_ss_info_1014_003e_1014_00cd, + &pci_ss_info_1014_003e_1014_00ce, + &pci_ss_info_1014_003e_1014_00cf, + &pci_ss_info_1014_003e_1014_00e4, + &pci_ss_info_1014_003e_1014_00e5, + &pci_ss_info_1014_003e_1014_016d, + NULL +}; +#define pci_ss_list_1014_0045 NULL +#define pci_ss_list_1014_0046 NULL +#define pci_ss_list_1014_0047 NULL +#define pci_ss_list_1014_0048 NULL +#define pci_ss_list_1014_0049 NULL +#define pci_ss_list_1014_004e NULL +#define pci_ss_list_1014_004f NULL +#define pci_ss_list_1014_0050 NULL +#define pci_ss_list_1014_0053 NULL +#define pci_ss_list_1014_0057 NULL +#define pci_ss_list_1014_005c NULL +#define pci_ss_list_1014_007c NULL +#define pci_ss_list_1014_007d NULL +static const pciSubsystemInfo *pci_ss_list_1014_0090[] = { + &pci_ss_info_1014_0090_1014_008e, + NULL +}; +#define pci_ss_list_1014_0095 NULL +static const pciSubsystemInfo *pci_ss_list_1014_0096[] = { + &pci_ss_info_1014_0096_1014_0097, + &pci_ss_info_1014_0096_1014_0098, + &pci_ss_info_1014_0096_1014_0099, + NULL +}; +#define pci_ss_list_1014_00a5 NULL +#define pci_ss_list_1014_00a6 NULL +#define pci_ss_list_1014_00b7 NULL +#define pci_ss_list_1014_00be NULL +#define pci_ss_list_1014_00dc NULL +#define pci_ss_list_1014_00fc NULL +#define pci_ss_list_1014_0105 NULL +#define pci_ss_list_1014_010f NULL +static const pciSubsystemInfo *pci_ss_list_1014_0142[] = { + &pci_ss_info_1014_0142_1014_0143, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1014_0144[] = { + &pci_ss_info_1014_0144_1014_0145, + NULL +}; +#define pci_ss_list_1014_0156 NULL +#define pci_ss_list_1014_01a7 NULL +static const pciSubsystemInfo *pci_ss_list_1014_01bd[] = { + &pci_ss_info_1014_01bd_1014_01be, + &pci_ss_info_1014_01bd_1014_01bf, + &pci_ss_info_1014_01bd_1014_0208, + &pci_ss_info_1014_01bd_1014_020e, + &pci_ss_info_1014_01bd_1014_022e, + &pci_ss_info_1014_01bd_1014_0258, + &pci_ss_info_1014_01bd_1014_0259, + NULL +}; +#define pci_ss_list_1014_0302 NULL +#define pci_ss_list_1014_ffff NULL +#endif +#define pci_ss_list_1017_5343 NULL +#define pci_ss_list_101a_0005 NULL +#define pci_ss_list_101c_0193 NULL +#define pci_ss_list_101c_0196 NULL +#define pci_ss_list_101c_0197 NULL +#define pci_ss_list_101c_0296 NULL +#define pci_ss_list_101c_3193 NULL +#define pci_ss_list_101c_3197 NULL +#define pci_ss_list_101c_3296 NULL +#define pci_ss_list_101c_4296 NULL +#define pci_ss_list_101c_9710 NULL +#define pci_ss_list_101c_9712 NULL +#define pci_ss_list_101c_c24a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_101e_1960[] = { + &pci_ss_info_101e_1960_101e_0471, + &pci_ss_info_101e_1960_101e_0475, + &pci_ss_info_101e_1960_101e_0493, + &pci_ss_info_101e_1960_1028_0471, + &pci_ss_info_101e_1960_1028_0475, + &pci_ss_info_101e_1960_1028_0493, + &pci_ss_info_101e_1960_1028_0511, + NULL +}; +#define pci_ss_list_101e_9010 NULL +#define pci_ss_list_101e_9030 NULL +#define pci_ss_list_101e_9031 NULL +#define pci_ss_list_101e_9032 NULL +#define pci_ss_list_101e_9033 NULL +#define pci_ss_list_101e_9040 NULL +#define pci_ss_list_101e_9060 NULL +static const pciSubsystemInfo *pci_ss_list_101e_9063[] = { + &pci_ss_info_101e_9063_101e_0767, + NULL +}; +#endif +#define pci_ss_list_1022_1100 NULL +#define pci_ss_list_1022_1101 NULL +#define pci_ss_list_1022_1102 NULL +#define pci_ss_list_1022_1103 NULL +static const pciSubsystemInfo *pci_ss_list_1022_2000[] = { + &pci_ss_info_1022_2000_1014_2000, + &pci_ss_info_1022_2000_103c_104c, + &pci_ss_info_1022_2000_103c_1064, + &pci_ss_info_1022_2000_103c_1065, + &pci_ss_info_1022_2000_103c_106c, + &pci_ss_info_1022_2000_103c_106e, + &pci_ss_info_1022_2000_103c_10ea, + &pci_ss_info_1022_2000_1113_1220, + &pci_ss_info_1022_2000_1259_2450, + &pci_ss_info_1022_2000_1259_2454, + &pci_ss_info_1022_2000_1259_2700, + &pci_ss_info_1022_2000_1259_2701, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1022_2001[] = { + &pci_ss_info_1022_2001_1092_0a78, + &pci_ss_info_1022_2001_1668_0299, + NULL +}; +#define pci_ss_list_1022_2020 NULL +#define pci_ss_list_1022_2040 NULL +#define pci_ss_list_1022_3000 NULL +#define pci_ss_list_1022_7006 NULL +#define pci_ss_list_1022_7007 NULL +#define pci_ss_list_1022_700c NULL +#define pci_ss_list_1022_700d NULL +#define pci_ss_list_1022_700e NULL +#define pci_ss_list_1022_700f NULL +#define pci_ss_list_1022_7400 NULL +#define pci_ss_list_1022_7401 NULL +#define pci_ss_list_1022_7403 NULL +#define pci_ss_list_1022_7404 NULL +#define pci_ss_list_1022_7408 NULL +#define pci_ss_list_1022_7409 NULL +#define pci_ss_list_1022_740b NULL +#define pci_ss_list_1022_740c NULL +#define pci_ss_list_1022_7410 NULL +#define pci_ss_list_1022_7411 NULL +#define pci_ss_list_1022_7413 NULL +#define pci_ss_list_1022_7414 NULL +static const pciSubsystemInfo *pci_ss_list_1022_7440[] = { + &pci_ss_info_1022_7440_1043_8044, + NULL +}; +#define pci_ss_list_1022_7441 NULL +static const pciSubsystemInfo *pci_ss_list_1022_7443[] = { + &pci_ss_info_1022_7443_1043_8044, + NULL +}; +#define pci_ss_list_1022_7445 NULL +#define pci_ss_list_1022_7446 NULL +#define pci_ss_list_1022_7448 NULL +#define pci_ss_list_1022_7449 NULL +#define pci_ss_list_1022_7450 NULL +#define pci_ss_list_1022_7451 NULL +#define pci_ss_list_1022_7454 NULL +#define pci_ss_list_1022_7455 NULL +#define pci_ss_list_1022_7460 NULL +#define pci_ss_list_1022_7461 NULL +#define pci_ss_list_1022_7462 NULL +#define pci_ss_list_1022_7464 NULL +#define pci_ss_list_1022_7468 NULL +#define pci_ss_list_1022_7469 NULL +#define pci_ss_list_1022_746a NULL +#define pci_ss_list_1022_746b NULL +#define pci_ss_list_1022_746d NULL +#define pci_ss_list_1022_746e NULL +#define pci_ss_list_1023_0194 NULL +#define pci_ss_list_1023_2000 NULL +#define pci_ss_list_1023_2001 NULL +static const pciSubsystemInfo *pci_ss_list_1023_8400[] = { + &pci_ss_info_1023_8400_1023_8400, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1023_8420[] = { + &pci_ss_info_1023_8420_0e11_b15a, + NULL +}; +#define pci_ss_list_1023_8500 NULL +static const pciSubsystemInfo *pci_ss_list_1023_8520[] = { + &pci_ss_info_1023_8520_0e11_b16e, + &pci_ss_info_1023_8520_1023_8520, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1023_8620[] = { + &pci_ss_info_1023_8620_1014_0502, + NULL +}; +#define pci_ss_list_1023_8820 NULL +#define pci_ss_list_1023_9320 NULL +#define pci_ss_list_1023_9350 NULL +#define pci_ss_list_1023_9360 NULL +#define pci_ss_list_1023_9382 NULL +#define pci_ss_list_1023_9383 NULL +#define pci_ss_list_1023_9385 NULL +#define pci_ss_list_1023_9386 NULL +#define pci_ss_list_1023_9388 NULL +#define pci_ss_list_1023_9397 NULL +#define pci_ss_list_1023_939a NULL +#define pci_ss_list_1023_9420 NULL +#define pci_ss_list_1023_9430 NULL +#define pci_ss_list_1023_9440 NULL +#define pci_ss_list_1023_9460 NULL +#define pci_ss_list_1023_9470 NULL +#define pci_ss_list_1023_9520 NULL +static const pciSubsystemInfo *pci_ss_list_1023_9525[] = { + &pci_ss_info_1023_9525_10cf_1094, + NULL +}; +#define pci_ss_list_1023_9540 NULL +#define pci_ss_list_1023_9660 NULL +#define pci_ss_list_1023_9680 NULL +#define pci_ss_list_1023_9682 NULL +#define pci_ss_list_1023_9683 NULL +#define pci_ss_list_1023_9685 NULL +static const pciSubsystemInfo *pci_ss_list_1023_9750[] = { + &pci_ss_info_1023_9750_1014_9750, + &pci_ss_info_1023_9750_1023_9750, + NULL +}; +#define pci_ss_list_1023_9753 NULL +#define pci_ss_list_1023_9754 NULL +#define pci_ss_list_1023_9759 NULL +#define pci_ss_list_1023_9783 NULL +#define pci_ss_list_1023_9785 NULL +#define pci_ss_list_1023_9850 NULL +static const pciSubsystemInfo *pci_ss_list_1023_9880[] = { + &pci_ss_info_1023_9880_1023_9880, + NULL +}; +#define pci_ss_list_1023_9910 NULL +#define pci_ss_list_1023_9930 NULL +#define pci_ss_list_1025_1435 NULL +#define pci_ss_list_1025_1445 NULL +#define pci_ss_list_1025_1449 NULL +#define pci_ss_list_1025_1451 NULL +#define pci_ss_list_1025_1461 NULL +#define pci_ss_list_1025_1489 NULL +#define pci_ss_list_1025_1511 NULL +#define pci_ss_list_1025_1512 NULL +#define pci_ss_list_1025_1513 NULL +static const pciSubsystemInfo *pci_ss_list_1025_1521[] = { + &pci_ss_info_1025_1521_10b9_1521, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1025_1523[] = { + &pci_ss_info_1025_1523_10b9_1523, + NULL +}; +#define pci_ss_list_1025_1531 NULL +static const pciSubsystemInfo *pci_ss_list_1025_1533[] = { + &pci_ss_info_1025_1533_10b9_1533, + NULL +}; +#define pci_ss_list_1025_1535 NULL +static const pciSubsystemInfo *pci_ss_list_1025_1541[] = { + &pci_ss_info_1025_1541_10b9_1541, + NULL +}; +#define pci_ss_list_1025_1542 NULL +#define pci_ss_list_1025_1543 NULL +#define pci_ss_list_1025_1561 NULL +#define pci_ss_list_1025_1621 NULL +#define pci_ss_list_1025_1631 NULL +#define pci_ss_list_1025_1641 NULL +#define pci_ss_list_1025_1647 NULL +#define pci_ss_list_1025_3141 NULL +#define pci_ss_list_1025_3143 NULL +#define pci_ss_list_1025_3145 NULL +#define pci_ss_list_1025_3147 NULL +#define pci_ss_list_1025_3149 NULL +#define pci_ss_list_1025_3151 NULL +#define pci_ss_list_1025_3307 NULL +#define pci_ss_list_1025_3309 NULL +#define pci_ss_list_1025_3321 NULL +#define pci_ss_list_1025_5212 NULL +#define pci_ss_list_1025_5215 NULL +#define pci_ss_list_1025_5217 NULL +#define pci_ss_list_1025_5219 NULL +#define pci_ss_list_1025_5225 NULL +#define pci_ss_list_1025_5229 NULL +#define pci_ss_list_1025_5235 NULL +#define pci_ss_list_1025_5237 NULL +#define pci_ss_list_1025_5240 NULL +#define pci_ss_list_1025_5241 NULL +#define pci_ss_list_1025_5242 NULL +#define pci_ss_list_1025_5243 NULL +#define pci_ss_list_1025_5244 NULL +#define pci_ss_list_1025_5247 NULL +#define pci_ss_list_1025_5251 NULL +#define pci_ss_list_1025_5427 NULL +#define pci_ss_list_1025_5451 NULL +#define pci_ss_list_1025_5453 NULL +static const pciSubsystemInfo *pci_ss_list_1025_7101[] = { + &pci_ss_info_1025_7101_10b9_7101, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1028_0001[] = { + &pci_ss_info_1028_0001_1028_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1028_0002[] = { + &pci_ss_info_1028_0002_1028_0002, + &pci_ss_info_1028_0002_1028_00d1, + &pci_ss_info_1028_0002_1028_00d9, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1028_0003[] = { + &pci_ss_info_1028_0003_1028_0003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1028_0004[] = { + &pci_ss_info_1028_0004_1028_00d0, + NULL +}; +#define pci_ss_list_1028_0005 NULL +#define pci_ss_list_1028_0006 NULL +#define pci_ss_list_1028_0007 NULL +#define pci_ss_list_1028_0008 NULL +static const pciSubsystemInfo *pci_ss_list_1028_000a[] = { + &pci_ss_info_1028_000a_1028_0106, + &pci_ss_info_1028_000a_1028_011b, + &pci_ss_info_1028_000a_1028_0121, + NULL +}; +#define pci_ss_list_1028_000c NULL +#define pci_ss_list_1028_000e NULL +#define pci_ss_list_1028_000f NULL +#define pci_ss_list_102a_0000 NULL +#define pci_ss_list_102a_0010 NULL +#define pci_ss_list_102b_0010 NULL +#define pci_ss_list_102b_0518 NULL +#define pci_ss_list_102b_0519 NULL +static const pciSubsystemInfo *pci_ss_list_102b_051a[] = { + &pci_ss_info_102b_051a_102b_0100, + &pci_ss_info_102b_051a_102b_1100, + &pci_ss_info_102b_051a_102b_1200, + &pci_ss_info_102b_051a_1100_102b, + &pci_ss_info_102b_051a_110a_0018, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_051b[] = { + &pci_ss_info_102b_051b_102b_051b, + &pci_ss_info_102b_051b_102b_1100, + &pci_ss_info_102b_051b_102b_1200, + NULL +}; +#define pci_ss_list_102b_051e NULL +#define pci_ss_list_102b_051f NULL +static const pciSubsystemInfo *pci_ss_list_102b_0520[] = { + &pci_ss_info_102b_0520_102b_dbc2, + &pci_ss_info_102b_0520_102b_dbc8, + &pci_ss_info_102b_0520_102b_dbe2, + &pci_ss_info_102b_0520_102b_dbe8, + &pci_ss_info_102b_0520_102b_ff03, + &pci_ss_info_102b_0520_102b_ff04, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_0521[] = { + &pci_ss_info_102b_0521_1014_ff03, + &pci_ss_info_102b_0521_102b_48e9, + &pci_ss_info_102b_0521_102b_48f8, + &pci_ss_info_102b_0521_102b_4a60, + &pci_ss_info_102b_0521_102b_4a64, + &pci_ss_info_102b_0521_102b_c93c, + &pci_ss_info_102b_0521_102b_c9b0, + &pci_ss_info_102b_0521_102b_c9bc, + &pci_ss_info_102b_0521_102b_ca60, + &pci_ss_info_102b_0521_102b_ca6c, + &pci_ss_info_102b_0521_102b_dbbc, + &pci_ss_info_102b_0521_102b_dbc2, + &pci_ss_info_102b_0521_102b_dbc3, + &pci_ss_info_102b_0521_102b_dbc8, + &pci_ss_info_102b_0521_102b_dbd2, + &pci_ss_info_102b_0521_102b_dbd3, + &pci_ss_info_102b_0521_102b_dbd4, + &pci_ss_info_102b_0521_102b_dbd5, + &pci_ss_info_102b_0521_102b_dbd8, + &pci_ss_info_102b_0521_102b_dbd9, + &pci_ss_info_102b_0521_102b_dbe2, + &pci_ss_info_102b_0521_102b_dbe3, + &pci_ss_info_102b_0521_102b_dbe8, + &pci_ss_info_102b_0521_102b_dbf2, + &pci_ss_info_102b_0521_102b_dbf3, + &pci_ss_info_102b_0521_102b_dbf4, + &pci_ss_info_102b_0521_102b_dbf5, + &pci_ss_info_102b_0521_102b_dbf8, + &pci_ss_info_102b_0521_102b_dbf9, + &pci_ss_info_102b_0521_102b_f806, + &pci_ss_info_102b_0521_102b_ff00, + &pci_ss_info_102b_0521_102b_ff02, + &pci_ss_info_102b_0521_102b_ff03, + &pci_ss_info_102b_0521_102b_ff04, + &pci_ss_info_102b_0521_110a_0032, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_0525[] = { + &pci_ss_info_102b_0525_0e11_b16f, + &pci_ss_info_102b_0525_102b_0328, + &pci_ss_info_102b_0525_102b_0338, + &pci_ss_info_102b_0525_102b_0378, + &pci_ss_info_102b_0525_102b_0541, + &pci_ss_info_102b_0525_102b_0542, + &pci_ss_info_102b_0525_102b_0543, + &pci_ss_info_102b_0525_102b_0641, + &pci_ss_info_102b_0525_102b_0642, + &pci_ss_info_102b_0525_102b_0643, + &pci_ss_info_102b_0525_102b_07c0, + &pci_ss_info_102b_0525_102b_07c1, + &pci_ss_info_102b_0525_102b_0d41, + &pci_ss_info_102b_0525_102b_0d42, + &pci_ss_info_102b_0525_102b_0e00, + &pci_ss_info_102b_0525_102b_0e01, + &pci_ss_info_102b_0525_102b_0e02, + &pci_ss_info_102b_0525_102b_0e03, + &pci_ss_info_102b_0525_102b_0f80, + &pci_ss_info_102b_0525_102b_0f81, + &pci_ss_info_102b_0525_102b_0f82, + &pci_ss_info_102b_0525_102b_0f83, + &pci_ss_info_102b_0525_102b_19d8, + &pci_ss_info_102b_0525_102b_19f8, + &pci_ss_info_102b_0525_102b_2159, + &pci_ss_info_102b_0525_102b_2179, + &pci_ss_info_102b_0525_102b_217d, + &pci_ss_info_102b_0525_102b_23c0, + &pci_ss_info_102b_0525_102b_23c1, + &pci_ss_info_102b_0525_102b_23c2, + &pci_ss_info_102b_0525_102b_23c3, + &pci_ss_info_102b_0525_102b_2f58, + &pci_ss_info_102b_0525_102b_2f78, + &pci_ss_info_102b_0525_102b_3693, + &pci_ss_info_102b_0525_102b_5dd0, + &pci_ss_info_102b_0525_102b_5f50, + &pci_ss_info_102b_0525_102b_5f51, + &pci_ss_info_102b_0525_102b_5f52, + &pci_ss_info_102b_0525_102b_9010, + &pci_ss_info_102b_0525_1458_0400, + &pci_ss_info_102b_0525_1705_0001, + &pci_ss_info_102b_0525_1705_0002, + &pci_ss_info_102b_0525_1705_0003, + &pci_ss_info_102b_0525_1705_0004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_0527[] = { + &pci_ss_info_102b_0527_102b_0840, + NULL +}; +#define pci_ss_list_102b_0d10 NULL +static const pciSubsystemInfo *pci_ss_list_102b_1000[] = { + &pci_ss_info_102b_1000_102b_ff01, + &pci_ss_info_102b_1000_102b_ff05, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_1001[] = { + &pci_ss_info_102b_1001_102b_1001, + &pci_ss_info_102b_1001_102b_ff00, + &pci_ss_info_102b_1001_102b_ff01, + &pci_ss_info_102b_1001_102b_ff03, + &pci_ss_info_102b_1001_102b_ff04, + &pci_ss_info_102b_1001_102b_ff05, + &pci_ss_info_102b_1001_110a_001e, + NULL +}; +#define pci_ss_list_102b_2007 NULL +static const pciSubsystemInfo *pci_ss_list_102b_2527[] = { + &pci_ss_info_102b_2527_102b_0f83, + &pci_ss_info_102b_2527_102b_0f84, + &pci_ss_info_102b_2527_102b_1e41, + NULL +}; +#define pci_ss_list_102b_4536 NULL +#define pci_ss_list_102b_6573 NULL +#define pci_ss_list_102c_00b8 NULL +static const pciSubsystemInfo *pci_ss_list_102c_00c0[] = { + &pci_ss_info_102c_00c0_102c_00c0, + NULL +}; +#define pci_ss_list_102c_00d0 NULL +#define pci_ss_list_102c_00d8 NULL +#define pci_ss_list_102c_00dc NULL +#define pci_ss_list_102c_00e0 NULL +#define pci_ss_list_102c_00e4 NULL +static const pciSubsystemInfo *pci_ss_list_102c_00e5[] = { + &pci_ss_info_102c_00e5_0e11_b049, + NULL +}; +#define pci_ss_list_102c_00f0 NULL +#define pci_ss_list_102c_00f4 NULL +#define pci_ss_list_102c_00f5 NULL +#define pci_ss_list_102c_0c30 NULL +#define pci_ss_list_102d_50dc NULL +#define pci_ss_list_102f_0009 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_102f_0020[] = { + &pci_ss_info_102f_0020_102f_00f8, + NULL +}; +#endif +#define pci_ss_list_1031_5601 NULL +#define pci_ss_list_1031_5607 NULL +#define pci_ss_list_1031_5631 NULL +#define pci_ss_list_1031_6057 NULL +#define pci_ss_list_1033_0001 NULL +#define pci_ss_list_1033_0002 NULL +#define pci_ss_list_1033_0003 NULL +#define pci_ss_list_1033_0004 NULL +#define pci_ss_list_1033_0005 NULL +#define pci_ss_list_1033_0006 NULL +#define pci_ss_list_1033_0007 NULL +#define pci_ss_list_1033_0008 NULL +#define pci_ss_list_1033_0009 NULL +#define pci_ss_list_1033_0016 NULL +#define pci_ss_list_1033_001a NULL +#define pci_ss_list_1033_0021 NULL +#define pci_ss_list_1033_0029 NULL +#define pci_ss_list_1033_002a NULL +#define pci_ss_list_1033_002c NULL +#define pci_ss_list_1033_002d NULL +static const pciSubsystemInfo *pci_ss_list_1033_0035[] = { + &pci_ss_info_1033_0035_1179_0001, + &pci_ss_info_1033_0035_12ee_7000, + &pci_ss_info_1033_0035_1799_0001, + NULL +}; +#define pci_ss_list_1033_003b NULL +#define pci_ss_list_1033_003e NULL +#define pci_ss_list_1033_0046 NULL +#define pci_ss_list_1033_005a NULL +#define pci_ss_list_1033_0063 NULL +static const pciSubsystemInfo *pci_ss_list_1033_0067[] = { + &pci_ss_info_1033_0067_1010_0020, + &pci_ss_info_1033_0067_1010_0080, + &pci_ss_info_1033_0067_1010_0088, + &pci_ss_info_1033_0067_1010_0090, + &pci_ss_info_1033_0067_1010_0098, + &pci_ss_info_1033_0067_1010_00a0, + &pci_ss_info_1033_0067_1010_00a8, + &pci_ss_info_1033_0067_1010_0120, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1033_0074[] = { + &pci_ss_info_1033_0074_1033_8014, + NULL +}; +#define pci_ss_list_1033_009b NULL +#define pci_ss_list_1033_00a6 NULL +static const pciSubsystemInfo *pci_ss_list_1033_00cd[] = { + &pci_ss_info_1033_00cd_12ee_8011, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1033_00e0[] = { + &pci_ss_info_1033_00e0_12ee_7001, + &pci_ss_info_1033_00e0_1799_0002, + NULL +}; +#define pci_ss_list_1036_0000 NULL +#define pci_ss_list_1039_0001 NULL +#define pci_ss_list_1039_0002 NULL +#define pci_ss_list_1039_0006 NULL +#define pci_ss_list_1039_0008 NULL +#define pci_ss_list_1039_0009 NULL +#define pci_ss_list_1039_0018 NULL +static const pciSubsystemInfo *pci_ss_list_1039_0200[] = { + &pci_ss_info_1039_0200_1039_0000, + NULL +}; +#define pci_ss_list_1039_0204 NULL +#define pci_ss_list_1039_0205 NULL +static const pciSubsystemInfo *pci_ss_list_1039_0300[] = { + &pci_ss_info_1039_0300_107d_2720, + NULL +}; +#define pci_ss_list_1039_0310 NULL +#define pci_ss_list_1039_0315 NULL +#define pci_ss_list_1039_0325 NULL +#define pci_ss_list_1039_0330 NULL +#define pci_ss_list_1039_0406 NULL +#define pci_ss_list_1039_0496 NULL +#define pci_ss_list_1039_0530 NULL +#define pci_ss_list_1039_0540 NULL +#define pci_ss_list_1039_0597 NULL +#define pci_ss_list_1039_0601 NULL +#define pci_ss_list_1039_0620 NULL +#define pci_ss_list_1039_0630 NULL +#define pci_ss_list_1039_0633 NULL +#define pci_ss_list_1039_0635 NULL +#define pci_ss_list_1039_0645 NULL +#define pci_ss_list_1039_0646 NULL +#define pci_ss_list_1039_0650 NULL +#define pci_ss_list_1039_0651 NULL +#define pci_ss_list_1039_0730 NULL +#define pci_ss_list_1039_0733 NULL +#define pci_ss_list_1039_0735 NULL +#define pci_ss_list_1039_0740 NULL +#define pci_ss_list_1039_0745 NULL +static const pciSubsystemInfo *pci_ss_list_1039_0900[] = { + &pci_ss_info_1039_0900_1039_0900, + NULL +}; +#define pci_ss_list_1039_0961 NULL +#define pci_ss_list_1039_0962 NULL +#define pci_ss_list_1039_3602 NULL +#define pci_ss_list_1039_5107 NULL +#define pci_ss_list_1039_5300 NULL +#define pci_ss_list_1039_5315 NULL +#define pci_ss_list_1039_5401 NULL +#define pci_ss_list_1039_5511 NULL +static const pciSubsystemInfo *pci_ss_list_1039_5513[] = { + &pci_ss_info_1039_5513_1019_0970, + &pci_ss_info_1039_5513_1039_5513, + NULL +}; +#define pci_ss_list_1039_5517 NULL +#define pci_ss_list_1039_5571 NULL +#define pci_ss_list_1039_5581 NULL +#define pci_ss_list_1039_5582 NULL +#define pci_ss_list_1039_5591 NULL +#define pci_ss_list_1039_5596 NULL +#define pci_ss_list_1039_5597 NULL +#define pci_ss_list_1039_5600 NULL +#define pci_ss_list_1039_6204 NULL +#define pci_ss_list_1039_6205 NULL +#define pci_ss_list_1039_6236 NULL +static const pciSubsystemInfo *pci_ss_list_1039_6300[] = { + &pci_ss_info_1039_6300_1019_0970, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_6306[] = { + &pci_ss_info_1039_6306_1039_6306, + NULL +}; +#define pci_ss_list_1039_6325 NULL +static const pciSubsystemInfo *pci_ss_list_1039_6326[] = { + &pci_ss_info_1039_6326_1039_6326, + &pci_ss_info_1039_6326_1092_0a50, + &pci_ss_info_1039_6326_1092_0a70, + &pci_ss_info_1039_6326_1092_4910, + &pci_ss_info_1039_6326_1092_4920, + &pci_ss_info_1039_6326_1569_6326, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_7001[] = { + &pci_ss_info_1039_7001_1039_7000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_7002[] = { + &pci_ss_info_1039_7002_1509_7002, + NULL +}; +#define pci_ss_list_1039_7007 NULL +#define pci_ss_list_1039_7012 NULL +#define pci_ss_list_1039_7013 NULL +static const pciSubsystemInfo *pci_ss_list_1039_7016[] = { + &pci_ss_info_1039_7016_1039_7016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_7018[] = { + &pci_ss_info_1039_7018_1014_01b6, + &pci_ss_info_1039_7018_1014_01b7, + &pci_ss_info_1039_7018_1019_7018, + &pci_ss_info_1039_7018_1025_000e, + &pci_ss_info_1039_7018_1025_0018, + &pci_ss_info_1039_7018_1039_7018, + &pci_ss_info_1039_7018_1043_800b, + &pci_ss_info_1039_7018_1054_7018, + &pci_ss_info_1039_7018_107d_5330, + &pci_ss_info_1039_7018_107d_5350, + &pci_ss_info_1039_7018_1170_3209, + &pci_ss_info_1039_7018_1462_400a, + &pci_ss_info_1039_7018_14a4_2089, + &pci_ss_info_1039_7018_14cd_2194, + &pci_ss_info_1039_7018_14ff_1100, + &pci_ss_info_1039_7018_152d_8808, + &pci_ss_info_1039_7018_1558_1103, + &pci_ss_info_1039_7018_1558_2200, + &pci_ss_info_1039_7018_1563_7018, + &pci_ss_info_1039_7018_15c5_0111, + &pci_ss_info_1039_7018_270f_a171, + &pci_ss_info_1039_7018_a0a0_0022, + NULL +}; +#define pci_ss_list_103c_1005 NULL +#define pci_ss_list_103c_1006 NULL +#define pci_ss_list_103c_1008 NULL +#define pci_ss_list_103c_100a NULL +#define pci_ss_list_103c_1028 NULL +static const pciSubsystemInfo *pci_ss_list_103c_1029[] = { + &pci_ss_info_103c_1029_107e_000f, + &pci_ss_info_103c_1029_9004_9210, + &pci_ss_info_103c_1029_9004_9211, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_103c_102a[] = { + &pci_ss_info_103c_102a_107e_000e, + &pci_ss_info_103c_102a_9004_9110, + &pci_ss_info_103c_102a_9004_9111, + NULL +}; +#define pci_ss_list_103c_1030 NULL +static const pciSubsystemInfo *pci_ss_list_103c_1031[] = { + &pci_ss_info_103c_1031_103c_1040, + &pci_ss_info_103c_1031_103c_1041, + &pci_ss_info_103c_1031_103c_1042, + NULL +}; +#define pci_ss_list_103c_1040 NULL +#define pci_ss_list_103c_1041 NULL +#define pci_ss_list_103c_1042 NULL +static const pciSubsystemInfo *pci_ss_list_103c_1048[] = { + &pci_ss_info_103c_1048_103c_1049, + &pci_ss_info_103c_1048_103c_104a, + &pci_ss_info_103c_1048_103c_104b, + &pci_ss_info_103c_1048_103c_1223, + &pci_ss_info_103c_1048_103c_1226, + &pci_ss_info_103c_1048_103c_1227, + &pci_ss_info_103c_1048_103c_1282, + NULL +}; +#define pci_ss_list_103c_1064 NULL +#define pci_ss_list_103c_108b NULL +#define pci_ss_list_103c_10c1 NULL +#define pci_ss_list_103c_10ed NULL +#define pci_ss_list_103c_1200 NULL +#define pci_ss_list_103c_1219 NULL +#define pci_ss_list_103c_121a NULL +#define pci_ss_list_103c_121b NULL +#define pci_ss_list_103c_121c NULL +#define pci_ss_list_103c_1229 NULL +#define pci_ss_list_103c_122a NULL +#define pci_ss_list_103c_122e NULL +#define pci_ss_list_103c_1290 NULL +#define pci_ss_list_103c_2910 NULL +#define pci_ss_list_103c_2925 NULL +#define pci_ss_list_1042_1000 NULL +#define pci_ss_list_1042_1001 NULL +#define pci_ss_list_1042_3000 NULL +#define pci_ss_list_1042_3010 NULL +#define pci_ss_list_1042_3020 NULL +#define pci_ss_list_1043_0675 NULL +#define pci_ss_list_1043_4021 NULL +#define pci_ss_list_1044_1012 NULL +#define pci_ss_list_1044_a400 NULL +#define pci_ss_list_1044_a500 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1044_a501[] = { + &pci_ss_info_1044_a501_1044_c001, + &pci_ss_info_1044_a501_1044_c002, + &pci_ss_info_1044_a501_1044_c003, + &pci_ss_info_1044_a501_1044_c004, + &pci_ss_info_1044_a501_1044_c005, + &pci_ss_info_1044_a501_1044_c00a, + &pci_ss_info_1044_a501_1044_c00b, + &pci_ss_info_1044_a501_1044_c00c, + &pci_ss_info_1044_a501_1044_c00d, + &pci_ss_info_1044_a501_1044_c00e, + &pci_ss_info_1044_a501_1044_c00f, + &pci_ss_info_1044_a501_1044_c014, + &pci_ss_info_1044_a501_1044_c015, + &pci_ss_info_1044_a501_1044_c016, + &pci_ss_info_1044_a501_1044_c01e, + &pci_ss_info_1044_a501_1044_c01f, + &pci_ss_info_1044_a501_1044_c020, + &pci_ss_info_1044_a501_1044_c021, + &pci_ss_info_1044_a501_1044_c028, + &pci_ss_info_1044_a501_1044_c029, + &pci_ss_info_1044_a501_1044_c02a, + &pci_ss_info_1044_a501_1044_c03c, + &pci_ss_info_1044_a501_1044_c03d, + &pci_ss_info_1044_a501_1044_c03e, + &pci_ss_info_1044_a501_1044_c046, + &pci_ss_info_1044_a501_1044_c047, + &pci_ss_info_1044_a501_1044_c048, + &pci_ss_info_1044_a501_1044_c050, + &pci_ss_info_1044_a501_1044_c051, + &pci_ss_info_1044_a501_1044_c052, + &pci_ss_info_1044_a501_1044_c05a, + &pci_ss_info_1044_a501_1044_c05b, + &pci_ss_info_1044_a501_1044_c064, + &pci_ss_info_1044_a501_1044_c065, + &pci_ss_info_1044_a501_1044_c066, + NULL +}; +#define pci_ss_list_1044_a511 NULL +#endif +#define pci_ss_list_1045_a0f8 NULL +#define pci_ss_list_1045_c101 NULL +#define pci_ss_list_1045_c178 NULL +#define pci_ss_list_1045_c556 NULL +#define pci_ss_list_1045_c557 NULL +#define pci_ss_list_1045_c558 NULL +#define pci_ss_list_1045_c567 NULL +#define pci_ss_list_1045_c568 NULL +#define pci_ss_list_1045_c569 NULL +#define pci_ss_list_1045_c621 NULL +#define pci_ss_list_1045_c700 NULL +#define pci_ss_list_1045_c701 NULL +#define pci_ss_list_1045_c814 NULL +#define pci_ss_list_1045_c822 NULL +#define pci_ss_list_1045_c824 NULL +#define pci_ss_list_1045_c825 NULL +#define pci_ss_list_1045_c832 NULL +#define pci_ss_list_1045_c861 NULL +#define pci_ss_list_1045_c895 NULL +#define pci_ss_list_1045_c935 NULL +#define pci_ss_list_1045_d568 NULL +#define pci_ss_list_1045_d721 NULL +#define pci_ss_list_1048_0d22 NULL +#define pci_ss_list_1048_1000 NULL +#define pci_ss_list_1048_3000 NULL +#define pci_ss_list_104a_0008 NULL +#define pci_ss_list_104a_0009 NULL +#define pci_ss_list_104a_0010 NULL +#define pci_ss_list_104a_0210 NULL +#define pci_ss_list_104a_0981 NULL +#define pci_ss_list_104a_1746 NULL +#define pci_ss_list_104a_2774 NULL +#define pci_ss_list_104a_3520 NULL +#define pci_ss_list_104b_0140 NULL +#define pci_ss_list_104b_1040 NULL +#define pci_ss_list_104b_8130 NULL +#define pci_ss_list_104c_0500 NULL +#define pci_ss_list_104c_0508 NULL +#define pci_ss_list_104c_1000 NULL +#define pci_ss_list_104c_104c NULL +#define pci_ss_list_104c_3d04 NULL +static const pciSubsystemInfo *pci_ss_list_104c_3d07[] = { + &pci_ss_info_104c_3d07_1011_4d10, + &pci_ss_info_104c_3d07_1040_000f, + &pci_ss_info_104c_3d07_1040_0011, + &pci_ss_info_104c_3d07_1048_0a31, + &pci_ss_info_104c_3d07_1048_0a32, + &pci_ss_info_104c_3d07_1048_0a35, + &pci_ss_info_104c_3d07_107d_2633, + &pci_ss_info_104c_3d07_1092_0127, + &pci_ss_info_104c_3d07_1092_0136, + &pci_ss_info_104c_3d07_1092_0141, + &pci_ss_info_104c_3d07_1092_0146, + &pci_ss_info_104c_3d07_1092_0148, + &pci_ss_info_104c_3d07_1092_0149, + &pci_ss_info_104c_3d07_1092_0152, + &pci_ss_info_104c_3d07_1092_0154, + &pci_ss_info_104c_3d07_1092_0155, + &pci_ss_info_104c_3d07_1092_0156, + &pci_ss_info_104c_3d07_1092_0157, + &pci_ss_info_104c_3d07_1097_3d01, + &pci_ss_info_104c_3d07_1102_100f, + &pci_ss_info_104c_3d07_3d3d_0100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8000[] = { + &pci_ss_info_104c_8000_e4bf_1010, + &pci_ss_info_104c_8000_e4bf_1020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8009[] = { + &pci_ss_info_104c_8009_104d_8032, + NULL +}; +#define pci_ss_list_104c_8017 NULL +static const pciSubsystemInfo *pci_ss_list_104c_8019[] = { + &pci_ss_info_104c_8019_11bd_000a, + &pci_ss_info_104c_8019_11bd_000e, + &pci_ss_info_104c_8019_e4bf_1010, + NULL +}; +#define pci_ss_list_104c_8020 NULL +static const pciSubsystemInfo *pci_ss_list_104c_8021[] = { + &pci_ss_info_104c_8021_104d_80df, + &pci_ss_info_104c_8021_104d_80e7, + NULL +}; +#define pci_ss_list_104c_8022 NULL +#define pci_ss_list_104c_8023 NULL +#define pci_ss_list_104c_8024 NULL +#define pci_ss_list_104c_8026 NULL +static const pciSubsystemInfo *pci_ss_list_104c_8027[] = { + &pci_ss_info_104c_8027_1028_00e6, + NULL +}; +#define pci_ss_list_104c_8400 NULL +#define pci_ss_list_104c_a001 NULL +#define pci_ss_list_104c_a100 NULL +#define pci_ss_list_104c_a102 NULL +#define pci_ss_list_104c_a106 NULL +#define pci_ss_list_104c_ac10 NULL +#define pci_ss_list_104c_ac11 NULL +#define pci_ss_list_104c_ac12 NULL +#define pci_ss_list_104c_ac13 NULL +#define pci_ss_list_104c_ac15 NULL +#define pci_ss_list_104c_ac16 NULL +#define pci_ss_list_104c_ac17 NULL +#define pci_ss_list_104c_ac18 NULL +#define pci_ss_list_104c_ac19 NULL +#define pci_ss_list_104c_ac1a NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac1b[] = { + &pci_ss_info_104c_ac1b_0e11_b113, + NULL +}; +#define pci_ss_list_104c_ac1c NULL +#define pci_ss_list_104c_ac1d NULL +#define pci_ss_list_104c_ac1e NULL +#define pci_ss_list_104c_ac1f NULL +#define pci_ss_list_104c_ac20 NULL +#define pci_ss_list_104c_ac21 NULL +#define pci_ss_list_104c_ac22 NULL +#define pci_ss_list_104c_ac23 NULL +#define pci_ss_list_104c_ac28 NULL +#define pci_ss_list_104c_ac30 NULL +#define pci_ss_list_104c_ac40 NULL +#define pci_ss_list_104c_ac41 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac42[] = { + &pci_ss_info_104c_ac42_1028_00e6, + NULL +}; +#define pci_ss_list_104c_ac50 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac51[] = { + &pci_ss_info_104c_ac51_1014_023b, + &pci_ss_info_104c_ac51_10cf_1095, + &pci_ss_info_104c_ac51_e4bf_1000, + NULL +}; +#define pci_ss_list_104c_ac52 NULL +#define pci_ss_list_104c_ac53 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac55[] = { + &pci_ss_info_104c_ac55_1014_0512, + NULL +}; +#define pci_ss_list_104c_ac56 NULL +#define pci_ss_list_104c_ac60 NULL +#define pci_ss_list_104c_fe00 NULL +#define pci_ss_list_104c_fe03 NULL +#define pci_ss_list_104d_8009 NULL +#define pci_ss_list_104d_8039 NULL +#define pci_ss_list_104d_8056 NULL +#define pci_ss_list_104d_808a NULL +#define pci_ss_list_104e_0017 NULL +#define pci_ss_list_104e_0107 NULL +#define pci_ss_list_104e_0109 NULL +#define pci_ss_list_104e_0111 NULL +#define pci_ss_list_104e_0217 NULL +#define pci_ss_list_104e_0317 NULL +#define pci_ss_list_1050_0000 NULL +#define pci_ss_list_1050_0001 NULL +#define pci_ss_list_1050_0105 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1050_0840[] = { + &pci_ss_info_1050_0840_1050_0001, + &pci_ss_info_1050_0840_1050_0840, + NULL +}; +#define pci_ss_list_1050_0940 NULL +#define pci_ss_list_1050_5a5a NULL +#define pci_ss_list_1050_6692 NULL +#define pci_ss_list_1050_9970 NULL +#endif +#define pci_ss_list_1055_9130 NULL +#define pci_ss_list_1055_9460 NULL +#define pci_ss_list_1055_9462 NULL +#define pci_ss_list_1055_9463 NULL +#define pci_ss_list_1057_0001 NULL +#define pci_ss_list_1057_0002 NULL +#define pci_ss_list_1057_0003 NULL +#define pci_ss_list_1057_0004 NULL +#define pci_ss_list_1057_0006 NULL +#define pci_ss_list_1057_0100 NULL +#define pci_ss_list_1057_0431 NULL +static const pciSubsystemInfo *pci_ss_list_1057_1801[] = { + &pci_ss_info_1057_1801_ecc0_0030, + NULL +}; +#define pci_ss_list_1057_18c0 NULL +#define pci_ss_list_1057_4801 NULL +#define pci_ss_list_1057_4802 NULL +#define pci_ss_list_1057_4803 NULL +#define pci_ss_list_1057_4806 NULL +#define pci_ss_list_1057_4d68 NULL +static const pciSubsystemInfo *pci_ss_list_1057_5600[] = { + &pci_ss_info_1057_5600_1057_0300, + &pci_ss_info_1057_5600_1057_0301, + &pci_ss_info_1057_5600_1057_0302, + &pci_ss_info_1057_5600_1057_5600, + &pci_ss_info_1057_5600_13d2_0300, + &pci_ss_info_1057_5600_13d2_0301, + &pci_ss_info_1057_5600_13d2_0302, + &pci_ss_info_1057_5600_1436_0300, + &pci_ss_info_1057_5600_1436_0301, + &pci_ss_info_1057_5600_1436_0302, + &pci_ss_info_1057_5600_144f_100c, + &pci_ss_info_1057_5600_1494_0300, + &pci_ss_info_1057_5600_1494_0301, + &pci_ss_info_1057_5600_14c8_0300, + &pci_ss_info_1057_5600_14c8_0302, + &pci_ss_info_1057_5600_1668_0300, + &pci_ss_info_1057_5600_1668_0302, + NULL +}; +#define pci_ss_list_1057_6400 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_105a_0d30[] = { + &pci_ss_info_105a_0d30_105a_4d33, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_0d38[] = { + &pci_ss_info_105a_0d38_105a_4d39, + NULL +}; +#define pci_ss_list_105a_1275 NULL +#define pci_ss_list_105a_3376 NULL +static const pciSubsystemInfo *pci_ss_list_105a_4d30[] = { + &pci_ss_info_105a_4d30_105a_4d33, + &pci_ss_info_105a_4d30_105a_4d39, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_4d33[] = { + &pci_ss_info_105a_4d33_105a_4d33, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_4d38[] = { + &pci_ss_info_105a_4d38_105a_4d30, + &pci_ss_info_105a_4d38_105a_4d33, + &pci_ss_info_105a_4d38_105a_4d39, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_4d68[] = { + &pci_ss_info_105a_4d68_105a_4d68, + NULL +}; +#define pci_ss_list_105a_4d69 NULL +static const pciSubsystemInfo *pci_ss_list_105a_5275[] = { + &pci_ss_info_105a_5275_105a_0275, + NULL +}; +#define pci_ss_list_105a_5300 NULL +#define pci_ss_list_105a_6268 NULL +static const pciSubsystemInfo *pci_ss_list_105a_6269[] = { + &pci_ss_info_105a_6269_105a_6269, + NULL +}; +#define pci_ss_list_105a_6621 NULL +#define pci_ss_list_105a_7275 NULL +#endif +#define pci_ss_list_105d_2309 NULL +static const pciSubsystemInfo *pci_ss_list_105d_2339[] = { + &pci_ss_info_105d_2339_105d_0000, + &pci_ss_info_105d_2339_105d_0001, + &pci_ss_info_105d_2339_105d_0002, + &pci_ss_info_105d_2339_105d_0003, + &pci_ss_info_105d_2339_105d_0004, + &pci_ss_info_105d_2339_105d_0005, + &pci_ss_info_105d_2339_105d_0006, + &pci_ss_info_105d_2339_105d_0007, + &pci_ss_info_105d_2339_105d_0008, + &pci_ss_info_105d_2339_105d_0009, + &pci_ss_info_105d_2339_105d_000a, + &pci_ss_info_105d_2339_105d_000b, + &pci_ss_info_105d_2339_11a4_000a, + &pci_ss_info_105d_2339_13cc_0000, + &pci_ss_info_105d_2339_13cc_0004, + &pci_ss_info_105d_2339_13cc_0005, + &pci_ss_info_105d_2339_13cc_0006, + &pci_ss_info_105d_2339_13cc_0008, + &pci_ss_info_105d_2339_13cc_0009, + &pci_ss_info_105d_2339_13cc_000a, + &pci_ss_info_105d_2339_13cc_000c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105d_493d[] = { + &pci_ss_info_105d_493d_11a4_000a, + &pci_ss_info_105d_493d_11a4_000b, + &pci_ss_info_105d_493d_13cc_0002, + &pci_ss_info_105d_493d_13cc_0003, + &pci_ss_info_105d_493d_13cc_0007, + &pci_ss_info_105d_493d_13cc_0008, + &pci_ss_info_105d_493d_13cc_0009, + &pci_ss_info_105d_493d_13cc_000a, + NULL +}; +#define pci_ss_list_105d_5348 NULL +#define pci_ss_list_1060_0001 NULL +#define pci_ss_list_1060_0002 NULL +#define pci_ss_list_1060_0101 NULL +#define pci_ss_list_1060_0881 NULL +#define pci_ss_list_1060_0886 NULL +#define pci_ss_list_1060_0891 NULL +#define pci_ss_list_1060_1001 NULL +#define pci_ss_list_1060_673a NULL +#define pci_ss_list_1060_673b NULL +#define pci_ss_list_1060_8710 NULL +#define pci_ss_list_1060_886a NULL +#define pci_ss_list_1060_8881 NULL +#define pci_ss_list_1060_8886 NULL +#define pci_ss_list_1060_888a NULL +#define pci_ss_list_1060_8891 NULL +#define pci_ss_list_1060_9017 NULL +#define pci_ss_list_1060_9018 NULL +#define pci_ss_list_1060_9026 NULL +#define pci_ss_list_1060_e881 NULL +#define pci_ss_list_1060_e886 NULL +#define pci_ss_list_1060_e88a NULL +#define pci_ss_list_1060_e891 NULL +#define pci_ss_list_1061_0001 NULL +#define pci_ss_list_1061_0002 NULL +#define pci_ss_list_1066_0000 NULL +#define pci_ss_list_1066_0001 NULL +#define pci_ss_list_1066_0002 NULL +#define pci_ss_list_1066_0003 NULL +#define pci_ss_list_1066_0004 NULL +#define pci_ss_list_1066_0005 NULL +#define pci_ss_list_1066_8002 NULL +#define pci_ss_list_1067_1002 NULL +#define pci_ss_list_1069_0001 NULL +#define pci_ss_list_1069_0002 NULL +#define pci_ss_list_1069_0010 NULL +#define pci_ss_list_1069_0050 NULL +#define pci_ss_list_1069_ba55 NULL +#define pci_ss_list_1069_ba56 NULL +#define pci_ss_list_106b_0001 NULL +#define pci_ss_list_106b_0002 NULL +#define pci_ss_list_106b_0003 NULL +#define pci_ss_list_106b_0004 NULL +#define pci_ss_list_106b_0007 NULL +#define pci_ss_list_106b_000e NULL +#define pci_ss_list_106b_0010 NULL +#define pci_ss_list_106b_0017 NULL +#define pci_ss_list_106b_0018 NULL +#define pci_ss_list_106b_0019 NULL +#define pci_ss_list_106b_001e NULL +#define pci_ss_list_106b_001f NULL +#define pci_ss_list_106b_0020 NULL +#define pci_ss_list_106b_0021 NULL +#define pci_ss_list_106b_0022 NULL +#define pci_ss_list_106b_0024 NULL +#define pci_ss_list_106b_0025 NULL +#define pci_ss_list_106b_0026 NULL +#define pci_ss_list_106b_0027 NULL +#define pci_ss_list_106b_0028 NULL +#define pci_ss_list_106b_0029 NULL +#define pci_ss_list_106b_002d NULL +#define pci_ss_list_106b_002e NULL +#define pci_ss_list_106b_002f NULL +#define pci_ss_list_106b_0030 NULL +#define pci_ss_list_106b_0031 NULL +#define pci_ss_list_106b_0032 NULL +#define pci_ss_list_106b_0033 NULL +#define pci_ss_list_106b_0034 NULL +#define pci_ss_list_106b_1645 NULL +#define pci_ss_list_106c_8801 NULL +#define pci_ss_list_106c_8802 NULL +#define pci_ss_list_106c_8803 NULL +#define pci_ss_list_106c_8804 NULL +#define pci_ss_list_106c_8805 NULL +#define pci_ss_list_1073_0001 NULL +#define pci_ss_list_1073_0002 NULL +#define pci_ss_list_1073_0003 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1073_0004[] = { + &pci_ss_info_1073_0004_1073_0004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_0005[] = { + &pci_ss_info_1073_0005_1073_0005, + NULL +}; +#define pci_ss_list_1073_0006 NULL +static const pciSubsystemInfo *pci_ss_list_1073_0008[] = { + &pci_ss_info_1073_0008_1073_0008, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_000a[] = { + &pci_ss_info_1073_000a_1073_0004, + &pci_ss_info_1073_000a_1073_000a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_000c[] = { + &pci_ss_info_1073_000c_107a_000c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_000d[] = { + &pci_ss_info_1073_000d_1073_000d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_0010[] = { + &pci_ss_info_1073_0010_1073_0006, + &pci_ss_info_1073_0010_1073_0010, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_0012[] = { + &pci_ss_info_1073_0012_1073_0012, + NULL +}; +#define pci_ss_list_1073_0020 NULL +static const pciSubsystemInfo *pci_ss_list_1073_2000[] = { + &pci_ss_info_1073_2000_1073_2000, + NULL +}; +#endif +#define pci_ss_list_1074_4e78 NULL +#define pci_ss_list_1077_1016 NULL +#define pci_ss_list_1077_1020 NULL +#define pci_ss_list_1077_1022 NULL +#define pci_ss_list_1077_1080 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1077_1216[] = { + &pci_ss_info_1077_1216_101e_8471, + &pci_ss_info_1077_1216_101e_8493, + NULL +}; +#define pci_ss_list_1077_1240 NULL +#define pci_ss_list_1077_1280 NULL +#define pci_ss_list_1077_2020 NULL +static const pciSubsystemInfo *pci_ss_list_1077_2100[] = { + &pci_ss_info_1077_2100_1077_0001, + NULL +}; +#define pci_ss_list_1077_2200 NULL +#define pci_ss_list_1077_2300 NULL +#define pci_ss_list_1077_2312 NULL +#endif +#define pci_ss_list_1078_0000 NULL +#define pci_ss_list_1078_0001 NULL +#define pci_ss_list_1078_0002 NULL +#define pci_ss_list_1078_0100 NULL +#define pci_ss_list_1078_0101 NULL +#define pci_ss_list_1078_0102 NULL +#define pci_ss_list_1078_0103 NULL +#define pci_ss_list_1078_0104 NULL +#define pci_ss_list_1078_0400 NULL +#define pci_ss_list_1078_0401 NULL +#define pci_ss_list_1078_0402 NULL +#define pci_ss_list_1078_0403 NULL +#define pci_ss_list_107d_0000 NULL +#define pci_ss_list_107e_0001 NULL +#define pci_ss_list_107e_0002 NULL +#define pci_ss_list_107e_0004 NULL +#define pci_ss_list_107e_0005 NULL +#define pci_ss_list_107e_0008 NULL +#define pci_ss_list_107e_9003 NULL +#define pci_ss_list_107e_9007 NULL +#define pci_ss_list_107e_9008 NULL +#define pci_ss_list_107e_900c NULL +#define pci_ss_list_107e_900e NULL +#define pci_ss_list_107e_9011 NULL +#define pci_ss_list_107e_9013 NULL +#define pci_ss_list_107e_9023 NULL +#define pci_ss_list_107e_9027 NULL +#define pci_ss_list_107e_9031 NULL +#define pci_ss_list_107e_9033 NULL +#define pci_ss_list_107f_0802 NULL +#define pci_ss_list_1080_0600 NULL +#define pci_ss_list_1080_c691 NULL +#define pci_ss_list_1080_c693 NULL +#define pci_ss_list_1081_0d47 NULL +#define pci_ss_list_1083_0001 NULL +#define pci_ss_list_108a_0001 NULL +#define pci_ss_list_108a_0010 NULL +#define pci_ss_list_108a_0040 NULL +#define pci_ss_list_108a_3000 NULL +#define pci_ss_list_108d_0001 NULL +#define pci_ss_list_108d_0002 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_108d_0004[] = { + &pci_ss_info_108d_0004_108d_0004, + NULL +}; +#define pci_ss_list_108d_0005 NULL +#define pci_ss_list_108d_0006 NULL +static const pciSubsystemInfo *pci_ss_list_108d_0007[] = { + &pci_ss_info_108d_0007_108d_0007, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_108d_0008[] = { + &pci_ss_info_108d_0008_108d_0008, + NULL +}; +#define pci_ss_list_108d_0011 NULL +#define pci_ss_list_108d_0012 NULL +#define pci_ss_list_108d_0013 NULL +#define pci_ss_list_108d_0014 NULL +static const pciSubsystemInfo *pci_ss_list_108d_0019[] = { + &pci_ss_info_108d_0019_108d_0016, + &pci_ss_info_108d_0019_108d_0017, + NULL +}; +#define pci_ss_list_108d_0021 NULL +#define pci_ss_list_108d_0022 NULL +#endif +#define pci_ss_list_108e_0001 NULL +#define pci_ss_list_108e_1000 NULL +#define pci_ss_list_108e_1001 NULL +#define pci_ss_list_108e_1100 NULL +#define pci_ss_list_108e_1101 NULL +#define pci_ss_list_108e_1102 NULL +#define pci_ss_list_108e_1103 NULL +#define pci_ss_list_108e_2bad NULL +#define pci_ss_list_108e_5000 NULL +#define pci_ss_list_108e_5043 NULL +#define pci_ss_list_108e_8000 NULL +#define pci_ss_list_108e_8001 NULL +#define pci_ss_list_108e_a000 NULL +#define pci_ss_list_108e_a001 NULL +#define pci_ss_list_1091_0020 NULL +#define pci_ss_list_1091_0021 NULL +#define pci_ss_list_1091_0040 NULL +#define pci_ss_list_1091_0041 NULL +#define pci_ss_list_1091_0060 NULL +#define pci_ss_list_1091_00e4 NULL +#define pci_ss_list_1091_0720 NULL +#define pci_ss_list_1092_00a0 NULL +#define pci_ss_list_1092_00a8 NULL +#define pci_ss_list_1092_0550 NULL +#define pci_ss_list_1092_08d4 NULL +#define pci_ss_list_1092_094c NULL +#define pci_ss_list_1092_1092 NULL +#define pci_ss_list_1092_6120 NULL +#define pci_ss_list_1092_8810 NULL +#define pci_ss_list_1092_8811 NULL +#define pci_ss_list_1092_8880 NULL +#define pci_ss_list_1092_8881 NULL +#define pci_ss_list_1092_88b0 NULL +#define pci_ss_list_1092_88b1 NULL +#define pci_ss_list_1092_88c0 NULL +#define pci_ss_list_1092_88c1 NULL +#define pci_ss_list_1092_88d0 NULL +#define pci_ss_list_1092_88d1 NULL +#define pci_ss_list_1092_88f0 NULL +#define pci_ss_list_1092_88f1 NULL +#define pci_ss_list_1092_9999 NULL +#define pci_ss_list_1093_0160 NULL +#define pci_ss_list_1093_0162 NULL +#define pci_ss_list_1093_1170 NULL +#define pci_ss_list_1093_1180 NULL +#define pci_ss_list_1093_1190 NULL +#define pci_ss_list_1093_1330 NULL +#define pci_ss_list_1093_1350 NULL +#define pci_ss_list_1093_2a60 NULL +#define pci_ss_list_1093_b001 NULL +#define pci_ss_list_1093_b011 NULL +#define pci_ss_list_1093_b021 NULL +#define pci_ss_list_1093_b031 NULL +#define pci_ss_list_1093_b041 NULL +#define pci_ss_list_1093_b051 NULL +#define pci_ss_list_1093_b061 NULL +#define pci_ss_list_1093_b071 NULL +#define pci_ss_list_1093_b081 NULL +#define pci_ss_list_1093_b091 NULL +#define pci_ss_list_1093_c801 NULL +#define pci_ss_list_1093_c831 NULL +#define pci_ss_list_1095_0640 NULL +#define pci_ss_list_1095_0643 NULL +#define pci_ss_list_1095_0646 NULL +#define pci_ss_list_1095_0647 NULL +#define pci_ss_list_1095_0648 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1095_0649[] = { + &pci_ss_info_1095_0649_0e11_005d, + &pci_ss_info_1095_0649_0e11_007e, + &pci_ss_info_1095_0649_101e_0649, + NULL +}; +#define pci_ss_list_1095_0650 NULL +static const pciSubsystemInfo *pci_ss_list_1095_0670[] = { + &pci_ss_info_1095_0670_1095_0670, + NULL +}; +#define pci_ss_list_1095_0673 NULL +#define pci_ss_list_1095_0680 NULL +#define pci_ss_list_1095_3112 NULL +#endif +#define pci_ss_list_1098_0001 NULL +#define pci_ss_list_1098_0002 NULL +#define pci_ss_list_109e_0350 NULL +#define pci_ss_list_109e_0351 NULL +static const pciSubsystemInfo *pci_ss_list_109e_0369[] = { + &pci_ss_info_109e_0369_1002_0001, + &pci_ss_info_109e_0369_1002_0003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_036c[] = { + &pci_ss_info_109e_036c_13e9_0070, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_036e[] = { + &pci_ss_info_109e_036e_0070_13eb, + &pci_ss_info_109e_036e_0070_ff01, + &pci_ss_info_109e_036e_107d_6606, + &pci_ss_info_109e_036e_11bd_0012, + &pci_ss_info_109e_036e_11bd_001c, + &pci_ss_info_109e_036e_127a_0001, + &pci_ss_info_109e_036e_127a_0002, + &pci_ss_info_109e_036e_127a_0003, + &pci_ss_info_109e_036e_127a_0048, + &pci_ss_info_109e_036e_144f_3000, + &pci_ss_info_109e_036e_1461_0004, + &pci_ss_info_109e_036e_14f1_0001, + &pci_ss_info_109e_036e_14f1_0002, + &pci_ss_info_109e_036e_14f1_0003, + &pci_ss_info_109e_036e_14f1_0048, + &pci_ss_info_109e_036e_1851_1850, + &pci_ss_info_109e_036e_1851_1851, + &pci_ss_info_109e_036e_1852_1852, + &pci_ss_info_109e_036e_bd11_1200, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_036f[] = { + &pci_ss_info_109e_036f_127a_0044, + &pci_ss_info_109e_036f_127a_0122, + &pci_ss_info_109e_036f_127a_0144, + &pci_ss_info_109e_036f_127a_0222, + &pci_ss_info_109e_036f_127a_0244, + &pci_ss_info_109e_036f_127a_0322, + &pci_ss_info_109e_036f_127a_0422, + &pci_ss_info_109e_036f_127a_1122, + &pci_ss_info_109e_036f_127a_1222, + &pci_ss_info_109e_036f_127a_1322, + &pci_ss_info_109e_036f_127a_1522, + &pci_ss_info_109e_036f_127a_1622, + &pci_ss_info_109e_036f_127a_1722, + &pci_ss_info_109e_036f_14f1_0044, + &pci_ss_info_109e_036f_14f1_0122, + &pci_ss_info_109e_036f_14f1_0144, + &pci_ss_info_109e_036f_14f1_0222, + &pci_ss_info_109e_036f_14f1_0244, + &pci_ss_info_109e_036f_14f1_0322, + &pci_ss_info_109e_036f_14f1_0422, + &pci_ss_info_109e_036f_14f1_1122, + &pci_ss_info_109e_036f_14f1_1222, + &pci_ss_info_109e_036f_14f1_1322, + &pci_ss_info_109e_036f_14f1_1522, + &pci_ss_info_109e_036f_14f1_1622, + &pci_ss_info_109e_036f_14f1_1722, + &pci_ss_info_109e_036f_1851_1850, + &pci_ss_info_109e_036f_1851_1851, + &pci_ss_info_109e_036f_1852_1852, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_0370[] = { + &pci_ss_info_109e_0370_1851_1850, + &pci_ss_info_109e_0370_1851_1851, + &pci_ss_info_109e_0370_1852_1852, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_0878[] = { + &pci_ss_info_109e_0878_0070_13eb, + &pci_ss_info_109e_0878_0070_ff01, + &pci_ss_info_109e_0878_1002_0001, + &pci_ss_info_109e_0878_1002_0003, + &pci_ss_info_109e_0878_11bd_0012, + &pci_ss_info_109e_0878_11bd_001c, + &pci_ss_info_109e_0878_127a_0001, + &pci_ss_info_109e_0878_127a_0002, + &pci_ss_info_109e_0878_127a_0003, + &pci_ss_info_109e_0878_127a_0048, + &pci_ss_info_109e_0878_13e9_0070, + &pci_ss_info_109e_0878_144f_3000, + &pci_ss_info_109e_0878_1461_0004, + &pci_ss_info_109e_0878_14f1_0001, + &pci_ss_info_109e_0878_14f1_0002, + &pci_ss_info_109e_0878_14f1_0003, + &pci_ss_info_109e_0878_14f1_0048, + &pci_ss_info_109e_0878_bd11_1200, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_0879[] = { + &pci_ss_info_109e_0879_127a_0044, + &pci_ss_info_109e_0879_127a_0122, + &pci_ss_info_109e_0879_127a_0144, + &pci_ss_info_109e_0879_127a_0222, + &pci_ss_info_109e_0879_127a_0244, + &pci_ss_info_109e_0879_127a_0322, + &pci_ss_info_109e_0879_127a_0422, + &pci_ss_info_109e_0879_127a_1122, + &pci_ss_info_109e_0879_127a_1222, + &pci_ss_info_109e_0879_127a_1322, + &pci_ss_info_109e_0879_127a_1522, + &pci_ss_info_109e_0879_127a_1622, + &pci_ss_info_109e_0879_127a_1722, + &pci_ss_info_109e_0879_14f1_0044, + &pci_ss_info_109e_0879_14f1_0122, + &pci_ss_info_109e_0879_14f1_0144, + &pci_ss_info_109e_0879_14f1_0222, + &pci_ss_info_109e_0879_14f1_0244, + &pci_ss_info_109e_0879_14f1_0322, + &pci_ss_info_109e_0879_14f1_0422, + &pci_ss_info_109e_0879_14f1_1122, + &pci_ss_info_109e_0879_14f1_1222, + &pci_ss_info_109e_0879_14f1_1322, + &pci_ss_info_109e_0879_14f1_1522, + &pci_ss_info_109e_0879_14f1_1622, + &pci_ss_info_109e_0879_14f1_1722, + NULL +}; +#define pci_ss_list_109e_0880 NULL +#define pci_ss_list_109e_2115 NULL +#define pci_ss_list_109e_2125 NULL +#define pci_ss_list_109e_2164 NULL +#define pci_ss_list_109e_2165 NULL +#define pci_ss_list_109e_8230 NULL +#define pci_ss_list_109e_8472 NULL +#define pci_ss_list_109e_8474 NULL +#define pci_ss_list_10a5_5449 NULL +#define pci_ss_list_10a8_0000 NULL +#define pci_ss_list_10a9_0001 NULL +#define pci_ss_list_10a9_0002 NULL +#define pci_ss_list_10a9_0003 NULL +#define pci_ss_list_10a9_0004 NULL +#define pci_ss_list_10a9_0005 NULL +#define pci_ss_list_10a9_0006 NULL +#define pci_ss_list_10a9_0007 NULL +#define pci_ss_list_10a9_0008 NULL +#define pci_ss_list_10a9_0009 NULL +#define pci_ss_list_10a9_0010 NULL +#define pci_ss_list_10a9_0011 NULL +#define pci_ss_list_10a9_0012 NULL +#define pci_ss_list_10a9_1001 NULL +#define pci_ss_list_10a9_1002 NULL +#define pci_ss_list_10a9_1003 NULL +#define pci_ss_list_10a9_1004 NULL +#define pci_ss_list_10a9_1005 NULL +#define pci_ss_list_10a9_1006 NULL +#define pci_ss_list_10a9_1007 NULL +#define pci_ss_list_10a9_1008 NULL +#define pci_ss_list_10a9_2001 NULL +#define pci_ss_list_10a9_2002 NULL +#define pci_ss_list_10a9_8001 NULL +#define pci_ss_list_10a9_8002 NULL +#define pci_ss_list_10aa_0000 NULL +#define pci_ss_list_10ad_0001 NULL +#define pci_ss_list_10ad_0003 NULL +#define pci_ss_list_10ad_0005 NULL +#define pci_ss_list_10ad_0103 NULL +#define pci_ss_list_10ad_0105 NULL +#define pci_ss_list_10ad_0565 NULL +#define pci_ss_list_10b3_3106 NULL +#define pci_ss_list_10b3_b106 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b4_1b1d[] = { + &pci_ss_info_10b4_1b1d_10b4_237e, + NULL +}; +#endif +#define pci_ss_list_10b5_0001 NULL +#define pci_ss_list_10b5_1076 NULL +#define pci_ss_list_10b5_1077 NULL +#define pci_ss_list_10b5_1078 NULL +#define pci_ss_list_10b5_1103 NULL +#define pci_ss_list_10b5_1146 NULL +#define pci_ss_list_10b5_1147 NULL +#define pci_ss_list_10b5_2724 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b5_9030[] = { + &pci_ss_info_10b5_9030_15ed_1002, + &pci_ss_info_10b5_9030_15ed_1003, + NULL +}; +#define pci_ss_list_10b5_9036 NULL +static const pciSubsystemInfo *pci_ss_list_10b5_9050[] = { + &pci_ss_info_10b5_9050_10b5_2036, + &pci_ss_info_10b5_9050_10b5_2273, + &pci_ss_info_10b5_9050_10b5_9050, + &pci_ss_info_10b5_9050_1522_0001, + &pci_ss_info_10b5_9050_1522_0002, + &pci_ss_info_10b5_9050_1522_0003, + &pci_ss_info_10b5_9050_1522_0004, + &pci_ss_info_10b5_9050_1522_0010, + &pci_ss_info_10b5_9050_1522_0020, + &pci_ss_info_10b5_9050_15ed_1000, + &pci_ss_info_10b5_9050_15ed_1001, + &pci_ss_info_10b5_9050_15ed_1002, + &pci_ss_info_10b5_9050_15ed_1003, + &pci_ss_info_10b5_9050_5654_5634, + &pci_ss_info_10b5_9050_d531_c002, + &pci_ss_info_10b5_9050_d84d_4006, + &pci_ss_info_10b5_9050_d84d_4008, + &pci_ss_info_10b5_9050_d84d_4014, + &pci_ss_info_10b5_9050_d84d_4018, + &pci_ss_info_10b5_9050_d84d_4025, + &pci_ss_info_10b5_9050_d84d_4027, + &pci_ss_info_10b5_9050_d84d_4028, + &pci_ss_info_10b5_9050_d84d_4036, + &pci_ss_info_10b5_9050_d84d_4037, + &pci_ss_info_10b5_9050_d84d_4038, + &pci_ss_info_10b5_9050_d84d_4052, + &pci_ss_info_10b5_9050_d84d_4053, + &pci_ss_info_10b5_9050_d84d_4055, + &pci_ss_info_10b5_9050_d84d_4058, + &pci_ss_info_10b5_9050_d84d_4065, + &pci_ss_info_10b5_9050_d84d_4068, + &pci_ss_info_10b5_9050_d84d_4078, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b5_9054[] = { + &pci_ss_info_10b5_9054_10b5_2455, + NULL +}; +#define pci_ss_list_10b5_9060 NULL +static const pciSubsystemInfo *pci_ss_list_10b5_906d[] = { + &pci_ss_info_10b5_906d_125c_0640, + NULL +}; +#define pci_ss_list_10b5_906e NULL +static const pciSubsystemInfo *pci_ss_list_10b5_9080[] = { + &pci_ss_info_10b5_9080_10b5_9080, + &pci_ss_info_10b5_9080_129d_0002, + NULL +}; +#endif +#define pci_ss_list_10b6_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b6_0002[] = { + &pci_ss_info_10b6_0002_10b6_0002, + &pci_ss_info_10b6_0002_10b6_0006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_0003[] = { + &pci_ss_info_10b6_0003_0e11_b0fd, + &pci_ss_info_10b6_0003_10b6_0003, + &pci_ss_info_10b6_0003_10b6_0007, + NULL +}; +#define pci_ss_list_10b6_0004 NULL +static const pciSubsystemInfo *pci_ss_list_10b6_0006[] = { + &pci_ss_info_10b6_0006_10b6_0006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_0007[] = { + &pci_ss_info_10b6_0007_10b6_0007, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_0009[] = { + &pci_ss_info_10b6_0009_10b6_0009, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_000a[] = { + &pci_ss_info_10b6_000a_10b6_000a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_000b[] = { + &pci_ss_info_10b6_000b_10b6_0008, + &pci_ss_info_10b6_000b_10b6_000b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_000c[] = { + &pci_ss_info_10b6_000c_10b6_000c, + NULL +}; +#define pci_ss_list_10b6_1000 NULL +#define pci_ss_list_10b6_1001 NULL +#endif +#define pci_ss_list_10b7_0001 NULL +#define pci_ss_list_10b7_1006 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b7_1007[] = { + &pci_ss_info_10b7_1007_10b7_615c, + NULL +}; +#define pci_ss_list_10b7_3390 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_3590[] = { + &pci_ss_info_10b7_3590_10b7_3590, + NULL +}; +#define pci_ss_list_10b7_4500 NULL +#define pci_ss_list_10b7_5055 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_5057[] = { + &pci_ss_info_10b7_5057_10b7_5a57, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_5157[] = { + &pci_ss_info_10b7_5157_10b7_5b57, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_5257[] = { + &pci_ss_info_10b7_5257_10b7_5c57, + NULL +}; +#define pci_ss_list_10b7_5900 NULL +#define pci_ss_list_10b7_5920 NULL +#define pci_ss_list_10b7_5950 NULL +#define pci_ss_list_10b7_5951 NULL +#define pci_ss_list_10b7_5952 NULL +#define pci_ss_list_10b7_5970 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_5b57[] = { + &pci_ss_info_10b7_5b57_10b7_5b57, + NULL +}; +#define pci_ss_list_10b7_6055 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_6056[] = { + &pci_ss_info_10b7_6056_10b7_6556, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_6560[] = { + &pci_ss_info_10b7_6560_10b7_656a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_6561[] = { + &pci_ss_info_10b7_6561_10b7_656b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_6562[] = { + &pci_ss_info_10b7_6562_10b7_656b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_6563[] = { + &pci_ss_info_10b7_6563_10b7_656b, + NULL +}; +#define pci_ss_list_10b7_6564 NULL +#define pci_ss_list_10b7_7646 NULL +#define pci_ss_list_10b7_7940 NULL +#define pci_ss_list_10b7_7980 NULL +#define pci_ss_list_10b7_7990 NULL +#define pci_ss_list_10b7_8811 NULL +#define pci_ss_list_10b7_9000 NULL +#define pci_ss_list_10b7_9001 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9004[] = { + &pci_ss_info_10b7_9004_10b7_9004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_9005[] = { + &pci_ss_info_10b7_9005_10b7_9005, + NULL +}; +#define pci_ss_list_10b7_9006 NULL +#define pci_ss_list_10b7_900a NULL +#define pci_ss_list_10b7_9050 NULL +#define pci_ss_list_10b7_9051 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9055[] = { + &pci_ss_info_10b7_9055_1028_0080, + &pci_ss_info_10b7_9055_1028_0081, + &pci_ss_info_10b7_9055_1028_0082, + &pci_ss_info_10b7_9055_1028_0083, + &pci_ss_info_10b7_9055_1028_0084, + &pci_ss_info_10b7_9055_1028_0085, + &pci_ss_info_10b7_9055_1028_0086, + &pci_ss_info_10b7_9055_1028_0087, + &pci_ss_info_10b7_9055_1028_0088, + &pci_ss_info_10b7_9055_1028_0089, + &pci_ss_info_10b7_9055_1028_0090, + &pci_ss_info_10b7_9055_1028_0091, + &pci_ss_info_10b7_9055_1028_0092, + &pci_ss_info_10b7_9055_1028_0093, + &pci_ss_info_10b7_9055_1028_0094, + &pci_ss_info_10b7_9055_1028_0095, + &pci_ss_info_10b7_9055_1028_0096, + &pci_ss_info_10b7_9055_1028_0097, + &pci_ss_info_10b7_9055_1028_0098, + &pci_ss_info_10b7_9055_1028_0099, + &pci_ss_info_10b7_9055_10b7_9055, + NULL +}; +#define pci_ss_list_10b7_9056 NULL +#define pci_ss_list_10b7_9058 NULL +#define pci_ss_list_10b7_905a NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9200[] = { + &pci_ss_info_10b7_9200_1028_0095, + &pci_ss_info_10b7_9200_10b7_1000, + &pci_ss_info_10b7_9200_10b7_7000, + NULL +}; +#define pci_ss_list_10b7_9201 NULL +#define pci_ss_list_10b7_9300 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9800[] = { + &pci_ss_info_10b7_9800_10b7_9800, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_9805[] = { + &pci_ss_info_10b7_9805_10b7_1201, + &pci_ss_info_10b7_9805_10b7_1202, + &pci_ss_info_10b7_9805_10b7_9805, + &pci_ss_info_10b7_9805_10f1_2462, + NULL +}; +#define pci_ss_list_10b7_9900 NULL +#define pci_ss_list_10b7_9902 NULL +#define pci_ss_list_10b7_9903 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9904[] = { + &pci_ss_info_10b7_9904_10b7_1000, + &pci_ss_info_10b7_9904_10b7_2000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_9905[] = { + &pci_ss_info_10b7_9905_10b7_1101, + &pci_ss_info_10b7_9905_10b7_1102, + &pci_ss_info_10b7_9905_10b7_2101, + &pci_ss_info_10b7_9905_10b7_2102, + NULL +}; +#define pci_ss_list_10b7_9908 NULL +#define pci_ss_list_10b7_9909 NULL +#define pci_ss_list_10b7_990b NULL +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b8_0005[] = { + &pci_ss_info_10b8_0005_1055_e000, + &pci_ss_info_10b8_0005_1055_e002, + &pci_ss_info_10b8_0005_10b8_a011, + &pci_ss_info_10b8_0005_10b8_a014, + &pci_ss_info_10b8_0005_10b8_a015, + &pci_ss_info_10b8_0005_10b8_a016, + &pci_ss_info_10b8_0005_10b8_a017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b8_0006[] = { + &pci_ss_info_10b8_0006_1055_e100, + &pci_ss_info_10b8_0006_1055_e102, + &pci_ss_info_10b8_0006_1055_e300, + &pci_ss_info_10b8_0006_1055_e302, + &pci_ss_info_10b8_0006_10b8_a012, + &pci_ss_info_10b8_0006_13a2_8002, + &pci_ss_info_10b8_0006_13a2_8006, + NULL +}; +#define pci_ss_list_10b8_1000 NULL +#define pci_ss_list_10b8_1001 NULL +#define pci_ss_list_10b8_a011 NULL +#define pci_ss_list_10b8_b106 NULL +#endif +static const pciSubsystemInfo *pci_ss_list_10b9_0111[] = { + &pci_ss_info_10b9_0111_10b9_0111, + NULL +}; +#define pci_ss_list_10b9_1435 NULL +#define pci_ss_list_10b9_1445 NULL +#define pci_ss_list_10b9_1449 NULL +#define pci_ss_list_10b9_1451 NULL +#define pci_ss_list_10b9_1461 NULL +#define pci_ss_list_10b9_1489 NULL +#define pci_ss_list_10b9_1511 NULL +#define pci_ss_list_10b9_1512 NULL +#define pci_ss_list_10b9_1513 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_1521[] = { + &pci_ss_info_10b9_1521_10b9_1521, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b9_1523[] = { + &pci_ss_info_10b9_1523_10b9_1523, + NULL +}; +#define pci_ss_list_10b9_1531 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_1533[] = { + &pci_ss_info_10b9_1533_10b9_1533, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b9_1541[] = { + &pci_ss_info_10b9_1541_10b9_1541, + NULL +}; +#define pci_ss_list_10b9_1543 NULL +#define pci_ss_list_10b9_1563 NULL +#define pci_ss_list_10b9_1621 NULL +#define pci_ss_list_10b9_1631 NULL +#define pci_ss_list_10b9_1632 NULL +#define pci_ss_list_10b9_1641 NULL +#define pci_ss_list_10b9_1644 NULL +#define pci_ss_list_10b9_1646 NULL +#define pci_ss_list_10b9_1647 NULL +#define pci_ss_list_10b9_1651 NULL +#define pci_ss_list_10b9_1671 NULL +#define pci_ss_list_10b9_1681 NULL +#define pci_ss_list_10b9_1687 NULL +#define pci_ss_list_10b9_3141 NULL +#define pci_ss_list_10b9_3143 NULL +#define pci_ss_list_10b9_3145 NULL +#define pci_ss_list_10b9_3147 NULL +#define pci_ss_list_10b9_3149 NULL +#define pci_ss_list_10b9_3151 NULL +#define pci_ss_list_10b9_3307 NULL +#define pci_ss_list_10b9_3309 NULL +#define pci_ss_list_10b9_5212 NULL +#define pci_ss_list_10b9_5215 NULL +#define pci_ss_list_10b9_5217 NULL +#define pci_ss_list_10b9_5219 NULL +#define pci_ss_list_10b9_5225 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_5229[] = { + &pci_ss_info_10b9_5229_1043_8053, + NULL +}; +#define pci_ss_list_10b9_5235 NULL +#define pci_ss_list_10b9_5237 NULL +#define pci_ss_list_10b9_5239 NULL +#define pci_ss_list_10b9_5243 NULL +#define pci_ss_list_10b9_5247 NULL +#define pci_ss_list_10b9_5249 NULL +#define pci_ss_list_10b9_5251 NULL +#define pci_ss_list_10b9_5253 NULL +#define pci_ss_list_10b9_5261 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_5451[] = { + &pci_ss_info_10b9_5451_1014_0506, + NULL +}; +#define pci_ss_list_10b9_5453 NULL +#define pci_ss_list_10b9_5455 NULL +#define pci_ss_list_10b9_5457 NULL +#define pci_ss_list_10b9_5459 NULL +#define pci_ss_list_10b9_545a NULL +#define pci_ss_list_10b9_5471 NULL +#define pci_ss_list_10b9_5473 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_7101[] = { + &pci_ss_info_10b9_7101_10b9_7101, + NULL +}; +#define pci_ss_list_10ba_0301 NULL +#define pci_ss_list_10bd_0e34 NULL +#define pci_ss_list_10c3_1100 NULL +#define pci_ss_list_10c8_0001 NULL +#define pci_ss_list_10c8_0002 NULL +#define pci_ss_list_10c8_0003 NULL +static const pciSubsystemInfo *pci_ss_list_10c8_0004[] = { + &pci_ss_info_10c8_0004_1014_00ba, + &pci_ss_info_10c8_0004_1025_1007, + &pci_ss_info_10c8_0004_1028_0074, + &pci_ss_info_10c8_0004_1028_0075, + &pci_ss_info_10c8_0004_1028_007d, + &pci_ss_info_10c8_0004_1028_007e, + &pci_ss_info_10c8_0004_1033_802f, + &pci_ss_info_10c8_0004_104d_801b, + &pci_ss_info_10c8_0004_104d_802f, + &pci_ss_info_10c8_0004_104d_830b, + &pci_ss_info_10c8_0004_10ba_0e00, + &pci_ss_info_10c8_0004_10c8_0004, + &pci_ss_info_10c8_0004_10cf_1029, + &pci_ss_info_10c8_0004_10f7_8308, + &pci_ss_info_10c8_0004_10f7_8309, + &pci_ss_info_10c8_0004_10f7_830b, + &pci_ss_info_10c8_0004_10f7_830d, + &pci_ss_info_10c8_0004_10f7_8312, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10c8_0005[] = { + &pci_ss_info_10c8_0005_1014_00dd, + NULL +}; +#define pci_ss_list_10c8_0006 NULL +static const pciSubsystemInfo *pci_ss_list_10c8_0016[] = { + &pci_ss_info_10c8_0016_10c8_0016, + NULL +}; +#define pci_ss_list_10c8_0025 NULL +#define pci_ss_list_10c8_0083 NULL +static const pciSubsystemInfo *pci_ss_list_10c8_8005[] = { + &pci_ss_info_10c8_8005_0e11_b0d1, + &pci_ss_info_10c8_8005_0e11_b126, + &pci_ss_info_10c8_8005_1014_00dd, + &pci_ss_info_10c8_8005_1025_1003, + &pci_ss_info_10c8_8005_1028_008f, + &pci_ss_info_10c8_8005_103c_0007, + &pci_ss_info_10c8_8005_103c_0008, + &pci_ss_info_10c8_8005_103c_000d, + &pci_ss_info_10c8_8005_10c8_8005, + &pci_ss_info_10c8_8005_110a_8005, + &pci_ss_info_10c8_8005_14c0_0004, + NULL +}; +#define pci_ss_list_10c8_8006 NULL +#define pci_ss_list_10c8_8016 NULL +#define pci_ss_list_10cd_1100 NULL +#define pci_ss_list_10cd_1200 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10cd_1300[] = { + &pci_ss_info_10cd_1300_10cd_1310, + NULL +}; +#define pci_ss_list_10cd_2300 NULL +#define pci_ss_list_10cd_2500 NULL +#endif +#define pci_ss_list_10cf_2001 NULL +#define pci_ss_list_10d9_0512 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10d9_0531[] = { + &pci_ss_info_10d9_0531_1186_1200, + NULL +}; +#define pci_ss_list_10d9_8625 NULL +#define pci_ss_list_10d9_8888 NULL +#endif +#define pci_ss_list_10da_0508 NULL +#define pci_ss_list_10da_3390 NULL +#define pci_ss_list_10dc_0001 NULL +#define pci_ss_list_10dc_0002 NULL +#define pci_ss_list_10dc_0021 NULL +#define pci_ss_list_10dc_0022 NULL +#define pci_ss_list_10dc_10dc NULL +#define pci_ss_list_10de_0008 NULL +#define pci_ss_list_10de_0009 NULL +#define pci_ss_list_10de_0010 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0020[] = { + &pci_ss_info_10de_0020_1043_0200, + &pci_ss_info_10de_0020_1048_0c18, + &pci_ss_info_10de_0020_1048_0c1b, + &pci_ss_info_10de_0020_1092_0550, + &pci_ss_info_10de_0020_1092_0552, + &pci_ss_info_10de_0020_1092_4804, + &pci_ss_info_10de_0020_1092_4808, + &pci_ss_info_10de_0020_1092_4810, + &pci_ss_info_10de_0020_1092_4812, + &pci_ss_info_10de_0020_1092_4815, + &pci_ss_info_10de_0020_1092_4820, + &pci_ss_info_10de_0020_1092_4822, + &pci_ss_info_10de_0020_1092_4904, + &pci_ss_info_10de_0020_1092_4914, + &pci_ss_info_10de_0020_1092_8225, + &pci_ss_info_10de_0020_10b4_273d, + &pci_ss_info_10de_0020_10b4_273e, + &pci_ss_info_10de_0020_10b4_2740, + &pci_ss_info_10de_0020_10de_0020, + &pci_ss_info_10de_0020_1102_1015, + &pci_ss_info_10de_0020_1102_1016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0028[] = { + &pci_ss_info_10de_0028_1043_0200, + &pci_ss_info_10de_0028_1043_0201, + &pci_ss_info_10de_0028_1043_0205, + &pci_ss_info_10de_0028_1043_4000, + &pci_ss_info_10de_0028_1092_4804, + &pci_ss_info_10de_0028_1092_4a00, + &pci_ss_info_10de_0028_1092_4a02, + &pci_ss_info_10de_0028_1092_5a00, + &pci_ss_info_10de_0028_1092_6a02, + &pci_ss_info_10de_0028_1092_7a02, + &pci_ss_info_10de_0028_10de_0005, + &pci_ss_info_10de_0028_10de_000f, + &pci_ss_info_10de_0028_1102_1020, + &pci_ss_info_10de_0028_1102_1026, + &pci_ss_info_10de_0028_14af_5810, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0029[] = { + &pci_ss_info_10de_0029_1043_0200, + &pci_ss_info_10de_0029_1043_0201, + &pci_ss_info_10de_0029_1043_0205, + &pci_ss_info_10de_0029_1102_1021, + &pci_ss_info_10de_0029_1102_1029, + &pci_ss_info_10de_0029_1102_102f, + &pci_ss_info_10de_0029_14af_5820, + NULL +}; +#define pci_ss_list_10de_002a NULL +#define pci_ss_list_10de_002b NULL +static const pciSubsystemInfo *pci_ss_list_10de_002c[] = { + &pci_ss_info_10de_002c_1043_0200, + &pci_ss_info_10de_002c_1043_0201, + &pci_ss_info_10de_002c_1092_6820, + &pci_ss_info_10de_002c_1102_1031, + &pci_ss_info_10de_002c_1102_1034, + &pci_ss_info_10de_002c_14af_5008, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_002d[] = { + &pci_ss_info_10de_002d_1043_0200, + &pci_ss_info_10de_002d_1043_0201, + &pci_ss_info_10de_002d_1048_0c3a, + &pci_ss_info_10de_002d_10de_001e, + &pci_ss_info_10de_002d_1102_1023, + &pci_ss_info_10de_002d_1102_1024, + &pci_ss_info_10de_002d_1102_102c, + &pci_ss_info_10de_002d_1462_8808, + &pci_ss_info_10de_002d_1554_1041, + NULL +}; +#define pci_ss_list_10de_002e NULL +#define pci_ss_list_10de_002f NULL +static const pciSubsystemInfo *pci_ss_list_10de_0060[] = { + &pci_ss_info_10de_0060_1043_80ad, + NULL +}; +#define pci_ss_list_10de_0064 NULL +#define pci_ss_list_10de_0065 NULL +#define pci_ss_list_10de_0066 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0067[] = { + &pci_ss_info_10de_0067_1043_0c11, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0068[] = { + &pci_ss_info_10de_0068_1043_0c11, + NULL +}; +#define pci_ss_list_10de_006a NULL +#define pci_ss_list_10de_006b NULL +#define pci_ss_list_10de_006e NULL +static const pciSubsystemInfo *pci_ss_list_10de_00a0[] = { + &pci_ss_info_10de_00a0_14af_5810, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0100[] = { + &pci_ss_info_10de_0100_1043_0200, + &pci_ss_info_10de_0100_1043_0201, + &pci_ss_info_10de_0100_1043_4008, + &pci_ss_info_10de_0100_1043_4009, + &pci_ss_info_10de_0100_1102_102d, + &pci_ss_info_10de_0100_14af_5022, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0101[] = { + &pci_ss_info_10de_0101_1043_0202, + &pci_ss_info_10de_0101_1043_400a, + &pci_ss_info_10de_0101_1043_400b, + &pci_ss_info_10de_0101_1102_102e, + &pci_ss_info_10de_0101_14af_5021, + NULL +}; +#define pci_ss_list_10de_0103 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0110[] = { + &pci_ss_info_10de_0110_1043_4015, + &pci_ss_info_10de_0110_1043_4031, + &pci_ss_info_10de_0110_1462_8817, + &pci_ss_info_10de_0110_14af_7102, + &pci_ss_info_10de_0110_14af_7103, + NULL +}; +#define pci_ss_list_10de_0111 NULL +#define pci_ss_list_10de_0112 NULL +#define pci_ss_list_10de_0113 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0150[] = { + &pci_ss_info_10de_0150_1043_4016, + &pci_ss_info_10de_0150_107d_2840, + &pci_ss_info_10de_0150_1462_8831, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0151[] = { + &pci_ss_info_10de_0151_1043_405f, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0152[] = { + &pci_ss_info_10de_0152_1048_0c56, + NULL +}; +#define pci_ss_list_10de_0153 NULL +#define pci_ss_list_10de_0170 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0171[] = { + &pci_ss_info_10de_0171_1462_8661, + &pci_ss_info_10de_0171_1462_8730, + &pci_ss_info_10de_0171_147b_8f00, + NULL +}; +#define pci_ss_list_10de_0172 NULL +#define pci_ss_list_10de_0173 NULL +#define pci_ss_list_10de_0174 NULL +#define pci_ss_list_10de_0175 NULL +#define pci_ss_list_10de_0176 NULL +#define pci_ss_list_10de_0178 NULL +#define pci_ss_list_10de_0179 NULL +#define pci_ss_list_10de_017a NULL +#define pci_ss_list_10de_017b NULL +#define pci_ss_list_10de_017c NULL +#define pci_ss_list_10de_0181 NULL +#define pci_ss_list_10de_0182 NULL +#define pci_ss_list_10de_0183 NULL +#define pci_ss_list_10de_0188 NULL +#define pci_ss_list_10de_018a NULL +#define pci_ss_list_10de_018b NULL +#define pci_ss_list_10de_01a0 NULL +#define pci_ss_list_10de_01a4 NULL +#define pci_ss_list_10de_01ab NULL +#define pci_ss_list_10de_01ac NULL +#define pci_ss_list_10de_01ad NULL +#define pci_ss_list_10de_01b1 NULL +#define pci_ss_list_10de_01b2 NULL +#define pci_ss_list_10de_01b4 NULL +#define pci_ss_list_10de_01b7 NULL +#define pci_ss_list_10de_01b8 NULL +#define pci_ss_list_10de_01bc NULL +#define pci_ss_list_10de_01c1 NULL +#define pci_ss_list_10de_01c2 NULL +#define pci_ss_list_10de_01c3 NULL +#define pci_ss_list_10de_01e8 NULL +#define pci_ss_list_10de_01f0 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0200[] = { + &pci_ss_info_10de_0200_1043_402f, + NULL +}; +#define pci_ss_list_10de_0201 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0202[] = { + &pci_ss_info_10de_0202_1043_405b, + &pci_ss_info_10de_0202_1545_002f, + NULL +}; +#define pci_ss_list_10de_0203 NULL +#define pci_ss_list_10de_0250 NULL +#define pci_ss_list_10de_0251 NULL +#define pci_ss_list_10de_0252 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0253[] = { + &pci_ss_info_10de_0253_107d_2896, + &pci_ss_info_10de_0253_147b_8f09, + NULL +}; +#define pci_ss_list_10de_0258 NULL +#define pci_ss_list_10de_0259 NULL +#define pci_ss_list_10de_025b NULL +#define pci_ss_list_10de_0280 NULL +#define pci_ss_list_10de_0281 NULL +#define pci_ss_list_10de_0282 NULL +#define pci_ss_list_10de_0288 NULL +#define pci_ss_list_10de_0289 NULL +#define pci_ss_list_10de_0300 NULL +#define pci_ss_list_10de_0301 NULL +#define pci_ss_list_10de_0302 NULL +#define pci_ss_list_10de_0308 NULL +#define pci_ss_list_10de_0309 NULL +#define pci_ss_list_10df_1ae5 NULL +#define pci_ss_list_10df_f085 NULL +#define pci_ss_list_10df_f095 NULL +#define pci_ss_list_10df_f098 NULL +#define pci_ss_list_10df_f700 NULL +#define pci_ss_list_10df_f800 NULL +#define pci_ss_list_10df_f900 NULL +#define pci_ss_list_10df_f980 NULL +#define pci_ss_list_10e0_5026 NULL +#define pci_ss_list_10e0_5027 NULL +#define pci_ss_list_10e0_5028 NULL +#define pci_ss_list_10e0_8849 NULL +#define pci_ss_list_10e0_8853 NULL +#define pci_ss_list_10e0_9128 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10e1_0391[] = { + &pci_ss_info_10e1_0391_10e1_0391, + NULL +}; +#define pci_ss_list_10e1_690c NULL +#define pci_ss_list_10e1_dc29 NULL +#endif +#define pci_ss_list_10e3_0000 NULL +#define pci_ss_list_10e3_0860 NULL +#define pci_ss_list_10e3_0862 NULL +#define pci_ss_list_10e8_2011 NULL +#define pci_ss_list_10e8_4750 NULL +#define pci_ss_list_10e8_5920 NULL +#define pci_ss_list_10e8_8043 NULL +#define pci_ss_list_10e8_8062 NULL +#define pci_ss_list_10e8_807d NULL +#define pci_ss_list_10e8_8088 NULL +#define pci_ss_list_10e8_8089 NULL +#define pci_ss_list_10e8_809c NULL +#define pci_ss_list_10e8_80d7 NULL +#define pci_ss_list_10e8_80d9 NULL +#define pci_ss_list_10e8_80da NULL +#define pci_ss_list_10e8_811a NULL +#define pci_ss_list_10e8_8170 NULL +#define pci_ss_list_10e8_82db NULL +#define pci_ss_list_10ea_1680 NULL +#define pci_ss_list_10ea_1682 NULL +#define pci_ss_list_10ea_1683 NULL +#define pci_ss_list_10ea_2000 NULL +#define pci_ss_list_10ea_2010 NULL +#define pci_ss_list_10ea_5000 NULL +#define pci_ss_list_10ea_5050 NULL +#define pci_ss_list_10ea_5202 NULL +#define pci_ss_list_10eb_0101 NULL +#define pci_ss_list_10eb_8111 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10ec_8029[] = { + &pci_ss_info_10ec_8029_10b8_2011, + &pci_ss_info_10ec_8029_10ec_8029, + &pci_ss_info_10ec_8029_1113_1208, + &pci_ss_info_10ec_8029_1186_0300, + &pci_ss_info_10ec_8029_1259_2400, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10ec_8129[] = { + &pci_ss_info_10ec_8129_10ec_8129, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10ec_8138[] = { + &pci_ss_info_10ec_8138_10ec_8138, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10ec_8139[] = { + &pci_ss_info_10ec_8139_1025_8920, + &pci_ss_info_10ec_8139_1025_8921, + &pci_ss_info_10ec_8139_10bd_0320, + &pci_ss_info_10ec_8139_10ec_8139, + &pci_ss_info_10ec_8139_1186_1300, + &pci_ss_info_10ec_8139_1186_1320, + &pci_ss_info_10ec_8139_1186_8139, + &pci_ss_info_10ec_8139_11f6_8139, + &pci_ss_info_10ec_8139_1259_2500, + &pci_ss_info_10ec_8139_1259_2503, + &pci_ss_info_10ec_8139_1429_d010, + &pci_ss_info_10ec_8139_1432_9130, + &pci_ss_info_10ec_8139_1436_8139, + &pci_ss_info_10ec_8139_146c_1439, + &pci_ss_info_10ec_8139_1489_6001, + &pci_ss_info_10ec_8139_1489_6002, + &pci_ss_info_10ec_8139_149c_139a, + &pci_ss_info_10ec_8139_149c_8139, + &pci_ss_info_10ec_8139_2646_0001, + &pci_ss_info_10ec_8139_8e2e_7000, + &pci_ss_info_10ec_8139_8e2e_7100, + &pci_ss_info_10ec_8139_a0a0_0007, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10ec_8169[] = { + &pci_ss_info_10ec_8169_1371_434e, + NULL +}; +#define pci_ss_list_10ec_8197 NULL +#endif +#define pci_ss_list_10ed_7310 NULL +#define pci_ss_list_10ee_3fc0 NULL +#define pci_ss_list_10ee_3fc1 NULL +#define pci_ss_list_10ee_3fc2 NULL +#define pci_ss_list_10ee_3fc3 NULL +#define pci_ss_list_10ee_3fc4 NULL +#define pci_ss_list_10ee_3fc5 NULL +#define pci_ss_list_10ef_8154 NULL +#define pci_ss_list_10f5_a001 NULL +#define pci_ss_list_10fa_000c NULL +#define pci_ss_list_10fb_186f NULL +#define pci_ss_list_10fc_0003 NULL +#define pci_ss_list_10fc_0005 NULL +#define pci_ss_list_1101_1060 NULL +#define pci_ss_list_1101_9100 NULL +#define pci_ss_list_1101_9400 NULL +#define pci_ss_list_1101_9401 NULL +#define pci_ss_list_1101_9500 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1102_0002[] = { + &pci_ss_info_1102_0002_1102_0020, + &pci_ss_info_1102_0002_1102_0021, + &pci_ss_info_1102_0002_1102_002f, + &pci_ss_info_1102_0002_1102_4001, + &pci_ss_info_1102_0002_1102_8022, + &pci_ss_info_1102_0002_1102_8023, + &pci_ss_info_1102_0002_1102_8024, + &pci_ss_info_1102_0002_1102_8025, + &pci_ss_info_1102_0002_1102_8026, + &pci_ss_info_1102_0002_1102_8027, + &pci_ss_info_1102_0002_1102_8028, + &pci_ss_info_1102_0002_1102_8031, + &pci_ss_info_1102_0002_1102_8040, + &pci_ss_info_1102_0002_1102_8051, + &pci_ss_info_1102_0002_1102_8061, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1102_0004[] = { + &pci_ss_info_1102_0004_1102_0051, + &pci_ss_info_1102_0004_1102_0053, + NULL +}; +#define pci_ss_list_1102_0006 NULL +static const pciSubsystemInfo *pci_ss_list_1102_4001[] = { + &pci_ss_info_1102_4001_1102_0010, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1102_7002[] = { + &pci_ss_info_1102_7002_1102_0020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1102_7003[] = { + &pci_ss_info_1102_7003_1102_0040, + NULL +}; +#define pci_ss_list_1102_7004 NULL +#define pci_ss_list_1102_8064 NULL +#define pci_ss_list_1102_8938 NULL +#endif +#define pci_ss_list_1103_0003 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1103_0004[] = { + &pci_ss_info_1103_0004_1103_0001, + &pci_ss_info_1103_0004_1103_0005, + NULL +}; +#define pci_ss_list_1103_0005 NULL +#define pci_ss_list_1103_0006 NULL +#define pci_ss_list_1103_0007 NULL +#define pci_ss_list_1103_0008 NULL +#endif +#define pci_ss_list_1105_1105 NULL +#define pci_ss_list_1105_8300 NULL +#define pci_ss_list_1105_8400 NULL +#define pci_ss_list_1106_0102 NULL +#define pci_ss_list_1106_0130 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0305[] = { + &pci_ss_info_1106_0305_1043_8033, + &pci_ss_info_1106_0305_1043_803e, + &pci_ss_info_1106_0305_1043_8042, + &pci_ss_info_1106_0305_147b_a401, + NULL +}; +#define pci_ss_list_1106_0391 NULL +#define pci_ss_list_1106_0501 NULL +#define pci_ss_list_1106_0505 NULL +#define pci_ss_list_1106_0561 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0571[] = { + &pci_ss_info_1106_0571_1043_8052, + &pci_ss_info_1106_0571_1106_0571, + &pci_ss_info_1106_0571_1179_0001, + &pci_ss_info_1106_0571_1458_5002, + NULL +}; +#define pci_ss_list_1106_0576 NULL +#define pci_ss_list_1106_0585 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0586[] = { + &pci_ss_info_1106_0586_1106_0000, + NULL +}; +#define pci_ss_list_1106_0595 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0596[] = { + &pci_ss_info_1106_0596_1106_0000, + &pci_ss_info_1106_0596_1458_0596, + NULL +}; +#define pci_ss_list_1106_0597 NULL +#define pci_ss_list_1106_0598 NULL +#define pci_ss_list_1106_0601 NULL +#define pci_ss_list_1106_0605 NULL +#define pci_ss_list_1106_0680 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0686[] = { + &pci_ss_info_1106_0686_1043_8033, + &pci_ss_info_1106_0686_1043_803e, + &pci_ss_info_1106_0686_1043_8040, + &pci_ss_info_1106_0686_1043_8042, + &pci_ss_info_1106_0686_1106_0000, + &pci_ss_info_1106_0686_1106_0686, + &pci_ss_info_1106_0686_1179_0001, + &pci_ss_info_1106_0686_147b_a702, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_0691[] = { + &pci_ss_info_1106_0691_1179_0001, + &pci_ss_info_1106_0691_1458_0691, + NULL +}; +#define pci_ss_list_1106_0693 NULL +#define pci_ss_list_1106_0698 NULL +#define pci_ss_list_1106_0926 NULL +#define pci_ss_list_1106_1000 NULL +#define pci_ss_list_1106_1106 NULL +#define pci_ss_list_1106_1571 NULL +#define pci_ss_list_1106_1595 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3038[] = { + &pci_ss_info_1106_3038_0925_1234, + &pci_ss_info_1106_3038_1179_0001, + NULL +}; +#define pci_ss_list_1106_3040 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3043[] = { + &pci_ss_info_1106_3043_10bd_0000, + &pci_ss_info_1106_3043_1106_0100, + &pci_ss_info_1106_3043_1186_1400, + NULL +}; +#define pci_ss_list_1106_3044 NULL +#define pci_ss_list_1106_3050 NULL +#define pci_ss_list_1106_3051 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3057[] = { + &pci_ss_info_1106_3057_1043_8033, + &pci_ss_info_1106_3057_1043_803e, + &pci_ss_info_1106_3057_1043_8040, + &pci_ss_info_1106_3057_1043_8042, + &pci_ss_info_1106_3057_1179_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3058[] = { + &pci_ss_info_1106_3058_0e11_b194, + &pci_ss_info_1106_3058_1106_4511, + &pci_ss_info_1106_3058_1458_7600, + &pci_ss_info_1106_3058_1462_3091, + &pci_ss_info_1106_3058_15dd_7609, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3059[] = { + &pci_ss_info_1106_3059_1458_a002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3065[] = { + &pci_ss_info_1106_3065_1106_0102, + &pci_ss_info_1106_3065_1186_1400, + &pci_ss_info_1106_3065_1186_1401, + NULL +}; +#define pci_ss_list_1106_3068 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3074[] = { + &pci_ss_info_1106_3074_1043_8052, + NULL +}; +#define pci_ss_list_1106_3091 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3099[] = { + &pci_ss_info_1106_3099_1043_8064, + &pci_ss_info_1106_3099_1043_807f, + NULL +}; +#define pci_ss_list_1106_3101 NULL +#define pci_ss_list_1106_3102 NULL +#define pci_ss_list_1106_3103 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3104[] = { + &pci_ss_info_1106_3104_1458_5004, + NULL +}; +#define pci_ss_list_1106_3106 NULL +#define pci_ss_list_1106_3109 NULL +#define pci_ss_list_1106_3112 NULL +#define pci_ss_list_1106_3116 NULL +#define pci_ss_list_1106_3122 NULL +#define pci_ss_list_1106_3123 NULL +#define pci_ss_list_1106_3128 NULL +#define pci_ss_list_1106_3133 NULL +#define pci_ss_list_1106_3147 NULL +#define pci_ss_list_1106_3148 NULL +#define pci_ss_list_1106_3156 NULL +#define pci_ss_list_1106_3168 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3177[] = { + &pci_ss_info_1106_3177_1458_5001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3189[] = { + &pci_ss_info_1106_3189_1458_5000, + NULL +}; +#define pci_ss_list_1106_5030 NULL +#define pci_ss_list_1106_6100 NULL +#define pci_ss_list_1106_8231 NULL +#define pci_ss_list_1106_8235 NULL +#define pci_ss_list_1106_8305 NULL +#define pci_ss_list_1106_8391 NULL +#define pci_ss_list_1106_8501 NULL +#define pci_ss_list_1106_8596 NULL +#define pci_ss_list_1106_8597 NULL +#define pci_ss_list_1106_8598 NULL +#define pci_ss_list_1106_8601 NULL +#define pci_ss_list_1106_8605 NULL +#define pci_ss_list_1106_8691 NULL +#define pci_ss_list_1106_8693 NULL +#define pci_ss_list_1106_b091 NULL +#define pci_ss_list_1106_b099 NULL +#define pci_ss_list_1106_b101 NULL +#define pci_ss_list_1106_b102 NULL +#define pci_ss_list_1106_b103 NULL +#define pci_ss_list_1106_b112 NULL +#define pci_ss_list_1106_b168 NULL +#define pci_ss_list_1107_0576 NULL +#define pci_ss_list_1108_0100 NULL +#define pci_ss_list_1108_0101 NULL +#define pci_ss_list_1108_0105 NULL +#define pci_ss_list_1108_0108 NULL +#define pci_ss_list_1108_0138 NULL +#define pci_ss_list_1108_0139 NULL +#define pci_ss_list_1108_013c NULL +#define pci_ss_list_1108_013d NULL +#define pci_ss_list_1109_1400 NULL +#define pci_ss_list_110a_0002 NULL +#define pci_ss_list_110a_0005 NULL +#define pci_ss_list_110a_2102 NULL +#define pci_ss_list_110a_4942 NULL +#define pci_ss_list_110a_6120 NULL +#define pci_ss_list_110b_0001 NULL +#define pci_ss_list_110b_0004 NULL +#define pci_ss_list_1110_6037 NULL +#define pci_ss_list_1110_6073 NULL +#define pci_ss_list_1112_2200 NULL +#define pci_ss_list_1112_2300 NULL +#define pci_ss_list_1112_2340 NULL +#define pci_ss_list_1112_2400 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1113_1211[] = { + &pci_ss_info_1113_1211_103c_1207, + &pci_ss_info_1113_1211_1113_1211, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1113_1216[] = { + &pci_ss_info_1113_1216_111a_1020, + NULL +}; +#define pci_ss_list_1113_1217 NULL +#define pci_ss_list_1113_5105 NULL +static const pciSubsystemInfo *pci_ss_list_1113_9211[] = { + &pci_ss_info_1113_9211_1113_9211, + NULL +}; +#define pci_ss_list_1113_9511 NULL +#endif +#define pci_ss_list_1116_0022 NULL +#define pci_ss_list_1116_0023 NULL +#define pci_ss_list_1116_0024 NULL +#define pci_ss_list_1116_0025 NULL +#define pci_ss_list_1116_0026 NULL +#define pci_ss_list_1116_0027 NULL +#define pci_ss_list_1116_0028 NULL +#define pci_ss_list_1117_9500 NULL +#define pci_ss_list_1117_9501 NULL +#define pci_ss_list_1119_0000 NULL +#define pci_ss_list_1119_0001 NULL +#define pci_ss_list_1119_0002 NULL +#define pci_ss_list_1119_0003 NULL +#define pci_ss_list_1119_0004 NULL +#define pci_ss_list_1119_0005 NULL +#define pci_ss_list_1119_0006 NULL +#define pci_ss_list_1119_0007 NULL +#define pci_ss_list_1119_0008 NULL +#define pci_ss_list_1119_0009 NULL +#define pci_ss_list_1119_000a NULL +#define pci_ss_list_1119_000b NULL +#define pci_ss_list_1119_000c NULL +#define pci_ss_list_1119_000d NULL +#define pci_ss_list_1119_0100 NULL +#define pci_ss_list_1119_0101 NULL +#define pci_ss_list_1119_0102 NULL +#define pci_ss_list_1119_0103 NULL +#define pci_ss_list_1119_0104 NULL +#define pci_ss_list_1119_0105 NULL +#define pci_ss_list_1119_0110 NULL +#define pci_ss_list_1119_0111 NULL +#define pci_ss_list_1119_0112 NULL +#define pci_ss_list_1119_0113 NULL +#define pci_ss_list_1119_0114 NULL +#define pci_ss_list_1119_0115 NULL +#define pci_ss_list_1119_0118 NULL +#define pci_ss_list_1119_0119 NULL +#define pci_ss_list_1119_011a NULL +#define pci_ss_list_1119_011b NULL +#define pci_ss_list_1119_0120 NULL +#define pci_ss_list_1119_0121 NULL +#define pci_ss_list_1119_0122 NULL +#define pci_ss_list_1119_0123 NULL +#define pci_ss_list_1119_0124 NULL +#define pci_ss_list_1119_0125 NULL +#define pci_ss_list_1119_0136 NULL +#define pci_ss_list_1119_0137 NULL +#define pci_ss_list_1119_0138 NULL +#define pci_ss_list_1119_0139 NULL +#define pci_ss_list_1119_013a NULL +#define pci_ss_list_1119_013b NULL +#define pci_ss_list_1119_013c NULL +#define pci_ss_list_1119_013d NULL +#define pci_ss_list_1119_013e NULL +#define pci_ss_list_1119_013f NULL +#define pci_ss_list_1119_0166 NULL +#define pci_ss_list_1119_0167 NULL +#define pci_ss_list_1119_0168 NULL +#define pci_ss_list_1119_0169 NULL +#define pci_ss_list_1119_016a NULL +#define pci_ss_list_1119_016b NULL +#define pci_ss_list_1119_016c NULL +#define pci_ss_list_1119_016d NULL +#define pci_ss_list_1119_016e NULL +#define pci_ss_list_1119_016f NULL +#define pci_ss_list_1119_01d6 NULL +#define pci_ss_list_1119_01d7 NULL +#define pci_ss_list_1119_01f6 NULL +#define pci_ss_list_1119_01f7 NULL +#define pci_ss_list_1119_01fc NULL +#define pci_ss_list_1119_01fd NULL +#define pci_ss_list_1119_01fe NULL +#define pci_ss_list_1119_01ff NULL +#define pci_ss_list_1119_0210 NULL +#define pci_ss_list_1119_0211 NULL +#define pci_ss_list_1119_0260 NULL +#define pci_ss_list_1119_0261 NULL +#define pci_ss_list_1119_0300 NULL +#define pci_ss_list_111a_0000 NULL +#define pci_ss_list_111a_0002 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_111a_0003[] = { + &pci_ss_info_111a_0003_111a_0000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_111a_0005[] = { + &pci_ss_info_111a_0005_111a_0001, + &pci_ss_info_111a_0005_111a_0009, + &pci_ss_info_111a_0005_111a_0101, + &pci_ss_info_111a_0005_111a_0109, + &pci_ss_info_111a_0005_111a_0809, + &pci_ss_info_111a_0005_111a_0909, + &pci_ss_info_111a_0005_111a_0a09, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_111a_0007[] = { + &pci_ss_info_111a_0007_111a_1001, + NULL +}; +#endif +#define pci_ss_list_111c_0001 NULL +#define pci_ss_list_111d_0001 NULL +#define pci_ss_list_111d_0003 NULL +#define pci_ss_list_111f_4a47 NULL +#define pci_ss_list_111f_5243 NULL +#define pci_ss_list_1127_0200 NULL +#define pci_ss_list_1127_0210 NULL +#define pci_ss_list_1127_0250 NULL +#define pci_ss_list_1127_0300 NULL +#define pci_ss_list_1127_0310 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1127_0400[] = { + &pci_ss_info_1127_0400_1127_0400, + NULL +}; +#endif +#define pci_ss_list_112f_0000 NULL +#define pci_ss_list_112f_0001 NULL +#define pci_ss_list_1131_1561 NULL +#define pci_ss_list_1131_1562 NULL +#define pci_ss_list_1131_3400 NULL +#define pci_ss_list_1131_7130 NULL +#define pci_ss_list_1131_7133 NULL +#define pci_ss_list_1131_7134 NULL +#define pci_ss_list_1131_7135 NULL +#define pci_ss_list_1131_7145 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1131_7146[] = { + &pci_ss_info_1131_7146_114b_2003, + &pci_ss_info_1131_7146_11bd_0006, + &pci_ss_info_1131_7146_11bd_000a, + NULL +}; +#endif +#define pci_ss_list_1133_7901 NULL +#define pci_ss_list_1133_7902 NULL +#define pci_ss_list_1133_7911 NULL +#define pci_ss_list_1133_7912 NULL +#define pci_ss_list_1133_7941 NULL +#define pci_ss_list_1133_7942 NULL +#define pci_ss_list_1133_7943 NULL +#define pci_ss_list_1133_7944 NULL +#define pci_ss_list_1133_b921 NULL +#define pci_ss_list_1133_b922 NULL +#define pci_ss_list_1133_b923 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1133_e001[] = { + &pci_ss_info_1133_e001_1133_e001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1133_e002[] = { + &pci_ss_info_1133_e002_1133_e002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1133_e003[] = { + &pci_ss_info_1133_e003_1133_e003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1133_e004[] = { + &pci_ss_info_1133_e004_1133_e004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1133_e005[] = { + &pci_ss_info_1133_e005_1133_e005, + NULL +}; +#define pci_ss_list_1133_e00b NULL +static const pciSubsystemInfo *pci_ss_list_1133_e010[] = { + &pci_ss_info_1133_e010_1133_e010, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1133_e012[] = { + &pci_ss_info_1133_e012_1133_e012, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1133_e014[] = { + &pci_ss_info_1133_e014_1133_e014, + NULL +}; +#define pci_ss_list_1133_e018 NULL +#endif +#define pci_ss_list_1134_0001 NULL +#define pci_ss_list_1135_0001 NULL +#define pci_ss_list_1138_8905 NULL +#define pci_ss_list_1139_0001 NULL +#define pci_ss_list_113c_0000 NULL +#define pci_ss_list_113c_0001 NULL +#define pci_ss_list_113c_0911 NULL +#define pci_ss_list_113c_0912 NULL +#define pci_ss_list_113c_0913 NULL +#define pci_ss_list_113c_0914 NULL +#define pci_ss_list_113f_0808 NULL +#define pci_ss_list_113f_1010 NULL +#define pci_ss_list_113f_80c0 NULL +#define pci_ss_list_113f_80c4 NULL +#define pci_ss_list_113f_80c8 NULL +#define pci_ss_list_113f_8888 NULL +#define pci_ss_list_113f_9090 NULL +#define pci_ss_list_1142_3210 NULL +#define pci_ss_list_1142_6422 NULL +#define pci_ss_list_1142_6424 NULL +#define pci_ss_list_1142_6425 NULL +#define pci_ss_list_1142_643d NULL +#define pci_ss_list_1144_0001 NULL +#define pci_ss_list_1145_8007 NULL +#define pci_ss_list_1145_f007 NULL +#define pci_ss_list_1145_f010 NULL +#define pci_ss_list_1145_f012 NULL +#define pci_ss_list_1145_f013 NULL +#define pci_ss_list_1145_f015 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1148_4000[] = { + &pci_ss_info_1148_4000_0e11_b03b, + &pci_ss_info_1148_4000_0e11_b03c, + &pci_ss_info_1148_4000_0e11_b03d, + &pci_ss_info_1148_4000_0e11_b03e, + &pci_ss_info_1148_4000_0e11_b03f, + &pci_ss_info_1148_4000_1148_5521, + &pci_ss_info_1148_4000_1148_5522, + &pci_ss_info_1148_4000_1148_5541, + &pci_ss_info_1148_4000_1148_5543, + &pci_ss_info_1148_4000_1148_5544, + &pci_ss_info_1148_4000_1148_5821, + &pci_ss_info_1148_4000_1148_5822, + &pci_ss_info_1148_4000_1148_5841, + &pci_ss_info_1148_4000_1148_5843, + &pci_ss_info_1148_4000_1148_5844, + NULL +}; +#define pci_ss_list_1148_4200 NULL +static const pciSubsystemInfo *pci_ss_list_1148_4300[] = { + &pci_ss_info_1148_4300_1148_9821, + &pci_ss_info_1148_4300_1148_9822, + &pci_ss_info_1148_4300_1148_9841, + &pci_ss_info_1148_4300_1148_9842, + &pci_ss_info_1148_4300_1148_9843, + &pci_ss_info_1148_4300_1148_9844, + &pci_ss_info_1148_4300_1148_9861, + &pci_ss_info_1148_4300_1148_9862, + &pci_ss_info_1148_4300_1148_9871, + &pci_ss_info_1148_4300_1148_9872, + &pci_ss_info_1148_4300_1259_2970, + &pci_ss_info_1148_4300_1259_2972, + &pci_ss_info_1148_4300_1259_2975, + &pci_ss_info_1148_4300_1259_2977, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1148_4320[] = { + &pci_ss_info_1148_4320_1148_5021, + &pci_ss_info_1148_4320_1148_5041, + &pci_ss_info_1148_4320_1148_5043, + &pci_ss_info_1148_4320_1148_5051, + &pci_ss_info_1148_4320_1148_5061, + &pci_ss_info_1148_4320_1148_5071, + &pci_ss_info_1148_4320_1148_9521, + NULL +}; +#define pci_ss_list_1148_4400 NULL +#endif +#define pci_ss_list_114a_5579 NULL +#define pci_ss_list_114a_5587 NULL +#define pci_ss_list_114a_6504 NULL +#define pci_ss_list_114a_7587 NULL +#define pci_ss_list_114f_0002 NULL +#define pci_ss_list_114f_0003 NULL +#define pci_ss_list_114f_0004 NULL +#define pci_ss_list_114f_0005 NULL +#define pci_ss_list_114f_0006 NULL +#define pci_ss_list_114f_0009 NULL +#define pci_ss_list_114f_000a NULL +#define pci_ss_list_114f_000c NULL +#define pci_ss_list_114f_000d NULL +#define pci_ss_list_114f_0011 NULL +#define pci_ss_list_114f_0012 NULL +#define pci_ss_list_114f_0013 NULL +#define pci_ss_list_114f_0014 NULL +#define pci_ss_list_114f_0015 NULL +#define pci_ss_list_114f_0016 NULL +#define pci_ss_list_114f_0017 NULL +#define pci_ss_list_114f_001a NULL +#define pci_ss_list_114f_001b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_114f_001d[] = { + &pci_ss_info_114f_001d_114f_0050, + &pci_ss_info_114f_001d_114f_0051, + &pci_ss_info_114f_001d_114f_0052, + &pci_ss_info_114f_001d_114f_0053, + NULL +}; +#define pci_ss_list_114f_0023 NULL +static const pciSubsystemInfo *pci_ss_list_114f_0024[] = { + &pci_ss_info_114f_0024_114f_0030, + &pci_ss_info_114f_0024_114f_0031, + NULL +}; +#define pci_ss_list_114f_0026 NULL +#define pci_ss_list_114f_0027 NULL +#define pci_ss_list_114f_0034 NULL +#define pci_ss_list_114f_0035 NULL +#define pci_ss_list_114f_0040 NULL +#define pci_ss_list_114f_0042 NULL +#define pci_ss_list_114f_0070 NULL +#define pci_ss_list_114f_0071 NULL +#define pci_ss_list_114f_0072 NULL +#define pci_ss_list_114f_0073 NULL +#define pci_ss_list_114f_6001 NULL +#endif +#define pci_ss_list_1158_3011 NULL +#define pci_ss_list_1158_9050 NULL +#define pci_ss_list_1158_9051 NULL +#define pci_ss_list_1159_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_115d_0003[] = { + &pci_ss_info_115d_0003_1014_0181, + &pci_ss_info_115d_0003_1014_1181, + &pci_ss_info_115d_0003_1014_8181, + &pci_ss_info_115d_0003_1014_9181, + &pci_ss_info_115d_0003_115d_0181, + &pci_ss_info_115d_0003_115d_1181, + &pci_ss_info_115d_0003_1179_0181, + &pci_ss_info_115d_0003_8086_8181, + &pci_ss_info_115d_0003_8086_9181, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_115d_0005[] = { + &pci_ss_info_115d_0005_1014_0182, + &pci_ss_info_115d_0005_1014_1182, + &pci_ss_info_115d_0005_115d_0182, + &pci_ss_info_115d_0005_115d_1182, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_115d_0007[] = { + &pci_ss_info_115d_0007_1014_0182, + &pci_ss_info_115d_0007_1014_1182, + &pci_ss_info_115d_0007_115d_0182, + &pci_ss_info_115d_0007_115d_1182, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_115d_000b[] = { + &pci_ss_info_115d_000b_1014_0183, + &pci_ss_info_115d_000b_115d_0183, + NULL +}; +#define pci_ss_list_115d_000c NULL +static const pciSubsystemInfo *pci_ss_list_115d_000f[] = { + &pci_ss_info_115d_000f_1014_0183, + &pci_ss_info_115d_000f_115d_0183, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_115d_0101[] = { + &pci_ss_info_115d_0101_115d_1081, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_115d_0103[] = { + &pci_ss_info_115d_0103_1014_9181, + &pci_ss_info_115d_0103_1115_1181, + &pci_ss_info_115d_0103_115d_1181, + &pci_ss_info_115d_0103_8086_9181, + NULL +}; +#endif +#define pci_ss_list_1163_0001 NULL +static const pciSubsystemInfo *pci_ss_list_1163_2000[] = { + &pci_ss_info_1163_2000_1092_2000, + NULL +}; +#define pci_ss_list_1165_0001 NULL +#define pci_ss_list_1166_0005 NULL +#define pci_ss_list_1166_0007 NULL +#define pci_ss_list_1166_0008 NULL +#define pci_ss_list_1166_0009 NULL +#define pci_ss_list_1166_0010 NULL +#define pci_ss_list_1166_0011 NULL +#define pci_ss_list_1166_0012 NULL +#define pci_ss_list_1166_0013 NULL +#define pci_ss_list_1166_0014 NULL +#define pci_ss_list_1166_0015 NULL +#define pci_ss_list_1166_0016 NULL +#define pci_ss_list_1166_0017 NULL +#define pci_ss_list_1166_0200 NULL +#define pci_ss_list_1166_0201 NULL +#define pci_ss_list_1166_0203 NULL +#define pci_ss_list_1166_0211 NULL +#define pci_ss_list_1166_0212 NULL +#define pci_ss_list_1166_0213 NULL +#define pci_ss_list_1166_0220 NULL +#define pci_ss_list_1166_0221 NULL +#define pci_ss_list_1166_0225 NULL +#define pci_ss_list_1166_0227 NULL +#define pci_ss_list_116a_6100 NULL +#define pci_ss_list_116a_6800 NULL +#define pci_ss_list_116a_7100 NULL +#define pci_ss_list_116a_7800 NULL +#define pci_ss_list_1178_afa1 NULL +#define pci_ss_list_1179_0103 NULL +#define pci_ss_list_1179_0404 NULL +#define pci_ss_list_1179_0406 NULL +#define pci_ss_list_1179_0407 NULL +#define pci_ss_list_1179_0601 NULL +#define pci_ss_list_1179_0603 NULL +#define pci_ss_list_1179_060a NULL +#define pci_ss_list_1179_060f NULL +#define pci_ss_list_1179_0617 NULL +#define pci_ss_list_1179_0618 NULL +#define pci_ss_list_1179_0701 NULL +#define pci_ss_list_1179_0804 NULL +#define pci_ss_list_1179_0805 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1179_0d01[] = { + &pci_ss_info_1179_0d01_1179_0001, + NULL +}; +#endif +#define pci_ss_list_1180_0465 NULL +#define pci_ss_list_1180_0466 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1180_0475[] = { + &pci_ss_info_1180_0475_144d_c006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1180_0476[] = { + &pci_ss_info_1180_0476_1014_0185, + &pci_ss_info_1180_0476_104d_80df, + &pci_ss_info_1180_0476_104d_80e7, + NULL +}; +#define pci_ss_list_1180_0477 NULL +static const pciSubsystemInfo *pci_ss_list_1180_0478[] = { + &pci_ss_info_1180_0478_1014_0184, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1180_0522[] = { + &pci_ss_info_1180_0522_1014_01cf, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1180_0551[] = { + &pci_ss_info_1180_0551_144d_c006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1180_0552[] = { + &pci_ss_info_1180_0552_1014_0511, + NULL +}; +#endif +#define pci_ss_list_1186_0100 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1186_1002[] = { + &pci_ss_info_1186_1002_1186_1002, + &pci_ss_info_1186_1002_1186_1012, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1186_1300[] = { + &pci_ss_info_1186_1300_1186_1300, + &pci_ss_info_1186_1300_1186_1301, + NULL +}; +#define pci_ss_list_1186_1340 NULL +#define pci_ss_list_1186_1561 NULL +#define pci_ss_list_1186_4000 NULL +#endif +#define pci_ss_list_118c_0014 NULL +#define pci_ss_list_118c_1117 NULL +#define pci_ss_list_118d_0001 NULL +#define pci_ss_list_118d_0012 NULL +#define pci_ss_list_118d_0014 NULL +#define pci_ss_list_118d_0024 NULL +#define pci_ss_list_118d_0044 NULL +#define pci_ss_list_118d_0112 NULL +#define pci_ss_list_118d_0114 NULL +#define pci_ss_list_118d_0124 NULL +#define pci_ss_list_118d_0144 NULL +#define pci_ss_list_118d_0212 NULL +#define pci_ss_list_118d_0214 NULL +#define pci_ss_list_118d_0224 NULL +#define pci_ss_list_118d_0244 NULL +#define pci_ss_list_118d_0312 NULL +#define pci_ss_list_118d_0314 NULL +#define pci_ss_list_118d_0324 NULL +#define pci_ss_list_118d_0344 NULL +#define pci_ss_list_1190_c731 NULL +#define pci_ss_list_1191_0003 NULL +#define pci_ss_list_1191_0004 NULL +#define pci_ss_list_1191_0005 NULL +#define pci_ss_list_1191_0006 NULL +#define pci_ss_list_1191_0007 NULL +#define pci_ss_list_1191_0008 NULL +#define pci_ss_list_1191_0009 NULL +#define pci_ss_list_1191_8002 NULL +#define pci_ss_list_1191_8010 NULL +#define pci_ss_list_1191_8020 NULL +#define pci_ss_list_1191_8030 NULL +#define pci_ss_list_1191_8040 NULL +#define pci_ss_list_1191_8050 NULL +#define pci_ss_list_1193_0001 NULL +#define pci_ss_list_1193_0002 NULL +#define pci_ss_list_119b_1221 NULL +#define pci_ss_list_119e_0001 NULL +#define pci_ss_list_119e_0003 NULL +#define pci_ss_list_11a9_4240 NULL +#define pci_ss_list_11ab_0146 NULL +#define pci_ss_list_11ab_4611 NULL +#define pci_ss_list_11ab_4620 NULL +#define pci_ss_list_11ab_4801 NULL +#define pci_ss_list_11ab_f003 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11ad_0002[] = { + &pci_ss_info_11ad_0002_11ad_0002, + &pci_ss_info_11ad_0002_11ad_0003, + &pci_ss_info_11ad_0002_11ad_f003, + &pci_ss_info_11ad_0002_11ad_ffff, + &pci_ss_info_11ad_0002_1385_f004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11ad_c115[] = { + &pci_ss_info_11ad_c115_11ad_c001, + NULL +}; +#endif +#define pci_ss_list_11b0_0002 NULL +#define pci_ss_list_11b0_0292 NULL +#define pci_ss_list_11b0_0960 NULL +#define pci_ss_list_11b0_c960 NULL +#define pci_ss_list_11b8_0001 NULL +#define pci_ss_list_11b9_c0ed NULL +#define pci_ss_list_11bc_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11c1_0440[] = { + &pci_ss_info_11c1_0440_1033_8015, + &pci_ss_info_11c1_0440_1033_8047, + &pci_ss_info_11c1_0440_1033_804f, + &pci_ss_info_11c1_0440_10cf_102c, + &pci_ss_info_11c1_0440_10cf_104a, + &pci_ss_info_11c1_0440_10cf_105f, + &pci_ss_info_11c1_0440_1179_0001, + &pci_ss_info_11c1_0440_11c1_0440, + &pci_ss_info_11c1_0440_122d_4101, + &pci_ss_info_11c1_0440_122d_4102, + &pci_ss_info_11c1_0440_13e0_0040, + &pci_ss_info_11c1_0440_13e0_0440, + &pci_ss_info_11c1_0440_13e0_0441, + &pci_ss_info_11c1_0440_13e0_0450, + &pci_ss_info_11c1_0440_13e0_f100, + &pci_ss_info_11c1_0440_13e0_f101, + &pci_ss_info_11c1_0440_144d_2101, + &pci_ss_info_11c1_0440_149f_0440, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11c1_0441[] = { + &pci_ss_info_11c1_0441_1033_804d, + &pci_ss_info_11c1_0441_1033_8065, + &pci_ss_info_11c1_0441_1092_0440, + &pci_ss_info_11c1_0441_1179_0001, + &pci_ss_info_11c1_0441_11c1_0440, + &pci_ss_info_11c1_0441_11c1_0441, + &pci_ss_info_11c1_0441_122d_4100, + &pci_ss_info_11c1_0441_13e0_0040, + &pci_ss_info_11c1_0441_13e0_0100, + &pci_ss_info_11c1_0441_13e0_0410, + &pci_ss_info_11c1_0441_13e0_0420, + &pci_ss_info_11c1_0441_13e0_0440, + &pci_ss_info_11c1_0441_13e0_0443, + &pci_ss_info_11c1_0441_13e0_f102, + &pci_ss_info_11c1_0441_1416_9804, + &pci_ss_info_11c1_0441_141d_0440, + &pci_ss_info_11c1_0441_144f_0441, + &pci_ss_info_11c1_0441_144f_0449, + &pci_ss_info_11c1_0441_144f_110d, + &pci_ss_info_11c1_0441_1468_0441, + &pci_ss_info_11c1_0441_1668_0440, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11c1_0442[] = { + &pci_ss_info_11c1_0442_11c1_0440, + &pci_ss_info_11c1_0442_11c1_0442, + &pci_ss_info_11c1_0442_13e0_0412, + &pci_ss_info_11c1_0442_13e0_0442, + &pci_ss_info_11c1_0442_13fc_2471, + &pci_ss_info_11c1_0442_144d_2104, + &pci_ss_info_11c1_0442_144f_1104, + &pci_ss_info_11c1_0442_149f_0440, + &pci_ss_info_11c1_0442_1668_0440, + NULL +}; +#define pci_ss_list_11c1_0443 NULL +#define pci_ss_list_11c1_0444 NULL +#define pci_ss_list_11c1_0445 NULL +#define pci_ss_list_11c1_0446 NULL +#define pci_ss_list_11c1_0447 NULL +static const pciSubsystemInfo *pci_ss_list_11c1_0448[] = { + &pci_ss_info_11c1_0448_1014_0131, + &pci_ss_info_11c1_0448_1033_8066, + &pci_ss_info_11c1_0448_13e0_0030, + &pci_ss_info_11c1_0448_13e0_0040, + &pci_ss_info_11c1_0448_1668_2400, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11c1_0449[] = { + &pci_ss_info_11c1_0449_0e11_b14d, + &pci_ss_info_11c1_0449_13e0_0020, + &pci_ss_info_11c1_0449_13e0_0041, + &pci_ss_info_11c1_0449_1436_0440, + &pci_ss_info_11c1_0449_144f_0449, + &pci_ss_info_11c1_0449_1468_0410, + &pci_ss_info_11c1_0449_1468_0440, + &pci_ss_info_11c1_0449_1468_0449, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11c1_044a[] = { + &pci_ss_info_11c1_044a_10cf_1072, + &pci_ss_info_11c1_044a_13e0_0012, + &pci_ss_info_11c1_044a_13e0_0042, + &pci_ss_info_11c1_044a_144f_1005, + NULL +}; +#define pci_ss_list_11c1_044b NULL +#define pci_ss_list_11c1_044c NULL +#define pci_ss_list_11c1_044d NULL +#define pci_ss_list_11c1_044e NULL +#define pci_ss_list_11c1_044f NULL +static const pciSubsystemInfo *pci_ss_list_11c1_0450[] = { + &pci_ss_info_11c1_0450_144f_4005, + NULL +}; +#define pci_ss_list_11c1_0451 NULL +#define pci_ss_list_11c1_0452 NULL +#define pci_ss_list_11c1_0453 NULL +#define pci_ss_list_11c1_0454 NULL +#define pci_ss_list_11c1_0455 NULL +#define pci_ss_list_11c1_0456 NULL +#define pci_ss_list_11c1_0457 NULL +#define pci_ss_list_11c1_0458 NULL +#define pci_ss_list_11c1_0459 NULL +#define pci_ss_list_11c1_045a NULL +#define pci_ss_list_11c1_045c NULL +#define pci_ss_list_11c1_0461 NULL +#define pci_ss_list_11c1_0462 NULL +#define pci_ss_list_11c1_0480 NULL +#define pci_ss_list_11c1_5801 NULL +#define pci_ss_list_11c1_5802 NULL +#define pci_ss_list_11c1_5803 NULL +static const pciSubsystemInfo *pci_ss_list_11c1_5811[] = { + &pci_ss_info_11c1_5811_dead_0800, + NULL +}; +#endif +#define pci_ss_list_11c8_0658 NULL +#define pci_ss_list_11c8_d665 NULL +#define pci_ss_list_11c8_d667 NULL +#define pci_ss_list_11c9_0010 NULL +#define pci_ss_list_11c9_0011 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11cb_2000[] = { + &pci_ss_info_11cb_2000_11cb_0200, + &pci_ss_info_11cb_2000_11cb_b008, + NULL +}; +#define pci_ss_list_11cb_4000 NULL +#define pci_ss_list_11cb_8000 NULL +#endif +#define pci_ss_list_11d1_01f7 NULL +#define pci_ss_list_11d4_1805 NULL +#define pci_ss_list_11d4_1889 NULL +#define pci_ss_list_11d5_0115 NULL +#define pci_ss_list_11d5_0117 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11de_6057[] = { + &pci_ss_info_11de_6057_1031_7efe, + &pci_ss_info_11de_6057_1031_fc00, + &pci_ss_info_11de_6057_13ca_4231, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11de_6120[] = { + &pci_ss_info_11de_6120_1328_f001, + NULL +}; +#endif +#define pci_ss_list_11e3_5030 NULL +#define pci_ss_list_11f0_4231 NULL +#define pci_ss_list_11f0_4232 NULL +#define pci_ss_list_11f0_4233 NULL +#define pci_ss_list_11f0_4234 NULL +#define pci_ss_list_11f0_4235 NULL +#define pci_ss_list_11f0_4236 NULL +#define pci_ss_list_11f0_4731 NULL +#define pci_ss_list_11f4_2915 NULL +#define pci_ss_list_11f6_0112 NULL +#define pci_ss_list_11f6_0113 NULL +#define pci_ss_list_11f6_1401 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11f6_2011[] = { + &pci_ss_info_11f6_2011_11f6_2011, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11f6_2201[] = { + &pci_ss_info_11f6_2201_11f6_2011, + NULL +}; +#define pci_ss_list_11f6_9881 NULL +#endif +#define pci_ss_list_11f8_7375 NULL +#define pci_ss_list_11fe_0001 NULL +#define pci_ss_list_11fe_0002 NULL +#define pci_ss_list_11fe_0003 NULL +#define pci_ss_list_11fe_0004 NULL +#define pci_ss_list_11fe_0005 NULL +#define pci_ss_list_11fe_0006 NULL +#define pci_ss_list_11fe_0007 NULL +#define pci_ss_list_11fe_0008 NULL +#define pci_ss_list_11fe_0009 NULL +#define pci_ss_list_11fe_000a NULL +#define pci_ss_list_11fe_000b NULL +#define pci_ss_list_11fe_000c NULL +#define pci_ss_list_11fe_8015 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1202_4300[] = { + &pci_ss_info_1202_4300_1202_9841, + &pci_ss_info_1202_4300_1202_9842, + &pci_ss_info_1202_4300_1202_9843, + &pci_ss_info_1202_4300_1202_9844, + NULL +}; +#endif +#define pci_ss_list_1208_4853 NULL +#define pci_ss_list_120e_0100 NULL +#define pci_ss_list_120e_0101 NULL +#define pci_ss_list_120e_0102 NULL +#define pci_ss_list_120e_0103 NULL +#define pci_ss_list_120e_0104 NULL +#define pci_ss_list_120e_0105 NULL +#define pci_ss_list_120e_0200 NULL +#define pci_ss_list_120e_0201 NULL +#define pci_ss_list_120e_0300 NULL +#define pci_ss_list_120e_0301 NULL +#define pci_ss_list_120e_0310 NULL +#define pci_ss_list_120e_0311 NULL +#define pci_ss_list_120e_0320 NULL +#define pci_ss_list_120e_0321 NULL +#define pci_ss_list_120e_0400 NULL +#define pci_ss_list_120f_0001 NULL +#define pci_ss_list_1217_6729 NULL +#define pci_ss_list_1217_673a NULL +#define pci_ss_list_1217_6832 NULL +#define pci_ss_list_1217_6836 NULL +#define pci_ss_list_1217_6872 NULL +#define pci_ss_list_1217_6925 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1217_6933[] = { + &pci_ss_info_1217_6933_1025_1016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1217_6972[] = { + &pci_ss_info_1217_6972_1179_0001, + NULL +}; +#endif +#define pci_ss_list_121a_0001 NULL +#define pci_ss_list_121a_0002 NULL +static const pciSubsystemInfo *pci_ss_list_121a_0003[] = { + &pci_ss_info_121a_0003_1092_0003, + &pci_ss_info_121a_0003_1092_4000, + &pci_ss_info_121a_0003_1092_4002, + &pci_ss_info_121a_0003_1092_4801, + &pci_ss_info_121a_0003_1092_4803, + &pci_ss_info_121a_0003_1092_8030, + &pci_ss_info_121a_0003_1092_8035, + &pci_ss_info_121a_0003_10b0_0001, + &pci_ss_info_121a_0003_1102_1018, + &pci_ss_info_121a_0003_121a_0001, + &pci_ss_info_121a_0003_121a_0003, + &pci_ss_info_121a_0003_121a_0004, + &pci_ss_info_121a_0003_139c_0016, + &pci_ss_info_121a_0003_139c_0017, + &pci_ss_info_121a_0003_14af_0002, + NULL +}; +#define pci_ss_list_121a_0004 NULL +static const pciSubsystemInfo *pci_ss_list_121a_0005[] = { + &pci_ss_info_121a_0005_121a_0004, + &pci_ss_info_121a_0005_121a_0030, + &pci_ss_info_121a_0005_121a_0031, + &pci_ss_info_121a_0005_121a_0034, + &pci_ss_info_121a_0005_121a_0036, + &pci_ss_info_121a_0005_121a_0037, + &pci_ss_info_121a_0005_121a_0038, + &pci_ss_info_121a_0005_121a_003a, + &pci_ss_info_121a_0005_121a_0044, + &pci_ss_info_121a_0005_121a_004b, + &pci_ss_info_121a_0005_121a_004c, + &pci_ss_info_121a_0005_121a_004d, + &pci_ss_info_121a_0005_121a_004e, + &pci_ss_info_121a_0005_121a_0051, + &pci_ss_info_121a_0005_121a_0052, + &pci_ss_info_121a_0005_121a_0060, + &pci_ss_info_121a_0005_121a_0061, + &pci_ss_info_121a_0005_121a_0062, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_121a_0009[] = { + &pci_ss_info_121a_0009_121a_0009, + NULL +}; +#define pci_ss_list_121a_0057 NULL +#define pci_ss_list_1220_1220 NULL +#define pci_ss_list_1223_0003 NULL +#define pci_ss_list_1223_0004 NULL +#define pci_ss_list_1223_0005 NULL +#define pci_ss_list_1223_0008 NULL +#define pci_ss_list_1223_0009 NULL +#define pci_ss_list_1223_000a NULL +#define pci_ss_list_1223_000b NULL +#define pci_ss_list_1223_000c NULL +#define pci_ss_list_1223_000d NULL +#define pci_ss_list_1223_000e NULL +#define pci_ss_list_122d_1206 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_122d_50dc[] = { + &pci_ss_info_122d_50dc_122d_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_122d_80da[] = { + &pci_ss_info_122d_80da_122d_0001, + NULL +}; +#endif +#define pci_ss_list_1236_0000 NULL +#define pci_ss_list_1236_6401 NULL +#define pci_ss_list_123d_0000 NULL +#define pci_ss_list_123d_0002 NULL +#define pci_ss_list_123d_0003 NULL +#define pci_ss_list_123f_00e4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_123f_8120[] = { + &pci_ss_info_123f_8120_11bd_0006, + &pci_ss_info_123f_8120_11bd_000a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_123f_8888[] = { + &pci_ss_info_123f_8888_1002_0001, + &pci_ss_info_123f_8888_1002_0002, + &pci_ss_info_123f_8888_1328_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1242_1560[] = { + &pci_ss_info_1242_1560_1242_6562, + &pci_ss_info_1242_1560_1242_656a, + NULL +}; +#define pci_ss_list_1242_4643 NULL +#endif +#define pci_ss_list_1244_0700 NULL +#define pci_ss_list_1244_0800 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1244_0a00[] = { + &pci_ss_info_1244_0a00_1244_0a00, + NULL +}; +#define pci_ss_list_1244_0e00 NULL +#define pci_ss_list_1244_1100 NULL +#define pci_ss_list_1244_1200 NULL +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_124b_0040[] = { + &pci_ss_info_124b_0040_124b_9080, + NULL +}; +#endif +#define pci_ss_list_124d_0000 NULL +#define pci_ss_list_124d_0002 NULL +#define pci_ss_list_124d_0003 NULL +#define pci_ss_list_124d_0004 NULL +#define pci_ss_list_124f_0041 NULL +#define pci_ss_list_1255_1110 NULL +#define pci_ss_list_1255_1210 NULL +#define pci_ss_list_1255_2110 NULL +#define pci_ss_list_1255_2120 NULL +#define pci_ss_list_1255_2130 NULL +#define pci_ss_list_1256_4201 NULL +#define pci_ss_list_1256_4401 NULL +#define pci_ss_list_1256_5201 NULL +#define pci_ss_list_1259_2560 NULL +#define pci_ss_list_125b_1400 NULL +#define pci_ss_list_125c_0640 NULL +#define pci_ss_list_125d_0000 NULL +#define pci_ss_list_125d_1948 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_125d_1968[] = { + &pci_ss_info_125d_1968_1028_0085, + &pci_ss_info_125d_1968_1033_8051, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1969[] = { + &pci_ss_info_125d_1969_1014_0166, + &pci_ss_info_125d_1969_125d_8888, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1978[] = { + &pci_ss_info_125d_1978_0e11_b112, + &pci_ss_info_125d_1978_1033_803c, + &pci_ss_info_125d_1978_1033_8058, + &pci_ss_info_125d_1978_1092_4000, + &pci_ss_info_125d_1978_1179_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1988[] = { + &pci_ss_info_125d_1988_1092_4100, + &pci_ss_info_125d_1988_125d_1988, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1989[] = { + &pci_ss_info_125d_1989_125d_1989, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1998[] = { + &pci_ss_info_125d_1998_1028_00e6, + NULL +}; +#define pci_ss_list_125d_1999 NULL +#define pci_ss_list_125d_199a NULL +#define pci_ss_list_125d_199b NULL +#define pci_ss_list_125d_2808 NULL +#define pci_ss_list_125d_2838 NULL +static const pciSubsystemInfo *pci_ss_list_125d_2898[] = { + &pci_ss_info_125d_2898_125d_0424, + &pci_ss_info_125d_2898_125d_0425, + &pci_ss_info_125d_2898_125d_0426, + &pci_ss_info_125d_2898_125d_0427, + &pci_ss_info_125d_2898_125d_0428, + &pci_ss_info_125d_2898_125d_0429, + &pci_ss_info_125d_2898_147a_c001, + &pci_ss_info_125d_2898_14fe_0428, + &pci_ss_info_125d_2898_14fe_0429, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1260_3873[] = { + &pci_ss_info_1260_3873_1186_3501, + &pci_ss_info_1260_3873_1668_0414, + &pci_ss_info_1260_3873_1737_3874, + &pci_ss_info_1260_3873_8086_2513, + NULL +}; +#define pci_ss_list_1260_8130 NULL +#define pci_ss_list_1260_8131 NULL +#endif +#define pci_ss_list_1266_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1266_1910[] = { + &pci_ss_info_1266_1910_1266_1910, + NULL +}; +#endif +#define pci_ss_list_1267_5352 NULL +#define pci_ss_list_1267_5a4b NULL +#define pci_ss_list_126f_0710 NULL +#define pci_ss_list_126f_0712 NULL +#define pci_ss_list_126f_0720 NULL +#define pci_ss_list_126f_0810 NULL +#define pci_ss_list_126f_0811 NULL +#define pci_ss_list_126f_0820 NULL +#define pci_ss_list_126f_0910 NULL +#define pci_ss_list_1273_0002 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1274_1371[] = { + &pci_ss_info_1274_1371_0e11_0024, + &pci_ss_info_1274_1371_0e11_b1a7, + &pci_ss_info_1274_1371_1033_80ac, + &pci_ss_info_1274_1371_1042_1854, + &pci_ss_info_1274_1371_107b_8054, + &pci_ss_info_1274_1371_1274_1371, + &pci_ss_info_1274_1371_1462_6470, + &pci_ss_info_1274_1371_1462_6560, + &pci_ss_info_1274_1371_1462_6630, + &pci_ss_info_1274_1371_1462_6631, + &pci_ss_info_1274_1371_1462_6632, + &pci_ss_info_1274_1371_1462_6633, + &pci_ss_info_1274_1371_1462_6820, + &pci_ss_info_1274_1371_1462_6822, + &pci_ss_info_1274_1371_1462_6830, + &pci_ss_info_1274_1371_1462_6880, + &pci_ss_info_1274_1371_1462_6900, + &pci_ss_info_1274_1371_1462_6910, + &pci_ss_info_1274_1371_1462_6930, + &pci_ss_info_1274_1371_1462_6990, + &pci_ss_info_1274_1371_1462_6991, + &pci_ss_info_1274_1371_14a4_2077, + &pci_ss_info_1274_1371_14a4_2105, + &pci_ss_info_1274_1371_14a4_2107, + &pci_ss_info_1274_1371_14a4_2172, + &pci_ss_info_1274_1371_1509_9902, + &pci_ss_info_1274_1371_1509_9903, + &pci_ss_info_1274_1371_1509_9904, + &pci_ss_info_1274_1371_1509_9905, + &pci_ss_info_1274_1371_152d_8801, + &pci_ss_info_1274_1371_152d_8802, + &pci_ss_info_1274_1371_152d_8803, + &pci_ss_info_1274_1371_152d_8804, + &pci_ss_info_1274_1371_152d_8805, + &pci_ss_info_1274_1371_270f_2001, + &pci_ss_info_1274_1371_270f_2200, + &pci_ss_info_1274_1371_270f_3000, + &pci_ss_info_1274_1371_270f_3100, + &pci_ss_info_1274_1371_270f_3102, + &pci_ss_info_1274_1371_270f_7060, + &pci_ss_info_1274_1371_8086_4249, + &pci_ss_info_1274_1371_8086_424c, + &pci_ss_info_1274_1371_8086_425a, + &pci_ss_info_1274_1371_8086_4341, + &pci_ss_info_1274_1371_8086_4343, + &pci_ss_info_1274_1371_8086_4649, + &pci_ss_info_1274_1371_8086_464a, + &pci_ss_info_1274_1371_8086_4d4f, + &pci_ss_info_1274_1371_8086_4f43, + &pci_ss_info_1274_1371_8086_5243, + &pci_ss_info_1274_1371_8086_5352, + &pci_ss_info_1274_1371_8086_5643, + &pci_ss_info_1274_1371_8086_5753, + NULL +}; +#define pci_ss_list_1274_5000 NULL +static const pciSubsystemInfo *pci_ss_list_1274_5880[] = { + &pci_ss_info_1274_5880_1274_2000, + &pci_ss_info_1274_5880_1274_2003, + &pci_ss_info_1274_5880_1274_5880, + &pci_ss_info_1274_5880_1458_a000, + &pci_ss_info_1274_5880_1462_6880, + &pci_ss_info_1274_5880_270f_2001, + &pci_ss_info_1274_5880_270f_2200, + &pci_ss_info_1274_5880_270f_7040, + NULL +}; +#endif +#define pci_ss_list_1278_0701 NULL +#define pci_ss_list_1279_0295 NULL +#define pci_ss_list_1279_0395 NULL +#define pci_ss_list_1279_0396 NULL +#define pci_ss_list_1279_0397 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_127a_1002[] = { + &pci_ss_info_127a_1002_1092_094c, + &pci_ss_info_127a_1002_122d_4002, + &pci_ss_info_127a_1002_122d_4005, + &pci_ss_info_127a_1002_122d_4007, + &pci_ss_info_127a_1002_122d_4012, + &pci_ss_info_127a_1002_122d_4017, + &pci_ss_info_127a_1002_122d_4018, + &pci_ss_info_127a_1002_127a_1002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1003[] = { + &pci_ss_info_127a_1003_0e11_b0bc, + &pci_ss_info_127a_1003_0e11_b114, + &pci_ss_info_127a_1003_1033_802b, + &pci_ss_info_127a_1003_13df_1003, + &pci_ss_info_127a_1003_13e0_0117, + &pci_ss_info_127a_1003_13e0_0147, + &pci_ss_info_127a_1003_13e0_0197, + &pci_ss_info_127a_1003_13e0_01c7, + &pci_ss_info_127a_1003_13e0_01f7, + &pci_ss_info_127a_1003_1436_1003, + &pci_ss_info_127a_1003_1436_1103, + &pci_ss_info_127a_1003_1436_1602, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1004[] = { + &pci_ss_info_127a_1004_1048_1500, + &pci_ss_info_127a_1004_10cf_1059, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1005[] = { + &pci_ss_info_127a_1005_1033_8029, + &pci_ss_info_127a_1005_1033_8054, + &pci_ss_info_127a_1005_10cf_103c, + &pci_ss_info_127a_1005_10cf_1055, + &pci_ss_info_127a_1005_10cf_1056, + &pci_ss_info_127a_1005_122d_4003, + &pci_ss_info_127a_1005_122d_4006, + &pci_ss_info_127a_1005_122d_4008, + &pci_ss_info_127a_1005_122d_4009, + &pci_ss_info_127a_1005_122d_4010, + &pci_ss_info_127a_1005_122d_4011, + &pci_ss_info_127a_1005_122d_4013, + &pci_ss_info_127a_1005_122d_4015, + &pci_ss_info_127a_1005_122d_4016, + &pci_ss_info_127a_1005_122d_4019, + &pci_ss_info_127a_1005_13df_1005, + &pci_ss_info_127a_1005_13e0_0187, + &pci_ss_info_127a_1005_13e0_01a7, + &pci_ss_info_127a_1005_13e0_01b7, + &pci_ss_info_127a_1005_13e0_01d7, + &pci_ss_info_127a_1005_1436_1005, + &pci_ss_info_127a_1005_1436_1105, + &pci_ss_info_127a_1005_1437_1105, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1022[] = { + &pci_ss_info_127a_1022_1436_1303, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1023[] = { + &pci_ss_info_127a_1023_122d_4020, + &pci_ss_info_127a_1023_122d_4023, + &pci_ss_info_127a_1023_13e0_0247, + &pci_ss_info_127a_1023_13e0_0297, + &pci_ss_info_127a_1023_13e0_02c7, + &pci_ss_info_127a_1023_1436_1203, + &pci_ss_info_127a_1023_1436_1303, + NULL +}; +#define pci_ss_list_127a_1024 NULL +static const pciSubsystemInfo *pci_ss_list_127a_1025[] = { + &pci_ss_info_127a_1025_10cf_106a, + &pci_ss_info_127a_1025_122d_4021, + &pci_ss_info_127a_1025_122d_4022, + &pci_ss_info_127a_1025_122d_4024, + &pci_ss_info_127a_1025_122d_4025, + NULL +}; +#define pci_ss_list_127a_1026 NULL +#define pci_ss_list_127a_1032 NULL +#define pci_ss_list_127a_1033 NULL +#define pci_ss_list_127a_1034 NULL +#define pci_ss_list_127a_1035 NULL +#define pci_ss_list_127a_1036 NULL +#define pci_ss_list_127a_1085 NULL +static const pciSubsystemInfo *pci_ss_list_127a_2005[] = { + &pci_ss_info_127a_2005_104d_8044, + &pci_ss_info_127a_2005_104d_8045, + &pci_ss_info_127a_2005_104d_8055, + &pci_ss_info_127a_2005_104d_8056, + &pci_ss_info_127a_2005_104d_805a, + &pci_ss_info_127a_2005_104d_805f, + &pci_ss_info_127a_2005_104d_8074, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_2013[] = { + &pci_ss_info_127a_2013_1179_0001, + &pci_ss_info_127a_2013_1179_ff00, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_2014[] = { + &pci_ss_info_127a_2014_10cf_1057, + &pci_ss_info_127a_2014_122d_4050, + &pci_ss_info_127a_2014_122d_4055, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_2015[] = { + &pci_ss_info_127a_2015_10cf_1063, + &pci_ss_info_127a_2015_10cf_1064, + &pci_ss_info_127a_2015_1468_2015, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_2016[] = { + &pci_ss_info_127a_2016_122d_4051, + &pci_ss_info_127a_2016_122d_4052, + &pci_ss_info_127a_2016_122d_4054, + &pci_ss_info_127a_2016_122d_4056, + &pci_ss_info_127a_2016_122d_4057, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_4311[] = { + &pci_ss_info_127a_4311_127a_4311, + &pci_ss_info_127a_4311_13e0_0210, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_4320[] = { + &pci_ss_info_127a_4320_1235_4320, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_4321[] = { + &pci_ss_info_127a_4321_1235_4321, + &pci_ss_info_127a_4321_1235_4324, + &pci_ss_info_127a_4321_13e0_0210, + &pci_ss_info_127a_4321_144d_2321, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_4322[] = { + &pci_ss_info_127a_4322_1235_4322, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_8234[] = { + &pci_ss_info_127a_8234_108d_0022, + &pci_ss_info_127a_8234_108d_0027, + NULL +}; +#endif +#define pci_ss_list_1282_9009 NULL +#define pci_ss_list_1282_9100 NULL +#define pci_ss_list_1282_9102 NULL +#define pci_ss_list_1282_9132 NULL +#define pci_ss_list_1283_673a NULL +#define pci_ss_list_1283_8330 NULL +#define pci_ss_list_1283_8888 NULL +#define pci_ss_list_1283_8889 NULL +#define pci_ss_list_1283_e886 NULL +#define pci_ss_list_1285_0100 NULL +#define pci_ss_list_1287_001e NULL +#define pci_ss_list_1287_001f NULL +#define pci_ss_list_128d_0021 NULL +#define pci_ss_list_128e_0008 NULL +#define pci_ss_list_128e_0009 NULL +#define pci_ss_list_128e_000a NULL +#define pci_ss_list_128e_000b NULL +#define pci_ss_list_128e_000c NULL +#define pci_ss_list_129a_0615 NULL +#define pci_ss_list_12ab_3000 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12ae_0001[] = { + &pci_ss_info_12ae_0001_12ae_0001, + &pci_ss_info_12ae_0001_1410_0104, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12ae_0002[] = { + &pci_ss_info_12ae_0002_12ae_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12b9_1006[] = { + &pci_ss_info_12b9_1006_12b9_005c, + &pci_ss_info_12b9_1006_12b9_005e, + &pci_ss_info_12b9_1006_12b9_0062, + &pci_ss_info_12b9_1006_12b9_0068, + &pci_ss_info_12b9_1006_12b9_007a, + &pci_ss_info_12b9_1006_12b9_007f, + &pci_ss_info_12b9_1006_12b9_0080, + &pci_ss_info_12b9_1006_12b9_0081, + &pci_ss_info_12b9_1006_12b9_0091, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12b9_1007[] = { + &pci_ss_info_12b9_1007_12b9_00a3, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12b9_1008[] = { + &pci_ss_info_12b9_1008_12b9_00a2, + &pci_ss_info_12b9_1008_12b9_00aa, + &pci_ss_info_12b9_1008_12b9_00ab, + &pci_ss_info_12b9_1008_12b9_00ac, + &pci_ss_info_12b9_1008_12b9_00ad, + NULL +}; +#endif +#define pci_ss_list_12be_3041 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12be_3042[] = { + &pci_ss_info_12be_3042_12be_3042, + NULL +}; +#endif +#define pci_ss_list_12c3_0058 NULL +#define pci_ss_list_12c3_5598 NULL +#define pci_ss_list_12c5_007e NULL +#define pci_ss_list_12c5_007f NULL +#define pci_ss_list_12c5_0081 NULL +#define pci_ss_list_12c5_0085 NULL +#define pci_ss_list_12c5_0086 NULL +#define pci_ss_list_12d2_0008 NULL +#define pci_ss_list_12d2_0009 NULL +static const pciSubsystemInfo *pci_ss_list_12d2_0018[] = { + &pci_ss_info_12d2_0018_1048_0c10, + &pci_ss_info_12d2_0018_107b_8030, + &pci_ss_info_12d2_0018_1092_0350, + &pci_ss_info_12d2_0018_1092_1092, + &pci_ss_info_12d2_0018_10b4_1b1b, + &pci_ss_info_12d2_0018_10b4_1b1d, + &pci_ss_info_12d2_0018_10b4_1b1e, + &pci_ss_info_12d2_0018_10b4_1b20, + &pci_ss_info_12d2_0018_10b4_1b21, + &pci_ss_info_12d2_0018_10b4_1b22, + &pci_ss_info_12d2_0018_10b4_1b23, + &pci_ss_info_12d2_0018_10b4_1b27, + &pci_ss_info_12d2_0018_10b4_1b88, + &pci_ss_info_12d2_0018_10b4_222a, + &pci_ss_info_12d2_0018_10b4_2230, + &pci_ss_info_12d2_0018_10b4_2232, + &pci_ss_info_12d2_0018_10b4_2235, + &pci_ss_info_12d2_0018_2a15_54a3, + NULL +}; +#define pci_ss_list_12d2_0019 NULL +#define pci_ss_list_12d2_0020 NULL +#define pci_ss_list_12d2_0028 NULL +#define pci_ss_list_12d2_0029 NULL +#define pci_ss_list_12d2_002c NULL +#define pci_ss_list_12d2_00a0 NULL +#define pci_ss_list_12e0_0010 NULL +#define pci_ss_list_12e0_0020 NULL +#define pci_ss_list_12e0_0030 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12eb_0001[] = { + &pci_ss_info_12eb_0001_104d_8036, + &pci_ss_info_12eb_0001_1092_2000, + &pci_ss_info_12eb_0001_1092_2100, + &pci_ss_info_12eb_0001_1092_2110, + &pci_ss_info_12eb_0001_1092_2200, + &pci_ss_info_12eb_0001_122d_1002, + &pci_ss_info_12eb_0001_12eb_0001, + &pci_ss_info_12eb_0001_5053_3355, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12eb_0002[] = { + &pci_ss_info_12eb_0002_104d_8049, + &pci_ss_info_12eb_0002_104d_807b, + &pci_ss_info_12eb_0002_1092_3000, + &pci_ss_info_12eb_0002_1092_3001, + &pci_ss_info_12eb_0002_1092_3002, + &pci_ss_info_12eb_0002_1092_3003, + &pci_ss_info_12eb_0002_1092_3004, + &pci_ss_info_12eb_0002_12eb_0001, + &pci_ss_info_12eb_0002_12eb_0002, + &pci_ss_info_12eb_0002_12eb_0088, + &pci_ss_info_12eb_0002_144d_3510, + &pci_ss_info_12eb_0002_5053_3356, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12eb_0003[] = { + &pci_ss_info_12eb_0003_104d_8049, + &pci_ss_info_12eb_0003_104d_8077, + &pci_ss_info_12eb_0003_109f_1000, + &pci_ss_info_12eb_0003_12eb_0003, + &pci_ss_info_12eb_0003_1462_6780, + &pci_ss_info_12eb_0003_14a4_2073, + &pci_ss_info_12eb_0003_14a4_2091, + &pci_ss_info_12eb_0003_14a4_2104, + &pci_ss_info_12eb_0003_14a4_2106, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12eb_8803[] = { + &pci_ss_info_12eb_8803_12eb_8803, + NULL +}; +#endif +#define pci_ss_list_12f8_0002 NULL +#define pci_ss_list_1307_0001 NULL +#define pci_ss_list_1307_000b NULL +#define pci_ss_list_1307_000c NULL +#define pci_ss_list_1307_000d NULL +#define pci_ss_list_1307_000f NULL +#define pci_ss_list_1307_0010 NULL +#define pci_ss_list_1307_0014 NULL +#define pci_ss_list_1307_0015 NULL +#define pci_ss_list_1307_0016 NULL +#define pci_ss_list_1307_0017 NULL +#define pci_ss_list_1307_0018 NULL +#define pci_ss_list_1307_0019 NULL +#define pci_ss_list_1307_001a NULL +#define pci_ss_list_1307_001b NULL +#define pci_ss_list_1307_001c NULL +#define pci_ss_list_1307_001d NULL +#define pci_ss_list_1307_001e NULL +#define pci_ss_list_1307_001f NULL +#define pci_ss_list_1307_0020 NULL +#define pci_ss_list_1307_0021 NULL +#define pci_ss_list_1307_0022 NULL +#define pci_ss_list_1307_0023 NULL +#define pci_ss_list_1307_0024 NULL +#define pci_ss_list_1307_0025 NULL +#define pci_ss_list_1307_0026 NULL +#define pci_ss_list_1307_0027 NULL +#define pci_ss_list_1307_0028 NULL +#define pci_ss_list_1307_0029 NULL +#define pci_ss_list_1307_002c NULL +#define pci_ss_list_1307_0033 NULL +#define pci_ss_list_1307_0034 NULL +#define pci_ss_list_1307_0035 NULL +#define pci_ss_list_1307_0036 NULL +#define pci_ss_list_1307_0037 NULL +#define pci_ss_list_1307_004c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1308_0001[] = { + &pci_ss_info_1308_0001_1308_0001, + NULL +}; +#endif +#define pci_ss_list_1317_0981 NULL +#define pci_ss_list_1317_0985 NULL +#define pci_ss_list_1317_1985 NULL +#define pci_ss_list_1318_0911 NULL +#define pci_ss_list_1319_0801 NULL +#define pci_ss_list_1319_0802 NULL +#define pci_ss_list_1319_1000 NULL +#define pci_ss_list_1319_1001 NULL +#define pci_ss_list_131f_1000 NULL +#define pci_ss_list_131f_1001 NULL +#define pci_ss_list_131f_1002 NULL +#define pci_ss_list_131f_1010 NULL +#define pci_ss_list_131f_1011 NULL +#define pci_ss_list_131f_1012 NULL +#define pci_ss_list_131f_1020 NULL +#define pci_ss_list_131f_1021 NULL +#define pci_ss_list_131f_1030 NULL +#define pci_ss_list_131f_1031 NULL +#define pci_ss_list_131f_1032 NULL +#define pci_ss_list_131f_1034 NULL +#define pci_ss_list_131f_1035 NULL +#define pci_ss_list_131f_1036 NULL +#define pci_ss_list_131f_1050 NULL +#define pci_ss_list_131f_1051 NULL +#define pci_ss_list_131f_1052 NULL +#define pci_ss_list_131f_2000 NULL +#define pci_ss_list_131f_2001 NULL +#define pci_ss_list_131f_2002 NULL +#define pci_ss_list_131f_2010 NULL +#define pci_ss_list_131f_2011 NULL +#define pci_ss_list_131f_2012 NULL +#define pci_ss_list_131f_2020 NULL +#define pci_ss_list_131f_2021 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_131f_2030[] = { + &pci_ss_info_131f_2030_131f_2030, + NULL +}; +#define pci_ss_list_131f_2031 NULL +#define pci_ss_list_131f_2032 NULL +#define pci_ss_list_131f_2040 NULL +#define pci_ss_list_131f_2041 NULL +#define pci_ss_list_131f_2042 NULL +#define pci_ss_list_131f_2050 NULL +#define pci_ss_list_131f_2051 NULL +#define pci_ss_list_131f_2052 NULL +#define pci_ss_list_131f_2060 NULL +#define pci_ss_list_131f_2061 NULL +#define pci_ss_list_131f_2062 NULL +#endif +#define pci_ss_list_1332_5415 NULL +#define pci_ss_list_134a_0001 NULL +#define pci_ss_list_134a_0002 NULL +#define pci_ss_list_134d_7890 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_134d_7891[] = { + &pci_ss_info_134d_7891_134d_0001, + NULL +}; +#define pci_ss_list_134d_7892 NULL +#define pci_ss_list_134d_7893 NULL +#define pci_ss_list_134d_7894 NULL +#define pci_ss_list_134d_7895 NULL +#define pci_ss_list_134d_7896 NULL +#define pci_ss_list_134d_7897 NULL +#endif +#define pci_ss_list_1353_0002 NULL +#define pci_ss_list_1353_0003 NULL +#define pci_ss_list_1353_0004 NULL +#define pci_ss_list_1353_0005 NULL +#define pci_ss_list_135c_0010 NULL +#define pci_ss_list_135c_0020 NULL +#define pci_ss_list_135c_0030 NULL +#define pci_ss_list_135c_0040 NULL +#define pci_ss_list_135c_0050 NULL +#define pci_ss_list_135c_0060 NULL +#define pci_ss_list_135c_00f0 NULL +#define pci_ss_list_135c_0170 NULL +#define pci_ss_list_135c_0180 NULL +#define pci_ss_list_135c_0190 NULL +#define pci_ss_list_135c_01a0 NULL +#define pci_ss_list_135c_01b0 NULL +#define pci_ss_list_135c_01c0 NULL +#define pci_ss_list_135e_7101 NULL +#define pci_ss_list_135e_7201 NULL +#define pci_ss_list_135e_7202 NULL +#define pci_ss_list_135e_7401 NULL +#define pci_ss_list_135e_7402 NULL +#define pci_ss_list_135e_7801 NULL +#define pci_ss_list_135e_8001 NULL +#define pci_ss_list_1385_4100 NULL +#define pci_ss_list_1385_620a NULL +#define pci_ss_list_1385_622a NULL +#define pci_ss_list_1385_630a NULL +#define pci_ss_list_1385_f311 NULL +#define pci_ss_list_1389_0001 NULL +#define pci_ss_list_1393_1040 NULL +#define pci_ss_list_1393_1680 NULL +#define pci_ss_list_1393_2040 NULL +#define pci_ss_list_1393_2180 NULL +#define pci_ss_list_1393_3200 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1394_0001[] = { + &pci_ss_info_1394_0001_1394_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1397_2bd0[] = { + &pci_ss_info_1397_2bd0_1397_2bd0, + &pci_ss_info_1397_2bd0_e4bf_1000, + NULL +}; +#endif +#define pci_ss_list_139a_0001 NULL +#define pci_ss_list_139a_0003 NULL +#define pci_ss_list_139a_0005 NULL +#define pci_ss_list_13a3_0005 NULL +#define pci_ss_list_13a3_0006 NULL +#define pci_ss_list_13a3_0007 NULL +#define pci_ss_list_13a3_0012 NULL +#define pci_ss_list_13a3_0014 NULL +#define pci_ss_list_13a3_0016 NULL +#define pci_ss_list_13a3_0017 NULL +#define pci_ss_list_13a3_0018 NULL +#define pci_ss_list_13a8_0158 NULL +#define pci_ss_list_13c0_0010 NULL +#define pci_ss_list_13c1_1000 NULL +#define pci_ss_list_13c1_1001 NULL +#define pci_ss_list_13c1_1002 NULL +#define pci_ss_list_13d0_2103 NULL +#define pci_ss_list_13d1_ab02 NULL +#define pci_ss_list_13d1_ab06 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13df_0001[] = { + &pci_ss_info_13df_0001_13df_0001, + NULL +}; +#endif +#define pci_ss_list_13f0_0201 NULL +#define pci_ss_list_13f4_1401 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13f6_0100[] = { + &pci_ss_info_13f6_0100_13f6_ffff, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_13f6_0101[] = { + &pci_ss_info_13f6_0101_13f6_0101, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_13f6_0111[] = { + &pci_ss_info_13f6_0111_1019_0970, + &pci_ss_info_13f6_0111_1043_8077, + &pci_ss_info_13f6_0111_1043_80e2, + &pci_ss_info_13f6_0111_13f6_0111, + NULL +}; +#define pci_ss_list_13f6_0211 NULL +#endif +#define pci_ss_list_13fe_1756 NULL +#define pci_ss_list_1400_1401 NULL +#define pci_ss_list_1407_0100 NULL +#define pci_ss_list_1407_0101 NULL +#define pci_ss_list_1407_0102 NULL +#define pci_ss_list_1407_0200 NULL +#define pci_ss_list_1407_0201 NULL +#define pci_ss_list_1407_0202 NULL +#define pci_ss_list_1407_0500 NULL +#define pci_ss_list_1407_0600 NULL +#define pci_ss_list_1407_8000 NULL +#define pci_ss_list_1407_8001 NULL +#define pci_ss_list_1407_8002 NULL +#define pci_ss_list_1407_8003 NULL +#define pci_ss_list_1407_8800 NULL +#define pci_ss_list_1409_7168 NULL +#define pci_ss_list_1412_1712 NULL +#define pci_ss_list_1412_1724 NULL +#define pci_ss_list_1415_8403 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1415_9501[] = { + &pci_ss_info_1415_9501_15ed_2000, + &pci_ss_info_1415_9501_15ed_2001, + NULL +}; +#define pci_ss_list_1415_950a NULL +#define pci_ss_list_1415_950b NULL +static const pciSubsystemInfo *pci_ss_list_1415_9511[] = { + &pci_ss_info_1415_9511_15ed_2000, + &pci_ss_info_1415_9511_15ed_2001, + NULL +}; +#define pci_ss_list_1415_9521 NULL +#endif +#define pci_ss_list_144a_7296 NULL +#define pci_ss_list_144a_7432 NULL +#define pci_ss_list_144a_7433 NULL +#define pci_ss_list_144a_7434 NULL +#define pci_ss_list_144a_7841 NULL +#define pci_ss_list_144a_8133 NULL +#define pci_ss_list_144a_8554 NULL +#define pci_ss_list_144a_9111 NULL +#define pci_ss_list_144a_9113 NULL +#define pci_ss_list_144a_9114 NULL +#define pci_ss_list_145f_0001 NULL +#define pci_ss_list_148d_1003 NULL +#define pci_ss_list_14af_7102 NULL +#define pci_ss_list_14b3_0000 NULL +#define pci_ss_list_14b5_0200 NULL +#define pci_ss_list_14b5_0300 NULL +#define pci_ss_list_14b5_0400 NULL +#define pci_ss_list_14b5_0600 NULL +#define pci_ss_list_14b5_0800 NULL +#define pci_ss_list_14b5_0900 NULL +#define pci_ss_list_14b5_0a00 NULL +#define pci_ss_list_14b5_0b00 NULL +#define pci_ss_list_14b7_0001 NULL +#define pci_ss_list_14b9_0001 NULL +#define pci_ss_list_14b9_0340 NULL +#define pci_ss_list_14b9_0350 NULL +#define pci_ss_list_14b9_4500 NULL +#define pci_ss_list_14b9_4800 NULL +#define pci_ss_list_14b9_a504 NULL +#define pci_ss_list_14d2_8001 NULL +#define pci_ss_list_14d2_8002 NULL +#define pci_ss_list_14d2_8010 NULL +#define pci_ss_list_14d2_8011 NULL +#define pci_ss_list_14d2_8020 NULL +#define pci_ss_list_14d2_8021 NULL +#define pci_ss_list_14d2_8040 NULL +#define pci_ss_list_14d2_8080 NULL +#define pci_ss_list_14d2_a000 NULL +#define pci_ss_list_14d2_a001 NULL +#define pci_ss_list_14d2_a003 NULL +#define pci_ss_list_14d2_a004 NULL +#define pci_ss_list_14d2_a005 NULL +#define pci_ss_list_14d2_e001 NULL +#define pci_ss_list_14d2_e010 NULL +#define pci_ss_list_14d2_e020 NULL +#define pci_ss_list_14db_2120 NULL +#define pci_ss_list_14dc_0000 NULL +#define pci_ss_list_14dc_0001 NULL +#define pci_ss_list_14dc_0002 NULL +#define pci_ss_list_14dc_0003 NULL +#define pci_ss_list_14dc_0004 NULL +#define pci_ss_list_14dc_0005 NULL +#define pci_ss_list_14dc_0006 NULL +#define pci_ss_list_14dc_0007 NULL +#define pci_ss_list_14dc_0008 NULL +#define pci_ss_list_14dc_0009 NULL +#define pci_ss_list_14dc_000a NULL +#define pci_ss_list_14dc_000b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14e4_1644[] = { + &pci_ss_info_14e4_1644_1014_0277, + &pci_ss_info_14e4_1644_1028_00d1, + &pci_ss_info_14e4_1644_1028_0106, + &pci_ss_info_14e4_1644_1028_0109, + &pci_ss_info_14e4_1644_1028_010a, + &pci_ss_info_14e4_1644_10b7_1000, + &pci_ss_info_14e4_1644_10b7_1001, + &pci_ss_info_14e4_1644_10b7_1002, + &pci_ss_info_14e4_1644_10b7_1003, + &pci_ss_info_14e4_1644_10b7_1004, + &pci_ss_info_14e4_1644_10b7_1005, + &pci_ss_info_14e4_1644_10b7_1008, + &pci_ss_info_14e4_1644_14e4_0002, + &pci_ss_info_14e4_1644_14e4_0003, + &pci_ss_info_14e4_1644_14e4_0004, + &pci_ss_info_14e4_1644_14e4_1028, + &pci_ss_info_14e4_1644_14e4_1644, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1645[] = { + &pci_ss_info_14e4_1645_0e11_007c, + &pci_ss_info_14e4_1645_0e11_007d, + &pci_ss_info_14e4_1645_0e11_0085, + &pci_ss_info_14e4_1645_0e11_0099, + &pci_ss_info_14e4_1645_0e11_009a, + &pci_ss_info_14e4_1645_0e11_00c1, + &pci_ss_info_14e4_1645_1028_0121, + &pci_ss_info_14e4_1645_10b7_1004, + &pci_ss_info_14e4_1645_10b7_1006, + &pci_ss_info_14e4_1645_10b7_1007, + &pci_ss_info_14e4_1645_10b7_1008, + &pci_ss_info_14e4_1645_14e4_0001, + &pci_ss_info_14e4_1645_14e4_0005, + &pci_ss_info_14e4_1645_14e4_0006, + &pci_ss_info_14e4_1645_14e4_0007, + &pci_ss_info_14e4_1645_14e4_0008, + &pci_ss_info_14e4_1645_14e4_8008, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1646[] = { + &pci_ss_info_14e4_1646_0e11_00bb, + &pci_ss_info_14e4_1646_1028_0126, + &pci_ss_info_14e4_1646_14e4_8009, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1647[] = { + &pci_ss_info_14e4_1647_0e11_0099, + &pci_ss_info_14e4_1647_0e11_009a, + &pci_ss_info_14e4_1647_14e4_0009, + &pci_ss_info_14e4_1647_14e4_000a, + &pci_ss_info_14e4_1647_14e4_000b, + &pci_ss_info_14e4_1647_14e4_8009, + &pci_ss_info_14e4_1647_14e4_800a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1648[] = { + &pci_ss_info_14e4_1648_0e11_00cf, + &pci_ss_info_14e4_1648_0e11_00d0, + &pci_ss_info_14e4_1648_0e11_00d1, + &pci_ss_info_14e4_1648_10b7_2000, + &pci_ss_info_14e4_1648_10b7_3000, + &pci_ss_info_14e4_1648_1166_1648, + NULL +}; +#define pci_ss_list_14e4_164d NULL +#define pci_ss_list_14e4_1653 NULL +#define pci_ss_list_14e4_165d NULL +static const pciSubsystemInfo *pci_ss_list_14e4_1696[] = { + &pci_ss_info_14e4_1696_14e4_000d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_16a6[] = { + &pci_ss_info_14e4_16a6_0e11_00bb, + &pci_ss_info_14e4_16a6_1028_0126, + &pci_ss_info_14e4_16a6_14e4_000c, + &pci_ss_info_14e4_16a6_14e4_8009, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_16a7[] = { + &pci_ss_info_14e4_16a7_0e11_00ca, + &pci_ss_info_14e4_16a7_0e11_00cb, + &pci_ss_info_14e4_16a7_14e4_0009, + &pci_ss_info_14e4_16a7_14e4_000a, + &pci_ss_info_14e4_16a7_14e4_000b, + &pci_ss_info_14e4_16a7_14e4_800a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_16a8[] = { + &pci_ss_info_14e4_16a8_10b7_2001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_16c6[] = { + &pci_ss_info_14e4_16c6_10b7_1100, + &pci_ss_info_14e4_16c6_14e4_000c, + &pci_ss_info_14e4_16c6_14e4_8009, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_16c7[] = { + &pci_ss_info_14e4_16c7_14e4_0009, + &pci_ss_info_14e4_16c7_14e4_000a, + NULL +}; +#define pci_ss_list_14e4_4210 NULL +#define pci_ss_list_14e4_4211 NULL +#define pci_ss_list_14e4_4212 NULL +#define pci_ss_list_14e4_4301 NULL +#define pci_ss_list_14e4_4401 NULL +#define pci_ss_list_14e4_4402 NULL +#define pci_ss_list_14e4_4410 NULL +#define pci_ss_list_14e4_4411 NULL +#define pci_ss_list_14e4_4412 NULL +#define pci_ss_list_14e4_5820 NULL +#define pci_ss_list_14e4_5821 NULL +#endif +#define pci_ss_list_14ea_ab06 NULL +#define pci_ss_list_14f1_1002 NULL +#define pci_ss_list_14f1_1003 NULL +#define pci_ss_list_14f1_1004 NULL +#define pci_ss_list_14f1_1005 NULL +#define pci_ss_list_14f1_1006 NULL +#define pci_ss_list_14f1_1022 NULL +#define pci_ss_list_14f1_1023 NULL +#define pci_ss_list_14f1_1024 NULL +#define pci_ss_list_14f1_1025 NULL +#define pci_ss_list_14f1_1026 NULL +#define pci_ss_list_14f1_1032 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14f1_1033[] = { + &pci_ss_info_14f1_1033_1033_8077, + &pci_ss_info_14f1_1033_122d_4027, + &pci_ss_info_14f1_1033_122d_4030, + &pci_ss_info_14f1_1033_122d_4034, + &pci_ss_info_14f1_1033_13e0_020d, + &pci_ss_info_14f1_1033_13e0_020e, + &pci_ss_info_14f1_1033_13e0_0261, + &pci_ss_info_14f1_1033_13e0_0290, + &pci_ss_info_14f1_1033_13e0_02a0, + &pci_ss_info_14f1_1033_13e0_02b0, + &pci_ss_info_14f1_1033_13e0_02c0, + &pci_ss_info_14f1_1033_13e0_02d0, + &pci_ss_info_14f1_1033_144f_1500, + &pci_ss_info_14f1_1033_144f_1501, + &pci_ss_info_14f1_1033_144f_150a, + &pci_ss_info_14f1_1033_144f_150b, + &pci_ss_info_14f1_1033_144f_1510, + NULL +}; +#define pci_ss_list_14f1_1034 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1035[] = { + &pci_ss_info_14f1_1035_10cf_1098, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14f1_1036[] = { + &pci_ss_info_14f1_1036_104d_8067, + &pci_ss_info_14f1_1036_122d_4029, + &pci_ss_info_14f1_1036_122d_4031, + &pci_ss_info_14f1_1036_13e0_0209, + &pci_ss_info_14f1_1036_13e0_020a, + &pci_ss_info_14f1_1036_13e0_0260, + &pci_ss_info_14f1_1036_13e0_0270, + NULL +}; +#define pci_ss_list_14f1_1052 NULL +#define pci_ss_list_14f1_1053 NULL +#define pci_ss_list_14f1_1054 NULL +#define pci_ss_list_14f1_1055 NULL +#define pci_ss_list_14f1_1056 NULL +#define pci_ss_list_14f1_1057 NULL +#define pci_ss_list_14f1_1059 NULL +#define pci_ss_list_14f1_1063 NULL +#define pci_ss_list_14f1_1064 NULL +#define pci_ss_list_14f1_1065 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1066[] = { + &pci_ss_info_14f1_1066_122d_4033, + NULL +}; +#define pci_ss_list_14f1_1433 NULL +#define pci_ss_list_14f1_1434 NULL +#define pci_ss_list_14f1_1435 NULL +#define pci_ss_list_14f1_1436 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1453[] = { + &pci_ss_info_14f1_1453_13e0_0240, + &pci_ss_info_14f1_1453_13e0_0250, + &pci_ss_info_14f1_1453_144f_1502, + &pci_ss_info_14f1_1453_144f_1503, + NULL +}; +#define pci_ss_list_14f1_1454 NULL +#define pci_ss_list_14f1_1455 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1456[] = { + &pci_ss_info_14f1_1456_122d_4035, + &pci_ss_info_14f1_1456_122d_4302, + NULL +}; +#define pci_ss_list_14f1_1610 NULL +#define pci_ss_list_14f1_1611 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1803[] = { + &pci_ss_info_14f1_1803_0e11_0023, + &pci_ss_info_14f1_1803_0e11_0043, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14f1_1815[] = { + &pci_ss_info_14f1_1815_0e11_0022, + &pci_ss_info_14f1_1815_0e11_0042, + NULL +}; +#define pci_ss_list_14f1_2003 NULL +#define pci_ss_list_14f1_2004 NULL +#define pci_ss_list_14f1_2005 NULL +#define pci_ss_list_14f1_2006 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2013[] = { + &pci_ss_info_14f1_2013_0e11_b195, + &pci_ss_info_14f1_2013_0e11_b196, + &pci_ss_info_14f1_2013_0e11_b1be, + &pci_ss_info_14f1_2013_1025_8013, + &pci_ss_info_14f1_2013_1033_809d, + &pci_ss_info_14f1_2013_1033_80bc, + &pci_ss_info_14f1_2013_155d_6793, + &pci_ss_info_14f1_2013_155d_8850, + NULL +}; +#define pci_ss_list_14f1_2014 NULL +#define pci_ss_list_14f1_2015 NULL +#define pci_ss_list_14f1_2016 NULL +#define pci_ss_list_14f1_2043 NULL +#define pci_ss_list_14f1_2044 NULL +#define pci_ss_list_14f1_2045 NULL +#define pci_ss_list_14f1_2046 NULL +#define pci_ss_list_14f1_2063 NULL +#define pci_ss_list_14f1_2064 NULL +#define pci_ss_list_14f1_2065 NULL +#define pci_ss_list_14f1_2066 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2093[] = { + &pci_ss_info_14f1_2093_155d_2f07, + NULL +}; +#define pci_ss_list_14f1_2143 NULL +#define pci_ss_list_14f1_2144 NULL +#define pci_ss_list_14f1_2145 NULL +#define pci_ss_list_14f1_2146 NULL +#define pci_ss_list_14f1_2163 NULL +#define pci_ss_list_14f1_2164 NULL +#define pci_ss_list_14f1_2165 NULL +#define pci_ss_list_14f1_2166 NULL +#define pci_ss_list_14f1_2343 NULL +#define pci_ss_list_14f1_2344 NULL +#define pci_ss_list_14f1_2345 NULL +#define pci_ss_list_14f1_2346 NULL +#define pci_ss_list_14f1_2363 NULL +#define pci_ss_list_14f1_2364 NULL +#define pci_ss_list_14f1_2365 NULL +#define pci_ss_list_14f1_2366 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2443[] = { + &pci_ss_info_14f1_2443_104d_8075, + &pci_ss_info_14f1_2443_104d_8083, + &pci_ss_info_14f1_2443_104d_8097, + NULL +}; +#define pci_ss_list_14f1_2444 NULL +#define pci_ss_list_14f1_2445 NULL +#define pci_ss_list_14f1_2446 NULL +#define pci_ss_list_14f1_2463 NULL +#define pci_ss_list_14f1_2464 NULL +#define pci_ss_list_14f1_2465 NULL +#define pci_ss_list_14f1_2466 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2f00[] = { + &pci_ss_info_14f1_2f00_13e0_8d84, + &pci_ss_info_14f1_2f00_13e0_8d85, + &pci_ss_info_14f1_2f00_14f1_2004, + NULL +}; +#define pci_ss_list_14f1_8234 NULL +#endif +#define pci_ss_list_1507_0001 NULL +#define pci_ss_list_1507_0002 NULL +#define pci_ss_list_1507_0003 NULL +#define pci_ss_list_1507_0100 NULL +#define pci_ss_list_1507_0431 NULL +#define pci_ss_list_1507_4801 NULL +#define pci_ss_list_1507_4802 NULL +#define pci_ss_list_1507_4803 NULL +#define pci_ss_list_1507_4806 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1516_0803[] = { + &pci_ss_info_1516_0803_1320_10bd, + NULL +}; +#endif +#define pci_ss_list_151a_1002 NULL +#define pci_ss_list_151a_1004 NULL +#define pci_ss_list_151a_1008 NULL +#define pci_ss_list_151f_0000 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1522_0100[] = { + &pci_ss_info_1522_0100_1522_0200, + &pci_ss_info_1522_0100_1522_0300, + &pci_ss_info_1522_0100_1522_0400, + &pci_ss_info_1522_0100_1522_0500, + &pci_ss_info_1522_0100_1522_0600, + &pci_ss_info_1522_0100_1522_0700, + &pci_ss_info_1522_0100_1522_0800, + NULL +}; +#endif +#define pci_ss_list_1524_1211 NULL +#define pci_ss_list_1524_1225 NULL +#define pci_ss_list_1524_1410 NULL +#define pci_ss_list_1524_1420 NULL +#define pci_ss_list_1543_3052 NULL +#define pci_ss_list_1543_4c22 NULL +#define pci_ss_list_1571_a001 NULL +#define pci_ss_list_1571_a002 NULL +#define pci_ss_list_1571_a003 NULL +#define pci_ss_list_1571_a004 NULL +#define pci_ss_list_1571_a005 NULL +#define pci_ss_list_1571_a006 NULL +#define pci_ss_list_1571_a007 NULL +#define pci_ss_list_1571_a008 NULL +#define pci_ss_list_1571_a009 NULL +#define pci_ss_list_1571_a00a NULL +#define pci_ss_list_1571_a00b NULL +#define pci_ss_list_1571_a00c NULL +#define pci_ss_list_1571_a00d NULL +#define pci_ss_list_1571_a201 NULL +#define pci_ss_list_1571_a202 NULL +#define pci_ss_list_1571_a203 NULL +#define pci_ss_list_1571_a204 NULL +#define pci_ss_list_1571_a205 NULL +#define pci_ss_list_1571_a206 NULL +#define pci_ss_list_157c_8001 NULL +#define pci_ss_list_1592_0781 NULL +#define pci_ss_list_1592_0782 NULL +#define pci_ss_list_1592_0783 NULL +#define pci_ss_list_1592_0785 NULL +#define pci_ss_list_1592_0786 NULL +#define pci_ss_list_1592_0787 NULL +#define pci_ss_list_1592_0788 NULL +#define pci_ss_list_1592_078a NULL +#define pci_ss_list_15a2_0001 NULL +#define pci_ss_list_15ad_0710 NULL +#define pci_ss_list_15b3_5274 NULL +#define pci_ss_list_15bc_2929 NULL +#define pci_ss_list_15c7_0349 NULL +#define pci_ss_list_15dc_0001 NULL +#define pci_ss_list_15e8_0130 NULL +#define pci_ss_list_1619_0400 NULL +#define pci_ss_list_1619_0440 NULL +#define pci_ss_list_1629_1003 NULL +#define pci_ss_list_1629_2002 NULL +#define pci_ss_list_1638_1100 NULL +#define pci_ss_list_163c_5449 NULL +#define pci_ss_list_165a_c100 NULL +#define pci_ss_list_165a_d200 NULL +#define pci_ss_list_165a_d300 NULL +#define pci_ss_list_16ab_1102 NULL +#define pci_ss_list_16ec_3685 NULL +#define pci_ss_list_173b_03e8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_173b_03ea[] = { + &pci_ss_info_173b_03ea_173b_0001, + NULL +}; +#endif +#define pci_ss_list_1743_8139 NULL +#define pci_ss_list_1796_0001 NULL +#define pci_ss_list_1796_0002 NULL +#define pci_ss_list_1796_0003 NULL +#define pci_ss_list_1796_0004 NULL +#define pci_ss_list_1796_0005 NULL +#define pci_ss_list_1796_0006 NULL +#define pci_ss_list_17cc_2280 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1813_4000[] = { + &pci_ss_info_1813_4000_16be_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1813_4100[] = { + &pci_ss_info_1813_4100_16be_0002, + NULL +}; +#endif +#define pci_ss_list_1888_0301 NULL +#define pci_ss_list_1888_0601 NULL +#define pci_ss_list_1888_0710 NULL +#define pci_ss_list_1888_0720 NULL +#define pci_ss_list_1a08_0000 NULL +#define pci_ss_list_1c1c_0001 NULL +#define pci_ss_list_1d44_a400 NULL +#define pci_ss_list_1de1_0391 NULL +#define pci_ss_list_1de1_2020 NULL +#define pci_ss_list_1de1_690c NULL +#define pci_ss_list_1de1_dc29 NULL +#define pci_ss_list_2348_2010 NULL +#define pci_ss_list_3388_0013 NULL +#define pci_ss_list_3388_0014 NULL +#define pci_ss_list_3388_0021 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_3388_8011[] = { + &pci_ss_info_3388_8011_3388_8011, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3388_8012[] = { + &pci_ss_info_3388_8012_3388_8012, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3388_8013[] = { + &pci_ss_info_3388_8013_3388_8013, + NULL +}; +#endif +#define pci_ss_list_3d3d_0001 NULL +#define pci_ss_list_3d3d_0002 NULL +#define pci_ss_list_3d3d_0003 NULL +#define pci_ss_list_3d3d_0004 NULL +#define pci_ss_list_3d3d_0005 NULL +#define pci_ss_list_3d3d_0006 NULL +#define pci_ss_list_3d3d_0007 NULL +#define pci_ss_list_3d3d_0008 NULL +static const pciSubsystemInfo *pci_ss_list_3d3d_0009[] = { + &pci_ss_info_3d3d_0009_1040_0011, + &pci_ss_info_3d3d_0009_3d3d_0100, + &pci_ss_info_3d3d_0009_3d3d_0111, + &pci_ss_info_3d3d_0009_3d3d_0114, + &pci_ss_info_3d3d_0009_3d3d_0116, + &pci_ss_info_3d3d_0009_3d3d_0119, + &pci_ss_info_3d3d_0009_3d3d_0120, + &pci_ss_info_3d3d_0009_3d3d_0125, + &pci_ss_info_3d3d_0009_3d3d_0127, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3d3d_000a[] = { + &pci_ss_info_3d3d_000a_3d3d_0121, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3d3d_000c[] = { + &pci_ss_info_3d3d_000c_3d3d_0144, + NULL +}; +#define pci_ss_list_3d3d_0100 NULL +#define pci_ss_list_3d3d_1004 NULL +#define pci_ss_list_3d3d_3d04 NULL +#define pci_ss_list_3d3d_ffff NULL +#define pci_ss_list_4005_0300 NULL +#define pci_ss_list_4005_0308 NULL +#define pci_ss_list_4005_0309 NULL +#define pci_ss_list_4005_1064 NULL +#define pci_ss_list_4005_2064 NULL +#define pci_ss_list_4005_2128 NULL +#define pci_ss_list_4005_2301 NULL +#define pci_ss_list_4005_2302 NULL +#define pci_ss_list_4005_2303 NULL +#define pci_ss_list_4005_2364 NULL +#define pci_ss_list_4005_2464 NULL +#define pci_ss_list_4005_2501 NULL +static const pciSubsystemInfo *pci_ss_list_4005_4000[] = { + &pci_ss_info_4005_4000_4005_4000, + NULL +}; +#define pci_ss_list_4005_4710 NULL +#define pci_ss_list_4033_1360 NULL +#define pci_ss_list_416c_0100 NULL +#define pci_ss_list_416c_0200 NULL +#define pci_ss_list_4444_0803 NULL +#define pci_ss_list_4916_1960 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_4a14_5000[] = { + &pci_ss_info_4a14_5000_4a14_5000, + NULL +}; +#endif +#define pci_ss_list_4d51_0200 NULL +#define pci_ss_list_4ddc_0100 NULL +#define pci_ss_list_4ddc_0801 NULL +#define pci_ss_list_4ddc_0802 NULL +#define pci_ss_list_4ddc_0811 NULL +#define pci_ss_list_4ddc_0812 NULL +#define pci_ss_list_4ddc_0881 NULL +#define pci_ss_list_4ddc_0882 NULL +#define pci_ss_list_4ddc_0891 NULL +#define pci_ss_list_4ddc_0892 NULL +#define pci_ss_list_4ddc_0901 NULL +#define pci_ss_list_4ddc_0902 NULL +#define pci_ss_list_4ddc_0903 NULL +#define pci_ss_list_4ddc_0904 NULL +#define pci_ss_list_4ddc_0b01 NULL +#define pci_ss_list_4ddc_0b02 NULL +#define pci_ss_list_4ddc_0b03 NULL +#define pci_ss_list_4ddc_0b04 NULL +#define pci_ss_list_5046_1001 NULL +#define pci_ss_list_5053_2010 NULL +#define pci_ss_list_5145_3031 NULL +#define pci_ss_list_5301_0001 NULL +#define pci_ss_list_5333_0551 NULL +#define pci_ss_list_5333_5631 NULL +#define pci_ss_list_5333_8800 NULL +#define pci_ss_list_5333_8801 NULL +#define pci_ss_list_5333_8810 NULL +#define pci_ss_list_5333_8811 NULL +#define pci_ss_list_5333_8812 NULL +#define pci_ss_list_5333_8813 NULL +#define pci_ss_list_5333_8814 NULL +#define pci_ss_list_5333_8815 NULL +#define pci_ss_list_5333_883d NULL +#define pci_ss_list_5333_8870 NULL +#define pci_ss_list_5333_8880 NULL +#define pci_ss_list_5333_8881 NULL +#define pci_ss_list_5333_8882 NULL +#define pci_ss_list_5333_8883 NULL +#define pci_ss_list_5333_88b0 NULL +#define pci_ss_list_5333_88b1 NULL +#define pci_ss_list_5333_88b2 NULL +#define pci_ss_list_5333_88b3 NULL +#define pci_ss_list_5333_88c0 NULL +#define pci_ss_list_5333_88c1 NULL +#define pci_ss_list_5333_88c2 NULL +#define pci_ss_list_5333_88c3 NULL +#define pci_ss_list_5333_88d0 NULL +#define pci_ss_list_5333_88d1 NULL +#define pci_ss_list_5333_88d2 NULL +#define pci_ss_list_5333_88d3 NULL +#define pci_ss_list_5333_88f0 NULL +#define pci_ss_list_5333_88f1 NULL +#define pci_ss_list_5333_88f2 NULL +#define pci_ss_list_5333_88f3 NULL +static const pciSubsystemInfo *pci_ss_list_5333_8900[] = { + &pci_ss_info_5333_8900_5333_8900, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8901[] = { + &pci_ss_info_5333_8901_5333_8901, + NULL +}; +#define pci_ss_list_5333_8902 NULL +#define pci_ss_list_5333_8903 NULL +static const pciSubsystemInfo *pci_ss_list_5333_8904[] = { + &pci_ss_info_5333_8904_1014_00db, + &pci_ss_info_5333_8904_5333_8904, + NULL +}; +#define pci_ss_list_5333_8905 NULL +#define pci_ss_list_5333_8906 NULL +#define pci_ss_list_5333_8907 NULL +#define pci_ss_list_5333_8908 NULL +#define pci_ss_list_5333_8909 NULL +#define pci_ss_list_5333_890a NULL +#define pci_ss_list_5333_890b NULL +#define pci_ss_list_5333_890c NULL +#define pci_ss_list_5333_890d NULL +#define pci_ss_list_5333_890e NULL +#define pci_ss_list_5333_890f NULL +static const pciSubsystemInfo *pci_ss_list_5333_8a01[] = { + &pci_ss_info_5333_8a01_0e11_b032, + &pci_ss_info_5333_8a01_10b4_1617, + &pci_ss_info_5333_8a01_10b4_1717, + &pci_ss_info_5333_8a01_5333_8a01, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a10[] = { + &pci_ss_info_5333_8a10_1092_8a10, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a13[] = { + &pci_ss_info_5333_8a13_5333_8a13, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a20[] = { + &pci_ss_info_5333_8a20_5333_8a20, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a21[] = { + &pci_ss_info_5333_8a21_5333_8a21, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a22[] = { + &pci_ss_info_5333_8a22_1033_8068, + &pci_ss_info_5333_8a22_1033_8069, + &pci_ss_info_5333_8a22_105d_0018, + &pci_ss_info_5333_8a22_105d_002a, + &pci_ss_info_5333_8a22_105d_003a, + &pci_ss_info_5333_8a22_105d_092f, + &pci_ss_info_5333_8a22_1092_4207, + &pci_ss_info_5333_8a22_1092_4800, + &pci_ss_info_5333_8a22_1092_4807, + &pci_ss_info_5333_8a22_1092_4808, + &pci_ss_info_5333_8a22_1092_4809, + &pci_ss_info_5333_8a22_1092_480e, + &pci_ss_info_5333_8a22_1092_4904, + &pci_ss_info_5333_8a22_1092_4905, + &pci_ss_info_5333_8a22_1092_4a09, + &pci_ss_info_5333_8a22_1092_4a0b, + &pci_ss_info_5333_8a22_1092_4a0f, + &pci_ss_info_5333_8a22_1092_4e01, + &pci_ss_info_5333_8a22_1102_101d, + &pci_ss_info_5333_8a22_1102_101e, + &pci_ss_info_5333_8a22_5333_8100, + &pci_ss_info_5333_8a22_5333_8110, + &pci_ss_info_5333_8a22_5333_8125, + &pci_ss_info_5333_8a22_5333_8143, + &pci_ss_info_5333_8a22_5333_8a22, + &pci_ss_info_5333_8a22_5333_8a2e, + &pci_ss_info_5333_8a22_5333_9125, + &pci_ss_info_5333_8a22_5333_9143, + NULL +}; +#define pci_ss_list_5333_8a23 NULL +#define pci_ss_list_5333_8a25 NULL +#define pci_ss_list_5333_8a26 NULL +#define pci_ss_list_5333_8c00 NULL +static const pciSubsystemInfo *pci_ss_list_5333_8c01[] = { + &pci_ss_info_5333_8c01_1179_0001, + NULL +}; +#define pci_ss_list_5333_8c02 NULL +#define pci_ss_list_5333_8c03 NULL +#define pci_ss_list_5333_8c10 NULL +#define pci_ss_list_5333_8c11 NULL +static const pciSubsystemInfo *pci_ss_list_5333_8c12[] = { + &pci_ss_info_5333_8c12_1014_017f, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8c13[] = { + &pci_ss_info_5333_8c13_1179_0001, + NULL +}; +#define pci_ss_list_5333_8c22 NULL +#define pci_ss_list_5333_8c24 NULL +#define pci_ss_list_5333_8c26 NULL +#define pci_ss_list_5333_8c2a NULL +#define pci_ss_list_5333_8c2b NULL +#define pci_ss_list_5333_8c2c NULL +#define pci_ss_list_5333_8c2d NULL +static const pciSubsystemInfo *pci_ss_list_5333_8c2e[] = { + &pci_ss_info_5333_8c2e_1014_01fc, + NULL +}; +#define pci_ss_list_5333_8c2f NULL +#define pci_ss_list_5333_8d01 NULL +#define pci_ss_list_5333_8d02 NULL +#define pci_ss_list_5333_8d03 NULL +#define pci_ss_list_5333_8d04 NULL +static const pciSubsystemInfo *pci_ss_list_5333_9102[] = { + &pci_ss_info_5333_9102_1092_5932, + &pci_ss_info_5333_9102_1092_5934, + &pci_ss_info_5333_9102_1092_5952, + &pci_ss_info_5333_9102_1092_5954, + &pci_ss_info_5333_9102_1092_5a35, + &pci_ss_info_5333_9102_1092_5a37, + &pci_ss_info_5333_9102_1092_5a55, + &pci_ss_info_5333_9102_1092_5a57, + NULL +}; +#define pci_ss_list_5333_ca00 NULL +#define pci_ss_list_5455_4458 NULL +#define pci_ss_list_5544_0001 NULL +#define pci_ss_list_5555_0003 NULL +#define pci_ss_list_6374_6773 NULL +#define pci_ss_list_6666_0001 NULL +#define pci_ss_list_6666_0002 NULL +#define pci_ss_list_8008_0010 NULL +#define pci_ss_list_8008_0011 NULL +#define pci_ss_list_8086_0007 NULL +#define pci_ss_list_8086_0008 NULL +#define pci_ss_list_8086_0039 NULL +#define pci_ss_list_8086_0122 NULL +#define pci_ss_list_8086_0482 NULL +#define pci_ss_list_8086_0483 NULL +#define pci_ss_list_8086_0484 NULL +#define pci_ss_list_8086_0486 NULL +#define pci_ss_list_8086_04a3 NULL +#define pci_ss_list_8086_04d0 NULL +#define pci_ss_list_8086_0600 NULL +#define pci_ss_list_8086_0960 NULL +#define pci_ss_list_8086_0962 NULL +#define pci_ss_list_8086_0964 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1000[] = { + &pci_ss_info_8086_1000_0e11_b0df, + &pci_ss_info_8086_1000_0e11_b0e0, + &pci_ss_info_8086_1000_0e11_b123, + &pci_ss_info_8086_1000_1014_0119, + &pci_ss_info_8086_1000_8086_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1001[] = { + &pci_ss_info_8086_1001_0e11_004a, + &pci_ss_info_8086_1001_1014_01ea, + &pci_ss_info_8086_1001_8086_1003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1002[] = { + &pci_ss_info_8086_1002_8086_200e, + &pci_ss_info_8086_1002_8086_2013, + &pci_ss_info_8086_1002_8086_2017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1004[] = { + &pci_ss_info_8086_1004_0e11_0049, + &pci_ss_info_8086_1004_0e11_b1a4, + &pci_ss_info_8086_1004_1014_10f2, + &pci_ss_info_8086_1004_8086_1004, + &pci_ss_info_8086_1004_8086_2004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1008[] = { + &pci_ss_info_8086_1008_8086_1107, + &pci_ss_info_8086_1008_8086_2107, + &pci_ss_info_8086_1008_8086_2110, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1009[] = { + &pci_ss_info_8086_1009_8086_1109, + &pci_ss_info_8086_1009_8086_2109, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_100c[] = { + &pci_ss_info_8086_100c_8086_1112, + &pci_ss_info_8086_100c_8086_2112, + NULL +}; +#define pci_ss_list_8086_100d NULL +static const pciSubsystemInfo *pci_ss_list_8086_100e[] = { + &pci_ss_info_8086_100e_8086_001e, + &pci_ss_info_8086_100e_8086_002e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_100f[] = { + &pci_ss_info_8086_100f_8086_1001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1010[] = { + &pci_ss_info_8086_1010_8086_1011, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1011[] = { + &pci_ss_info_8086_1011_8086_1002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1012[] = { + &pci_ss_info_8086_1012_8086_1012, + NULL +}; +#define pci_ss_list_8086_1015 NULL +#define pci_ss_list_8086_1029 NULL +#define pci_ss_list_8086_1030 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1031[] = { + &pci_ss_info_8086_1031_1014_0209, + &pci_ss_info_8086_1031_104d_80e7, + &pci_ss_info_8086_1031_107b_5350, + &pci_ss_info_8086_1031_1179_0001, + &pci_ss_info_8086_1031_144d_c000, + &pci_ss_info_8086_1031_144d_c001, + &pci_ss_info_8086_1031_144d_c003, + &pci_ss_info_8086_1031_144d_c006, + NULL +}; +#define pci_ss_list_8086_1032 NULL +#define pci_ss_list_8086_1033 NULL +#define pci_ss_list_8086_1034 NULL +#define pci_ss_list_8086_1035 NULL +#define pci_ss_list_8086_1036 NULL +#define pci_ss_list_8086_1037 NULL +#define pci_ss_list_8086_1038 NULL +#define pci_ss_list_8086_1039 NULL +#define pci_ss_list_8086_103a NULL +#define pci_ss_list_8086_103b NULL +#define pci_ss_list_8086_103c NULL +#define pci_ss_list_8086_103d NULL +#define pci_ss_list_8086_103e NULL +static const pciSubsystemInfo *pci_ss_list_8086_1040[] = { + &pci_ss_info_8086_1040_16be_1040, + NULL +}; +#define pci_ss_list_8086_1059 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1130[] = { + &pci_ss_info_8086_1130_1025_1016, + &pci_ss_info_8086_1130_1043_8027, + &pci_ss_info_8086_1130_104d_80df, + NULL +}; +#define pci_ss_list_8086_1131 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1132[] = { + &pci_ss_info_8086_1132_1025_1016, + &pci_ss_info_8086_1132_104d_80df, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1161[] = { + &pci_ss_info_8086_1161_8086_1161, + NULL +}; +#define pci_ss_list_8086_1162 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1200[] = { + &pci_ss_info_8086_1200_172a_0000, + NULL +}; +#define pci_ss_list_8086_1209 NULL +#define pci_ss_list_8086_1221 NULL +#define pci_ss_list_8086_1222 NULL +#define pci_ss_list_8086_1223 NULL +#define pci_ss_list_8086_1225 NULL +#define pci_ss_list_8086_1226 NULL +#define pci_ss_list_8086_1227 NULL +#define pci_ss_list_8086_1228 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1229[] = { + &pci_ss_info_8086_1229_0e11_3001, + &pci_ss_info_8086_1229_0e11_3002, + &pci_ss_info_8086_1229_0e11_3003, + &pci_ss_info_8086_1229_0e11_3004, + &pci_ss_info_8086_1229_0e11_3005, + &pci_ss_info_8086_1229_0e11_3006, + &pci_ss_info_8086_1229_0e11_3007, + &pci_ss_info_8086_1229_0e11_b01e, + &pci_ss_info_8086_1229_0e11_b01f, + &pci_ss_info_8086_1229_0e11_b02f, + &pci_ss_info_8086_1229_0e11_b04a, + &pci_ss_info_8086_1229_0e11_b0c6, + &pci_ss_info_8086_1229_0e11_b0c7, + &pci_ss_info_8086_1229_0e11_b0d7, + &pci_ss_info_8086_1229_0e11_b0dd, + &pci_ss_info_8086_1229_0e11_b0de, + &pci_ss_info_8086_1229_0e11_b0e1, + &pci_ss_info_8086_1229_0e11_b134, + &pci_ss_info_8086_1229_0e11_b13c, + &pci_ss_info_8086_1229_0e11_b144, + &pci_ss_info_8086_1229_0e11_b163, + &pci_ss_info_8086_1229_0e11_b164, + &pci_ss_info_8086_1229_0e11_b1a4, + &pci_ss_info_8086_1229_1014_005c, + &pci_ss_info_8086_1229_1014_01bc, + &pci_ss_info_8086_1229_1014_01f1, + &pci_ss_info_8086_1229_1014_01f2, + &pci_ss_info_8086_1229_1014_0207, + &pci_ss_info_8086_1229_1014_0232, + &pci_ss_info_8086_1229_1014_023a, + &pci_ss_info_8086_1229_1014_105c, + &pci_ss_info_8086_1229_1014_2205, + &pci_ss_info_8086_1229_1014_305c, + &pci_ss_info_8086_1229_1014_405c, + &pci_ss_info_8086_1229_1014_505c, + &pci_ss_info_8086_1229_1014_605c, + &pci_ss_info_8086_1229_1014_705c, + &pci_ss_info_8086_1229_1014_805c, + &pci_ss_info_8086_1229_1028_009b, + &pci_ss_info_8086_1229_1033_8000, + &pci_ss_info_8086_1229_1033_8016, + &pci_ss_info_8086_1229_1033_801f, + &pci_ss_info_8086_1229_1033_8026, + &pci_ss_info_8086_1229_1033_8063, + &pci_ss_info_8086_1229_1033_8064, + &pci_ss_info_8086_1229_103c_10c0, + &pci_ss_info_8086_1229_103c_10c3, + &pci_ss_info_8086_1229_103c_10ca, + &pci_ss_info_8086_1229_103c_10cb, + &pci_ss_info_8086_1229_103c_10e3, + &pci_ss_info_8086_1229_103c_10e4, + &pci_ss_info_8086_1229_103c_1200, + &pci_ss_info_8086_1229_10c3_1100, + &pci_ss_info_8086_1229_10cf_1115, + &pci_ss_info_8086_1229_10cf_1143, + &pci_ss_info_8086_1229_1179_0001, + &pci_ss_info_8086_1229_1179_0002, + &pci_ss_info_8086_1229_1179_0003, + &pci_ss_info_8086_1229_1259_2560, + &pci_ss_info_8086_1229_1259_2561, + &pci_ss_info_8086_1229_1266_0001, + &pci_ss_info_8086_1229_144d_2501, + &pci_ss_info_8086_1229_144d_2502, + &pci_ss_info_8086_1229_1668_1100, + &pci_ss_info_8086_1229_8086_0001, + &pci_ss_info_8086_1229_8086_0002, + &pci_ss_info_8086_1229_8086_0003, + &pci_ss_info_8086_1229_8086_0004, + &pci_ss_info_8086_1229_8086_0005, + &pci_ss_info_8086_1229_8086_0006, + &pci_ss_info_8086_1229_8086_0007, + &pci_ss_info_8086_1229_8086_0008, + &pci_ss_info_8086_1229_8086_0009, + &pci_ss_info_8086_1229_8086_000a, + &pci_ss_info_8086_1229_8086_000b, + &pci_ss_info_8086_1229_8086_000c, + &pci_ss_info_8086_1229_8086_000d, + &pci_ss_info_8086_1229_8086_000e, + &pci_ss_info_8086_1229_8086_000f, + &pci_ss_info_8086_1229_8086_0010, + &pci_ss_info_8086_1229_8086_0011, + &pci_ss_info_8086_1229_8086_0012, + &pci_ss_info_8086_1229_8086_0013, + &pci_ss_info_8086_1229_8086_0030, + &pci_ss_info_8086_1229_8086_0031, + &pci_ss_info_8086_1229_8086_0040, + &pci_ss_info_8086_1229_8086_0041, + &pci_ss_info_8086_1229_8086_0042, + &pci_ss_info_8086_1229_8086_0050, + &pci_ss_info_8086_1229_8086_1009, + &pci_ss_info_8086_1229_8086_100c, + &pci_ss_info_8086_1229_8086_1012, + &pci_ss_info_8086_1229_8086_1013, + &pci_ss_info_8086_1229_8086_1015, + &pci_ss_info_8086_1229_8086_1017, + &pci_ss_info_8086_1229_8086_1030, + &pci_ss_info_8086_1229_8086_1040, + &pci_ss_info_8086_1229_8086_1041, + &pci_ss_info_8086_1229_8086_1042, + &pci_ss_info_8086_1229_8086_1050, + &pci_ss_info_8086_1229_8086_1051, + &pci_ss_info_8086_1229_8086_1052, + &pci_ss_info_8086_1229_8086_10f0, + &pci_ss_info_8086_1229_8086_2009, + &pci_ss_info_8086_1229_8086_200d, + &pci_ss_info_8086_1229_8086_200e, + &pci_ss_info_8086_1229_8086_200f, + &pci_ss_info_8086_1229_8086_2010, + &pci_ss_info_8086_1229_8086_2013, + &pci_ss_info_8086_1229_8086_2016, + &pci_ss_info_8086_1229_8086_2017, + &pci_ss_info_8086_1229_8086_2018, + &pci_ss_info_8086_1229_8086_2019, + &pci_ss_info_8086_1229_8086_2101, + &pci_ss_info_8086_1229_8086_2102, + &pci_ss_info_8086_1229_8086_2103, + &pci_ss_info_8086_1229_8086_2104, + &pci_ss_info_8086_1229_8086_2105, + &pci_ss_info_8086_1229_8086_2106, + &pci_ss_info_8086_1229_8086_2107, + &pci_ss_info_8086_1229_8086_2108, + &pci_ss_info_8086_1229_8086_2200, + &pci_ss_info_8086_1229_8086_2201, + &pci_ss_info_8086_1229_8086_2202, + &pci_ss_info_8086_1229_8086_2203, + &pci_ss_info_8086_1229_8086_2204, + &pci_ss_info_8086_1229_8086_2205, + &pci_ss_info_8086_1229_8086_2206, + &pci_ss_info_8086_1229_8086_2207, + &pci_ss_info_8086_1229_8086_2208, + &pci_ss_info_8086_1229_8086_2402, + &pci_ss_info_8086_1229_8086_2407, + &pci_ss_info_8086_1229_8086_2408, + &pci_ss_info_8086_1229_8086_2409, + &pci_ss_info_8086_1229_8086_240f, + &pci_ss_info_8086_1229_8086_2410, + &pci_ss_info_8086_1229_8086_2411, + &pci_ss_info_8086_1229_8086_2412, + &pci_ss_info_8086_1229_8086_2413, + &pci_ss_info_8086_1229_8086_3000, + &pci_ss_info_8086_1229_8086_3001, + &pci_ss_info_8086_1229_8086_3002, + &pci_ss_info_8086_1229_8086_3006, + &pci_ss_info_8086_1229_8086_3007, + &pci_ss_info_8086_1229_8086_3008, + &pci_ss_info_8086_1229_8086_3010, + &pci_ss_info_8086_1229_8086_3011, + &pci_ss_info_8086_1229_8086_3012, + NULL +}; +#define pci_ss_list_8086_122d NULL +#define pci_ss_list_8086_122e NULL +#define pci_ss_list_8086_1230 NULL +#define pci_ss_list_8086_1231 NULL +#define pci_ss_list_8086_1234 NULL +#define pci_ss_list_8086_1235 NULL +#define pci_ss_list_8086_1237 NULL +#define pci_ss_list_8086_1239 NULL +#define pci_ss_list_8086_123b NULL +#define pci_ss_list_8086_123c NULL +#define pci_ss_list_8086_123d NULL +#define pci_ss_list_8086_123f NULL +#define pci_ss_list_8086_1240 NULL +#define pci_ss_list_8086_124b NULL +#define pci_ss_list_8086_1250 NULL +#define pci_ss_list_8086_1360 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1361[] = { + &pci_ss_info_8086_1361_8086_1361, + &pci_ss_info_8086_1361_8086_8000, + NULL +}; +#define pci_ss_list_8086_1460 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1461[] = { + &pci_ss_info_8086_1461_15d9_3480, + NULL +}; +#define pci_ss_list_8086_1462 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1960[] = { + &pci_ss_info_8086_1960_101e_0431, + &pci_ss_info_8086_1960_101e_0438, + &pci_ss_info_8086_1960_101e_0466, + &pci_ss_info_8086_1960_101e_0467, + &pci_ss_info_8086_1960_101e_0490, + &pci_ss_info_8086_1960_101e_0762, + &pci_ss_info_8086_1960_101e_09a0, + &pci_ss_info_8086_1960_1028_0467, + &pci_ss_info_8086_1960_1028_1111, + &pci_ss_info_8086_1960_103c_03a2, + &pci_ss_info_8086_1960_103c_10c6, + &pci_ss_info_8086_1960_103c_10c7, + &pci_ss_info_8086_1960_103c_10cc, + &pci_ss_info_8086_1960_103c_10cd, + &pci_ss_info_8086_1960_105a_0000, + &pci_ss_info_8086_1960_105a_2168, + &pci_ss_info_8086_1960_105a_5168, + &pci_ss_info_8086_1960_1111_1111, + &pci_ss_info_8086_1960_1111_1112, + &pci_ss_info_8086_1960_113c_03a2, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1962[] = { + &pci_ss_info_8086_1962_105a_0000, + NULL +}; +#define pci_ss_list_8086_1a21 NULL +#define pci_ss_list_8086_1a23 NULL +#define pci_ss_list_8086_1a24 NULL +#define pci_ss_list_8086_1a30 NULL +#define pci_ss_list_8086_1a31 NULL +#define pci_ss_list_8086_2410 NULL +#define pci_ss_list_8086_2411 NULL +#define pci_ss_list_8086_2412 NULL +#define pci_ss_list_8086_2413 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2415[] = { + &pci_ss_info_8086_2415_1028_0095, + &pci_ss_info_8086_2415_11d4_0040, + &pci_ss_info_8086_2415_11d4_0048, + &pci_ss_info_8086_2415_11d4_5340, + NULL +}; +#define pci_ss_list_8086_2416 NULL +#define pci_ss_list_8086_2418 NULL +#define pci_ss_list_8086_2420 NULL +#define pci_ss_list_8086_2421 NULL +#define pci_ss_list_8086_2422 NULL +#define pci_ss_list_8086_2423 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2425[] = { + &pci_ss_info_8086_2425_11d4_0040, + &pci_ss_info_8086_2425_11d4_0048, + NULL +}; +#define pci_ss_list_8086_2426 NULL +#define pci_ss_list_8086_2428 NULL +#define pci_ss_list_8086_2440 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2442[] = { + &pci_ss_info_8086_2442_1014_01c6, + &pci_ss_info_8086_2442_1025_1016, + &pci_ss_info_8086_2442_104d_80df, + &pci_ss_info_8086_2442_147b_0507, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2443[] = { + &pci_ss_info_8086_2443_1014_01c6, + &pci_ss_info_8086_2443_1025_1016, + &pci_ss_info_8086_2443_1043_8027, + &pci_ss_info_8086_2443_104d_80df, + &pci_ss_info_8086_2443_147b_0507, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2444[] = { + &pci_ss_info_8086_2444_1025_1016, + &pci_ss_info_8086_2444_104d_80df, + &pci_ss_info_8086_2444_147b_0507, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2445[] = { + &pci_ss_info_8086_2445_1014_01c6, + &pci_ss_info_8086_2445_1025_1016, + &pci_ss_info_8086_2445_104d_80df, + &pci_ss_info_8086_2445_1462_3370, + &pci_ss_info_8086_2445_147b_0507, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2446[] = { + &pci_ss_info_8086_2446_1025_1016, + &pci_ss_info_8086_2446_104d_80df, + NULL +}; +#define pci_ss_list_8086_2448 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2449[] = { + &pci_ss_info_8086_2449_0e11_0012, + &pci_ss_info_8086_2449_0e11_0091, + &pci_ss_info_8086_2449_1014_01ce, + &pci_ss_info_8086_2449_1014_01dc, + &pci_ss_info_8086_2449_1014_01eb, + &pci_ss_info_8086_2449_1014_01ec, + &pci_ss_info_8086_2449_1014_0202, + &pci_ss_info_8086_2449_1014_0205, + &pci_ss_info_8086_2449_1014_0217, + &pci_ss_info_8086_2449_1014_0234, + &pci_ss_info_8086_2449_1014_023d, + &pci_ss_info_8086_2449_1014_0244, + &pci_ss_info_8086_2449_1014_0245, + &pci_ss_info_8086_2449_109f_315d, + &pci_ss_info_8086_2449_109f_3181, + &pci_ss_info_8086_2449_1186_7801, + &pci_ss_info_8086_2449_144d_2602, + &pci_ss_info_8086_2449_8086_3010, + &pci_ss_info_8086_2449_8086_3011, + &pci_ss_info_8086_2449_8086_3012, + &pci_ss_info_8086_2449_8086_3013, + &pci_ss_info_8086_2449_8086_3014, + &pci_ss_info_8086_2449_8086_3015, + &pci_ss_info_8086_2449_8086_3016, + &pci_ss_info_8086_2449_8086_3017, + &pci_ss_info_8086_2449_8086_3018, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_244a[] = { + &pci_ss_info_8086_244a_1025_1016, + &pci_ss_info_8086_244a_104d_80df, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_244b[] = { + &pci_ss_info_8086_244b_1014_01c6, + &pci_ss_info_8086_244b_1043_8027, + &pci_ss_info_8086_244b_147b_0507, + NULL +}; +#define pci_ss_list_8086_244c NULL +#define pci_ss_list_8086_244e NULL +#define pci_ss_list_8086_2450 NULL +#define pci_ss_list_8086_2452 NULL +#define pci_ss_list_8086_2453 NULL +#define pci_ss_list_8086_2459 NULL +#define pci_ss_list_8086_245b NULL +#define pci_ss_list_8086_245d NULL +#define pci_ss_list_8086_245e NULL +#define pci_ss_list_8086_2480 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2482[] = { + &pci_ss_info_8086_2482_1014_0220, + &pci_ss_info_8086_2482_104d_80e7, + &pci_ss_info_8086_2482_15d9_3480, + &pci_ss_info_8086_2482_8086_1958, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2483[] = { + &pci_ss_info_8086_2483_1014_0220, + &pci_ss_info_8086_2483_104d_80e7, + &pci_ss_info_8086_2483_15d9_3480, + &pci_ss_info_8086_2483_8086_1958, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2484[] = { + &pci_ss_info_8086_2484_1014_0220, + &pci_ss_info_8086_2484_104d_80e7, + &pci_ss_info_8086_2484_15d9_3480, + &pci_ss_info_8086_2484_8086_1958, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2485[] = { + &pci_ss_info_8086_2485_1014_0222, + &pci_ss_info_8086_2485_1014_0508, + &pci_ss_info_8086_2485_1014_051c, + &pci_ss_info_8086_2485_104d_80e7, + &pci_ss_info_8086_2485_144d_c006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2486[] = { + &pci_ss_info_8086_2486_1014_0223, + &pci_ss_info_8086_2486_1014_0503, + &pci_ss_info_8086_2486_1014_051a, + &pci_ss_info_8086_2486_104d_80e7, + &pci_ss_info_8086_2486_1179_0001, + &pci_ss_info_8086_2486_134d_4c21, + &pci_ss_info_8086_2486_144d_2115, + &pci_ss_info_8086_2486_14f1_5421, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2487[] = { + &pci_ss_info_8086_2487_1014_0220, + &pci_ss_info_8086_2487_104d_80e7, + &pci_ss_info_8086_2487_15d9_3480, + &pci_ss_info_8086_2487_8086_1958, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_248a[] = { + &pci_ss_info_8086_248a_1014_0220, + &pci_ss_info_8086_248a_104d_80e7, + &pci_ss_info_8086_248a_8086_1958, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_248b[] = { + &pci_ss_info_8086_248b_15d9_3480, + NULL +}; +#define pci_ss_list_8086_248c NULL +static const pciSubsystemInfo *pci_ss_list_8086_24c0[] = { + &pci_ss_info_8086_24c0_1462_5800, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c2[] = { + &pci_ss_info_8086_24c2_1462_5800, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c3[] = { + &pci_ss_info_8086_24c3_1462_5800, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c4[] = { + &pci_ss_info_8086_24c4_1462_5800, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c5[] = { + &pci_ss_info_8086_24c5_1462_5800, + NULL +}; +#define pci_ss_list_8086_24c6 NULL +static const pciSubsystemInfo *pci_ss_list_8086_24c7[] = { + &pci_ss_info_8086_24c7_1462_5800, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24cb[] = { + &pci_ss_info_8086_24cb_1462_5800, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24cd[] = { + &pci_ss_info_8086_24cd_1462_3981, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2500[] = { + &pci_ss_info_8086_2500_1028_0095, + &pci_ss_info_8086_2500_1043_801c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2501[] = { + &pci_ss_info_8086_2501_1043_801c, + NULL +}; +#define pci_ss_list_8086_250b NULL +#define pci_ss_list_8086_250f NULL +#define pci_ss_list_8086_2520 NULL +#define pci_ss_list_8086_2521 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2530[] = { + &pci_ss_info_8086_2530_147b_0507, + NULL +}; +#define pci_ss_list_8086_2531 NULL +#define pci_ss_list_8086_2532 NULL +#define pci_ss_list_8086_2533 NULL +#define pci_ss_list_8086_2534 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2540[] = { + &pci_ss_info_8086_2540_15d9_3480, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2541[] = { + &pci_ss_info_8086_2541_15d9_3480, + NULL +}; +#define pci_ss_list_8086_2543 NULL +#define pci_ss_list_8086_2544 NULL +#define pci_ss_list_8086_2545 NULL +#define pci_ss_list_8086_2546 NULL +#define pci_ss_list_8086_2547 NULL +#define pci_ss_list_8086_2548 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2560[] = { + &pci_ss_info_8086_2560_1462_5800, + NULL +}; +#define pci_ss_list_8086_2561 NULL +#define pci_ss_list_8086_2562 NULL +#define pci_ss_list_8086_2570 NULL +#define pci_ss_list_8086_2572 NULL +#define pci_ss_list_8086_3092 NULL +static const pciSubsystemInfo *pci_ss_list_8086_3575[] = { + &pci_ss_info_8086_3575_1014_021d, + &pci_ss_info_8086_3575_104d_80e7, + NULL +}; +#define pci_ss_list_8086_3576 NULL +static const pciSubsystemInfo *pci_ss_list_8086_3577[] = { + &pci_ss_info_8086_3577_1014_0513, + NULL +}; +#define pci_ss_list_8086_3578 NULL +#define pci_ss_list_8086_3580 NULL +#define pci_ss_list_8086_3582 NULL +#define pci_ss_list_8086_5200 NULL +static const pciSubsystemInfo *pci_ss_list_8086_5201[] = { + &pci_ss_info_8086_5201_8086_0001, + NULL +}; +#define pci_ss_list_8086_530d NULL +#define pci_ss_list_8086_7000 NULL +#define pci_ss_list_8086_7010 NULL +#define pci_ss_list_8086_7020 NULL +#define pci_ss_list_8086_7030 NULL +#define pci_ss_list_8086_7100 NULL +#define pci_ss_list_8086_7110 NULL +#define pci_ss_list_8086_7111 NULL +#define pci_ss_list_8086_7112 NULL +#define pci_ss_list_8086_7113 NULL +#define pci_ss_list_8086_7120 NULL +#define pci_ss_list_8086_7121 NULL +#define pci_ss_list_8086_7122 NULL +#define pci_ss_list_8086_7123 NULL +#define pci_ss_list_8086_7124 NULL +#define pci_ss_list_8086_7125 NULL +#define pci_ss_list_8086_7126 NULL +#define pci_ss_list_8086_7128 NULL +#define pci_ss_list_8086_712a NULL +#define pci_ss_list_8086_7180 NULL +#define pci_ss_list_8086_7181 NULL +static const pciSubsystemInfo *pci_ss_list_8086_7190[] = { + &pci_ss_info_8086_7190_0e11_0500, + &pci_ss_info_8086_7190_0e11_b110, + &pci_ss_info_8086_7190_1179_0001, + NULL +}; +#define pci_ss_list_8086_7191 NULL +static const pciSubsystemInfo *pci_ss_list_8086_7192[] = { + &pci_ss_info_8086_7192_0e11_0460, + NULL +}; +#define pci_ss_list_8086_7194 NULL +static const pciSubsystemInfo *pci_ss_list_8086_7195[] = { + &pci_ss_info_8086_7195_10cf_1099, + &pci_ss_info_8086_7195_11d4_0040, + &pci_ss_info_8086_7195_11d4_0048, + NULL +}; +#define pci_ss_list_8086_7196 NULL +#define pci_ss_list_8086_7198 NULL +#define pci_ss_list_8086_7199 NULL +#define pci_ss_list_8086_719a NULL +#define pci_ss_list_8086_719b NULL +#define pci_ss_list_8086_71a0 NULL +#define pci_ss_list_8086_71a1 NULL +#define pci_ss_list_8086_71a2 NULL +#define pci_ss_list_8086_7600 NULL +#define pci_ss_list_8086_7601 NULL +#define pci_ss_list_8086_7602 NULL +#define pci_ss_list_8086_7603 NULL +static const pciSubsystemInfo *pci_ss_list_8086_7800[] = { + &pci_ss_info_8086_7800_003d_0008, + &pci_ss_info_8086_7800_003d_000b, + &pci_ss_info_8086_7800_1092_0100, + &pci_ss_info_8086_7800_10b4_201a, + &pci_ss_info_8086_7800_10b4_202f, + &pci_ss_info_8086_7800_8086_0000, + &pci_ss_info_8086_7800_8086_0100, + NULL +}; +#define pci_ss_list_8086_84c4 NULL +#define pci_ss_list_8086_84c5 NULL +#define pci_ss_list_8086_84ca NULL +#define pci_ss_list_8086_84cb NULL +#define pci_ss_list_8086_84e0 NULL +#define pci_ss_list_8086_84e1 NULL +#define pci_ss_list_8086_84e2 NULL +#define pci_ss_list_8086_84e3 NULL +#define pci_ss_list_8086_84e4 NULL +#define pci_ss_list_8086_84e6 NULL +#define pci_ss_list_8086_84ea NULL +#define pci_ss_list_8086_9621 NULL +#define pci_ss_list_8086_9622 NULL +#define pci_ss_list_8086_9641 NULL +#define pci_ss_list_8086_96a1 NULL +#define pci_ss_list_8086_b152 NULL +#define pci_ss_list_8086_b154 NULL +static const pciSubsystemInfo *pci_ss_list_8086_b555[] = { + &pci_ss_info_8086_b555_e4bf_1000, + NULL +}; +#define pci_ss_list_8086_ffff NULL +#define pci_ss_list_8800_2008 NULL +#define pci_ss_list_8e2e_3000 NULL +#define pci_ss_list_9004_1078 NULL +#define pci_ss_list_9004_1160 NULL +#define pci_ss_list_9004_2178 NULL +#define pci_ss_list_9004_3860 NULL +#define pci_ss_list_9004_3b78 NULL +#define pci_ss_list_9004_5075 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_9004_5078[] = { + &pci_ss_info_9004_5078_9004_7850, + NULL +}; +#define pci_ss_list_9004_5175 NULL +#define pci_ss_list_9004_5178 NULL +#define pci_ss_list_9004_5275 NULL +#define pci_ss_list_9004_5278 NULL +#define pci_ss_list_9004_5375 NULL +#define pci_ss_list_9004_5378 NULL +#define pci_ss_list_9004_5475 NULL +#define pci_ss_list_9004_5478 NULL +#define pci_ss_list_9004_5575 NULL +#define pci_ss_list_9004_5578 NULL +static const pciSubsystemInfo *pci_ss_list_9004_5647[] = { + &pci_ss_info_9004_5647_9004_7710, + &pci_ss_info_9004_5647_9004_7711, + NULL +}; +#define pci_ss_list_9004_5675 NULL +#define pci_ss_list_9004_5678 NULL +#define pci_ss_list_9004_5775 NULL +#define pci_ss_list_9004_5778 NULL +#define pci_ss_list_9004_5800 NULL +#define pci_ss_list_9004_5900 NULL +#define pci_ss_list_9004_5905 NULL +#define pci_ss_list_9004_6038 NULL +static const pciSubsystemInfo *pci_ss_list_9004_6075[] = { + &pci_ss_info_9004_6075_9004_7560, + NULL +}; +#define pci_ss_list_9004_6078 NULL +static const pciSubsystemInfo *pci_ss_list_9004_6178[] = { + &pci_ss_info_9004_6178_9004_7861, + NULL +}; +#define pci_ss_list_9004_6278 NULL +#define pci_ss_list_9004_6378 NULL +#define pci_ss_list_9004_6478 NULL +#define pci_ss_list_9004_6578 NULL +#define pci_ss_list_9004_6678 NULL +#define pci_ss_list_9004_6778 NULL +static const pciSubsystemInfo *pci_ss_list_9004_6915[] = { + &pci_ss_info_9004_6915_9004_0008, + &pci_ss_info_9004_6915_9004_0009, + &pci_ss_info_9004_6915_9004_0010, + &pci_ss_info_9004_6915_9004_0018, + &pci_ss_info_9004_6915_9004_0019, + &pci_ss_info_9004_6915_9004_0020, + &pci_ss_info_9004_6915_9004_0028, + &pci_ss_info_9004_6915_9004_8008, + &pci_ss_info_9004_6915_9004_8009, + &pci_ss_info_9004_6915_9004_8010, + &pci_ss_info_9004_6915_9004_8018, + &pci_ss_info_9004_6915_9004_8019, + &pci_ss_info_9004_6915_9004_8020, + &pci_ss_info_9004_6915_9004_8028, + NULL +}; +#define pci_ss_list_9004_7078 NULL +#define pci_ss_list_9004_7178 NULL +#define pci_ss_list_9004_7278 NULL +#define pci_ss_list_9004_7378 NULL +#define pci_ss_list_9004_7478 NULL +#define pci_ss_list_9004_7578 NULL +#define pci_ss_list_9004_7678 NULL +#define pci_ss_list_9004_7778 NULL +#define pci_ss_list_9004_7810 NULL +static const pciSubsystemInfo *pci_ss_list_9004_7815[] = { + &pci_ss_info_9004_7815_9004_7815, + &pci_ss_info_9004_7815_9004_7840, + NULL +}; +#define pci_ss_list_9004_7850 NULL +#define pci_ss_list_9004_7855 NULL +#define pci_ss_list_9004_7860 NULL +#define pci_ss_list_9004_7870 NULL +#define pci_ss_list_9004_7871 NULL +#define pci_ss_list_9004_7872 NULL +#define pci_ss_list_9004_7873 NULL +#define pci_ss_list_9004_7874 NULL +#define pci_ss_list_9004_7880 NULL +#define pci_ss_list_9004_7890 NULL +#define pci_ss_list_9004_7891 NULL +#define pci_ss_list_9004_7892 NULL +#define pci_ss_list_9004_7893 NULL +#define pci_ss_list_9004_7894 NULL +static const pciSubsystemInfo *pci_ss_list_9004_7895[] = { + &pci_ss_info_9004_7895_9004_7890, + &pci_ss_info_9004_7895_9004_7891, + &pci_ss_info_9004_7895_9004_7892, + &pci_ss_info_9004_7895_9004_7894, + &pci_ss_info_9004_7895_9004_7895, + &pci_ss_info_9004_7895_9004_7896, + &pci_ss_info_9004_7895_9004_7897, + NULL +}; +#define pci_ss_list_9004_7896 NULL +#define pci_ss_list_9004_7897 NULL +static const pciSubsystemInfo *pci_ss_list_9004_8078[] = { + &pci_ss_info_9004_8078_9004_7880, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9004_8178[] = { + &pci_ss_info_9004_8178_9004_7881, + NULL +}; +#define pci_ss_list_9004_8278 NULL +#define pci_ss_list_9004_8378 NULL +#define pci_ss_list_9004_8478 NULL +#define pci_ss_list_9004_8578 NULL +#define pci_ss_list_9004_8678 NULL +static const pciSubsystemInfo *pci_ss_list_9004_8778[] = { + &pci_ss_info_9004_8778_9004_7887, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9004_8878[] = { + &pci_ss_info_9004_8878_9004_7888, + NULL +}; +#define pci_ss_list_9004_8b78 NULL +#define pci_ss_list_9004_ec78 NULL +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_9005_0010[] = { + &pci_ss_info_9005_0010_9005_2180, + &pci_ss_info_9005_0010_9005_8100, + &pci_ss_info_9005_0010_9005_a180, + &pci_ss_info_9005_0010_9005_e100, + NULL +}; +#define pci_ss_list_9005_0011 NULL +static const pciSubsystemInfo *pci_ss_list_9005_0013[] = { + &pci_ss_info_9005_0013_9005_0003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_001f[] = { + &pci_ss_info_9005_001f_9005_000f, + &pci_ss_info_9005_001f_9005_a180, + NULL +}; +#define pci_ss_list_9005_0020 NULL +#define pci_ss_list_9005_002f NULL +#define pci_ss_list_9005_0030 NULL +#define pci_ss_list_9005_003f NULL +static const pciSubsystemInfo *pci_ss_list_9005_0050[] = { + &pci_ss_info_9005_0050_9005_f500, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0051[] = { + &pci_ss_info_9005_0051_9005_b500, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0053[] = { + &pci_ss_info_9005_0053_9005_ffff, + NULL +}; +#define pci_ss_list_9005_005f NULL +static const pciSubsystemInfo *pci_ss_list_9005_0080[] = { + &pci_ss_info_9005_0080_0e11_e2a0, + &pci_ss_info_9005_0080_9005_62a0, + &pci_ss_info_9005_0080_9005_e220, + &pci_ss_info_9005_0080_9005_e2a0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0081[] = { + &pci_ss_info_9005_0081_9005_62a1, + NULL +}; +#define pci_ss_list_9005_0083 NULL +static const pciSubsystemInfo *pci_ss_list_9005_008f[] = { + &pci_ss_info_9005_008f_1179_0001, + &pci_ss_info_9005_008f_15d9_9005, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_00c0[] = { + &pci_ss_info_9005_00c0_0e11_f620, + &pci_ss_info_9005_00c0_9005_f620, + NULL +}; +#define pci_ss_list_9005_00c1 NULL +#define pci_ss_list_9005_00c3 NULL +static const pciSubsystemInfo *pci_ss_list_9005_00c5[] = { + &pci_ss_info_9005_00c5_1028_00c5, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_00cf[] = { + &pci_ss_info_9005_00cf_1028_00d1, + &pci_ss_info_9005_00cf_10f1_2462, + &pci_ss_info_9005_00cf_15d9_9005, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0250[] = { + &pci_ss_info_9005_0250_1014_0279, + &pci_ss_info_9005_0250_1014_028c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0285[] = { + &pci_ss_info_9005_0285_1028_0287, + NULL +}; +#define pci_ss_list_9005_8000 NULL +#define pci_ss_list_9005_800f NULL +#define pci_ss_list_9005_8010 NULL +static const pciSubsystemInfo *pci_ss_list_9005_8011[] = { + &pci_ss_info_9005_8011_0e11_00ac, + &pci_ss_info_9005_8011_9005_0041, + NULL +}; +#define pci_ss_list_9005_8012 NULL +#define pci_ss_list_9005_8013 NULL +#define pci_ss_list_9005_8014 NULL +#define pci_ss_list_9005_801e NULL +#define pci_ss_list_9005_801f NULL +#define pci_ss_list_9005_8090 NULL +#define pci_ss_list_9005_8091 NULL +#define pci_ss_list_9005_8092 NULL +#define pci_ss_list_9005_8093 NULL +#define pci_ss_list_9005_8094 NULL +#define pci_ss_list_9005_809e NULL +#define pci_ss_list_9005_809f NULL +#endif +#define pci_ss_list_907f_2015 NULL +#define pci_ss_list_9412_6565 NULL +#define pci_ss_list_9699_6565 NULL +#define pci_ss_list_9710_9815 NULL +#define pci_ss_list_9710_9835 NULL +#define pci_ss_list_cddd_0101 NULL +#define pci_ss_list_cddd_0200 NULL +#define pci_ss_list_d4d4_0601 NULL +#define pci_ss_list_e000_e000 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_e159_0001[] = { + &pci_ss_info_e159_0001_0059_0001, + &pci_ss_info_e159_0001_0059_0003, + NULL +}; +#define pci_ss_list_e159_0002 NULL +#endif +#define pci_ss_list_ea60_9896 NULL +#define pci_ss_list_ea60_9897 NULL +#define pci_ss_list_ea60_9898 NULL +#define pci_ss_list_eace_3100 NULL +#define pci_ss_list_eace_3200 NULL +#define pci_ss_list_eace_320e NULL +#define pci_ss_list_eace_340e NULL +#define pci_ss_list_eace_341e NULL +#define pci_ss_list_eace_3500 NULL +#define pci_ss_list_eace_351c NULL +#define pci_ss_list_eace_4100 NULL +#define pci_ss_list_eace_4110 NULL +#define pci_ss_list_eace_4220 NULL +#define pci_ss_list_eace_422e NULL +#define pci_ss_list_ec80_ec00 NULL +#define pci_ss_list_ecc0_0050 NULL +#define pci_ss_list_ecc0_0051 NULL +#define pci_ss_list_ecc0_0060 NULL +#define pci_ss_list_ecc0_0070 NULL +#define pci_ss_list_ecc0_0071 NULL +#define pci_ss_list_ecc0_0072 NULL +#define pci_ss_list_ecc0_0080 NULL +#define pci_ss_list_edd8_a091 NULL +#define pci_ss_list_edd8_a099 NULL +#define pci_ss_list_edd8_a0a1 NULL +#define pci_ss_list_edd8_a0a9 NULL +#define pci_ss_list_f1d0_cafe NULL +#define pci_ss_list_f1d0_efac NULL +#define pci_ss_list_f1d0_facd NULL +#define pci_ss_list_feda_a0fa NULL +#define pci_ss_list_feda_a10e NULL +#define pci_ss_list_fffe_0710 NULL +#ifdef INIT_VENDOR_SUBSYS_INFO +#define pci_ss_list_0000 NULL +#define pci_ss_list_001a NULL +#define pci_ss_list_0033 NULL +static const pciSubsystemInfo *pci_ss_list_003d[] = { + &pci_ss_info_003d_0008, + &pci_ss_info_003d_000b, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0059[] = { + &pci_ss_info_0059_0001, + &pci_ss_info_0059_0003, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0070[] = { + &pci_ss_info_0070_13eb, + &pci_ss_info_0070_ff01, + NULL +}; +#endif +#define pci_ss_list_0100 NULL +#define pci_ss_list_0675 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0925[] = { + &pci_ss_info_0925_1234, + NULL +}; +#endif +#define pci_ss_list_09c1 NULL +#define pci_ss_list_0a89 NULL +static const pciSubsystemInfo *pci_ss_list_0e11[] = { + &pci_ss_info_0e11_0012, + &pci_ss_info_0e11_0022, + &pci_ss_info_0e11_0023, + &pci_ss_info_0e11_0024, + &pci_ss_info_0e11_0042, + &pci_ss_info_0e11_0043, + &pci_ss_info_0e11_0049, + &pci_ss_info_0e11_004a, + &pci_ss_info_0e11_005d, + &pci_ss_info_0e11_007c, + &pci_ss_info_0e11_007d, + &pci_ss_info_0e11_007e, + &pci_ss_info_0e11_0085, + &pci_ss_info_0e11_0091, + &pci_ss_info_0e11_0099, + &pci_ss_info_0e11_009a, + &pci_ss_info_0e11_00ac, + &pci_ss_info_0e11_00bb, + &pci_ss_info_0e11_00c1, + &pci_ss_info_0e11_00ca, + &pci_ss_info_0e11_00cb, + &pci_ss_info_0e11_00cf, + &pci_ss_info_0e11_00d0, + &pci_ss_info_0e11_00d1, + &pci_ss_info_0e11_0460, + &pci_ss_info_0e11_0500, + &pci_ss_info_0e11_3001, + &pci_ss_info_0e11_3002, + &pci_ss_info_0e11_3003, + &pci_ss_info_0e11_3004, + &pci_ss_info_0e11_3005, + &pci_ss_info_0e11_3006, + &pci_ss_info_0e11_3007, + &pci_ss_info_0e11_4030, + &pci_ss_info_0e11_4031, + &pci_ss_info_0e11_4032, + &pci_ss_info_0e11_4033, + &pci_ss_info_0e11_4040, + &pci_ss_info_0e11_4048, + &pci_ss_info_0e11_4050, + &pci_ss_info_0e11_4051, + &pci_ss_info_0e11_4058, + &pci_ss_info_0e11_7004, + &pci_ss_info_0e11_b01e, + &pci_ss_info_0e11_b01f, + &pci_ss_info_0e11_b02f, + &pci_ss_info_0e11_b032, + &pci_ss_info_0e11_b03b, + &pci_ss_info_0e11_b03c, + &pci_ss_info_0e11_b03d, + &pci_ss_info_0e11_b03e, + &pci_ss_info_0e11_b03f, + &pci_ss_info_0e11_b049, + &pci_ss_info_0e11_b04a, + &pci_ss_info_0e11_b0bc, + &pci_ss_info_0e11_b0c6, + &pci_ss_info_0e11_b0c7, + &pci_ss_info_0e11_b0d1, + &pci_ss_info_0e11_b0d7, + &pci_ss_info_0e11_b0dd, + &pci_ss_info_0e11_b0de, + &pci_ss_info_0e11_b0df, + &pci_ss_info_0e11_b0e0, + &pci_ss_info_0e11_b0e1, + &pci_ss_info_0e11_b0e8, + &pci_ss_info_0e11_b0fd, + &pci_ss_info_0e11_b10e, + &pci_ss_info_0e11_b110, + &pci_ss_info_0e11_b111, + &pci_ss_info_0e11_b112, + &pci_ss_info_0e11_b113, + &pci_ss_info_0e11_b114, + &pci_ss_info_0e11_b123, + &pci_ss_info_0e11_b126, + &pci_ss_info_0e11_b134, + &pci_ss_info_0e11_b13c, + &pci_ss_info_0e11_b144, + &pci_ss_info_0e11_b14d, + &pci_ss_info_0e11_b15a, + &pci_ss_info_0e11_b163, + &pci_ss_info_0e11_b164, + &pci_ss_info_0e11_b16e, + &pci_ss_info_0e11_b16f, + &pci_ss_info_0e11_b194, + &pci_ss_info_0e11_b195, + &pci_ss_info_0e11_b196, + &pci_ss_info_0e11_b1a4, + &pci_ss_info_0e11_b1a7, + &pci_ss_info_0e11_b1be, + &pci_ss_info_0e11_e2a0, + &pci_ss_info_0e11_f620, + NULL +}; +#define pci_ss_list_0e55 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1000[] = { + &pci_ss_info_1000_1000, + NULL +}; +#endif +#define pci_ss_list_1001 NULL +static const pciSubsystemInfo *pci_ss_list_1002[] = { + &pci_ss_info_1002_0001, + &pci_ss_info_1002_0002, + &pci_ss_info_1002_0003, + &pci_ss_info_1002_0004, + &pci_ss_info_1002_0008, + &pci_ss_info_1002_0009, + &pci_ss_info_1002_000a, + &pci_ss_info_1002_000b, + &pci_ss_info_1002_0014, + &pci_ss_info_1002_0018, + &pci_ss_info_1002_001a, + &pci_ss_info_1002_001c, + &pci_ss_info_1002_0028, + &pci_ss_info_1002_0029, + &pci_ss_info_1002_002a, + &pci_ss_info_1002_002b, + &pci_ss_info_1002_0038, + &pci_ss_info_1002_0039, + &pci_ss_info_1002_003a, + &pci_ss_info_1002_0040, + &pci_ss_info_1002_0044, + &pci_ss_info_1002_0048, + &pci_ss_info_1002_0061, + &pci_ss_info_1002_0062, + &pci_ss_info_1002_0063, + &pci_ss_info_1002_0068, + &pci_ss_info_1002_0080, + &pci_ss_info_1002_0084, + &pci_ss_info_1002_0087, + &pci_ss_info_1002_0088, + &pci_ss_info_1002_008a, + &pci_ss_info_1002_00ba, + &pci_ss_info_1002_010a, + &pci_ss_info_1002_0139, + &pci_ss_info_1002_013a, + &pci_ss_info_1002_0152, + &pci_ss_info_1002_0162, + &pci_ss_info_1002_0172, + &pci_ss_info_1002_028a, + &pci_ss_info_1002_02aa, + &pci_ss_info_1002_0448, + &pci_ss_info_1002_053a, + &pci_ss_info_1002_2000, + &pci_ss_info_1002_2001, + &pci_ss_info_1002_4742, + &pci_ss_info_1002_4744, + &pci_ss_info_1002_474d, + &pci_ss_info_1002_474e, + &pci_ss_info_1002_474f, + &pci_ss_info_1002_4750, + &pci_ss_info_1002_4752, + &pci_ss_info_1002_4753, + &pci_ss_info_1002_4756, + &pci_ss_info_1002_4757, + &pci_ss_info_1002_475a, + &pci_ss_info_1002_4c42, + &pci_ss_info_1002_4c49, + &pci_ss_info_1002_4c50, + &pci_ss_info_1002_5654, + &pci_ss_info_1002_8001, + &pci_ss_info_1002_8008, + NULL +}; +#define pci_ss_list_1003 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1004[] = { + &pci_ss_info_1004_0304, + &pci_ss_info_1004_0305, + &pci_ss_info_1004_0306, + NULL +}; +#endif +#define pci_ss_list_1005 NULL +#define pci_ss_list_1006 NULL +#define pci_ss_list_1007 NULL +#define pci_ss_list_1008 NULL +#define pci_ss_list_100a NULL +#define pci_ss_list_100b NULL +#define pci_ss_list_100c NULL +#define pci_ss_list_100d NULL +#define pci_ss_list_100e NULL +static const pciSubsystemInfo *pci_ss_list_1010[] = { + &pci_ss_info_1010_0020, + &pci_ss_info_1010_0080, + &pci_ss_info_1010_0088, + &pci_ss_info_1010_0090, + &pci_ss_info_1010_0098, + &pci_ss_info_1010_00a0, + &pci_ss_info_1010_00a8, + &pci_ss_info_1010_0120, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1011[] = { + &pci_ss_info_1011_4d10, + &pci_ss_info_1011_500a, + &pci_ss_info_1011_500b, + NULL +}; +#define pci_ss_list_1012 NULL +static const pciSubsystemInfo *pci_ss_list_1013[] = { + &pci_ss_info_1013_00bc, + &pci_ss_info_1013_4280, + &pci_ss_info_1013_4281, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1014[] = { + &pci_ss_info_1014_0001, + &pci_ss_info_1014_002e, + &pci_ss_info_1014_003e, + &pci_ss_info_1014_005c, + &pci_ss_info_1014_008e, + &pci_ss_info_1014_0097, + &pci_ss_info_1014_0098, + &pci_ss_info_1014_0099, + &pci_ss_info_1014_00ba, + &pci_ss_info_1014_00cd, + &pci_ss_info_1014_00ce, + &pci_ss_info_1014_00cf, + &pci_ss_info_1014_00db, + &pci_ss_info_1014_00dd, + &pci_ss_info_1014_00e4, + &pci_ss_info_1014_00e5, + &pci_ss_info_1014_0119, + &pci_ss_info_1014_0131, + &pci_ss_info_1014_0143, + &pci_ss_info_1014_0145, + &pci_ss_info_1014_0154, + &pci_ss_info_1014_0166, + &pci_ss_info_1014_016d, + &pci_ss_info_1014_017f, + &pci_ss_info_1014_0181, + &pci_ss_info_1014_0182, + &pci_ss_info_1014_0183, + &pci_ss_info_1014_0184, + &pci_ss_info_1014_0185, + &pci_ss_info_1014_01b6, + &pci_ss_info_1014_01b7, + &pci_ss_info_1014_01bc, + &pci_ss_info_1014_01be, + &pci_ss_info_1014_01bf, + &pci_ss_info_1014_01c6, + &pci_ss_info_1014_01ce, + &pci_ss_info_1014_01cf, + &pci_ss_info_1014_01dc, + &pci_ss_info_1014_01ea, + &pci_ss_info_1014_01eb, + &pci_ss_info_1014_01ec, + &pci_ss_info_1014_01f1, + &pci_ss_info_1014_01f2, + &pci_ss_info_1014_01fc, + &pci_ss_info_1014_0202, + &pci_ss_info_1014_0205, + &pci_ss_info_1014_0207, + &pci_ss_info_1014_0208, + &pci_ss_info_1014_0209, + &pci_ss_info_1014_020e, + &pci_ss_info_1014_0217, + &pci_ss_info_1014_021d, + &pci_ss_info_1014_0220, + &pci_ss_info_1014_0222, + &pci_ss_info_1014_0223, + &pci_ss_info_1014_022e, + &pci_ss_info_1014_0232, + &pci_ss_info_1014_0234, + &pci_ss_info_1014_0235, + &pci_ss_info_1014_0239, + &pci_ss_info_1014_023a, + &pci_ss_info_1014_023b, + &pci_ss_info_1014_023d, + &pci_ss_info_1014_0244, + &pci_ss_info_1014_0245, + &pci_ss_info_1014_0258, + &pci_ss_info_1014_0259, + &pci_ss_info_1014_0277, + &pci_ss_info_1014_0279, + &pci_ss_info_1014_028c, + &pci_ss_info_1014_0502, + &pci_ss_info_1014_0503, + &pci_ss_info_1014_0506, + &pci_ss_info_1014_0508, + &pci_ss_info_1014_0511, + &pci_ss_info_1014_0512, + &pci_ss_info_1014_0513, + &pci_ss_info_1014_0517, + &pci_ss_info_1014_051a, + &pci_ss_info_1014_051c, + &pci_ss_info_1014_1010, + &pci_ss_info_1014_105c, + &pci_ss_info_1014_10f2, + &pci_ss_info_1014_1181, + &pci_ss_info_1014_1182, + &pci_ss_info_1014_2000, + &pci_ss_info_1014_2205, + &pci_ss_info_1014_305c, + &pci_ss_info_1014_405c, + &pci_ss_info_1014_505c, + &pci_ss_info_1014_605c, + &pci_ss_info_1014_705c, + &pci_ss_info_1014_805c, + &pci_ss_info_1014_8181, + &pci_ss_info_1014_9181, + &pci_ss_info_1014_9750, + &pci_ss_info_1014_ff03, + NULL +}; +#endif +#define pci_ss_list_1015 NULL +#define pci_ss_list_1016 NULL +#define pci_ss_list_1017 NULL +#define pci_ss_list_1018 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1019[] = { + &pci_ss_info_1019_0970, + &pci_ss_info_1019_7018, + NULL +}; +#endif +#define pci_ss_list_101a NULL +#define pci_ss_list_101b NULL +#define pci_ss_list_101c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_101e[] = { + &pci_ss_info_101e_0431, + &pci_ss_info_101e_0438, + &pci_ss_info_101e_0466, + &pci_ss_info_101e_0467, + &pci_ss_info_101e_0471, + &pci_ss_info_101e_0475, + &pci_ss_info_101e_0490, + &pci_ss_info_101e_0493, + &pci_ss_info_101e_0649, + &pci_ss_info_101e_0762, + &pci_ss_info_101e_0767, + &pci_ss_info_101e_09a0, + &pci_ss_info_101e_8471, + &pci_ss_info_101e_8493, + NULL +}; +#endif +#define pci_ss_list_101f NULL +#define pci_ss_list_1020 NULL +#define pci_ss_list_1021 NULL +#define pci_ss_list_1022 NULL +static const pciSubsystemInfo *pci_ss_list_1023[] = { + &pci_ss_info_1023_8400, + &pci_ss_info_1023_8520, + &pci_ss_info_1023_9750, + &pci_ss_info_1023_9880, + NULL +}; +#define pci_ss_list_1024 NULL +static const pciSubsystemInfo *pci_ss_list_1025[] = { + &pci_ss_info_1025_000e, + &pci_ss_info_1025_0018, + &pci_ss_info_1025_0310, + &pci_ss_info_1025_0315, + &pci_ss_info_1025_1003, + &pci_ss_info_1025_1007, + &pci_ss_info_1025_1016, + &pci_ss_info_1025_8013, + &pci_ss_info_1025_8920, + &pci_ss_info_1025_8921, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1028[] = { + &pci_ss_info_1028_0001, + &pci_ss_info_1028_0002, + &pci_ss_info_1028_0003, + &pci_ss_info_1028_0074, + &pci_ss_info_1028_0075, + &pci_ss_info_1028_007d, + &pci_ss_info_1028_007e, + &pci_ss_info_1028_0080, + &pci_ss_info_1028_0081, + &pci_ss_info_1028_0082, + &pci_ss_info_1028_0083, + &pci_ss_info_1028_0084, + &pci_ss_info_1028_0085, + &pci_ss_info_1028_0086, + &pci_ss_info_1028_0087, + &pci_ss_info_1028_0088, + &pci_ss_info_1028_0089, + &pci_ss_info_1028_008f, + &pci_ss_info_1028_0090, + &pci_ss_info_1028_0091, + &pci_ss_info_1028_0092, + &pci_ss_info_1028_0093, + &pci_ss_info_1028_0094, + &pci_ss_info_1028_0095, + &pci_ss_info_1028_0096, + &pci_ss_info_1028_0097, + &pci_ss_info_1028_0098, + &pci_ss_info_1028_0099, + &pci_ss_info_1028_009b, + &pci_ss_info_1028_00c5, + &pci_ss_info_1028_00d0, + &pci_ss_info_1028_00d1, + &pci_ss_info_1028_00d9, + &pci_ss_info_1028_00e6, + &pci_ss_info_1028_0106, + &pci_ss_info_1028_0109, + &pci_ss_info_1028_010a, + &pci_ss_info_1028_011b, + &pci_ss_info_1028_0121, + &pci_ss_info_1028_0126, + &pci_ss_info_1028_0287, + &pci_ss_info_1028_0467, + &pci_ss_info_1028_0471, + &pci_ss_info_1028_0475, + &pci_ss_info_1028_0493, + &pci_ss_info_1028_0511, + &pci_ss_info_1028_0518, + &pci_ss_info_1028_0520, + &pci_ss_info_1028_0531, + &pci_ss_info_1028_1010, + &pci_ss_info_1028_1111, + &pci_ss_info_1028_4082, + &pci_ss_info_1028_8082, + &pci_ss_info_1028_c082, + NULL +}; +#define pci_ss_list_1029 NULL +#define pci_ss_list_102a NULL +static const pciSubsystemInfo *pci_ss_list_102b[] = { + &pci_ss_info_102b_0100, + &pci_ss_info_102b_0328, + &pci_ss_info_102b_0338, + &pci_ss_info_102b_0378, + &pci_ss_info_102b_051b, + &pci_ss_info_102b_0541, + &pci_ss_info_102b_0542, + &pci_ss_info_102b_0543, + &pci_ss_info_102b_0641, + &pci_ss_info_102b_0642, + &pci_ss_info_102b_0643, + &pci_ss_info_102b_07c0, + &pci_ss_info_102b_07c1, + &pci_ss_info_102b_0840, + &pci_ss_info_102b_0d41, + &pci_ss_info_102b_0d42, + &pci_ss_info_102b_0e00, + &pci_ss_info_102b_0e01, + &pci_ss_info_102b_0e02, + &pci_ss_info_102b_0e03, + &pci_ss_info_102b_0f80, + &pci_ss_info_102b_0f81, + &pci_ss_info_102b_0f82, + &pci_ss_info_102b_0f83, + &pci_ss_info_102b_0f84, + &pci_ss_info_102b_1001, + &pci_ss_info_102b_1100, + &pci_ss_info_102b_1200, + &pci_ss_info_102b_19d8, + &pci_ss_info_102b_19f8, + &pci_ss_info_102b_1e41, + &pci_ss_info_102b_2159, + &pci_ss_info_102b_2179, + &pci_ss_info_102b_217d, + &pci_ss_info_102b_23c0, + &pci_ss_info_102b_23c1, + &pci_ss_info_102b_23c2, + &pci_ss_info_102b_23c3, + &pci_ss_info_102b_2f58, + &pci_ss_info_102b_2f78, + &pci_ss_info_102b_3693, + &pci_ss_info_102b_48e9, + &pci_ss_info_102b_48f8, + &pci_ss_info_102b_4a60, + &pci_ss_info_102b_4a64, + &pci_ss_info_102b_5dd0, + &pci_ss_info_102b_5f50, + &pci_ss_info_102b_5f51, + &pci_ss_info_102b_5f52, + &pci_ss_info_102b_9010, + &pci_ss_info_102b_c93c, + &pci_ss_info_102b_c9b0, + &pci_ss_info_102b_c9bc, + &pci_ss_info_102b_ca60, + &pci_ss_info_102b_ca6c, + &pci_ss_info_102b_dbbc, + &pci_ss_info_102b_dbc2, + &pci_ss_info_102b_dbc3, + &pci_ss_info_102b_dbc8, + &pci_ss_info_102b_dbd2, + &pci_ss_info_102b_dbd3, + &pci_ss_info_102b_dbd4, + &pci_ss_info_102b_dbd5, + &pci_ss_info_102b_dbd8, + &pci_ss_info_102b_dbd9, + &pci_ss_info_102b_dbe2, + &pci_ss_info_102b_dbe3, + &pci_ss_info_102b_dbe8, + &pci_ss_info_102b_dbf2, + &pci_ss_info_102b_dbf3, + &pci_ss_info_102b_dbf4, + &pci_ss_info_102b_dbf5, + &pci_ss_info_102b_dbf8, + &pci_ss_info_102b_dbf9, + &pci_ss_info_102b_f806, + &pci_ss_info_102b_ff00, + &pci_ss_info_102b_ff01, + &pci_ss_info_102b_ff02, + &pci_ss_info_102b_ff03, + &pci_ss_info_102b_ff04, + &pci_ss_info_102b_ff05, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102c[] = { + &pci_ss_info_102c_00c0, + NULL +}; +#define pci_ss_list_102d NULL +#define pci_ss_list_102e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_102f[] = { + &pci_ss_info_102f_00f8, + NULL +}; +#endif +#define pci_ss_list_1030 NULL +static const pciSubsystemInfo *pci_ss_list_1031[] = { + &pci_ss_info_1031_7efe, + &pci_ss_info_1031_fc00, + NULL +}; +#define pci_ss_list_1032 NULL +static const pciSubsystemInfo *pci_ss_list_1033[] = { + &pci_ss_info_1033_8000, + &pci_ss_info_1033_800c, + &pci_ss_info_1033_800d, + &pci_ss_info_1033_8014, + &pci_ss_info_1033_8015, + &pci_ss_info_1033_8016, + &pci_ss_info_1033_801f, + &pci_ss_info_1033_8026, + &pci_ss_info_1033_8029, + &pci_ss_info_1033_802b, + &pci_ss_info_1033_802f, + &pci_ss_info_1033_803c, + &pci_ss_info_1033_8047, + &pci_ss_info_1033_804d, + &pci_ss_info_1033_804f, + &pci_ss_info_1033_8051, + &pci_ss_info_1033_8054, + &pci_ss_info_1033_8058, + &pci_ss_info_1033_8063, + &pci_ss_info_1033_8064, + &pci_ss_info_1033_8065, + &pci_ss_info_1033_8066, + &pci_ss_info_1033_8068, + &pci_ss_info_1033_8069, + &pci_ss_info_1033_806a, + &pci_ss_info_1033_8077, + &pci_ss_info_1033_809d, + &pci_ss_info_1033_80ac, + &pci_ss_info_1033_80bc, + NULL +}; +#define pci_ss_list_1034 NULL +#define pci_ss_list_1035 NULL +#define pci_ss_list_1036 NULL +#define pci_ss_list_1037 NULL +#define pci_ss_list_1038 NULL +static const pciSubsystemInfo *pci_ss_list_1039[] = { + &pci_ss_info_1039_0000, + &pci_ss_info_1039_0900, + &pci_ss_info_1039_5513, + &pci_ss_info_1039_6306, + &pci_ss_info_1039_6326, + &pci_ss_info_1039_7000, + &pci_ss_info_1039_7016, + &pci_ss_info_1039_7018, + NULL +}; +#define pci_ss_list_103a NULL +#define pci_ss_list_103b NULL +static const pciSubsystemInfo *pci_ss_list_103c[] = { + &pci_ss_info_103c_0007, + &pci_ss_info_103c_0008, + &pci_ss_info_103c_000d, + &pci_ss_info_103c_03a2, + &pci_ss_info_103c_1040, + &pci_ss_info_103c_1041, + &pci_ss_info_103c_1042, + &pci_ss_info_103c_1049, + &pci_ss_info_103c_104a, + &pci_ss_info_103c_104b, + &pci_ss_info_103c_104c, + &pci_ss_info_103c_1064, + &pci_ss_info_103c_1065, + &pci_ss_info_103c_106c, + &pci_ss_info_103c_106e, + &pci_ss_info_103c_10c0, + &pci_ss_info_103c_10c2, + &pci_ss_info_103c_10c3, + &pci_ss_info_103c_10c6, + &pci_ss_info_103c_10c7, + &pci_ss_info_103c_10ca, + &pci_ss_info_103c_10cb, + &pci_ss_info_103c_10cc, + &pci_ss_info_103c_10cd, + &pci_ss_info_103c_10e3, + &pci_ss_info_103c_10e4, + &pci_ss_info_103c_10ea, + &pci_ss_info_103c_1200, + &pci_ss_info_103c_1207, + &pci_ss_info_103c_1223, + &pci_ss_info_103c_1226, + &pci_ss_info_103c_1227, + &pci_ss_info_103c_1279, + &pci_ss_info_103c_1282, + NULL +}; +#define pci_ss_list_103e NULL +#define pci_ss_list_103f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1040[] = { + &pci_ss_info_1040_000f, + &pci_ss_info_1040_0011, + NULL +}; +#endif +#define pci_ss_list_1041 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1042[] = { + &pci_ss_info_1042_1854, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1043[] = { + &pci_ss_info_1043_0200, + &pci_ss_info_1043_0201, + &pci_ss_info_1043_0202, + &pci_ss_info_1043_0205, + &pci_ss_info_1043_0c11, + &pci_ss_info_1043_4000, + &pci_ss_info_1043_4008, + &pci_ss_info_1043_4009, + &pci_ss_info_1043_400a, + &pci_ss_info_1043_400b, + &pci_ss_info_1043_4015, + &pci_ss_info_1043_4016, + &pci_ss_info_1043_402f, + &pci_ss_info_1043_4031, + &pci_ss_info_1043_405b, + &pci_ss_info_1043_405f, + &pci_ss_info_1043_800b, + &pci_ss_info_1043_801c, + &pci_ss_info_1043_8027, + &pci_ss_info_1043_8033, + &pci_ss_info_1043_803e, + &pci_ss_info_1043_8040, + &pci_ss_info_1043_8042, + &pci_ss_info_1043_8044, + &pci_ss_info_1043_8052, + &pci_ss_info_1043_8053, + &pci_ss_info_1043_8064, + &pci_ss_info_1043_8077, + &pci_ss_info_1043_807f, + &pci_ss_info_1043_80ad, + &pci_ss_info_1043_80e2, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1044[] = { + &pci_ss_info_1044_c001, + &pci_ss_info_1044_c002, + &pci_ss_info_1044_c003, + &pci_ss_info_1044_c004, + &pci_ss_info_1044_c005, + &pci_ss_info_1044_c00a, + &pci_ss_info_1044_c00b, + &pci_ss_info_1044_c00c, + &pci_ss_info_1044_c00d, + &pci_ss_info_1044_c00e, + &pci_ss_info_1044_c00f, + &pci_ss_info_1044_c014, + &pci_ss_info_1044_c015, + &pci_ss_info_1044_c016, + &pci_ss_info_1044_c01e, + &pci_ss_info_1044_c01f, + &pci_ss_info_1044_c020, + &pci_ss_info_1044_c021, + &pci_ss_info_1044_c028, + &pci_ss_info_1044_c029, + &pci_ss_info_1044_c02a, + &pci_ss_info_1044_c03c, + &pci_ss_info_1044_c03d, + &pci_ss_info_1044_c03e, + &pci_ss_info_1044_c046, + &pci_ss_info_1044_c047, + &pci_ss_info_1044_c048, + &pci_ss_info_1044_c050, + &pci_ss_info_1044_c051, + &pci_ss_info_1044_c052, + &pci_ss_info_1044_c05a, + &pci_ss_info_1044_c05b, + &pci_ss_info_1044_c064, + &pci_ss_info_1044_c065, + &pci_ss_info_1044_c066, + NULL +}; +#endif +#define pci_ss_list_1045 NULL +#define pci_ss_list_1046 NULL +#define pci_ss_list_1047 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1048[] = { + &pci_ss_info_1048_0a31, + &pci_ss_info_1048_0a32, + &pci_ss_info_1048_0a35, + &pci_ss_info_1048_0c10, + &pci_ss_info_1048_0c18, + &pci_ss_info_1048_0c1b, + &pci_ss_info_1048_0c3a, + &pci_ss_info_1048_0c56, + &pci_ss_info_1048_1500, + NULL +}; +#endif +#define pci_ss_list_1049 NULL +#define pci_ss_list_104a NULL +#define pci_ss_list_104b NULL +#define pci_ss_list_104c NULL +static const pciSubsystemInfo *pci_ss_list_104d[] = { + &pci_ss_info_104d_801b, + &pci_ss_info_104d_802f, + &pci_ss_info_104d_8032, + &pci_ss_info_104d_8036, + &pci_ss_info_104d_8044, + &pci_ss_info_104d_8045, + &pci_ss_info_104d_8049, + &pci_ss_info_104d_8055, + &pci_ss_info_104d_8056, + &pci_ss_info_104d_805a, + &pci_ss_info_104d_805f, + &pci_ss_info_104d_8067, + &pci_ss_info_104d_8074, + &pci_ss_info_104d_8075, + &pci_ss_info_104d_8077, + &pci_ss_info_104d_807b, + &pci_ss_info_104d_8083, + &pci_ss_info_104d_8097, + &pci_ss_info_104d_80df, + &pci_ss_info_104d_80e7, + &pci_ss_info_104d_830b, + NULL +}; +#define pci_ss_list_104e NULL +#define pci_ss_list_104f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1050[] = { + &pci_ss_info_1050_0001, + &pci_ss_info_1050_0840, + NULL +}; +#endif +#define pci_ss_list_1051 NULL +#define pci_ss_list_1052 NULL +#define pci_ss_list_1053 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1054[] = { + &pci_ss_info_1054_7018, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1055[] = { + &pci_ss_info_1055_e000, + &pci_ss_info_1055_e002, + &pci_ss_info_1055_e100, + &pci_ss_info_1055_e102, + &pci_ss_info_1055_e300, + &pci_ss_info_1055_e302, + NULL +}; +#endif +#define pci_ss_list_1056 NULL +static const pciSubsystemInfo *pci_ss_list_1057[] = { + &pci_ss_info_1057_0300, + &pci_ss_info_1057_0301, + &pci_ss_info_1057_0302, + &pci_ss_info_1057_5600, + NULL +}; +#define pci_ss_list_1058 NULL +#define pci_ss_list_1059 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_105a[] = { + &pci_ss_info_105a_0000, + &pci_ss_info_105a_0275, + &pci_ss_info_105a_2168, + &pci_ss_info_105a_4d30, + &pci_ss_info_105a_4d33, + &pci_ss_info_105a_4d39, + &pci_ss_info_105a_4d68, + &pci_ss_info_105a_5168, + &pci_ss_info_105a_6269, + NULL +}; +#endif +#define pci_ss_list_105b NULL +#define pci_ss_list_105c NULL +static const pciSubsystemInfo *pci_ss_list_105d[] = { + &pci_ss_info_105d_0000, + &pci_ss_info_105d_0001, + &pci_ss_info_105d_0002, + &pci_ss_info_105d_0003, + &pci_ss_info_105d_0004, + &pci_ss_info_105d_0005, + &pci_ss_info_105d_0006, + &pci_ss_info_105d_0007, + &pci_ss_info_105d_0008, + &pci_ss_info_105d_0009, + &pci_ss_info_105d_000a, + &pci_ss_info_105d_000b, + &pci_ss_info_105d_0018, + &pci_ss_info_105d_002a, + &pci_ss_info_105d_003a, + &pci_ss_info_105d_092f, + NULL +}; +#define pci_ss_list_105e NULL +#define pci_ss_list_105f NULL +#define pci_ss_list_1060 NULL +#define pci_ss_list_1061 NULL +#define pci_ss_list_1062 NULL +#define pci_ss_list_1063 NULL +#define pci_ss_list_1064 NULL +#define pci_ss_list_1065 NULL +#define pci_ss_list_1066 NULL +#define pci_ss_list_1067 NULL +#define pci_ss_list_1068 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1069[] = { + &pci_ss_info_1069_0020, + NULL +}; +#endif +#define pci_ss_list_106a NULL +#define pci_ss_list_106b NULL +#define pci_ss_list_106c NULL +#define pci_ss_list_106d NULL +#define pci_ss_list_106e NULL +#define pci_ss_list_106f NULL +#define pci_ss_list_1070 NULL +#define pci_ss_list_1071 NULL +#define pci_ss_list_1072 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1073[] = { + &pci_ss_info_1073_0004, + &pci_ss_info_1073_0005, + &pci_ss_info_1073_0006, + &pci_ss_info_1073_0008, + &pci_ss_info_1073_000a, + &pci_ss_info_1073_000d, + &pci_ss_info_1073_0010, + &pci_ss_info_1073_0012, + &pci_ss_info_1073_2000, + NULL +}; +#endif +#define pci_ss_list_1074 NULL +#define pci_ss_list_1075 NULL +#define pci_ss_list_1076 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1077[] = { + &pci_ss_info_1077_0001, + NULL +}; +#endif +#define pci_ss_list_1078 NULL +#define pci_ss_list_1079 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_107a[] = { + &pci_ss_info_107a_000c, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_107b[] = { + &pci_ss_info_107b_5350, + &pci_ss_info_107b_8030, + &pci_ss_info_107b_8054, + NULL +}; +#endif +#define pci_ss_list_107c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_107d[] = { + &pci_ss_info_107d_2633, + &pci_ss_info_107d_2720, + &pci_ss_info_107d_2840, + &pci_ss_info_107d_2896, + &pci_ss_info_107d_5330, + &pci_ss_info_107d_5350, + &pci_ss_info_107d_6606, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_107e[] = { + &pci_ss_info_107e_000e, + &pci_ss_info_107e_000f, + NULL +}; +#endif +#define pci_ss_list_107f NULL +#define pci_ss_list_1080 NULL +#define pci_ss_list_1081 NULL +#define pci_ss_list_1082 NULL +#define pci_ss_list_1083 NULL +#define pci_ss_list_1084 NULL +#define pci_ss_list_1085 NULL +#define pci_ss_list_1086 NULL +#define pci_ss_list_1087 NULL +#define pci_ss_list_1088 NULL +#define pci_ss_list_1089 NULL +#define pci_ss_list_108a NULL +#define pci_ss_list_108c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_108d[] = { + &pci_ss_info_108d_0004, + &pci_ss_info_108d_0007, + &pci_ss_info_108d_0008, + &pci_ss_info_108d_0016, + &pci_ss_info_108d_0017, + &pci_ss_info_108d_0022, + &pci_ss_info_108d_0027, + NULL +}; +#endif +#define pci_ss_list_108e NULL +#define pci_ss_list_108f NULL +#define pci_ss_list_1090 NULL +#define pci_ss_list_1091 NULL +static const pciSubsystemInfo *pci_ss_list_1092[] = { + &pci_ss_info_1092_0003, + &pci_ss_info_1092_0100, + &pci_ss_info_1092_0127, + &pci_ss_info_1092_0136, + &pci_ss_info_1092_0141, + &pci_ss_info_1092_0146, + &pci_ss_info_1092_0148, + &pci_ss_info_1092_0149, + &pci_ss_info_1092_0152, + &pci_ss_info_1092_0154, + &pci_ss_info_1092_0155, + &pci_ss_info_1092_0156, + &pci_ss_info_1092_0157, + &pci_ss_info_1092_0350, + &pci_ss_info_1092_0440, + &pci_ss_info_1092_0550, + &pci_ss_info_1092_0552, + &pci_ss_info_1092_094c, + &pci_ss_info_1092_0a50, + &pci_ss_info_1092_0a70, + &pci_ss_info_1092_0a78, + &pci_ss_info_1092_1092, + &pci_ss_info_1092_2000, + &pci_ss_info_1092_2100, + &pci_ss_info_1092_2110, + &pci_ss_info_1092_2200, + &pci_ss_info_1092_3000, + &pci_ss_info_1092_3001, + &pci_ss_info_1092_3002, + &pci_ss_info_1092_3003, + &pci_ss_info_1092_3004, + &pci_ss_info_1092_4000, + &pci_ss_info_1092_4002, + &pci_ss_info_1092_4100, + &pci_ss_info_1092_4207, + &pci_ss_info_1092_4800, + &pci_ss_info_1092_4801, + &pci_ss_info_1092_4803, + &pci_ss_info_1092_4804, + &pci_ss_info_1092_4807, + &pci_ss_info_1092_4808, + &pci_ss_info_1092_4809, + &pci_ss_info_1092_480e, + &pci_ss_info_1092_4810, + &pci_ss_info_1092_4812, + &pci_ss_info_1092_4815, + &pci_ss_info_1092_4820, + &pci_ss_info_1092_4822, + &pci_ss_info_1092_4904, + &pci_ss_info_1092_4905, + &pci_ss_info_1092_4910, + &pci_ss_info_1092_4914, + &pci_ss_info_1092_4920, + &pci_ss_info_1092_4a00, + &pci_ss_info_1092_4a02, + &pci_ss_info_1092_4a09, + &pci_ss_info_1092_4a0b, + &pci_ss_info_1092_4a0f, + &pci_ss_info_1092_4e01, + &pci_ss_info_1092_5932, + &pci_ss_info_1092_5934, + &pci_ss_info_1092_5952, + &pci_ss_info_1092_5954, + &pci_ss_info_1092_5a00, + &pci_ss_info_1092_5a35, + &pci_ss_info_1092_5a37, + &pci_ss_info_1092_5a55, + &pci_ss_info_1092_5a57, + &pci_ss_info_1092_6820, + &pci_ss_info_1092_6a02, + &pci_ss_info_1092_7a02, + &pci_ss_info_1092_8000, + &pci_ss_info_1092_8030, + &pci_ss_info_1092_8035, + &pci_ss_info_1092_8225, + &pci_ss_info_1092_8760, + &pci_ss_info_1092_8a10, + NULL +}; +#define pci_ss_list_1093 NULL +#define pci_ss_list_1094 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1095[] = { + &pci_ss_info_1095_0670, + NULL +}; +#endif +#define pci_ss_list_1096 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1097[] = { + &pci_ss_info_1097_3d01, + NULL +}; +#endif +#define pci_ss_list_1098 NULL +#define pci_ss_list_1099 NULL +#define pci_ss_list_109a NULL +#define pci_ss_list_109b NULL +#define pci_ss_list_109c NULL +#define pci_ss_list_109d NULL +#define pci_ss_list_109e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_109f[] = { + &pci_ss_info_109f_1000, + &pci_ss_info_109f_315d, + &pci_ss_info_109f_3181, + NULL +}; +#endif +#define pci_ss_list_10a0 NULL +#define pci_ss_list_10a1 NULL +#define pci_ss_list_10a2 NULL +#define pci_ss_list_10a3 NULL +#define pci_ss_list_10a4 NULL +#define pci_ss_list_10a5 NULL +#define pci_ss_list_10a6 NULL +#define pci_ss_list_10a7 NULL +#define pci_ss_list_10a8 NULL +#define pci_ss_list_10a9 NULL +#define pci_ss_list_10aa NULL +#define pci_ss_list_10ab NULL +#define pci_ss_list_10ac NULL +#define pci_ss_list_10ad NULL +#define pci_ss_list_10ae NULL +#define pci_ss_list_10af NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b0[] = { + &pci_ss_info_10b0_0001, + NULL +}; +#endif +#define pci_ss_list_10b1 NULL +#define pci_ss_list_10b2 NULL +#define pci_ss_list_10b3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b4[] = { + &pci_ss_info_10b4_1617, + &pci_ss_info_10b4_1717, + &pci_ss_info_10b4_1b1b, + &pci_ss_info_10b4_1b1d, + &pci_ss_info_10b4_1b1e, + &pci_ss_info_10b4_1b20, + &pci_ss_info_10b4_1b21, + &pci_ss_info_10b4_1b22, + &pci_ss_info_10b4_1b23, + &pci_ss_info_10b4_1b27, + &pci_ss_info_10b4_1b88, + &pci_ss_info_10b4_201a, + &pci_ss_info_10b4_202f, + &pci_ss_info_10b4_222a, + &pci_ss_info_10b4_2230, + &pci_ss_info_10b4_2232, + &pci_ss_info_10b4_2235, + &pci_ss_info_10b4_237e, + &pci_ss_info_10b4_273d, + &pci_ss_info_10b4_273e, + &pci_ss_info_10b4_2740, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b5[] = { + &pci_ss_info_10b5_2036, + &pci_ss_info_10b5_2273, + &pci_ss_info_10b5_2455, + &pci_ss_info_10b5_9050, + &pci_ss_info_10b5_9080, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b6[] = { + &pci_ss_info_10b6_0002, + &pci_ss_info_10b6_0003, + &pci_ss_info_10b6_0006, + &pci_ss_info_10b6_0007, + &pci_ss_info_10b6_0008, + &pci_ss_info_10b6_0009, + &pci_ss_info_10b6_000a, + &pci_ss_info_10b6_000b, + &pci_ss_info_10b6_000c, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b7[] = { + &pci_ss_info_10b7_1000, + &pci_ss_info_10b7_1001, + &pci_ss_info_10b7_1002, + &pci_ss_info_10b7_1003, + &pci_ss_info_10b7_1004, + &pci_ss_info_10b7_1005, + &pci_ss_info_10b7_1006, + &pci_ss_info_10b7_1007, + &pci_ss_info_10b7_1008, + &pci_ss_info_10b7_1100, + &pci_ss_info_10b7_1101, + &pci_ss_info_10b7_1102, + &pci_ss_info_10b7_1201, + &pci_ss_info_10b7_1202, + &pci_ss_info_10b7_2000, + &pci_ss_info_10b7_2001, + &pci_ss_info_10b7_2101, + &pci_ss_info_10b7_2102, + &pci_ss_info_10b7_3000, + &pci_ss_info_10b7_3590, + &pci_ss_info_10b7_5a57, + &pci_ss_info_10b7_5b57, + &pci_ss_info_10b7_5c57, + &pci_ss_info_10b7_615c, + &pci_ss_info_10b7_6556, + &pci_ss_info_10b7_656a, + &pci_ss_info_10b7_656b, + &pci_ss_info_10b7_7000, + &pci_ss_info_10b7_9004, + &pci_ss_info_10b7_9005, + &pci_ss_info_10b7_9055, + &pci_ss_info_10b7_9800, + &pci_ss_info_10b7_9805, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b8[] = { + &pci_ss_info_10b8_2001, + &pci_ss_info_10b8_2002, + &pci_ss_info_10b8_2003, + &pci_ss_info_10b8_2005, + &pci_ss_info_10b8_2011, + &pci_ss_info_10b8_8034, + &pci_ss_info_10b8_a011, + &pci_ss_info_10b8_a012, + &pci_ss_info_10b8_a014, + &pci_ss_info_10b8_a015, + &pci_ss_info_10b8_a016, + &pci_ss_info_10b8_a017, + NULL +}; +#endif +static const pciSubsystemInfo *pci_ss_list_10b9[] = { + &pci_ss_info_10b9_0111, + &pci_ss_info_10b9_1521, + &pci_ss_info_10b9_1523, + &pci_ss_info_10b9_1533, + &pci_ss_info_10b9_1541, + &pci_ss_info_10b9_7101, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10ba[] = { + &pci_ss_info_10ba_0e00, + NULL +}; +#endif +#define pci_ss_list_10bb NULL +#define pci_ss_list_10bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10bd[] = { + &pci_ss_info_10bd_0000, + &pci_ss_info_10bd_0320, + NULL +}; +#endif +#define pci_ss_list_10be NULL +#define pci_ss_list_10bf NULL +#define pci_ss_list_10c0 NULL +#define pci_ss_list_10c1 NULL +#define pci_ss_list_10c2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10c3[] = { + &pci_ss_info_10c3_1100, + NULL +}; +#endif +#define pci_ss_list_10c4 NULL +#define pci_ss_list_10c5 NULL +#define pci_ss_list_10c6 NULL +#define pci_ss_list_10c7 NULL +static const pciSubsystemInfo *pci_ss_list_10c8[] = { + &pci_ss_info_10c8_0004, + &pci_ss_info_10c8_0016, + &pci_ss_info_10c8_8005, + NULL +}; +#define pci_ss_list_10c9 NULL +#define pci_ss_list_10ca NULL +#define pci_ss_list_10cb NULL +#define pci_ss_list_10cc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10cd[] = { + &pci_ss_info_10cd_1310, + NULL +}; +#endif +#define pci_ss_list_10ce NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10cf[] = { + &pci_ss_info_10cf_1029, + &pci_ss_info_10cf_102c, + &pci_ss_info_10cf_103c, + &pci_ss_info_10cf_104a, + &pci_ss_info_10cf_1055, + &pci_ss_info_10cf_1056, + &pci_ss_info_10cf_1057, + &pci_ss_info_10cf_1059, + &pci_ss_info_10cf_105f, + &pci_ss_info_10cf_1063, + &pci_ss_info_10cf_1064, + &pci_ss_info_10cf_106a, + &pci_ss_info_10cf_1072, + &pci_ss_info_10cf_1094, + &pci_ss_info_10cf_1095, + &pci_ss_info_10cf_1098, + &pci_ss_info_10cf_1099, + &pci_ss_info_10cf_10a8, + &pci_ss_info_10cf_10a9, + &pci_ss_info_10cf_10aa, + &pci_ss_info_10cf_10ab, + &pci_ss_info_10cf_10ac, + &pci_ss_info_10cf_10ad, + &pci_ss_info_10cf_10b4, + &pci_ss_info_10cf_1115, + &pci_ss_info_10cf_1143, + NULL +}; +#endif +#define pci_ss_list_10d0 NULL +#define pci_ss_list_10d1 NULL +#define pci_ss_list_10d2 NULL +#define pci_ss_list_10d3 NULL +#define pci_ss_list_10d4 NULL +#define pci_ss_list_10d5 NULL +#define pci_ss_list_10d6 NULL +#define pci_ss_list_10d7 NULL +#define pci_ss_list_10d8 NULL +#define pci_ss_list_10d9 NULL +#define pci_ss_list_10da NULL +#define pci_ss_list_10db NULL +#define pci_ss_list_10dc NULL +#define pci_ss_list_10dd NULL +static const pciSubsystemInfo *pci_ss_list_10de[] = { + &pci_ss_info_10de_0005, + &pci_ss_info_10de_000f, + &pci_ss_info_10de_001e, + &pci_ss_info_10de_0020, + NULL +}; +#define pci_ss_list_10df NULL +#define pci_ss_list_10e0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10e1[] = { + &pci_ss_info_10e1_0391, + NULL +}; +#endif +#define pci_ss_list_10e2 NULL +#define pci_ss_list_10e3 NULL +#define pci_ss_list_10e4 NULL +#define pci_ss_list_10e5 NULL +#define pci_ss_list_10e6 NULL +#define pci_ss_list_10e7 NULL +#define pci_ss_list_10e8 NULL +#define pci_ss_list_10e9 NULL +#define pci_ss_list_10ea NULL +#define pci_ss_list_10eb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10ec[] = { + &pci_ss_info_10ec_8029, + &pci_ss_info_10ec_8129, + &pci_ss_info_10ec_8138, + &pci_ss_info_10ec_8139, + NULL +}; +#endif +#define pci_ss_list_10ed NULL +#define pci_ss_list_10ee NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10ef[] = { + &pci_ss_info_10ef_8169, + NULL +}; +#endif +#define pci_ss_list_10f0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10f1[] = { + &pci_ss_info_10f1_0002, + &pci_ss_info_10f1_2462, + NULL +}; +#endif +#define pci_ss_list_10f2 NULL +#define pci_ss_list_10f3 NULL +#define pci_ss_list_10f4 NULL +#define pci_ss_list_10f5 NULL +#define pci_ss_list_10f6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10f7[] = { + &pci_ss_info_10f7_8308, + &pci_ss_info_10f7_8309, + &pci_ss_info_10f7_830b, + &pci_ss_info_10f7_830d, + &pci_ss_info_10f7_8312, + NULL +}; +#endif +#define pci_ss_list_10f8 NULL +#define pci_ss_list_10f9 NULL +#define pci_ss_list_10fa NULL +#define pci_ss_list_10fb NULL +#define pci_ss_list_10fc NULL +#define pci_ss_list_10fd NULL +#define pci_ss_list_10fe NULL +#define pci_ss_list_10ff NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1100[] = { + &pci_ss_info_1100_102b, + NULL +}; +#endif +#define pci_ss_list_1101 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1102[] = { + &pci_ss_info_1102_0010, + &pci_ss_info_1102_0020, + &pci_ss_info_1102_0021, + &pci_ss_info_1102_002f, + &pci_ss_info_1102_0040, + &pci_ss_info_1102_0051, + &pci_ss_info_1102_0053, + &pci_ss_info_1102_100f, + &pci_ss_info_1102_1015, + &pci_ss_info_1102_1016, + &pci_ss_info_1102_1018, + &pci_ss_info_1102_101d, + &pci_ss_info_1102_101e, + &pci_ss_info_1102_1020, + &pci_ss_info_1102_1021, + &pci_ss_info_1102_1023, + &pci_ss_info_1102_1024, + &pci_ss_info_1102_1026, + &pci_ss_info_1102_1029, + &pci_ss_info_1102_102c, + &pci_ss_info_1102_102d, + &pci_ss_info_1102_102e, + &pci_ss_info_1102_102f, + &pci_ss_info_1102_1031, + &pci_ss_info_1102_1034, + &pci_ss_info_1102_4001, + &pci_ss_info_1102_8022, + &pci_ss_info_1102_8023, + &pci_ss_info_1102_8024, + &pci_ss_info_1102_8025, + &pci_ss_info_1102_8026, + &pci_ss_info_1102_8027, + &pci_ss_info_1102_8028, + &pci_ss_info_1102_8031, + &pci_ss_info_1102_8040, + &pci_ss_info_1102_8051, + &pci_ss_info_1102_8061, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1103[] = { + &pci_ss_info_1103_0001, + &pci_ss_info_1103_0005, + NULL +}; +#endif +#define pci_ss_list_1104 NULL +#define pci_ss_list_1105 NULL +static const pciSubsystemInfo *pci_ss_list_1106[] = { + &pci_ss_info_1106_0000, + &pci_ss_info_1106_0100, + &pci_ss_info_1106_0102, + &pci_ss_info_1106_0571, + &pci_ss_info_1106_0686, + &pci_ss_info_1106_4511, + NULL +}; +#define pci_ss_list_1107 NULL +#define pci_ss_list_1108 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1109[] = { + &pci_ss_info_1109_2400, + &pci_ss_info_1109_2a00, + &pci_ss_info_1109_2b00, + &pci_ss_info_1109_3000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_110a[] = { + &pci_ss_info_110a_0018, + &pci_ss_info_110a_001e, + &pci_ss_info_110a_0032, + &pci_ss_info_110a_8005, + NULL +}; +#endif +#define pci_ss_list_110b NULL +#define pci_ss_list_110c NULL +#define pci_ss_list_110d NULL +#define pci_ss_list_110e NULL +#define pci_ss_list_110f NULL +#define pci_ss_list_1110 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1111[] = { + &pci_ss_info_1111_1111, + &pci_ss_info_1111_1112, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1112[] = { + &pci_ss_info_1112_2300, + &pci_ss_info_1112_2320, + &pci_ss_info_1112_2340, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1113[] = { + &pci_ss_info_1113_1207, + &pci_ss_info_1113_1208, + &pci_ss_info_1113_1211, + &pci_ss_info_1113_1220, + &pci_ss_info_1113_2220, + &pci_ss_info_1113_9211, + NULL +}; +#endif +#define pci_ss_list_1114 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1115[] = { + &pci_ss_info_1115_1181, + NULL +}; +#endif +#define pci_ss_list_1116 NULL +#define pci_ss_list_1117 NULL +#define pci_ss_list_1118 NULL +#define pci_ss_list_1119 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_111a[] = { + &pci_ss_info_111a_0000, + &pci_ss_info_111a_0001, + &pci_ss_info_111a_0009, + &pci_ss_info_111a_0101, + &pci_ss_info_111a_0109, + &pci_ss_info_111a_0809, + &pci_ss_info_111a_0909, + &pci_ss_info_111a_0a09, + &pci_ss_info_111a_1001, + &pci_ss_info_111a_1020, + NULL +}; +#endif +#define pci_ss_list_111b NULL +#define pci_ss_list_111c NULL +#define pci_ss_list_111d NULL +#define pci_ss_list_111e NULL +#define pci_ss_list_111f NULL +#define pci_ss_list_1120 NULL +#define pci_ss_list_1121 NULL +#define pci_ss_list_1122 NULL +#define pci_ss_list_1123 NULL +#define pci_ss_list_1124 NULL +#define pci_ss_list_1125 NULL +#define pci_ss_list_1126 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1127[] = { + &pci_ss_info_1127_0400, + NULL +}; +#endif +#define pci_ss_list_1129 NULL +#define pci_ss_list_112a NULL +#define pci_ss_list_112b NULL +#define pci_ss_list_112c NULL +#define pci_ss_list_112d NULL +#define pci_ss_list_112e NULL +#define pci_ss_list_112f NULL +#define pci_ss_list_1130 NULL +#define pci_ss_list_1131 NULL +#define pci_ss_list_1132 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1133[] = { + &pci_ss_info_1133_e001, + &pci_ss_info_1133_e002, + &pci_ss_info_1133_e003, + &pci_ss_info_1133_e004, + &pci_ss_info_1133_e005, + &pci_ss_info_1133_e010, + &pci_ss_info_1133_e012, + &pci_ss_info_1133_e014, + NULL +}; +#endif +#define pci_ss_list_1134 NULL +#define pci_ss_list_1135 NULL +#define pci_ss_list_1136 NULL +#define pci_ss_list_1137 NULL +#define pci_ss_list_1138 NULL +#define pci_ss_list_1139 NULL +#define pci_ss_list_113a NULL +#define pci_ss_list_113b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_113c[] = { + &pci_ss_info_113c_03a2, + NULL +}; +#endif +#define pci_ss_list_113d NULL +#define pci_ss_list_113e NULL +#define pci_ss_list_113f NULL +#define pci_ss_list_1140 NULL +#define pci_ss_list_1141 NULL +#define pci_ss_list_1142 NULL +#define pci_ss_list_1143 NULL +#define pci_ss_list_1144 NULL +#define pci_ss_list_1145 NULL +#define pci_ss_list_1146 NULL +#define pci_ss_list_1147 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1148[] = { + &pci_ss_info_1148_5021, + &pci_ss_info_1148_5041, + &pci_ss_info_1148_5043, + &pci_ss_info_1148_5051, + &pci_ss_info_1148_5061, + &pci_ss_info_1148_5071, + &pci_ss_info_1148_5521, + &pci_ss_info_1148_5522, + &pci_ss_info_1148_5541, + &pci_ss_info_1148_5543, + &pci_ss_info_1148_5544, + &pci_ss_info_1148_5821, + &pci_ss_info_1148_5822, + &pci_ss_info_1148_5841, + &pci_ss_info_1148_5843, + &pci_ss_info_1148_5844, + &pci_ss_info_1148_9521, + &pci_ss_info_1148_9821, + &pci_ss_info_1148_9822, + &pci_ss_info_1148_9841, + &pci_ss_info_1148_9842, + &pci_ss_info_1148_9843, + &pci_ss_info_1148_9844, + &pci_ss_info_1148_9861, + &pci_ss_info_1148_9862, + &pci_ss_info_1148_9871, + &pci_ss_info_1148_9872, + NULL +}; +#endif +#define pci_ss_list_1149 NULL +#define pci_ss_list_114a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_114b[] = { + &pci_ss_info_114b_2003, + NULL +}; +#endif +#define pci_ss_list_114c NULL +#define pci_ss_list_114d NULL +#define pci_ss_list_114e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_114f[] = { + &pci_ss_info_114f_0030, + &pci_ss_info_114f_0031, + &pci_ss_info_114f_0050, + &pci_ss_info_114f_0051, + &pci_ss_info_114f_0052, + &pci_ss_info_114f_0053, + NULL +}; +#endif +#define pci_ss_list_1150 NULL +#define pci_ss_list_1151 NULL +#define pci_ss_list_1152 NULL +#define pci_ss_list_1153 NULL +#define pci_ss_list_1154 NULL +#define pci_ss_list_1155 NULL +#define pci_ss_list_1156 NULL +#define pci_ss_list_1157 NULL +#define pci_ss_list_1158 NULL +#define pci_ss_list_1159 NULL +#define pci_ss_list_115a NULL +#define pci_ss_list_115b NULL +#define pci_ss_list_115c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_115d[] = { + &pci_ss_info_115d_0002, + &pci_ss_info_115d_0181, + &pci_ss_info_115d_0182, + &pci_ss_info_115d_0183, + &pci_ss_info_115d_1081, + &pci_ss_info_115d_1181, + &pci_ss_info_115d_1182, + NULL +}; +#endif +#define pci_ss_list_115e NULL +#define pci_ss_list_115f NULL +#define pci_ss_list_1160 NULL +#define pci_ss_list_1161 NULL +#define pci_ss_list_1162 NULL +#define pci_ss_list_1163 NULL +#define pci_ss_list_1164 NULL +#define pci_ss_list_1165 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1166[] = { + &pci_ss_info_1166_1648, + NULL +}; +#endif +#define pci_ss_list_1167 NULL +#define pci_ss_list_1168 NULL +#define pci_ss_list_1169 NULL +#define pci_ss_list_116a NULL +#define pci_ss_list_116b NULL +#define pci_ss_list_116c NULL +#define pci_ss_list_116d NULL +#define pci_ss_list_116e NULL +#define pci_ss_list_116f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1170[] = { + &pci_ss_info_1170_3209, + NULL +}; +#endif +#define pci_ss_list_1171 NULL +#define pci_ss_list_1172 NULL +#define pci_ss_list_1173 NULL +#define pci_ss_list_1174 NULL +#define pci_ss_list_1175 NULL +#define pci_ss_list_1176 NULL +#define pci_ss_list_1177 NULL +#define pci_ss_list_1178 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1179[] = { + &pci_ss_info_1179_0001, + &pci_ss_info_1179_0002, + &pci_ss_info_1179_0003, + &pci_ss_info_1179_0181, + &pci_ss_info_1179_0203, + &pci_ss_info_1179_0204, + &pci_ss_info_1179_ff00, + NULL +}; +#endif +#define pci_ss_list_117a NULL +#define pci_ss_list_117b NULL +#define pci_ss_list_117c NULL +#define pci_ss_list_117d NULL +#define pci_ss_list_117e NULL +#define pci_ss_list_117f NULL +#define pci_ss_list_1180 NULL +#define pci_ss_list_1181 NULL +#define pci_ss_list_1183 NULL +#define pci_ss_list_1184 NULL +#define pci_ss_list_1185 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1186[] = { + &pci_ss_info_1186_0100, + &pci_ss_info_1186_0300, + &pci_ss_info_1186_1002, + &pci_ss_info_1186_1012, + &pci_ss_info_1186_1100, + &pci_ss_info_1186_1101, + &pci_ss_info_1186_1102, + &pci_ss_info_1186_1112, + &pci_ss_info_1186_1140, + &pci_ss_info_1186_1142, + &pci_ss_info_1186_1200, + &pci_ss_info_1186_1300, + &pci_ss_info_1186_1301, + &pci_ss_info_1186_1320, + &pci_ss_info_1186_1400, + &pci_ss_info_1186_1401, + &pci_ss_info_1186_3501, + &pci_ss_info_1186_7801, + &pci_ss_info_1186_8139, + NULL +}; +#endif +#define pci_ss_list_1187 NULL +#define pci_ss_list_1188 NULL +#define pci_ss_list_1189 NULL +#define pci_ss_list_118a NULL +#define pci_ss_list_118b NULL +#define pci_ss_list_118c NULL +#define pci_ss_list_118d NULL +#define pci_ss_list_118e NULL +#define pci_ss_list_118f NULL +#define pci_ss_list_1190 NULL +#define pci_ss_list_1191 NULL +#define pci_ss_list_1192 NULL +#define pci_ss_list_1193 NULL +#define pci_ss_list_1194 NULL +#define pci_ss_list_1195 NULL +#define pci_ss_list_1196 NULL +#define pci_ss_list_1197 NULL +#define pci_ss_list_1198 NULL +#define pci_ss_list_1199 NULL +#define pci_ss_list_119a NULL +#define pci_ss_list_119b NULL +#define pci_ss_list_119c NULL +#define pci_ss_list_119d NULL +#define pci_ss_list_119e NULL +#define pci_ss_list_119f NULL +#define pci_ss_list_11a0 NULL +#define pci_ss_list_11a1 NULL +#define pci_ss_list_11a2 NULL +#define pci_ss_list_11a3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11a4[] = { + &pci_ss_info_11a4_000a, + &pci_ss_info_11a4_000b, + NULL +}; +#endif +#define pci_ss_list_11a5 NULL +#define pci_ss_list_11a6 NULL +#define pci_ss_list_11a7 NULL +#define pci_ss_list_11a8 NULL +#define pci_ss_list_11a9 NULL +#define pci_ss_list_11aa NULL +#define pci_ss_list_11ab NULL +#define pci_ss_list_11ac NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11ad[] = { + &pci_ss_info_11ad_0002, + &pci_ss_info_11ad_0003, + &pci_ss_info_11ad_c001, + &pci_ss_info_11ad_f003, + &pci_ss_info_11ad_ffff, + NULL +}; +#endif +#define pci_ss_list_11ae NULL +#define pci_ss_list_11af NULL +#define pci_ss_list_11b0 NULL +#define pci_ss_list_11b1 NULL +#define pci_ss_list_11b2 NULL +#define pci_ss_list_11b3 NULL +#define pci_ss_list_11b4 NULL +#define pci_ss_list_11b5 NULL +#define pci_ss_list_11b6 NULL +#define pci_ss_list_11b7 NULL +#define pci_ss_list_11b8 NULL +#define pci_ss_list_11b9 NULL +#define pci_ss_list_11ba NULL +#define pci_ss_list_11bb NULL +#define pci_ss_list_11bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11bd[] = { + &pci_ss_info_11bd_0006, + &pci_ss_info_11bd_000a, + &pci_ss_info_11bd_000e, + &pci_ss_info_11bd_0012, + &pci_ss_info_11bd_001c, + NULL +}; +#endif +#define pci_ss_list_11be NULL +#define pci_ss_list_11bf NULL +#define pci_ss_list_11c0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11c1[] = { + &pci_ss_info_11c1_0440, + &pci_ss_info_11c1_0441, + &pci_ss_info_11c1_0442, + NULL +}; +#endif +#define pci_ss_list_11c2 NULL +#define pci_ss_list_11c3 NULL +#define pci_ss_list_11c4 NULL +#define pci_ss_list_11c5 NULL +#define pci_ss_list_11c6 NULL +#define pci_ss_list_11c7 NULL +#define pci_ss_list_11c8 NULL +#define pci_ss_list_11c9 NULL +#define pci_ss_list_11ca NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11cb[] = { + &pci_ss_info_11cb_0200, + &pci_ss_info_11cb_b008, + NULL +}; +#endif +#define pci_ss_list_11cc NULL +#define pci_ss_list_11cd NULL +#define pci_ss_list_11ce NULL +#define pci_ss_list_11cf NULL +#define pci_ss_list_11d0 NULL +#define pci_ss_list_11d1 NULL +#define pci_ss_list_11d2 NULL +#define pci_ss_list_11d3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11d4[] = { + &pci_ss_info_11d4_0040, + &pci_ss_info_11d4_0048, + &pci_ss_info_11d4_5340, + NULL +}; +#endif +#define pci_ss_list_11d5 NULL +#define pci_ss_list_11d6 NULL +#define pci_ss_list_11d7 NULL +#define pci_ss_list_11d8 NULL +#define pci_ss_list_11d9 NULL +#define pci_ss_list_11da NULL +#define pci_ss_list_11db NULL +#define pci_ss_list_11dc NULL +#define pci_ss_list_11dd NULL +#define pci_ss_list_11de NULL +#define pci_ss_list_11df NULL +#define pci_ss_list_11e0 NULL +#define pci_ss_list_11e1 NULL +#define pci_ss_list_11e2 NULL +#define pci_ss_list_11e3 NULL +#define pci_ss_list_11e4 NULL +#define pci_ss_list_11e5 NULL +#define pci_ss_list_11e6 NULL +#define pci_ss_list_11e7 NULL +#define pci_ss_list_11e8 NULL +#define pci_ss_list_11e9 NULL +#define pci_ss_list_11ea NULL +#define pci_ss_list_11eb NULL +#define pci_ss_list_11ec NULL +#define pci_ss_list_11ed NULL +#define pci_ss_list_11ee NULL +#define pci_ss_list_11ef NULL +#define pci_ss_list_11f0 NULL +#define pci_ss_list_11f1 NULL +#define pci_ss_list_11f2 NULL +#define pci_ss_list_11f3 NULL +#define pci_ss_list_11f4 NULL +#define pci_ss_list_11f5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11f6[] = { + &pci_ss_info_11f6_0503, + &pci_ss_info_11f6_2011, + &pci_ss_info_11f6_8139, + NULL +}; +#endif +#define pci_ss_list_11f7 NULL +#define pci_ss_list_11f8 NULL +#define pci_ss_list_11f9 NULL +#define pci_ss_list_11fa NULL +#define pci_ss_list_11fb NULL +#define pci_ss_list_11fc NULL +#define pci_ss_list_11fd NULL +#define pci_ss_list_11fe NULL +#define pci_ss_list_11ff NULL +#define pci_ss_list_1200 NULL +#define pci_ss_list_1201 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1202[] = { + &pci_ss_info_1202_9841, + &pci_ss_info_1202_9842, + &pci_ss_info_1202_9843, + &pci_ss_info_1202_9844, + NULL +}; +#endif +#define pci_ss_list_1203 NULL +#define pci_ss_list_1204 NULL +#define pci_ss_list_1205 NULL +#define pci_ss_list_1206 NULL +#define pci_ss_list_1208 NULL +#define pci_ss_list_1209 NULL +#define pci_ss_list_120a NULL +#define pci_ss_list_120b NULL +#define pci_ss_list_120c NULL +#define pci_ss_list_120d NULL +#define pci_ss_list_120e NULL +#define pci_ss_list_120f NULL +#define pci_ss_list_1210 NULL +#define pci_ss_list_1211 NULL +#define pci_ss_list_1212 NULL +#define pci_ss_list_1213 NULL +#define pci_ss_list_1214 NULL +#define pci_ss_list_1215 NULL +#define pci_ss_list_1216 NULL +#define pci_ss_list_1217 NULL +#define pci_ss_list_1218 NULL +#define pci_ss_list_1219 NULL +static const pciSubsystemInfo *pci_ss_list_121a[] = { + &pci_ss_info_121a_0001, + &pci_ss_info_121a_0003, + &pci_ss_info_121a_0004, + &pci_ss_info_121a_0009, + &pci_ss_info_121a_0030, + &pci_ss_info_121a_0031, + &pci_ss_info_121a_0034, + &pci_ss_info_121a_0036, + &pci_ss_info_121a_0037, + &pci_ss_info_121a_0038, + &pci_ss_info_121a_003a, + &pci_ss_info_121a_0044, + &pci_ss_info_121a_004b, + &pci_ss_info_121a_004c, + &pci_ss_info_121a_004d, + &pci_ss_info_121a_004e, + &pci_ss_info_121a_0051, + &pci_ss_info_121a_0052, + &pci_ss_info_121a_0060, + &pci_ss_info_121a_0061, + &pci_ss_info_121a_0062, + NULL +}; +#define pci_ss_list_121b NULL +#define pci_ss_list_121c NULL +#define pci_ss_list_121d NULL +#define pci_ss_list_121e NULL +#define pci_ss_list_121f NULL +#define pci_ss_list_1220 NULL +#define pci_ss_list_1221 NULL +#define pci_ss_list_1222 NULL +#define pci_ss_list_1223 NULL +#define pci_ss_list_1224 NULL +#define pci_ss_list_1225 NULL +#define pci_ss_list_1227 NULL +#define pci_ss_list_1228 NULL +#define pci_ss_list_1229 NULL +#define pci_ss_list_122a NULL +#define pci_ss_list_122b NULL +#define pci_ss_list_122c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_122d[] = { + &pci_ss_info_122d_0001, + &pci_ss_info_122d_1002, + &pci_ss_info_122d_1206, + &pci_ss_info_122d_1207, + &pci_ss_info_122d_1208, + &pci_ss_info_122d_4002, + &pci_ss_info_122d_4003, + &pci_ss_info_122d_4005, + &pci_ss_info_122d_4006, + &pci_ss_info_122d_4007, + &pci_ss_info_122d_4008, + &pci_ss_info_122d_4009, + &pci_ss_info_122d_4010, + &pci_ss_info_122d_4011, + &pci_ss_info_122d_4012, + &pci_ss_info_122d_4013, + &pci_ss_info_122d_4015, + &pci_ss_info_122d_4016, + &pci_ss_info_122d_4017, + &pci_ss_info_122d_4018, + &pci_ss_info_122d_4019, + &pci_ss_info_122d_4020, + &pci_ss_info_122d_4021, + &pci_ss_info_122d_4022, + &pci_ss_info_122d_4023, + &pci_ss_info_122d_4024, + &pci_ss_info_122d_4025, + &pci_ss_info_122d_4027, + &pci_ss_info_122d_4029, + &pci_ss_info_122d_4030, + &pci_ss_info_122d_4031, + &pci_ss_info_122d_4033, + &pci_ss_info_122d_4034, + &pci_ss_info_122d_4035, + &pci_ss_info_122d_4050, + &pci_ss_info_122d_4051, + &pci_ss_info_122d_4052, + &pci_ss_info_122d_4054, + &pci_ss_info_122d_4055, + &pci_ss_info_122d_4056, + &pci_ss_info_122d_4057, + &pci_ss_info_122d_4100, + &pci_ss_info_122d_4101, + &pci_ss_info_122d_4102, + &pci_ss_info_122d_4302, + NULL +}; +#endif +#define pci_ss_list_122e NULL +#define pci_ss_list_122f NULL +#define pci_ss_list_1230 NULL +#define pci_ss_list_1231 NULL +#define pci_ss_list_1232 NULL +#define pci_ss_list_1233 NULL +#define pci_ss_list_1234 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1235[] = { + &pci_ss_info_1235_4320, + &pci_ss_info_1235_4321, + &pci_ss_info_1235_4322, + &pci_ss_info_1235_4324, + NULL +}; +#endif +#define pci_ss_list_1236 NULL +#define pci_ss_list_1237 NULL +#define pci_ss_list_1238 NULL +#define pci_ss_list_1239 NULL +#define pci_ss_list_123a NULL +#define pci_ss_list_123b NULL +#define pci_ss_list_123c NULL +#define pci_ss_list_123d NULL +#define pci_ss_list_123e NULL +#define pci_ss_list_123f NULL +#define pci_ss_list_1240 NULL +#define pci_ss_list_1241 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1242[] = { + &pci_ss_info_1242_6562, + &pci_ss_info_1242_656a, + NULL +}; +#endif +#define pci_ss_list_1243 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1244[] = { + &pci_ss_info_1244_0a00, + NULL +}; +#endif +#define pci_ss_list_1245 NULL +#define pci_ss_list_1246 NULL +#define pci_ss_list_1247 NULL +#define pci_ss_list_1248 NULL +#define pci_ss_list_1249 NULL +#define pci_ss_list_124a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_124b[] = { + &pci_ss_info_124b_9080, + NULL +}; +#endif +#define pci_ss_list_124c NULL +#define pci_ss_list_124d NULL +#define pci_ss_list_124e NULL +#define pci_ss_list_124f NULL +#define pci_ss_list_1250 NULL +#define pci_ss_list_1251 NULL +#define pci_ss_list_1253 NULL +#define pci_ss_list_1254 NULL +#define pci_ss_list_1255 NULL +#define pci_ss_list_1256 NULL +#define pci_ss_list_1257 NULL +#define pci_ss_list_1258 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1259[] = { + &pci_ss_info_1259_2400, + &pci_ss_info_1259_2450, + &pci_ss_info_1259_2454, + &pci_ss_info_1259_2500, + &pci_ss_info_1259_2503, + &pci_ss_info_1259_2560, + &pci_ss_info_1259_2561, + &pci_ss_info_1259_2700, + &pci_ss_info_1259_2701, + &pci_ss_info_1259_2800, + &pci_ss_info_1259_2970, + &pci_ss_info_1259_2972, + &pci_ss_info_1259_2975, + &pci_ss_info_1259_2977, + NULL +}; +#endif +#define pci_ss_list_125a NULL +#define pci_ss_list_125b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_125c[] = { + &pci_ss_info_125c_0640, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_125d[] = { + &pci_ss_info_125d_0424, + &pci_ss_info_125d_0425, + &pci_ss_info_125d_0426, + &pci_ss_info_125d_0427, + &pci_ss_info_125d_0428, + &pci_ss_info_125d_0429, + &pci_ss_info_125d_1988, + &pci_ss_info_125d_1989, + &pci_ss_info_125d_8888, + NULL +}; +#endif +#define pci_ss_list_125e NULL +#define pci_ss_list_125f NULL +#define pci_ss_list_1260 NULL +#define pci_ss_list_1261 NULL +#define pci_ss_list_1262 NULL +#define pci_ss_list_1263 NULL +#define pci_ss_list_1264 NULL +#define pci_ss_list_1265 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1266[] = { + &pci_ss_info_1266_0001, + &pci_ss_info_1266_0004, + &pci_ss_info_1266_1910, + NULL +}; +#endif +#define pci_ss_list_1267 NULL +#define pci_ss_list_1268 NULL +#define pci_ss_list_1269 NULL +#define pci_ss_list_126a NULL +#define pci_ss_list_126b NULL +#define pci_ss_list_126c NULL +#define pci_ss_list_126d NULL +#define pci_ss_list_126e NULL +#define pci_ss_list_126f NULL +#define pci_ss_list_1270 NULL +#define pci_ss_list_1271 NULL +#define pci_ss_list_1272 NULL +#define pci_ss_list_1273 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1274[] = { + &pci_ss_info_1274_1371, + &pci_ss_info_1274_2000, + &pci_ss_info_1274_2003, + &pci_ss_info_1274_5880, + NULL +}; +#endif +#define pci_ss_list_1275 NULL +#define pci_ss_list_1276 NULL +#define pci_ss_list_1277 NULL +#define pci_ss_list_1278 NULL +#define pci_ss_list_1279 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_127a[] = { + &pci_ss_info_127a_0001, + &pci_ss_info_127a_0002, + &pci_ss_info_127a_0003, + &pci_ss_info_127a_0044, + &pci_ss_info_127a_0048, + &pci_ss_info_127a_0122, + &pci_ss_info_127a_0144, + &pci_ss_info_127a_0222, + &pci_ss_info_127a_0244, + &pci_ss_info_127a_0322, + &pci_ss_info_127a_0422, + &pci_ss_info_127a_1002, + &pci_ss_info_127a_1122, + &pci_ss_info_127a_1222, + &pci_ss_info_127a_1322, + &pci_ss_info_127a_1522, + &pci_ss_info_127a_1622, + &pci_ss_info_127a_1722, + &pci_ss_info_127a_4311, + NULL +}; +#endif +#define pci_ss_list_127b NULL +#define pci_ss_list_127c NULL +#define pci_ss_list_127d NULL +#define pci_ss_list_127e NULL +#define pci_ss_list_127f NULL +#define pci_ss_list_1280 NULL +#define pci_ss_list_1281 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1282[] = { + &pci_ss_info_1282_9100, + NULL +}; +#endif +#define pci_ss_list_1283 NULL +#define pci_ss_list_1284 NULL +#define pci_ss_list_1285 NULL +#define pci_ss_list_1286 NULL +#define pci_ss_list_1287 NULL +#define pci_ss_list_1288 NULL +#define pci_ss_list_1289 NULL +#define pci_ss_list_128a NULL +#define pci_ss_list_128b NULL +#define pci_ss_list_128c NULL +#define pci_ss_list_128d NULL +#define pci_ss_list_128e NULL +#define pci_ss_list_128f NULL +#define pci_ss_list_1290 NULL +#define pci_ss_list_1291 NULL +#define pci_ss_list_1292 NULL +#define pci_ss_list_1293 NULL +#define pci_ss_list_1294 NULL +#define pci_ss_list_1295 NULL +#define pci_ss_list_1296 NULL +#define pci_ss_list_1297 NULL +#define pci_ss_list_1298 NULL +#define pci_ss_list_1299 NULL +#define pci_ss_list_129a NULL +#define pci_ss_list_129b NULL +#define pci_ss_list_129c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_129d[] = { + &pci_ss_info_129d_0002, + NULL +}; +#endif +#define pci_ss_list_129e NULL +#define pci_ss_list_129f NULL +#define pci_ss_list_12a0 NULL +#define pci_ss_list_12a1 NULL +#define pci_ss_list_12a2 NULL +#define pci_ss_list_12a3 NULL +#define pci_ss_list_12a4 NULL +#define pci_ss_list_12a5 NULL +#define pci_ss_list_12a6 NULL +#define pci_ss_list_12a7 NULL +#define pci_ss_list_12a8 NULL +#define pci_ss_list_12a9 NULL +#define pci_ss_list_12aa NULL +#define pci_ss_list_12ab NULL +#define pci_ss_list_12ac NULL +#define pci_ss_list_12ad NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12ae[] = { + &pci_ss_info_12ae_0001, + &pci_ss_info_12ae_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12af[] = { + &pci_ss_info_12af_0019, + NULL +}; +#endif +#define pci_ss_list_12b0 NULL +#define pci_ss_list_12b1 NULL +#define pci_ss_list_12b2 NULL +#define pci_ss_list_12b3 NULL +#define pci_ss_list_12b4 NULL +#define pci_ss_list_12b5 NULL +#define pci_ss_list_12b6 NULL +#define pci_ss_list_12b7 NULL +#define pci_ss_list_12b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12b9[] = { + &pci_ss_info_12b9_005c, + &pci_ss_info_12b9_005e, + &pci_ss_info_12b9_0062, + &pci_ss_info_12b9_0068, + &pci_ss_info_12b9_007a, + &pci_ss_info_12b9_007f, + &pci_ss_info_12b9_0080, + &pci_ss_info_12b9_0081, + &pci_ss_info_12b9_0091, + &pci_ss_info_12b9_00a2, + &pci_ss_info_12b9_00a3, + &pci_ss_info_12b9_00aa, + &pci_ss_info_12b9_00ab, + &pci_ss_info_12b9_00ac, + &pci_ss_info_12b9_00ad, + NULL +}; +#endif +#define pci_ss_list_12ba NULL +#define pci_ss_list_12bb NULL +#define pci_ss_list_12bc NULL +#define pci_ss_list_12bd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12be[] = { + &pci_ss_info_12be_3042, + NULL +}; +#endif +#define pci_ss_list_12bf NULL +#define pci_ss_list_12c0 NULL +#define pci_ss_list_12c1 NULL +#define pci_ss_list_12c2 NULL +#define pci_ss_list_12c3 NULL +#define pci_ss_list_12c4 NULL +#define pci_ss_list_12c5 NULL +#define pci_ss_list_12c6 NULL +#define pci_ss_list_12c7 NULL +#define pci_ss_list_12c8 NULL +#define pci_ss_list_12c9 NULL +#define pci_ss_list_12ca NULL +#define pci_ss_list_12cb NULL +#define pci_ss_list_12cc NULL +#define pci_ss_list_12cd NULL +#define pci_ss_list_12ce NULL +#define pci_ss_list_12cf NULL +#define pci_ss_list_12d0 NULL +#define pci_ss_list_12d1 NULL +#define pci_ss_list_12d2 NULL +#define pci_ss_list_12d3 NULL +#define pci_ss_list_12d4 NULL +#define pci_ss_list_12d5 NULL +#define pci_ss_list_12d6 NULL +#define pci_ss_list_12d7 NULL +#define pci_ss_list_12d8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12d9[] = { + &pci_ss_info_12d9_000a, + NULL +}; +#endif +#define pci_ss_list_12da NULL +#define pci_ss_list_12db NULL +#define pci_ss_list_12dc NULL +#define pci_ss_list_12dd NULL +#define pci_ss_list_12de NULL +#define pci_ss_list_12df NULL +#define pci_ss_list_12e0 NULL +#define pci_ss_list_12e1 NULL +#define pci_ss_list_12e2 NULL +#define pci_ss_list_12e3 NULL +#define pci_ss_list_12e4 NULL +#define pci_ss_list_12e5 NULL +#define pci_ss_list_12e6 NULL +#define pci_ss_list_12e7 NULL +#define pci_ss_list_12e8 NULL +#define pci_ss_list_12e9 NULL +#define pci_ss_list_12ea NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12eb[] = { + &pci_ss_info_12eb_0001, + &pci_ss_info_12eb_0002, + &pci_ss_info_12eb_0003, + &pci_ss_info_12eb_0088, + &pci_ss_info_12eb_8803, + NULL +}; +#endif +#define pci_ss_list_12ec NULL +#define pci_ss_list_12ed NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12ee[] = { + &pci_ss_info_12ee_7000, + &pci_ss_info_12ee_7001, + &pci_ss_info_12ee_8011, + NULL +}; +#endif +#define pci_ss_list_12ef NULL +#define pci_ss_list_12f0 NULL +#define pci_ss_list_12f1 NULL +#define pci_ss_list_12f2 NULL +#define pci_ss_list_12f3 NULL +#define pci_ss_list_12f4 NULL +#define pci_ss_list_12f5 NULL +#define pci_ss_list_12f6 NULL +#define pci_ss_list_12f7 NULL +#define pci_ss_list_12f8 NULL +#define pci_ss_list_12f9 NULL +#define pci_ss_list_12fb NULL +#define pci_ss_list_12fc NULL +#define pci_ss_list_12fd NULL +#define pci_ss_list_12fe NULL +#define pci_ss_list_12ff NULL +#define pci_ss_list_1300 NULL +#define pci_ss_list_1302 NULL +#define pci_ss_list_1303 NULL +#define pci_ss_list_1304 NULL +#define pci_ss_list_1305 NULL +#define pci_ss_list_1306 NULL +#define pci_ss_list_1307 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1308[] = { + &pci_ss_info_1308_0001, + NULL +}; +#endif +#define pci_ss_list_1309 NULL +#define pci_ss_list_130a NULL +#define pci_ss_list_130b NULL +#define pci_ss_list_130c NULL +#define pci_ss_list_130d NULL +#define pci_ss_list_130e NULL +#define pci_ss_list_130f NULL +#define pci_ss_list_1310 NULL +#define pci_ss_list_1311 NULL +#define pci_ss_list_1312 NULL +#define pci_ss_list_1313 NULL +#define pci_ss_list_1316 NULL +#define pci_ss_list_1317 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1318[] = { + &pci_ss_info_1318_0000, + NULL +}; +#endif +#define pci_ss_list_1319 NULL +#define pci_ss_list_131a NULL +#define pci_ss_list_131c NULL +#define pci_ss_list_131d NULL +#define pci_ss_list_131e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_131f[] = { + &pci_ss_info_131f_2030, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1320[] = { + &pci_ss_info_1320_10bd, + NULL +}; +#endif +#define pci_ss_list_1321 NULL +#define pci_ss_list_1322 NULL +#define pci_ss_list_1323 NULL +#define pci_ss_list_1324 NULL +#define pci_ss_list_1325 NULL +#define pci_ss_list_1326 NULL +#define pci_ss_list_1327 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1328[] = { + &pci_ss_info_1328_0001, + &pci_ss_info_1328_f001, + NULL +}; +#endif +#define pci_ss_list_1329 NULL +#define pci_ss_list_132a NULL +#define pci_ss_list_132b NULL +#define pci_ss_list_132c NULL +#define pci_ss_list_132d NULL +#define pci_ss_list_1330 NULL +#define pci_ss_list_1331 NULL +#define pci_ss_list_1332 NULL +#define pci_ss_list_1334 NULL +#define pci_ss_list_1335 NULL +#define pci_ss_list_1337 NULL +#define pci_ss_list_1338 NULL +#define pci_ss_list_133a NULL +#define pci_ss_list_133b NULL +#define pci_ss_list_133c NULL +#define pci_ss_list_133d NULL +#define pci_ss_list_133e NULL +#define pci_ss_list_133f NULL +#define pci_ss_list_1340 NULL +#define pci_ss_list_1341 NULL +#define pci_ss_list_1342 NULL +#define pci_ss_list_1343 NULL +#define pci_ss_list_1344 NULL +#define pci_ss_list_1345 NULL +#define pci_ss_list_1347 NULL +#define pci_ss_list_1349 NULL +#define pci_ss_list_134a NULL +#define pci_ss_list_134b NULL +#define pci_ss_list_134c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_134d[] = { + &pci_ss_info_134d_0001, + &pci_ss_info_134d_4c21, + NULL +}; +#endif +#define pci_ss_list_134e NULL +#define pci_ss_list_134f NULL +#define pci_ss_list_1350 NULL +#define pci_ss_list_1351 NULL +#define pci_ss_list_1353 NULL +#define pci_ss_list_1354 NULL +#define pci_ss_list_1355 NULL +#define pci_ss_list_1356 NULL +#define pci_ss_list_1359 NULL +#define pci_ss_list_135a NULL +#define pci_ss_list_135b NULL +#define pci_ss_list_135c NULL +#define pci_ss_list_135d NULL +#define pci_ss_list_135e NULL +#define pci_ss_list_135f NULL +#define pci_ss_list_1360 NULL +#define pci_ss_list_1361 NULL +#define pci_ss_list_1362 NULL +#define pci_ss_list_1363 NULL +#define pci_ss_list_1364 NULL +#define pci_ss_list_1365 NULL +#define pci_ss_list_1366 NULL +#define pci_ss_list_1367 NULL +#define pci_ss_list_1368 NULL +#define pci_ss_list_1369 NULL +#define pci_ss_list_136a NULL +#define pci_ss_list_136b NULL +#define pci_ss_list_136c NULL +#define pci_ss_list_136d NULL +#define pci_ss_list_136f NULL +#define pci_ss_list_1370 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1371[] = { + &pci_ss_info_1371_434e, + NULL +}; +#endif +#define pci_ss_list_1373 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1374[] = { + &pci_ss_info_1374_0001, + &pci_ss_info_1374_0002, + &pci_ss_info_1374_0003, + &pci_ss_info_1374_0007, + &pci_ss_info_1374_0008, + NULL +}; +#endif +#define pci_ss_list_1375 NULL +#define pci_ss_list_1376 NULL +#define pci_ss_list_1377 NULL +#define pci_ss_list_1378 NULL +#define pci_ss_list_1379 NULL +#define pci_ss_list_137a NULL +#define pci_ss_list_137b NULL +#define pci_ss_list_137c NULL +#define pci_ss_list_137d NULL +#define pci_ss_list_137e NULL +#define pci_ss_list_137f NULL +#define pci_ss_list_1380 NULL +#define pci_ss_list_1381 NULL +#define pci_ss_list_1382 NULL +#define pci_ss_list_1383 NULL +#define pci_ss_list_1384 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1385[] = { + &pci_ss_info_1385_1100, + &pci_ss_info_1385_2100, + &pci_ss_info_1385_f004, + NULL +}; +#endif +#define pci_ss_list_1386 NULL +#define pci_ss_list_1387 NULL +#define pci_ss_list_1388 NULL +#define pci_ss_list_1389 NULL +#define pci_ss_list_138a NULL +#define pci_ss_list_138b NULL +#define pci_ss_list_138c NULL +#define pci_ss_list_138d NULL +#define pci_ss_list_138e NULL +#define pci_ss_list_138f NULL +#define pci_ss_list_1390 NULL +#define pci_ss_list_1391 NULL +#define pci_ss_list_1392 NULL +#define pci_ss_list_1393 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1394[] = { + &pci_ss_info_1394_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1395[] = { + &pci_ss_info_1395_0001, + NULL +}; +#endif +#define pci_ss_list_1396 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1397[] = { + &pci_ss_info_1397_2bd0, + NULL +}; +#endif +#define pci_ss_list_1398 NULL +#define pci_ss_list_1399 NULL +#define pci_ss_list_139a NULL +#define pci_ss_list_139b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_139c[] = { + &pci_ss_info_139c_0016, + &pci_ss_info_139c_0017, + NULL +}; +#endif +#define pci_ss_list_139d NULL +#define pci_ss_list_139e NULL +#define pci_ss_list_139f NULL +#define pci_ss_list_13a0 NULL +#define pci_ss_list_13a1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13a2[] = { + &pci_ss_info_13a2_8002, + &pci_ss_info_13a2_8006, + NULL +}; +#endif +#define pci_ss_list_13a3 NULL +#define pci_ss_list_13a4 NULL +#define pci_ss_list_13a5 NULL +#define pci_ss_list_13a6 NULL +#define pci_ss_list_13a7 NULL +#define pci_ss_list_13a8 NULL +#define pci_ss_list_13a9 NULL +#define pci_ss_list_13aa NULL +#define pci_ss_list_13ab NULL +#define pci_ss_list_13ac NULL +#define pci_ss_list_13ad NULL +#define pci_ss_list_13ae NULL +#define pci_ss_list_13af NULL +#define pci_ss_list_13b0 NULL +#define pci_ss_list_13b1 NULL +#define pci_ss_list_13b2 NULL +#define pci_ss_list_13b3 NULL +#define pci_ss_list_13b4 NULL +#define pci_ss_list_13b5 NULL +#define pci_ss_list_13b6 NULL +#define pci_ss_list_13b7 NULL +#define pci_ss_list_13b8 NULL +#define pci_ss_list_13b9 NULL +#define pci_ss_list_13ba NULL +#define pci_ss_list_13bb NULL +#define pci_ss_list_13bc NULL +#define pci_ss_list_13bd NULL +#define pci_ss_list_13be NULL +#define pci_ss_list_13bf NULL +#define pci_ss_list_13c0 NULL +#define pci_ss_list_13c1 NULL +#define pci_ss_list_13c2 NULL +#define pci_ss_list_13c3 NULL +#define pci_ss_list_13c4 NULL +#define pci_ss_list_13c5 NULL +#define pci_ss_list_13c6 NULL +#define pci_ss_list_13c7 NULL +#define pci_ss_list_13c8 NULL +#define pci_ss_list_13c9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13ca[] = { + &pci_ss_info_13ca_4231, + NULL +}; +#endif +#define pci_ss_list_13cb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13cc[] = { + &pci_ss_info_13cc_0000, + &pci_ss_info_13cc_0002, + &pci_ss_info_13cc_0003, + &pci_ss_info_13cc_0004, + &pci_ss_info_13cc_0005, + &pci_ss_info_13cc_0006, + &pci_ss_info_13cc_0007, + &pci_ss_info_13cc_0008, + &pci_ss_info_13cc_0009, + &pci_ss_info_13cc_000a, + &pci_ss_info_13cc_000c, + NULL +}; +#endif +#define pci_ss_list_13cd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13ce[] = { + &pci_ss_info_13ce_8031, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13cf[] = { + &pci_ss_info_13cf_8031, + NULL +}; +#endif +#define pci_ss_list_13d0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13d1[] = { + &pci_ss_info_13d1_ab01, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13d2[] = { + &pci_ss_info_13d2_0300, + &pci_ss_info_13d2_0301, + &pci_ss_info_13d2_0302, + NULL +}; +#endif +#define pci_ss_list_13d3 NULL +#define pci_ss_list_13d4 NULL +#define pci_ss_list_13d5 NULL +#define pci_ss_list_13d6 NULL +#define pci_ss_list_13d7 NULL +#define pci_ss_list_13d8 NULL +#define pci_ss_list_13d9 NULL +#define pci_ss_list_13da NULL +#define pci_ss_list_13db NULL +#define pci_ss_list_13dc NULL +#define pci_ss_list_13dd NULL +#define pci_ss_list_13de NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13df[] = { + &pci_ss_info_13df_0001, + &pci_ss_info_13df_1003, + &pci_ss_info_13df_1005, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13e0[] = { + &pci_ss_info_13e0_0012, + &pci_ss_info_13e0_0020, + &pci_ss_info_13e0_0030, + &pci_ss_info_13e0_0040, + &pci_ss_info_13e0_0041, + &pci_ss_info_13e0_0042, + &pci_ss_info_13e0_0100, + &pci_ss_info_13e0_0117, + &pci_ss_info_13e0_0147, + &pci_ss_info_13e0_0187, + &pci_ss_info_13e0_0197, + &pci_ss_info_13e0_01a7, + &pci_ss_info_13e0_01b7, + &pci_ss_info_13e0_01c7, + &pci_ss_info_13e0_01d7, + &pci_ss_info_13e0_01f7, + &pci_ss_info_13e0_0209, + &pci_ss_info_13e0_020a, + &pci_ss_info_13e0_020d, + &pci_ss_info_13e0_020e, + &pci_ss_info_13e0_0210, + &pci_ss_info_13e0_0240, + &pci_ss_info_13e0_0247, + &pci_ss_info_13e0_0250, + &pci_ss_info_13e0_0260, + &pci_ss_info_13e0_0261, + &pci_ss_info_13e0_0270, + &pci_ss_info_13e0_0290, + &pci_ss_info_13e0_0297, + &pci_ss_info_13e0_02a0, + &pci_ss_info_13e0_02b0, + &pci_ss_info_13e0_02c0, + &pci_ss_info_13e0_02c7, + &pci_ss_info_13e0_02d0, + &pci_ss_info_13e0_0410, + &pci_ss_info_13e0_0412, + &pci_ss_info_13e0_0420, + &pci_ss_info_13e0_0440, + &pci_ss_info_13e0_0441, + &pci_ss_info_13e0_0442, + &pci_ss_info_13e0_0443, + &pci_ss_info_13e0_0450, + &pci_ss_info_13e0_8d84, + &pci_ss_info_13e0_8d85, + &pci_ss_info_13e0_f100, + &pci_ss_info_13e0_f101, + &pci_ss_info_13e0_f102, + NULL +}; +#endif +#define pci_ss_list_13e1 NULL +#define pci_ss_list_13e2 NULL +#define pci_ss_list_13e3 NULL +#define pci_ss_list_13e4 NULL +#define pci_ss_list_13e5 NULL +#define pci_ss_list_13e6 NULL +#define pci_ss_list_13e7 NULL +#define pci_ss_list_13e8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13e9[] = { + &pci_ss_info_13e9_0070, + NULL +}; +#endif +#define pci_ss_list_13ea NULL +#define pci_ss_list_13eb NULL +#define pci_ss_list_13ec NULL +#define pci_ss_list_13ed NULL +#define pci_ss_list_13ee NULL +#define pci_ss_list_13ef NULL +#define pci_ss_list_13f0 NULL +#define pci_ss_list_13f1 NULL +#define pci_ss_list_13f2 NULL +#define pci_ss_list_13f3 NULL +#define pci_ss_list_13f4 NULL +#define pci_ss_list_13f5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13f6[] = { + &pci_ss_info_13f6_0101, + &pci_ss_info_13f6_0111, + &pci_ss_info_13f6_ffff, + NULL +}; +#endif +#define pci_ss_list_13f7 NULL +#define pci_ss_list_13f8 NULL +#define pci_ss_list_13f9 NULL +#define pci_ss_list_13fa NULL +#define pci_ss_list_13fb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13fc[] = { + &pci_ss_info_13fc_2471, + NULL +}; +#endif +#define pci_ss_list_13fd NULL +#define pci_ss_list_13fe NULL +#define pci_ss_list_13ff NULL +#define pci_ss_list_1400 NULL +#define pci_ss_list_1401 NULL +#define pci_ss_list_1402 NULL +#define pci_ss_list_1403 NULL +#define pci_ss_list_1404 NULL +#define pci_ss_list_1405 NULL +#define pci_ss_list_1406 NULL +#define pci_ss_list_1407 NULL +#define pci_ss_list_1408 NULL +#define pci_ss_list_1409 NULL +#define pci_ss_list_140a NULL +#define pci_ss_list_140b NULL +#define pci_ss_list_140c NULL +#define pci_ss_list_140d NULL +#define pci_ss_list_140e NULL +#define pci_ss_list_140f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1410[] = { + &pci_ss_info_1410_0104, + NULL +}; +#endif +#define pci_ss_list_1411 NULL +#define pci_ss_list_1412 NULL +#define pci_ss_list_1413 NULL +#define pci_ss_list_1414 NULL +#define pci_ss_list_1415 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1416[] = { + &pci_ss_info_1416_9804, + NULL +}; +#endif +#define pci_ss_list_1417 NULL +#define pci_ss_list_1418 NULL +#define pci_ss_list_1419 NULL +#define pci_ss_list_141a NULL +#define pci_ss_list_141b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_141d[] = { + &pci_ss_info_141d_0440, + NULL +}; +#endif +#define pci_ss_list_141e NULL +#define pci_ss_list_141f NULL +#define pci_ss_list_1420 NULL +#define pci_ss_list_1421 NULL +#define pci_ss_list_1422 NULL +#define pci_ss_list_1423 NULL +#define pci_ss_list_1424 NULL +#define pci_ss_list_1425 NULL +#define pci_ss_list_1426 NULL +#define pci_ss_list_1427 NULL +#define pci_ss_list_1428 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1429[] = { + &pci_ss_info_1429_d010, + NULL +}; +#endif +#define pci_ss_list_142a NULL +#define pci_ss_list_142b NULL +#define pci_ss_list_142c NULL +#define pci_ss_list_142d NULL +#define pci_ss_list_142e NULL +#define pci_ss_list_142f NULL +#define pci_ss_list_1430 NULL +#define pci_ss_list_1431 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1432[] = { + &pci_ss_info_1432_9130, + NULL +}; +#endif +#define pci_ss_list_1433 NULL +#define pci_ss_list_1435 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1436[] = { + &pci_ss_info_1436_0300, + &pci_ss_info_1436_0301, + &pci_ss_info_1436_0302, + &pci_ss_info_1436_0440, + &pci_ss_info_1436_1003, + &pci_ss_info_1436_1005, + &pci_ss_info_1436_1103, + &pci_ss_info_1436_1105, + &pci_ss_info_1436_1203, + &pci_ss_info_1436_1303, + &pci_ss_info_1436_1602, + &pci_ss_info_1436_8139, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1437[] = { + &pci_ss_info_1437_1105, + NULL +}; +#endif +#define pci_ss_list_1438 NULL +#define pci_ss_list_1439 NULL +#define pci_ss_list_143a NULL +#define pci_ss_list_143b NULL +#define pci_ss_list_143c NULL +#define pci_ss_list_143d NULL +#define pci_ss_list_143e NULL +#define pci_ss_list_143f NULL +#define pci_ss_list_1440 NULL +#define pci_ss_list_1441 NULL +#define pci_ss_list_1442 NULL +#define pci_ss_list_1443 NULL +#define pci_ss_list_1444 NULL +#define pci_ss_list_1445 NULL +#define pci_ss_list_1446 NULL +#define pci_ss_list_1447 NULL +#define pci_ss_list_1448 NULL +#define pci_ss_list_1449 NULL +#define pci_ss_list_144a NULL +#define pci_ss_list_144b NULL +#define pci_ss_list_144c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_144d[] = { + &pci_ss_info_144d_2101, + &pci_ss_info_144d_2104, + &pci_ss_info_144d_2115, + &pci_ss_info_144d_2321, + &pci_ss_info_144d_2501, + &pci_ss_info_144d_2502, + &pci_ss_info_144d_2602, + &pci_ss_info_144d_3510, + &pci_ss_info_144d_c000, + &pci_ss_info_144d_c001, + &pci_ss_info_144d_c003, + &pci_ss_info_144d_c006, + NULL +}; +#endif +#define pci_ss_list_144e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_144f[] = { + &pci_ss_info_144f_0441, + &pci_ss_info_144f_0449, + &pci_ss_info_144f_1005, + &pci_ss_info_144f_100c, + &pci_ss_info_144f_1104, + &pci_ss_info_144f_110d, + &pci_ss_info_144f_1500, + &pci_ss_info_144f_1501, + &pci_ss_info_144f_1502, + &pci_ss_info_144f_1503, + &pci_ss_info_144f_150a, + &pci_ss_info_144f_150b, + &pci_ss_info_144f_1510, + &pci_ss_info_144f_3000, + &pci_ss_info_144f_4005, + NULL +}; +#endif +#define pci_ss_list_1450 NULL +#define pci_ss_list_1451 NULL +#define pci_ss_list_1453 NULL +#define pci_ss_list_1454 NULL +#define pci_ss_list_1455 NULL +#define pci_ss_list_1456 NULL +#define pci_ss_list_1457 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1458[] = { + &pci_ss_info_1458_0400, + &pci_ss_info_1458_0596, + &pci_ss_info_1458_0691, + &pci_ss_info_1458_4000, + &pci_ss_info_1458_4002, + &pci_ss_info_1458_5000, + &pci_ss_info_1458_5001, + &pci_ss_info_1458_5002, + &pci_ss_info_1458_5004, + &pci_ss_info_1458_7600, + &pci_ss_info_1458_a000, + &pci_ss_info_1458_a002, + NULL +}; +#endif +#define pci_ss_list_1459 NULL +#define pci_ss_list_145a NULL +#define pci_ss_list_145b NULL +#define pci_ss_list_145c NULL +#define pci_ss_list_145d NULL +#define pci_ss_list_145e NULL +#define pci_ss_list_145f NULL +#define pci_ss_list_1460 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1461[] = { + &pci_ss_info_1461_0004, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1462[] = { + &pci_ss_info_1462_3091, + &pci_ss_info_1462_3370, + &pci_ss_info_1462_3981, + &pci_ss_info_1462_400a, + &pci_ss_info_1462_5800, + &pci_ss_info_1462_6470, + &pci_ss_info_1462_6560, + &pci_ss_info_1462_6630, + &pci_ss_info_1462_6631, + &pci_ss_info_1462_6632, + &pci_ss_info_1462_6633, + &pci_ss_info_1462_6780, + &pci_ss_info_1462_6820, + &pci_ss_info_1462_6822, + &pci_ss_info_1462_6830, + &pci_ss_info_1462_6880, + &pci_ss_info_1462_6900, + &pci_ss_info_1462_6910, + &pci_ss_info_1462_6930, + &pci_ss_info_1462_6990, + &pci_ss_info_1462_6991, + &pci_ss_info_1462_8661, + &pci_ss_info_1462_8730, + &pci_ss_info_1462_8808, + &pci_ss_info_1462_8817, + &pci_ss_info_1462_8831, + NULL +}; +#endif +#define pci_ss_list_1463 NULL +#define pci_ss_list_1464 NULL +#define pci_ss_list_1465 NULL +#define pci_ss_list_1466 NULL +#define pci_ss_list_1467 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1468[] = { + &pci_ss_info_1468_0410, + &pci_ss_info_1468_0440, + &pci_ss_info_1468_0441, + &pci_ss_info_1468_0449, + &pci_ss_info_1468_2015, + NULL +}; +#endif +#define pci_ss_list_1469 NULL +#define pci_ss_list_146a NULL +#define pci_ss_list_146b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_146c[] = { + &pci_ss_info_146c_1439, + NULL +}; +#endif +#define pci_ss_list_146d NULL +#define pci_ss_list_146e NULL +#define pci_ss_list_146f NULL +#define pci_ss_list_1470 NULL +#define pci_ss_list_1471 NULL +#define pci_ss_list_1472 NULL +#define pci_ss_list_1473 NULL +#define pci_ss_list_1474 NULL +#define pci_ss_list_1475 NULL +#define pci_ss_list_1476 NULL +#define pci_ss_list_1477 NULL +#define pci_ss_list_1478 NULL +#define pci_ss_list_1479 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_147a[] = { + &pci_ss_info_147a_c001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_147b[] = { + &pci_ss_info_147b_0507, + &pci_ss_info_147b_8f00, + &pci_ss_info_147b_8f09, + &pci_ss_info_147b_a401, + &pci_ss_info_147b_a702, + NULL +}; +#endif +#define pci_ss_list_147c NULL +#define pci_ss_list_147d NULL +#define pci_ss_list_147e NULL +#define pci_ss_list_147f NULL +#define pci_ss_list_1480 NULL +#define pci_ss_list_1481 NULL +#define pci_ss_list_1482 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1483[] = { + &pci_ss_info_1483_5020, + &pci_ss_info_1483_5021, + &pci_ss_info_1483_5022, + NULL +}; +#endif +#define pci_ss_list_1484 NULL +#define pci_ss_list_1485 NULL +#define pci_ss_list_1486 NULL +#define pci_ss_list_1487 NULL +#define pci_ss_list_1488 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1489[] = { + &pci_ss_info_1489_6001, + &pci_ss_info_1489_6002, + NULL +}; +#endif +#define pci_ss_list_148a NULL +#define pci_ss_list_148b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_148c[] = { + &pci_ss_info_148c_2003, + &pci_ss_info_148c_2023, + &pci_ss_info_148c_2024, + &pci_ss_info_148c_2025, + &pci_ss_info_148c_2026, + &pci_ss_info_148c_2036, + &pci_ss_info_148c_2039, + NULL +}; +#endif +#define pci_ss_list_148d NULL +#define pci_ss_list_148e NULL +#define pci_ss_list_148f NULL +#define pci_ss_list_1490 NULL +#define pci_ss_list_1491 NULL +#define pci_ss_list_1492 NULL +#define pci_ss_list_1493 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1494[] = { + &pci_ss_info_1494_0300, + &pci_ss_info_1494_0301, + NULL +}; +#endif +#define pci_ss_list_1495 NULL +#define pci_ss_list_1496 NULL +#define pci_ss_list_1497 NULL +#define pci_ss_list_1498 NULL +#define pci_ss_list_1499 NULL +#define pci_ss_list_149a NULL +#define pci_ss_list_149b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_149c[] = { + &pci_ss_info_149c_139a, + &pci_ss_info_149c_8139, + NULL +}; +#endif +#define pci_ss_list_149d NULL +#define pci_ss_list_149e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_149f[] = { + &pci_ss_info_149f_0440, + NULL +}; +#endif +#define pci_ss_list_14a0 NULL +#define pci_ss_list_14a1 NULL +#define pci_ss_list_14a2 NULL +#define pci_ss_list_14a3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14a4[] = { + &pci_ss_info_14a4_2073, + &pci_ss_info_14a4_2077, + &pci_ss_info_14a4_2089, + &pci_ss_info_14a4_2091, + &pci_ss_info_14a4_2104, + &pci_ss_info_14a4_2105, + &pci_ss_info_14a4_2106, + &pci_ss_info_14a4_2107, + &pci_ss_info_14a4_2172, + NULL +}; +#endif +#define pci_ss_list_14a5 NULL +#define pci_ss_list_14a6 NULL +#define pci_ss_list_14a7 NULL +#define pci_ss_list_14a8 NULL +#define pci_ss_list_14a9 NULL +#define pci_ss_list_14aa NULL +#define pci_ss_list_14ab NULL +#define pci_ss_list_14ac NULL +#define pci_ss_list_14ad NULL +#define pci_ss_list_14ae NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14af[] = { + &pci_ss_info_14af_0002, + &pci_ss_info_14af_5008, + &pci_ss_info_14af_5021, + &pci_ss_info_14af_5022, + &pci_ss_info_14af_5810, + &pci_ss_info_14af_5820, + &pci_ss_info_14af_7102, + &pci_ss_info_14af_7103, + NULL +}; +#endif +#define pci_ss_list_14b0 NULL +#define pci_ss_list_14b1 NULL +#define pci_ss_list_14b2 NULL +#define pci_ss_list_14b3 NULL +#define pci_ss_list_14b4 NULL +#define pci_ss_list_14b5 NULL +#define pci_ss_list_14b6 NULL +#define pci_ss_list_14b7 NULL +#define pci_ss_list_14b8 NULL +#define pci_ss_list_14b9 NULL +#define pci_ss_list_14ba NULL +#define pci_ss_list_14bb NULL +#define pci_ss_list_14bc NULL +#define pci_ss_list_14bd NULL +#define pci_ss_list_14be NULL +#define pci_ss_list_14bf NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14c0[] = { + &pci_ss_info_14c0_0004, + &pci_ss_info_14c0_000c, + NULL +}; +#endif +#define pci_ss_list_14c1 NULL +#define pci_ss_list_14c2 NULL +#define pci_ss_list_14c3 NULL +#define pci_ss_list_14c4 NULL +#define pci_ss_list_14c5 NULL +#define pci_ss_list_14c6 NULL +#define pci_ss_list_14c7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14c8[] = { + &pci_ss_info_14c8_0300, + &pci_ss_info_14c8_0302, + NULL +}; +#endif +#define pci_ss_list_14c9 NULL +#define pci_ss_list_14ca NULL +#define pci_ss_list_14cb NULL +#define pci_ss_list_14cc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14cd[] = { + &pci_ss_info_14cd_2194, + NULL +}; +#endif +#define pci_ss_list_14ce NULL +#define pci_ss_list_14cf NULL +#define pci_ss_list_14d0 NULL +#define pci_ss_list_14d1 NULL +#define pci_ss_list_14d2 NULL +#define pci_ss_list_14d3 NULL +#define pci_ss_list_14d4 NULL +#define pci_ss_list_14d5 NULL +#define pci_ss_list_14d6 NULL +#define pci_ss_list_14d7 NULL +#define pci_ss_list_14d8 NULL +#define pci_ss_list_14d9 NULL +#define pci_ss_list_14da NULL +#define pci_ss_list_14db NULL +#define pci_ss_list_14dc NULL +#define pci_ss_list_14dd NULL +#define pci_ss_list_14de NULL +#define pci_ss_list_14df NULL +#define pci_ss_list_14e1 NULL +#define pci_ss_list_14e2 NULL +#define pci_ss_list_14e3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14e4[] = { + &pci_ss_info_14e4_0001, + &pci_ss_info_14e4_0002, + &pci_ss_info_14e4_0003, + &pci_ss_info_14e4_0004, + &pci_ss_info_14e4_0005, + &pci_ss_info_14e4_0006, + &pci_ss_info_14e4_0007, + &pci_ss_info_14e4_0008, + &pci_ss_info_14e4_0009, + &pci_ss_info_14e4_000a, + &pci_ss_info_14e4_000b, + &pci_ss_info_14e4_000c, + &pci_ss_info_14e4_000d, + &pci_ss_info_14e4_1028, + &pci_ss_info_14e4_1644, + &pci_ss_info_14e4_8008, + &pci_ss_info_14e4_8009, + &pci_ss_info_14e4_800a, + NULL +}; +#endif +#define pci_ss_list_14e5 NULL +#define pci_ss_list_14e6 NULL +#define pci_ss_list_14e7 NULL +#define pci_ss_list_14e8 NULL +#define pci_ss_list_14e9 NULL +#define pci_ss_list_14ea NULL +#define pci_ss_list_14eb NULL +#define pci_ss_list_14ec NULL +#define pci_ss_list_14ed NULL +#define pci_ss_list_14ee NULL +#define pci_ss_list_14ef NULL +#define pci_ss_list_14f0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14f1[] = { + &pci_ss_info_14f1_0001, + &pci_ss_info_14f1_0002, + &pci_ss_info_14f1_0003, + &pci_ss_info_14f1_0044, + &pci_ss_info_14f1_0048, + &pci_ss_info_14f1_0122, + &pci_ss_info_14f1_0144, + &pci_ss_info_14f1_0222, + &pci_ss_info_14f1_0244, + &pci_ss_info_14f1_0322, + &pci_ss_info_14f1_0422, + &pci_ss_info_14f1_1122, + &pci_ss_info_14f1_1222, + &pci_ss_info_14f1_1322, + &pci_ss_info_14f1_1522, + &pci_ss_info_14f1_1622, + &pci_ss_info_14f1_1722, + &pci_ss_info_14f1_2004, + &pci_ss_info_14f1_5421, + NULL +}; +#endif +#define pci_ss_list_14f2 NULL +#define pci_ss_list_14f3 NULL +#define pci_ss_list_14f4 NULL +#define pci_ss_list_14f5 NULL +#define pci_ss_list_14f6 NULL +#define pci_ss_list_14f7 NULL +#define pci_ss_list_14f8 NULL +#define pci_ss_list_14f9 NULL +#define pci_ss_list_14fa NULL +#define pci_ss_list_14fb NULL +#define pci_ss_list_14fc NULL +#define pci_ss_list_14fd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14fe[] = { + &pci_ss_info_14fe_0428, + &pci_ss_info_14fe_0429, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14ff[] = { + &pci_ss_info_14ff_1100, + NULL +}; +#endif +#define pci_ss_list_1500 NULL +#define pci_ss_list_1501 NULL +#define pci_ss_list_1502 NULL +#define pci_ss_list_1503 NULL +#define pci_ss_list_1504 NULL +#define pci_ss_list_1505 NULL +#define pci_ss_list_1506 NULL +#define pci_ss_list_1507 NULL +#define pci_ss_list_1508 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1509[] = { + &pci_ss_info_1509_7002, + &pci_ss_info_1509_9902, + &pci_ss_info_1509_9903, + &pci_ss_info_1509_9904, + &pci_ss_info_1509_9905, + &pci_ss_info_1509_9a00, + NULL +}; +#endif +#define pci_ss_list_150a NULL +#define pci_ss_list_150b NULL +#define pci_ss_list_150c NULL +#define pci_ss_list_150d NULL +#define pci_ss_list_150e NULL +#define pci_ss_list_150f NULL +#define pci_ss_list_1510 NULL +#define pci_ss_list_1511 NULL +#define pci_ss_list_1512 NULL +#define pci_ss_list_1513 NULL +#define pci_ss_list_1514 NULL +#define pci_ss_list_1515 NULL +#define pci_ss_list_1516 NULL +#define pci_ss_list_1517 NULL +#define pci_ss_list_1518 NULL +#define pci_ss_list_1519 NULL +#define pci_ss_list_151a NULL +#define pci_ss_list_151b NULL +#define pci_ss_list_151c NULL +#define pci_ss_list_151d NULL +#define pci_ss_list_151e NULL +#define pci_ss_list_151f NULL +#define pci_ss_list_1520 NULL +#define pci_ss_list_1521 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1522[] = { + &pci_ss_info_1522_0001, + &pci_ss_info_1522_0002, + &pci_ss_info_1522_0003, + &pci_ss_info_1522_0004, + &pci_ss_info_1522_0010, + &pci_ss_info_1522_0020, + &pci_ss_info_1522_0200, + &pci_ss_info_1522_0300, + &pci_ss_info_1522_0400, + &pci_ss_info_1522_0500, + &pci_ss_info_1522_0600, + &pci_ss_info_1522_0700, + &pci_ss_info_1522_0800, + NULL +}; +#endif +#define pci_ss_list_1523 NULL +#define pci_ss_list_1524 NULL +#define pci_ss_list_1525 NULL +#define pci_ss_list_1526 NULL +#define pci_ss_list_1527 NULL +#define pci_ss_list_1528 NULL +#define pci_ss_list_1529 NULL +#define pci_ss_list_152a NULL +#define pci_ss_list_152b NULL +#define pci_ss_list_152c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_152d[] = { + &pci_ss_info_152d_8801, + &pci_ss_info_152d_8802, + &pci_ss_info_152d_8803, + &pci_ss_info_152d_8804, + &pci_ss_info_152d_8805, + &pci_ss_info_152d_8808, + NULL +}; +#endif +#define pci_ss_list_152e NULL +#define pci_ss_list_152f NULL +#define pci_ss_list_1530 NULL +#define pci_ss_list_1531 NULL +#define pci_ss_list_1532 NULL +#define pci_ss_list_1533 NULL +#define pci_ss_list_1534 NULL +#define pci_ss_list_1535 NULL +#define pci_ss_list_1537 NULL +#define pci_ss_list_1538 NULL +#define pci_ss_list_1539 NULL +#define pci_ss_list_153a NULL +#define pci_ss_list_153b NULL +#define pci_ss_list_153c NULL +#define pci_ss_list_153d NULL +#define pci_ss_list_153e NULL +#define pci_ss_list_153f NULL +#define pci_ss_list_1540 NULL +#define pci_ss_list_1541 NULL +#define pci_ss_list_1542 NULL +#define pci_ss_list_1543 NULL +#define pci_ss_list_1544 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1545[] = { + &pci_ss_info_1545_002f, + NULL +}; +#endif +#define pci_ss_list_1546 NULL +#define pci_ss_list_1547 NULL +#define pci_ss_list_1548 NULL +#define pci_ss_list_1549 NULL +#define pci_ss_list_154a NULL +#define pci_ss_list_154b NULL +#define pci_ss_list_154c NULL +#define pci_ss_list_154d NULL +#define pci_ss_list_154e NULL +#define pci_ss_list_154f NULL +#define pci_ss_list_1550 NULL +#define pci_ss_list_1551 NULL +#define pci_ss_list_1552 NULL +#define pci_ss_list_1553 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1554[] = { + &pci_ss_info_1554_1041, + NULL +}; +#endif +#define pci_ss_list_1555 NULL +#define pci_ss_list_1556 NULL +#define pci_ss_list_1557 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1558[] = { + &pci_ss_info_1558_1103, + &pci_ss_info_1558_2200, + NULL +}; +#endif +#define pci_ss_list_1559 NULL +#define pci_ss_list_155a NULL +#define pci_ss_list_155b NULL +#define pci_ss_list_155c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_155d[] = { + &pci_ss_info_155d_2f07, + &pci_ss_info_155d_6793, + &pci_ss_info_155d_8850, + NULL +}; +#endif +#define pci_ss_list_155e NULL +#define pci_ss_list_155f NULL +#define pci_ss_list_1560 NULL +#define pci_ss_list_1561 NULL +#define pci_ss_list_1562 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1563[] = { + &pci_ss_info_1563_7018, + NULL +}; +#endif +#define pci_ss_list_1564 NULL +#define pci_ss_list_1565 NULL +#define pci_ss_list_1566 NULL +#define pci_ss_list_1567 NULL +#define pci_ss_list_1568 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1569[] = { + &pci_ss_info_1569_6326, + NULL +}; +#endif +#define pci_ss_list_156a NULL +#define pci_ss_list_156b NULL +#define pci_ss_list_156c NULL +#define pci_ss_list_156d NULL +#define pci_ss_list_156e NULL +#define pci_ss_list_156f NULL +#define pci_ss_list_1570 NULL +#define pci_ss_list_1571 NULL +#define pci_ss_list_1572 NULL +#define pci_ss_list_1573 NULL +#define pci_ss_list_1574 NULL +#define pci_ss_list_1575 NULL +#define pci_ss_list_1576 NULL +#define pci_ss_list_1578 NULL +#define pci_ss_list_1579 NULL +#define pci_ss_list_157a NULL +#define pci_ss_list_157b NULL +#define pci_ss_list_157c NULL +#define pci_ss_list_157d NULL +#define pci_ss_list_157e NULL +#define pci_ss_list_157f NULL +#define pci_ss_list_1580 NULL +#define pci_ss_list_1581 NULL +#define pci_ss_list_1582 NULL +#define pci_ss_list_1583 NULL +#define pci_ss_list_1584 NULL +#define pci_ss_list_1585 NULL +#define pci_ss_list_1586 NULL +#define pci_ss_list_1587 NULL +#define pci_ss_list_1588 NULL +#define pci_ss_list_1589 NULL +#define pci_ss_list_158a NULL +#define pci_ss_list_158b NULL +#define pci_ss_list_158c NULL +#define pci_ss_list_158d NULL +#define pci_ss_list_158e NULL +#define pci_ss_list_158f NULL +#define pci_ss_list_1590 NULL +#define pci_ss_list_1591 NULL +#define pci_ss_list_1592 NULL +#define pci_ss_list_1593 NULL +#define pci_ss_list_1594 NULL +#define pci_ss_list_1595 NULL +#define pci_ss_list_1596 NULL +#define pci_ss_list_1597 NULL +#define pci_ss_list_1598 NULL +#define pci_ss_list_1599 NULL +#define pci_ss_list_159a NULL +#define pci_ss_list_159b NULL +#define pci_ss_list_159c NULL +#define pci_ss_list_159d NULL +#define pci_ss_list_159e NULL +#define pci_ss_list_159f NULL +#define pci_ss_list_15a0 NULL +#define pci_ss_list_15a1 NULL +#define pci_ss_list_15a2 NULL +#define pci_ss_list_15a3 NULL +#define pci_ss_list_15a4 NULL +#define pci_ss_list_15a5 NULL +#define pci_ss_list_15a6 NULL +#define pci_ss_list_15a7 NULL +#define pci_ss_list_15a8 NULL +#define pci_ss_list_15aa NULL +#define pci_ss_list_15ab NULL +#define pci_ss_list_15ac NULL +#define pci_ss_list_15ad NULL +#define pci_ss_list_15ae NULL +#define pci_ss_list_15b0 NULL +#define pci_ss_list_15b1 NULL +#define pci_ss_list_15b2 NULL +#define pci_ss_list_15b3 NULL +#define pci_ss_list_15b4 NULL +#define pci_ss_list_15b5 NULL +#define pci_ss_list_15b6 NULL +#define pci_ss_list_15b7 NULL +#define pci_ss_list_15b8 NULL +#define pci_ss_list_15b9 NULL +#define pci_ss_list_15ba NULL +#define pci_ss_list_15bb NULL +#define pci_ss_list_15bc NULL +#define pci_ss_list_15bd NULL +#define pci_ss_list_15be NULL +#define pci_ss_list_15bf NULL +#define pci_ss_list_15c0 NULL +#define pci_ss_list_15c1 NULL +#define pci_ss_list_15c2 NULL +#define pci_ss_list_15c3 NULL +#define pci_ss_list_15c4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15c5[] = { + &pci_ss_info_15c5_0111, + NULL +}; +#endif +#define pci_ss_list_15c6 NULL +#define pci_ss_list_15c7 NULL +#define pci_ss_list_15c8 NULL +#define pci_ss_list_15c9 NULL +#define pci_ss_list_15ca NULL +#define pci_ss_list_15cb NULL +#define pci_ss_list_15cc NULL +#define pci_ss_list_15cd NULL +#define pci_ss_list_15ce NULL +#define pci_ss_list_15cf NULL +#define pci_ss_list_15d1 NULL +#define pci_ss_list_15d2 NULL +#define pci_ss_list_15d3 NULL +#define pci_ss_list_15d4 NULL +#define pci_ss_list_15d5 NULL +#define pci_ss_list_15d6 NULL +#define pci_ss_list_15d7 NULL +#define pci_ss_list_15d8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15d9[] = { + &pci_ss_info_15d9_3480, + &pci_ss_info_15d9_9005, + NULL +}; +#endif +#define pci_ss_list_15da NULL +#define pci_ss_list_15db NULL +#define pci_ss_list_15dc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15dd[] = { + &pci_ss_info_15dd_7609, + NULL +}; +#endif +#define pci_ss_list_15de NULL +#define pci_ss_list_15df NULL +#define pci_ss_list_15e0 NULL +#define pci_ss_list_15e1 NULL +#define pci_ss_list_15e2 NULL +#define pci_ss_list_15e3 NULL +#define pci_ss_list_15e4 NULL +#define pci_ss_list_15e5 NULL +#define pci_ss_list_15e6 NULL +#define pci_ss_list_15e7 NULL +#define pci_ss_list_15e8 NULL +#define pci_ss_list_15e9 NULL +#define pci_ss_list_15ea NULL +#define pci_ss_list_15eb NULL +#define pci_ss_list_15ec NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15ed[] = { + &pci_ss_info_15ed_1000, + &pci_ss_info_15ed_1001, + &pci_ss_info_15ed_1002, + &pci_ss_info_15ed_1003, + &pci_ss_info_15ed_2000, + &pci_ss_info_15ed_2001, + NULL +}; +#endif +#define pci_ss_list_15ee NULL +#define pci_ss_list_15ef NULL +#define pci_ss_list_15f0 NULL +#define pci_ss_list_15f1 NULL +#define pci_ss_list_15f2 NULL +#define pci_ss_list_15f3 NULL +#define pci_ss_list_15f4 NULL +#define pci_ss_list_15f5 NULL +#define pci_ss_list_15f6 NULL +#define pci_ss_list_15f7 NULL +#define pci_ss_list_15f8 NULL +#define pci_ss_list_15f9 NULL +#define pci_ss_list_15fa NULL +#define pci_ss_list_15fb NULL +#define pci_ss_list_15fc NULL +#define pci_ss_list_15fd NULL +#define pci_ss_list_15fe NULL +#define pci_ss_list_15ff NULL +#define pci_ss_list_1600 NULL +#define pci_ss_list_1601 NULL +#define pci_ss_list_1602 NULL +#define pci_ss_list_1603 NULL +#define pci_ss_list_1604 NULL +#define pci_ss_list_1605 NULL +#define pci_ss_list_1606 NULL +#define pci_ss_list_1607 NULL +#define pci_ss_list_1608 NULL +#define pci_ss_list_1609 NULL +#define pci_ss_list_1612 NULL +#define pci_ss_list_1619 NULL +#define pci_ss_list_1629 NULL +#define pci_ss_list_1638 NULL +#define pci_ss_list_163c NULL +#define pci_ss_list_1657 NULL +#define pci_ss_list_165a NULL +#define pci_ss_list_165d NULL +#define pci_ss_list_1661 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1668[] = { + &pci_ss_info_1668_0299, + &pci_ss_info_1668_0300, + &pci_ss_info_1668_0302, + &pci_ss_info_1668_0414, + &pci_ss_info_1668_0440, + &pci_ss_info_1668_1100, + &pci_ss_info_1668_2400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1681[] = { + &pci_ss_info_1681_0040, + &pci_ss_info_1681_0050, + &pci_ss_info_1681_a011, + NULL +}; +#endif +#define pci_ss_list_16ab NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16be[] = { + &pci_ss_info_16be_0001, + &pci_ss_info_16be_0002, + &pci_ss_info_16be_1040, + NULL +}; +#endif +#define pci_ss_list_16ec NULL +#define pci_ss_list_16f6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1705[] = { + &pci_ss_info_1705_0001, + &pci_ss_info_1705_0002, + &pci_ss_info_1705_0003, + &pci_ss_info_1705_0004, + NULL +}; +#endif +#define pci_ss_list_170b NULL +#define pci_ss_list_170c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_172a[] = { + &pci_ss_info_172a_0000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1737[] = { + &pci_ss_info_1737_3874, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_173b[] = { + &pci_ss_info_173b_0001, + NULL +}; +#endif +#define pci_ss_list_1743 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_174b[] = { + &pci_ss_info_174b_7112, + &pci_ss_info_174b_7147, + &pci_ss_info_174b_7149, + &pci_ss_info_174b_7161, + &pci_ss_info_174b_7176, + &pci_ss_info_174b_7192, + NULL +}; +#endif +#define pci_ss_list_175e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1787[] = { + &pci_ss_info_1787_0202, + NULL +}; +#endif +#define pci_ss_list_1796 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1799[] = { + &pci_ss_info_1799_0001, + &pci_ss_info_1799_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17af[] = { + &pci_ss_info_17af_0202, + &pci_ss_info_17af_2005, + &pci_ss_info_17af_2006, + NULL +}; +#endif +#define pci_ss_list_17cc NULL +#define pci_ss_list_1813 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1851[] = { + &pci_ss_info_1851_1850, + &pci_ss_info_1851_1851, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1852[] = { + &pci_ss_info_1852_1852, + NULL +}; +#endif +#define pci_ss_list_1888 NULL +#define pci_ss_list_1a08 NULL +#define pci_ss_list_1b13 NULL +#define pci_ss_list_1c1c NULL +#define pci_ss_list_1d44 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1de1[] = { + &pci_ss_info_1de1_1020, + &pci_ss_info_1de1_3904, + &pci_ss_info_1de1_3907, + NULL +}; +#endif +#define pci_ss_list_2000 NULL +#define pci_ss_list_2001 NULL +#define pci_ss_list_2003 NULL +#define pci_ss_list_2004 NULL +#define pci_ss_list_21c3 NULL +#define pci_ss_list_2348 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_2646[] = { + &pci_ss_info_2646_0001, + NULL +}; +#endif +#define pci_ss_list_270b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_270f[] = { + &pci_ss_info_270f_2001, + &pci_ss_info_270f_2200, + &pci_ss_info_270f_3000, + &pci_ss_info_270f_3100, + &pci_ss_info_270f_3102, + &pci_ss_info_270f_7040, + &pci_ss_info_270f_7060, + &pci_ss_info_270f_a171, + NULL +}; +#endif +#define pci_ss_list_2711 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_2a15[] = { + &pci_ss_info_2a15_54a3, + NULL +}; +#endif +#define pci_ss_list_3000 NULL +#define pci_ss_list_3142 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_3388[] = { + &pci_ss_info_3388_8011, + &pci_ss_info_3388_8012, + &pci_ss_info_3388_8013, + NULL +}; +#endif +#define pci_ss_list_3411 NULL +#define pci_ss_list_3513 NULL +#define pci_ss_list_38ef NULL +static const pciSubsystemInfo *pci_ss_list_3d3d[] = { + &pci_ss_info_3d3d_0100, + &pci_ss_info_3d3d_0111, + &pci_ss_info_3d3d_0114, + &pci_ss_info_3d3d_0116, + &pci_ss_info_3d3d_0119, + &pci_ss_info_3d3d_0120, + &pci_ss_info_3d3d_0121, + &pci_ss_info_3d3d_0125, + &pci_ss_info_3d3d_0127, + &pci_ss_info_3d3d_0144, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_4005[] = { + &pci_ss_info_4005_4000, + NULL +}; +#define pci_ss_list_4033 NULL +#define pci_ss_list_4143 NULL +#define pci_ss_list_416c NULL +#define pci_ss_list_4444 NULL +#define pci_ss_list_4468 NULL +#define pci_ss_list_4594 NULL +#define pci_ss_list_45fb NULL +#define pci_ss_list_4680 NULL +#define pci_ss_list_4843 NULL +#define pci_ss_list_4916 NULL +#define pci_ss_list_4943 NULL +#define pci_ss_list_4978 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_4a14[] = { + &pci_ss_info_4a14_5000, + NULL +}; +#endif +#define pci_ss_list_4b10 NULL +#define pci_ss_list_4c48 NULL +#define pci_ss_list_4c53 NULL +#define pci_ss_list_4ca1 NULL +#define pci_ss_list_4d51 NULL +#define pci_ss_list_4d54 NULL +#define pci_ss_list_4ddc NULL +#define pci_ss_list_5046 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_5053[] = { + &pci_ss_info_5053_3355, + &pci_ss_info_5053_3356, + NULL +}; +#endif +#define pci_ss_list_5136 NULL +#define pci_ss_list_5143 NULL +#define pci_ss_list_5145 NULL +#define pci_ss_list_5168 NULL +#define pci_ss_list_5301 NULL +static const pciSubsystemInfo *pci_ss_list_5333[] = { + &pci_ss_info_5333_8100, + &pci_ss_info_5333_8110, + &pci_ss_info_5333_8125, + &pci_ss_info_5333_8143, + &pci_ss_info_5333_8900, + &pci_ss_info_5333_8901, + &pci_ss_info_5333_8904, + &pci_ss_info_5333_8a01, + &pci_ss_info_5333_8a13, + &pci_ss_info_5333_8a20, + &pci_ss_info_5333_8a21, + &pci_ss_info_5333_8a22, + &pci_ss_info_5333_8a2e, + &pci_ss_info_5333_9125, + &pci_ss_info_5333_9143, + NULL +}; +#define pci_ss_list_544c NULL +#define pci_ss_list_5455 NULL +#define pci_ss_list_5519 NULL +#define pci_ss_list_5544 NULL +#define pci_ss_list_5555 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_5654[] = { + &pci_ss_info_5654_5634, + NULL +}; +#endif +#define pci_ss_list_5700 NULL +#define pci_ss_list_6356 NULL +#define pci_ss_list_6374 NULL +#define pci_ss_list_6409 NULL +#define pci_ss_list_6666 NULL +#define pci_ss_list_7604 NULL +#define pci_ss_list_7bde NULL +#define pci_ss_list_7fed NULL +#define pci_ss_list_8008 NULL +static const pciSubsystemInfo *pci_ss_list_8086[] = { + &pci_ss_info_8086_0000, + &pci_ss_info_8086_0001, + &pci_ss_info_8086_0002, + &pci_ss_info_8086_0003, + &pci_ss_info_8086_0004, + &pci_ss_info_8086_0005, + &pci_ss_info_8086_0006, + &pci_ss_info_8086_0007, + &pci_ss_info_8086_0008, + &pci_ss_info_8086_0009, + &pci_ss_info_8086_000a, + &pci_ss_info_8086_000b, + &pci_ss_info_8086_000c, + &pci_ss_info_8086_000d, + &pci_ss_info_8086_000e, + &pci_ss_info_8086_000f, + &pci_ss_info_8086_0010, + &pci_ss_info_8086_0011, + &pci_ss_info_8086_0012, + &pci_ss_info_8086_0013, + &pci_ss_info_8086_001e, + &pci_ss_info_8086_002a, + &pci_ss_info_8086_002b, + &pci_ss_info_8086_002e, + &pci_ss_info_8086_0030, + &pci_ss_info_8086_0031, + &pci_ss_info_8086_0040, + &pci_ss_info_8086_0041, + &pci_ss_info_8086_0042, + &pci_ss_info_8086_0050, + &pci_ss_info_8086_0100, + &pci_ss_info_8086_1000, + &pci_ss_info_8086_1001, + &pci_ss_info_8086_1002, + &pci_ss_info_8086_1003, + &pci_ss_info_8086_1004, + &pci_ss_info_8086_1009, + &pci_ss_info_8086_100c, + &pci_ss_info_8086_1011, + &pci_ss_info_8086_1012, + &pci_ss_info_8086_1013, + &pci_ss_info_8086_1015, + &pci_ss_info_8086_1017, + &pci_ss_info_8086_1030, + &pci_ss_info_8086_1040, + &pci_ss_info_8086_1041, + &pci_ss_info_8086_1042, + &pci_ss_info_8086_1050, + &pci_ss_info_8086_1051, + &pci_ss_info_8086_1052, + &pci_ss_info_8086_10f0, + &pci_ss_info_8086_1107, + &pci_ss_info_8086_1109, + &pci_ss_info_8086_1112, + &pci_ss_info_8086_1161, + &pci_ss_info_8086_1361, + &pci_ss_info_8086_1958, + &pci_ss_info_8086_2004, + &pci_ss_info_8086_2009, + &pci_ss_info_8086_200d, + &pci_ss_info_8086_200e, + &pci_ss_info_8086_200f, + &pci_ss_info_8086_2010, + &pci_ss_info_8086_2013, + &pci_ss_info_8086_2016, + &pci_ss_info_8086_2017, + &pci_ss_info_8086_2018, + &pci_ss_info_8086_2019, + &pci_ss_info_8086_2101, + &pci_ss_info_8086_2102, + &pci_ss_info_8086_2103, + &pci_ss_info_8086_2104, + &pci_ss_info_8086_2105, + &pci_ss_info_8086_2106, + &pci_ss_info_8086_2107, + &pci_ss_info_8086_2108, + &pci_ss_info_8086_2109, + &pci_ss_info_8086_2110, + &pci_ss_info_8086_2112, + &pci_ss_info_8086_2200, + &pci_ss_info_8086_2201, + &pci_ss_info_8086_2202, + &pci_ss_info_8086_2203, + &pci_ss_info_8086_2204, + &pci_ss_info_8086_2205, + &pci_ss_info_8086_2206, + &pci_ss_info_8086_2207, + &pci_ss_info_8086_2208, + &pci_ss_info_8086_2402, + &pci_ss_info_8086_2407, + &pci_ss_info_8086_2408, + &pci_ss_info_8086_2409, + &pci_ss_info_8086_240f, + &pci_ss_info_8086_2410, + &pci_ss_info_8086_2411, + &pci_ss_info_8086_2412, + &pci_ss_info_8086_2413, + &pci_ss_info_8086_2513, + &pci_ss_info_8086_3000, + &pci_ss_info_8086_3001, + &pci_ss_info_8086_3002, + &pci_ss_info_8086_3006, + &pci_ss_info_8086_3007, + &pci_ss_info_8086_3008, + &pci_ss_info_8086_3010, + &pci_ss_info_8086_3011, + &pci_ss_info_8086_3012, + &pci_ss_info_8086_3013, + &pci_ss_info_8086_3014, + &pci_ss_info_8086_3015, + &pci_ss_info_8086_3016, + &pci_ss_info_8086_3017, + &pci_ss_info_8086_3018, + &pci_ss_info_8086_4152, + &pci_ss_info_8086_4249, + &pci_ss_info_8086_424c, + &pci_ss_info_8086_425a, + &pci_ss_info_8086_4341, + &pci_ss_info_8086_4343, + &pci_ss_info_8086_4649, + &pci_ss_info_8086_464a, + &pci_ss_info_8086_4d4f, + &pci_ss_info_8086_4f43, + &pci_ss_info_8086_5243, + &pci_ss_info_8086_5352, + &pci_ss_info_8086_5643, + &pci_ss_info_8086_5753, + &pci_ss_info_8086_8000, + &pci_ss_info_8086_8181, + &pci_ss_info_8086_9181, + NULL +}; +#define pci_ss_list_8800 NULL +#define pci_ss_list_8866 NULL +#define pci_ss_list_8888 NULL +#define pci_ss_list_8e0e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_8e2e[] = { + &pci_ss_info_8e2e_7000, + &pci_ss_info_8e2e_7100, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_9004[] = { + &pci_ss_info_9004_0008, + &pci_ss_info_9004_0009, + &pci_ss_info_9004_0010, + &pci_ss_info_9004_0018, + &pci_ss_info_9004_0019, + &pci_ss_info_9004_0020, + &pci_ss_info_9004_0028, + &pci_ss_info_9004_7560, + &pci_ss_info_9004_7710, + &pci_ss_info_9004_7711, + &pci_ss_info_9004_7815, + &pci_ss_info_9004_7840, + &pci_ss_info_9004_7850, + &pci_ss_info_9004_7861, + &pci_ss_info_9004_7880, + &pci_ss_info_9004_7881, + &pci_ss_info_9004_7887, + &pci_ss_info_9004_7888, + &pci_ss_info_9004_7890, + &pci_ss_info_9004_7891, + &pci_ss_info_9004_7892, + &pci_ss_info_9004_7894, + &pci_ss_info_9004_7895, + &pci_ss_info_9004_7896, + &pci_ss_info_9004_7897, + &pci_ss_info_9004_8008, + &pci_ss_info_9004_8009, + &pci_ss_info_9004_8010, + &pci_ss_info_9004_8018, + &pci_ss_info_9004_8019, + &pci_ss_info_9004_8020, + &pci_ss_info_9004_8028, + &pci_ss_info_9004_9110, + &pci_ss_info_9004_9111, + &pci_ss_info_9004_9210, + &pci_ss_info_9004_9211, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_9005[] = { + &pci_ss_info_9005_0003, + &pci_ss_info_9005_000f, + &pci_ss_info_9005_0041, + &pci_ss_info_9005_0365, + &pci_ss_info_9005_1364, + &pci_ss_info_9005_1365, + &pci_ss_info_9005_2180, + &pci_ss_info_9005_62a0, + &pci_ss_info_9005_62a1, + &pci_ss_info_9005_8100, + &pci_ss_info_9005_a180, + &pci_ss_info_9005_b500, + &pci_ss_info_9005_e100, + &pci_ss_info_9005_e220, + &pci_ss_info_9005_e2a0, + &pci_ss_info_9005_f500, + &pci_ss_info_9005_f620, + &pci_ss_info_9005_ffff, + NULL +}; +#endif +#define pci_ss_list_907f NULL +#define pci_ss_list_919a NULL +#define pci_ss_list_9412 NULL +#define pci_ss_list_9699 NULL +#define pci_ss_list_9710 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_a0a0[] = { + &pci_ss_info_a0a0_0007, + &pci_ss_info_a0a0_0022, + NULL +}; +#endif +#define pci_ss_list_a0f1 NULL +#define pci_ss_list_a200 NULL +#define pci_ss_list_a259 NULL +#define pci_ss_list_a25b NULL +#define pci_ss_list_a304 NULL +#define pci_ss_list_a727 NULL +#define pci_ss_list_aa42 NULL +#define pci_ss_list_ac1e NULL +#define pci_ss_list_b1b3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_bd11[] = { + &pci_ss_info_bd11_1200, + NULL +}; +#endif +#define pci_ss_list_c001 NULL +#define pci_ss_list_c0a9 NULL +#define pci_ss_list_c0de NULL +#define pci_ss_list_c0fe NULL +#define pci_ss_list_ca50 NULL +#define pci_ss_list_cafe NULL +#define pci_ss_list_cccc NULL +#define pci_ss_list_cddd NULL +#define pci_ss_list_d4d4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_d531[] = { + &pci_ss_info_d531_c002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_d84d[] = { + &pci_ss_info_d84d_4006, + &pci_ss_info_d84d_4008, + &pci_ss_info_d84d_4014, + &pci_ss_info_d84d_4018, + &pci_ss_info_d84d_4025, + &pci_ss_info_d84d_4027, + &pci_ss_info_d84d_4028, + &pci_ss_info_d84d_4036, + &pci_ss_info_d84d_4037, + &pci_ss_info_d84d_4038, + &pci_ss_info_d84d_4052, + &pci_ss_info_d84d_4053, + &pci_ss_info_d84d_4055, + &pci_ss_info_d84d_4058, + &pci_ss_info_d84d_4065, + &pci_ss_info_d84d_4068, + &pci_ss_info_d84d_4078, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_dead[] = { + &pci_ss_info_dead_0800, + NULL +}; +#endif +#define pci_ss_list_e000 NULL +#define pci_ss_list_e159 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_e4bf[] = { + &pci_ss_info_e4bf_1000, + &pci_ss_info_e4bf_1010, + &pci_ss_info_e4bf_1020, + NULL +}; +#endif +#define pci_ss_list_ea01 NULL +#define pci_ss_list_ea60 NULL +#define pci_ss_list_eabb NULL +#define pci_ss_list_eace NULL +#define pci_ss_list_ec80 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_ecc0[] = { + &pci_ss_info_ecc0_0030, + NULL +}; +#endif +#define pci_ss_list_edd8 NULL +#define pci_ss_list_f1d0 NULL +#define pci_ss_list_fa57 NULL +#define pci_ss_list_febd NULL +#define pci_ss_list_feda NULL +#define pci_ss_list_fffe NULL +#define pci_ss_list_ffff NULL +#endif /* INIT_VENDOR_SUBSYS_INFO */ +#endif /* INIT_SUBSYS_INFO */ +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0675_1700 = { + 0x1700, pci_device_0675_1700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0675_1700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0675_1702 = { + 0x1702, pci_device_0675_1702, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0675_1702, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_09c1_0704 = { + 0x0704, pci_device_09c1_0704, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_09c1_0704, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_0e11_0001 = { + 0x0001, pci_device_0e11_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0002 = { + 0x0002, pci_device_0e11_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0049 = { + 0x0049, pci_device_0e11_0049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_004a = { + 0x004a, pci_device_0e11_004a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_004a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0508 = { + 0x0508, pci_device_0e11_0508, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0508, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_1000 = { + 0x1000, pci_device_0e11_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_2000 = { + 0x2000, pci_device_0e11_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_3032 = { + 0x3032, pci_device_0e11_3032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_3032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_3033 = { + 0x3033, pci_device_0e11_3033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_3033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_3034 = { + 0x3034, pci_device_0e11_3034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_3034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4000 = { + 0x4000, pci_device_0e11_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_6010 = { + 0x6010, pci_device_0e11_6010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_6010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_7020 = { + 0x7020, pci_device_0e11_7020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_7020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0ec = { + 0xa0ec, pci_device_0e11_a0ec, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0ec, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0f0 = { + 0xa0f0, pci_device_0e11_a0f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0f3 = { + 0xa0f3, pci_device_0e11_a0f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0f7 = { + 0xa0f7, pci_device_0e11_a0f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0f8 = { + 0xa0f8, pci_device_0e11_a0f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0fc = { + 0xa0fc, pci_device_0e11_a0fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae10 = { + 0xae10, pci_device_0e11_ae10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae29 = { + 0xae29, pci_device_0e11_ae29, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae29, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae2a = { + 0xae2a, pci_device_0e11_ae2a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae2a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae2b = { + 0xae2b, pci_device_0e11_ae2b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae2b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae31 = { + 0xae31, pci_device_0e11_ae31, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae31, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae32 = { + 0xae32, pci_device_0e11_ae32, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae32, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae33 = { + 0xae33, pci_device_0e11_ae33, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae33, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae34 = { + 0xae34, pci_device_0e11_ae34, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae34, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae35 = { + 0xae35, pci_device_0e11_ae35, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae35, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae40 = { + 0xae40, pci_device_0e11_ae40, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae40, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae43 = { + 0xae43, pci_device_0e11_ae43, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae43, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae69 = { + 0xae69, pci_device_0e11_ae69, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae69, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae6c = { + 0xae6c, pci_device_0e11_ae6c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae6c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae6d = { + 0xae6d, pci_device_0e11_ae6d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae6d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b011 = { + 0xb011, pci_device_0e11_b011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b012 = { + 0xb012, pci_device_0e11_b012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b01e = { + 0xb01e, pci_device_0e11_b01e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b01e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b01f = { + 0xb01f, pci_device_0e11_b01f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b01f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b02f = { + 0xb02f, pci_device_0e11_b02f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b02f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b030 = { + 0xb030, pci_device_0e11_b030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b04a = { + 0xb04a, pci_device_0e11_b04a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b04a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b060 = { + 0xb060, pci_device_0e11_b060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0c6 = { + 0xb0c6, pci_device_0e11_b0c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0c7 = { + 0xb0c7, pci_device_0e11_b0c7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0c7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0d7 = { + 0xb0d7, pci_device_0e11_b0d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0dd = { + 0xb0dd, pci_device_0e11_b0dd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0dd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0de = { + 0xb0de, pci_device_0e11_b0de, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0de, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0df = { + 0xb0df, pci_device_0e11_b0df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0e0 = { + 0xb0e0, pci_device_0e11_b0e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0e1 = { + 0xb0e1, pci_device_0e11_b0e1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0e1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b123 = { + 0xb123, pci_device_0e11_b123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b134 = { + 0xb134, pci_device_0e11_b134, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b134, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b13c = { + 0xb13c, pci_device_0e11_b13c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b13c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b144 = { + 0xb144, pci_device_0e11_b144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b163 = { + 0xb163, pci_device_0e11_b163, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b163, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b164 = { + 0xb164, pci_device_0e11_b164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b178 = { + 0xb178, pci_device_0e11_b178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b1a4 = { + 0xb1a4, pci_device_0e11_b1a4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b1a4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_f130 = { + 0xf130, pci_device_0e11_f130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_f130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_f150 = { + 0xf150, pci_device_0e11_f150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_f150, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1000_0001 = { + 0x0001, pci_device_1000_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0002 = { + 0x0002, pci_device_1000_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0003 = { + 0x0003, pci_device_1000_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0004 = { + 0x0004, pci_device_1000_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0005 = { + 0x0005, pci_device_1000_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0006 = { + 0x0006, pci_device_1000_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000a = { + 0x000a, pci_device_1000_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000b = { + 0x000b, pci_device_1000_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000c = { + 0x000c, pci_device_1000_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000d = { + 0x000d, pci_device_1000_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000f = { + 0x000f, pci_device_1000_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0010 = { + 0x0010, pci_device_1000_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0012 = { + 0x0012, pci_device_1000_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0013 = { + 0x0013, pci_device_1000_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0020 = { + 0x0020, pci_device_1000_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0021 = { + 0x0021, pci_device_1000_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0030 = { + 0x0030, pci_device_1000_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0040 = { + 0x0040, pci_device_1000_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_008f = { + 0x008f, pci_device_1000_008f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_008f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0621 = { + 0x0621, pci_device_1000_0621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0622 = { + 0x0622, pci_device_1000_0622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0623 = { + 0x0623, pci_device_1000_0623, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0623, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0624 = { + 0x0624, pci_device_1000_0624, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0624, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0625 = { + 0x0625, pci_device_1000_0625, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0625, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0626 = { + 0x0626, pci_device_1000_0626, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0626, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0627 = { + 0x0627, pci_device_1000_0627, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0627, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0628 = { + 0x0628, pci_device_1000_0628, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0628, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0629 = { + 0x0629, pci_device_1000_0629, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0629, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0701 = { + 0x0701, pci_device_1000_0701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0702 = { + 0x0702, pci_device_1000_0702, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0702, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0901 = { + 0x0901, pci_device_1000_0901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_1000 = { + 0x1000, pci_device_1000_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_1960 = { + 0x1960, pci_device_1000_1960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_1960, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1001_0010 = { + 0x0010, pci_device_1001_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0011 = { + 0x0011, pci_device_1001_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0012 = { + 0x0012, pci_device_1001_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0013 = { + 0x0013, pci_device_1001_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0014 = { + 0x0014, pci_device_1001_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0015 = { + 0x0015, pci_device_1001_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0016 = { + 0x0016, pci_device_1001_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0017 = { + 0x0017, pci_device_1001_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_9100 = { + 0x9100, pci_device_1001_9100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_9100, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1002_4144 = { + 0x4144, pci_device_1002_4144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4145 = { + 0x4145, pci_device_1002_4145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4146 = { + 0x4146, pci_device_1002_4146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4147 = { + 0x4147, pci_device_1002_4147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4158 = { + 0x4158, pci_device_1002_4158, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4158, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4242 = { + 0x4242, pci_device_1002_4242, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4242, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4336 = { + 0x4336, pci_device_1002_4336, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4336, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4337 = { + 0x4337, pci_device_1002_4337, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4337, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4354 = { + 0x4354, pci_device_1002_4354, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4354, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4358 = { + 0x4358, pci_device_1002_4358, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4358, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4554 = { + 0x4554, pci_device_1002_4554, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4554, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4654 = { + 0x4654, pci_device_1002_4654, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4654, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4742 = { + 0x4742, pci_device_1002_4742, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4742, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4744 = { + 0x4744, pci_device_1002_4744, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4744, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4747 = { + 0x4747, pci_device_1002_4747, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4747, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4749 = { + 0x4749, pci_device_1002_4749, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4749, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_474c = { + 0x474c, pci_device_1002_474c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_474c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_474d = { + 0x474d, pci_device_1002_474d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_474d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_474e = { + 0x474e, pci_device_1002_474e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_474e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_474f = { + 0x474f, pci_device_1002_474f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_474f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4750 = { + 0x4750, pci_device_1002_4750, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4750, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4751 = { + 0x4751, pci_device_1002_4751, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4751, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4752 = { + 0x4752, pci_device_1002_4752, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4752, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4753 = { + 0x4753, pci_device_1002_4753, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4753, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4754 = { + 0x4754, pci_device_1002_4754, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4754, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4755 = { + 0x4755, pci_device_1002_4755, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4755, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4756 = { + 0x4756, pci_device_1002_4756, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4756, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4757 = { + 0x4757, pci_device_1002_4757, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4757, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4758 = { + 0x4758, pci_device_1002_4758, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4758, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4759 = { + 0x4759, pci_device_1002_4759, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4759, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_475a = { + 0x475a, pci_device_1002_475a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_475a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4964 = { + 0x4964, pci_device_1002_4964, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4964, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4965 = { + 0x4965, pci_device_1002_4965, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4965, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4966 = { + 0x4966, pci_device_1002_4966, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4966, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4967 = { + 0x4967, pci_device_1002_4967, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4967, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_496e = { + 0x496e, pci_device_1002_496e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_496e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c42 = { + 0x4c42, pci_device_1002_4c42, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c42, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c44 = { + 0x4c44, pci_device_1002_4c44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c45 = { + 0x4c45, pci_device_1002_4c45, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c45, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c46 = { + 0x4c46, pci_device_1002_4c46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c47 = { + 0x4c47, pci_device_1002_4c47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c47, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c49 = { + 0x4c49, pci_device_1002_4c49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c4d = { + 0x4c4d, pci_device_1002_4c4d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c4d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c4e = { + 0x4c4e, pci_device_1002_4c4e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c4e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c50 = { + 0x4c50, pci_device_1002_4c50, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c50, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c51 = { + 0x4c51, pci_device_1002_4c51, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c51, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c52 = { + 0x4c52, pci_device_1002_4c52, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c52, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c53 = { + 0x4c53, pci_device_1002_4c53, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c53, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c54 = { + 0x4c54, pci_device_1002_4c54, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c54, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c57 = { + 0x4c57, pci_device_1002_4c57, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c57, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c58 = { + 0x4c58, pci_device_1002_4c58, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c58, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c59 = { + 0x4c59, pci_device_1002_4c59, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c59, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c5a = { + 0x4c5a, pci_device_1002_4c5a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c5a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c64 = { + 0x4c64, pci_device_1002_4c64, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c64, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c65 = { + 0x4c65, pci_device_1002_4c65, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c65, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c66 = { + 0x4c66, pci_device_1002_4c66, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c66, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c67 = { + 0x4c67, pci_device_1002_4c67, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c67, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4d46 = { + 0x4d46, pci_device_1002_4d46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4d46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4d4c = { + 0x4d4c, pci_device_1002_4d4c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4d4c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e44 = { + 0x4e44, pci_device_1002_4e44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e45 = { + 0x4e45, pci_device_1002_4e45, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e45, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e46 = { + 0x4e46, pci_device_1002_4e46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e47 = { + 0x4e47, pci_device_1002_4e47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e47, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e64 = { + 0x4e64, pci_device_1002_4e64, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e64, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e65 = { + 0x4e65, pci_device_1002_4e65, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e65, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e66 = { + 0x4e66, pci_device_1002_4e66, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e66, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e67 = { + 0x4e67, pci_device_1002_4e67, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e67, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5041 = { + 0x5041, pci_device_1002_5041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5042 = { + 0x5042, pci_device_1002_5042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5043 = { + 0x5043, pci_device_1002_5043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5044 = { + 0x5044, pci_device_1002_5044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5045 = { + 0x5045, pci_device_1002_5045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5046 = { + 0x5046, pci_device_1002_5046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5047 = { + 0x5047, pci_device_1002_5047, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5047, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5048 = { + 0x5048, pci_device_1002_5048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5049 = { + 0x5049, pci_device_1002_5049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504a = { + 0x504a, pci_device_1002_504a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504b = { + 0x504b, pci_device_1002_504b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504c = { + 0x504c, pci_device_1002_504c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504d = { + 0x504d, pci_device_1002_504d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504e = { + 0x504e, pci_device_1002_504e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504f = { + 0x504f, pci_device_1002_504f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5050 = { + 0x5050, pci_device_1002_5050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5051 = { + 0x5051, pci_device_1002_5051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5052 = { + 0x5052, pci_device_1002_5052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5053 = { + 0x5053, pci_device_1002_5053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5054 = { + 0x5054, pci_device_1002_5054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5055 = { + 0x5055, pci_device_1002_5055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5056 = { + 0x5056, pci_device_1002_5056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5057 = { + 0x5057, pci_device_1002_5057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5058 = { + 0x5058, pci_device_1002_5058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5144 = { + 0x5144, pci_device_1002_5144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5145 = { + 0x5145, pci_device_1002_5145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5146 = { + 0x5146, pci_device_1002_5146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5147 = { + 0x5147, pci_device_1002_5147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5148 = { + 0x5148, pci_device_1002_5148, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5148, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5149 = { + 0x5149, pci_device_1002_5149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514a = { + 0x514a, pci_device_1002_514a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514b = { + 0x514b, pci_device_1002_514b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514c = { + 0x514c, pci_device_1002_514c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514d = { + 0x514d, pci_device_1002_514d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514e = { + 0x514e, pci_device_1002_514e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514f = { + 0x514f, pci_device_1002_514f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5157 = { + 0x5157, pci_device_1002_5157, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5157, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5158 = { + 0x5158, pci_device_1002_5158, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5158, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5159 = { + 0x5159, pci_device_1002_5159, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5159, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_515a = { + 0x515a, pci_device_1002_515a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_515a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5168 = { + 0x5168, pci_device_1002_5168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5169 = { + 0x5169, pci_device_1002_5169, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5169, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_516a = { + 0x516a, pci_device_1002_516a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_516a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_516b = { + 0x516b, pci_device_1002_516b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_516b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_516c = { + 0x516c, pci_device_1002_516c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_516c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5245 = { + 0x5245, pci_device_1002_5245, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5245, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5246 = { + 0x5246, pci_device_1002_5246, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5246, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5247 = { + 0x5247, pci_device_1002_5247, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5247, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_524b = { + 0x524b, pci_device_1002_524b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_524b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_524c = { + 0x524c, pci_device_1002_524c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_524c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5345 = { + 0x5345, pci_device_1002_5345, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5345, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5346 = { + 0x5346, pci_device_1002_5346, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5346, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5347 = { + 0x5347, pci_device_1002_5347, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5347, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5348 = { + 0x5348, pci_device_1002_5348, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5348, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_534b = { + 0x534b, pci_device_1002_534b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_534b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_534c = { + 0x534c, pci_device_1002_534c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_534c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_534d = { + 0x534d, pci_device_1002_534d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_534d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_534e = { + 0x534e, pci_device_1002_534e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_534e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5354 = { + 0x5354, pci_device_1002_5354, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5354, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5446 = { + 0x5446, pci_device_1002_5446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_544c = { + 0x544c, pci_device_1002_544c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_544c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5452 = { + 0x5452, pci_device_1002_5452, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5452, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5453 = { + 0x5453, pci_device_1002_5453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5454 = { + 0x5454, pci_device_1002_5454, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5454, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5455 = { + 0x5455, pci_device_1002_5455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5654 = { + 0x5654, pci_device_1002_5654, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5654, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5655 = { + 0x5655, pci_device_1002_5655, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5655, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5656 = { + 0x5656, pci_device_1002_5656, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5656, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_700f = { + 0x700f, pci_device_1002_700f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_700f, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1003_0201 = { + 0x0201, pci_device_1003_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1003_0201, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1004_0005 = { + 0x0005, pci_device_1004_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0006 = { + 0x0006, pci_device_1004_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0007 = { + 0x0007, pci_device_1004_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0008 = { + 0x0008, pci_device_1004_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0009 = { + 0x0009, pci_device_1004_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_000c = { + 0x000c, pci_device_1004_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_000d = { + 0x000d, pci_device_1004_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0101 = { + 0x0101, pci_device_1004_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0102 = { + 0x0102, pci_device_1004_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0103 = { + 0x0103, pci_device_1004_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0104 = { + 0x0104, pci_device_1004_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0105 = { + 0x0105, pci_device_1004_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0200 = { + 0x0200, pci_device_1004_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0280 = { + 0x0280, pci_device_1004_0280, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0280, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0304 = { + 0x0304, pci_device_1004_0304, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0304, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0305 = { + 0x0305, pci_device_1004_0305, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0305, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0306 = { + 0x0306, pci_device_1004_0306, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0306, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0307 = { + 0x0307, pci_device_1004_0307, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0307, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0308 = { + 0x0308, pci_device_1004_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0702 = { + 0x0702, pci_device_1004_0702, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0702, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0703 = { + 0x0703, pci_device_1004_0703, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0703, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1005_2064 = { + 0x2064, pci_device_1005_2064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2128 = { + 0x2128, pci_device_1005_2128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2128, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2301 = { + 0x2301, pci_device_1005_2301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2302 = { + 0x2302, pci_device_1005_2302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2364 = { + 0x2364, pci_device_1005_2364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2464 = { + 0x2464, pci_device_1005_2464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2501 = { + 0x2501, pci_device_1005_2501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0001 = { + 0x0001, pci_device_100b_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0002 = { + 0x0002, pci_device_100b_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_000e = { + 0x000e, pci_device_100b_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_000e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_000f = { + 0x000f, pci_device_100b_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0011 = { + 0x0011, pci_device_100b_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0012 = { + 0x0012, pci_device_100b_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0020 = { + 0x0020, pci_device_100b_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0022 = { + 0x0022, pci_device_100b_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0500 = { + 0x0500, pci_device_100b_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0501 = { + 0x0501, pci_device_100b_0501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0502 = { + 0x0502, pci_device_100b_0502, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0502, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0503 = { + 0x0503, pci_device_100b_0503, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0503, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0504 = { + 0x0504, pci_device_100b_0504, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0504, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0505 = { + 0x0505, pci_device_100b_0505, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0505, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_d001 = { + 0xd001, pci_device_100b_d001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_d001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3202 = { + 0x3202, pci_device_100c_3202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3205 = { + 0x3205, pci_device_100c_3205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3206 = { + 0x3206, pci_device_100c_3206, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3206, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3207 = { + 0x3207, pci_device_100c_3207, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3207, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3208 = { + 0x3208, pci_device_100c_3208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_4702 = { + 0x4702, pci_device_100c_4702, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_4702, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100e_9000 = { + 0x9000, pci_device_100e_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100e_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100e_9001 = { + 0x9001, pci_device_100e_9001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100e_9001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100e_9002 = { + 0x9002, pci_device_100e_9002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100e_9002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100e_9100 = { + 0x9100, pci_device_100e_9100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100e_9100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0001 = { + 0x0001, pci_device_1011_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0002 = { + 0x0002, pci_device_1011_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0004 = { + 0x0004, pci_device_1011_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0007 = { + 0x0007, pci_device_1011_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0008 = { + 0x0008, pci_device_1011_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0009 = { + 0x0009, pci_device_1011_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_000a = { + 0x000a, pci_device_1011_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_000d = { + 0x000d, pci_device_1011_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_000f = { + 0x000f, pci_device_1011_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0014 = { + 0x0014, pci_device_1011_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0016 = { + 0x0016, pci_device_1011_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0019 = { + 0x0019, pci_device_1011_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_001a = { + 0x001a, pci_device_1011_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0021 = { + 0x0021, pci_device_1011_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0022 = { + 0x0022, pci_device_1011_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0023 = { + 0x0023, pci_device_1011_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0024 = { + 0x0024, pci_device_1011_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0025 = { + 0x0025, pci_device_1011_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0026 = { + 0x0026, pci_device_1011_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0034 = { + 0x0034, pci_device_1011_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0045 = { + 0x0045, pci_device_1011_0045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0046 = { + 0x0046, pci_device_1011_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_1065 = { + 0x1065, pci_device_1011_1065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_1065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_0038 = { + 0x0038, pci_device_1013_0038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_0038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_0040 = { + 0x0040, pci_device_1013_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_004c = { + 0x004c, pci_device_1013_004c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_004c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00a0 = { + 0x00a0, pci_device_1013_00a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00a2 = { + 0x00a2, pci_device_1013_00a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00a4 = { + 0x00a4, pci_device_1013_00a4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00a4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00a8 = { + 0x00a8, pci_device_1013_00a8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00a8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00ac = { + 0x00ac, pci_device_1013_00ac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00ac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00b0 = { + 0x00b0, pci_device_1013_00b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00b8 = { + 0x00b8, pci_device_1013_00b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00bc = { + 0x00bc, pci_device_1013_00bc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00bc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d0 = { + 0x00d0, pci_device_1013_00d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d2 = { + 0x00d2, pci_device_1013_00d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d4 = { + 0x00d4, pci_device_1013_00d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d5 = { + 0x00d5, pci_device_1013_00d5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d6 = { + 0x00d6, pci_device_1013_00d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00e8 = { + 0x00e8, pci_device_1013_00e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1100 = { + 0x1100, pci_device_1013_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1110 = { + 0x1110, pci_device_1013_1110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1112 = { + 0x1112, pci_device_1013_1112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1113 = { + 0x1113, pci_device_1013_1113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1200 = { + 0x1200, pci_device_1013_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1202 = { + 0x1202, pci_device_1013_1202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1204 = { + 0x1204, pci_device_1013_1204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_4400 = { + 0x4400, pci_device_1013_4400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_4400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_6001 = { + 0x6001, pci_device_1013_6001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_6001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_6003 = { + 0x6003, pci_device_1013_6003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_6003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_6004 = { + 0x6004, pci_device_1013_6004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_6004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_6005 = { + 0x6005, pci_device_1013_6005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_6005, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1014_0002 = { + 0x0002, pci_device_1014_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0005 = { + 0x0005, pci_device_1014_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0007 = { + 0x0007, pci_device_1014_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_000a = { + 0x000a, pci_device_1014_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0017 = { + 0x0017, pci_device_1014_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0018 = { + 0x0018, pci_device_1014_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_001b = { + 0x001b, pci_device_1014_001b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_001b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_001c = { + 0x001c, pci_device_1014_001c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_001c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_001d = { + 0x001d, pci_device_1014_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0020 = { + 0x0020, pci_device_1014_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0022 = { + 0x0022, pci_device_1014_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_002d = { + 0x002d, pci_device_1014_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_002e = { + 0x002e, pci_device_1014_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0036 = { + 0x0036, pci_device_1014_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_003a = { + 0x003a, pci_device_1014_003a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_003a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_003e = { + 0x003e, pci_device_1014_003e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_003e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0045 = { + 0x0045, pci_device_1014_0045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0046 = { + 0x0046, pci_device_1014_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0047 = { + 0x0047, pci_device_1014_0047, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0047, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0048 = { + 0x0048, pci_device_1014_0048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0049 = { + 0x0049, pci_device_1014_0049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_004e = { + 0x004e, pci_device_1014_004e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_004e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_004f = { + 0x004f, pci_device_1014_004f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_004f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0050 = { + 0x0050, pci_device_1014_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0053 = { + 0x0053, pci_device_1014_0053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0057 = { + 0x0057, pci_device_1014_0057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_005c = { + 0x005c, pci_device_1014_005c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_005c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_007c = { + 0x007c, pci_device_1014_007c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_007c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_007d = { + 0x007d, pci_device_1014_007d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_007d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0090 = { + 0x0090, pci_device_1014_0090, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0090, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0095 = { + 0x0095, pci_device_1014_0095, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0095, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0096 = { + 0x0096, pci_device_1014_0096, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0096, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00a5 = { + 0x00a5, pci_device_1014_00a5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00a5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00a6 = { + 0x00a6, pci_device_1014_00a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00b7 = { + 0x00b7, pci_device_1014_00b7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00b7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00be = { + 0x00be, pci_device_1014_00be, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00be, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00dc = { + 0x00dc, pci_device_1014_00dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00fc = { + 0x00fc, pci_device_1014_00fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0105 = { + 0x0105, pci_device_1014_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_010f = { + 0x010f, pci_device_1014_010f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_010f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0142 = { + 0x0142, pci_device_1014_0142, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0142, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0144 = { + 0x0144, pci_device_1014_0144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0156 = { + 0x0156, pci_device_1014_0156, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0156, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_01a7 = { + 0x01a7, pci_device_1014_01a7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_01a7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_01bd = { + 0x01bd, pci_device_1014_01bd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_01bd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0302 = { + 0x0302, pci_device_1014_0302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_ffff = { + 0xffff, pci_device_1014_ffff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_ffff, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1017_5343 = { + 0x5343, pci_device_1017_5343, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1017_5343, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_101a_0005 = { + 0x0005, pci_device_101a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101a_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_101c_0193 = { + 0x0193, pci_device_101c_0193, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_0193, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_0196 = { + 0x0196, pci_device_101c_0196, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_0196, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_0197 = { + 0x0197, pci_device_101c_0197, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_0197, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_0296 = { + 0x0296, pci_device_101c_0296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_0296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_3193 = { + 0x3193, pci_device_101c_3193, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_3193, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_3197 = { + 0x3197, pci_device_101c_3197, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_3197, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_3296 = { + 0x3296, pci_device_101c_3296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_3296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_4296 = { + 0x4296, pci_device_101c_4296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_4296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_9710 = { + 0x9710, pci_device_101c_9710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_9710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_9712 = { + 0x9712, pci_device_101c_9712, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_9712, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_c24a = { + 0xc24a, pci_device_101c_c24a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_c24a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_101e_1960 = { + 0x1960, pci_device_101e_1960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_1960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9010 = { + 0x9010, pci_device_101e_9010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9030 = { + 0x9030, pci_device_101e_9030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9031 = { + 0x9031, pci_device_101e_9031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9032 = { + 0x9032, pci_device_101e_9032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9033 = { + 0x9033, pci_device_101e_9033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9040 = { + 0x9040, pci_device_101e_9040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9060 = { + 0x9060, pci_device_101e_9060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9063 = { + 0x9063, pci_device_101e_9063, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9063, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1022_1100 = { + 0x1100, pci_device_1022_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_1101 = { + 0x1101, pci_device_1022_1101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_1101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_1102 = { + 0x1102, pci_device_1022_1102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_1102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_1103 = { + 0x1103, pci_device_1022_1103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_1103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2000 = { + 0x2000, pci_device_1022_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2001 = { + 0x2001, pci_device_1022_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2020 = { + 0x2020, pci_device_1022_2020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2040 = { + 0x2040, pci_device_1022_2040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_3000 = { + 0x3000, pci_device_1022_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_3000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7006 = { + 0x7006, pci_device_1022_7006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7007 = { + 0x7007, pci_device_1022_7007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700c = { + 0x700c, pci_device_1022_700c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700d = { + 0x700d, pci_device_1022_700d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700e = { + 0x700e, pci_device_1022_700e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700f = { + 0x700f, pci_device_1022_700f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7400 = { + 0x7400, pci_device_1022_7400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7401 = { + 0x7401, pci_device_1022_7401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7403 = { + 0x7403, pci_device_1022_7403, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7403, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7404 = { + 0x7404, pci_device_1022_7404, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7404, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7408 = { + 0x7408, pci_device_1022_7408, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7408, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7409 = { + 0x7409, pci_device_1022_7409, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7409, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_740b = { + 0x740b, pci_device_1022_740b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_740b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_740c = { + 0x740c, pci_device_1022_740c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_740c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7410 = { + 0x7410, pci_device_1022_7410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7411 = { + 0x7411, pci_device_1022_7411, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7411, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7413 = { + 0x7413, pci_device_1022_7413, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7413, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7414 = { + 0x7414, pci_device_1022_7414, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7414, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7440 = { + 0x7440, pci_device_1022_7440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7441 = { + 0x7441, pci_device_1022_7441, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7441, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7443 = { + 0x7443, pci_device_1022_7443, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7443, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7445 = { + 0x7445, pci_device_1022_7445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7446 = { + 0x7446, pci_device_1022_7446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7448 = { + 0x7448, pci_device_1022_7448, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7448, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7449 = { + 0x7449, pci_device_1022_7449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7450 = { + 0x7450, pci_device_1022_7450, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7450, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7451 = { + 0x7451, pci_device_1022_7451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7454 = { + 0x7454, pci_device_1022_7454, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7454, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7455 = { + 0x7455, pci_device_1022_7455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7460 = { + 0x7460, pci_device_1022_7460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7461 = { + 0x7461, pci_device_1022_7461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7462 = { + 0x7462, pci_device_1022_7462, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7462, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7464 = { + 0x7464, pci_device_1022_7464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7468 = { + 0x7468, pci_device_1022_7468, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7468, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7469 = { + 0x7469, pci_device_1022_7469, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7469, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_746a = { + 0x746a, pci_device_1022_746a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_746a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_746b = { + 0x746b, pci_device_1022_746b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_746b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_746d = { + 0x746d, pci_device_1022_746d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_746d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_746e = { + 0x746e, pci_device_1022_746e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_746e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_0194 = { + 0x0194, pci_device_1023_0194, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_0194, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_2000 = { + 0x2000, pci_device_1023_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_2001 = { + 0x2001, pci_device_1023_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_2001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8400 = { + 0x8400, pci_device_1023_8400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8420 = { + 0x8420, pci_device_1023_8420, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8420, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8500 = { + 0x8500, pci_device_1023_8500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8520 = { + 0x8520, pci_device_1023_8520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8620 = { + 0x8620, pci_device_1023_8620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8820 = { + 0x8820, pci_device_1023_8820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8820, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9320 = { + 0x9320, pci_device_1023_9320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9350 = { + 0x9350, pci_device_1023_9350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9360 = { + 0x9360, pci_device_1023_9360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9382 = { + 0x9382, pci_device_1023_9382, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9382, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9383 = { + 0x9383, pci_device_1023_9383, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9383, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9385 = { + 0x9385, pci_device_1023_9385, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9385, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9386 = { + 0x9386, pci_device_1023_9386, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9386, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9388 = { + 0x9388, pci_device_1023_9388, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9388, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9397 = { + 0x9397, pci_device_1023_9397, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9397, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_939a = { + 0x939a, pci_device_1023_939a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_939a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9420 = { + 0x9420, pci_device_1023_9420, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9420, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9430 = { + 0x9430, pci_device_1023_9430, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9430, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9440 = { + 0x9440, pci_device_1023_9440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9460 = { + 0x9460, pci_device_1023_9460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9470 = { + 0x9470, pci_device_1023_9470, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9470, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9520 = { + 0x9520, pci_device_1023_9520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9525 = { + 0x9525, pci_device_1023_9525, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9525, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9540 = { + 0x9540, pci_device_1023_9540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9660 = { + 0x9660, pci_device_1023_9660, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9660, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9680 = { + 0x9680, pci_device_1023_9680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9682 = { + 0x9682, pci_device_1023_9682, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9682, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9683 = { + 0x9683, pci_device_1023_9683, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9683, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9685 = { + 0x9685, pci_device_1023_9685, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9685, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9750 = { + 0x9750, pci_device_1023_9750, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9750, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9753 = { + 0x9753, pci_device_1023_9753, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9753, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9754 = { + 0x9754, pci_device_1023_9754, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9754, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9759 = { + 0x9759, pci_device_1023_9759, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9759, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9783 = { + 0x9783, pci_device_1023_9783, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9783, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9785 = { + 0x9785, pci_device_1023_9785, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9785, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9850 = { + 0x9850, pci_device_1023_9850, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9850, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9880 = { + 0x9880, pci_device_1023_9880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9910 = { + 0x9910, pci_device_1023_9910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9910, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9930 = { + 0x9930, pci_device_1023_9930, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9930, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1435 = { + 0x1435, pci_device_1025_1435, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1435, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1445 = { + 0x1445, pci_device_1025_1445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1449 = { + 0x1449, pci_device_1025_1449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1451 = { + 0x1451, pci_device_1025_1451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1461 = { + 0x1461, pci_device_1025_1461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1489 = { + 0x1489, pci_device_1025_1489, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1489, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1511 = { + 0x1511, pci_device_1025_1511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1512 = { + 0x1512, pci_device_1025_1512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1512, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1513 = { + 0x1513, pci_device_1025_1513, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1513, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1521 = { + 0x1521, pci_device_1025_1521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1523 = { + 0x1523, pci_device_1025_1523, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1523, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1531 = { + 0x1531, pci_device_1025_1531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1533 = { + 0x1533, pci_device_1025_1533, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1533, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1535 = { + 0x1535, pci_device_1025_1535, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1535, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1541 = { + 0x1541, pci_device_1025_1541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1542 = { + 0x1542, pci_device_1025_1542, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1542, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1543 = { + 0x1543, pci_device_1025_1543, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1543, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1561 = { + 0x1561, pci_device_1025_1561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1621 = { + 0x1621, pci_device_1025_1621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1631 = { + 0x1631, pci_device_1025_1631, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1631, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1641 = { + 0x1641, pci_device_1025_1641, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1641, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1647 = { + 0x1647, pci_device_1025_1647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3141 = { + 0x3141, pci_device_1025_3141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3141, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3143 = { + 0x3143, pci_device_1025_3143, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3143, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3145 = { + 0x3145, pci_device_1025_3145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3147 = { + 0x3147, pci_device_1025_3147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3149 = { + 0x3149, pci_device_1025_3149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3151 = { + 0x3151, pci_device_1025_3151, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3151, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3307 = { + 0x3307, pci_device_1025_3307, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3307, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3309 = { + 0x3309, pci_device_1025_3309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3321 = { + 0x3321, pci_device_1025_3321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5212 = { + 0x5212, pci_device_1025_5212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5215 = { + 0x5215, pci_device_1025_5215, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5215, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5217 = { + 0x5217, pci_device_1025_5217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5219 = { + 0x5219, pci_device_1025_5219, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5219, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5225 = { + 0x5225, pci_device_1025_5225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5229 = { + 0x5229, pci_device_1025_5229, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5229, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5235 = { + 0x5235, pci_device_1025_5235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5237 = { + 0x5237, pci_device_1025_5237, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5237, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5240 = { + 0x5240, pci_device_1025_5240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5241 = { + 0x5241, pci_device_1025_5241, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5241, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5242 = { + 0x5242, pci_device_1025_5242, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5242, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5243 = { + 0x5243, pci_device_1025_5243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5243, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5244 = { + 0x5244, pci_device_1025_5244, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5244, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5247 = { + 0x5247, pci_device_1025_5247, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5247, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5251 = { + 0x5251, pci_device_1025_5251, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5251, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5427 = { + 0x5427, pci_device_1025_5427, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5427, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5451 = { + 0x5451, pci_device_1025_5451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5453 = { + 0x5453, pci_device_1025_5453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_7101 = { + 0x7101, pci_device_1025_7101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_7101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0001 = { + 0x0001, pci_device_1028_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0002 = { + 0x0002, pci_device_1028_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0003 = { + 0x0003, pci_device_1028_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0004 = { + 0x0004, pci_device_1028_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0005 = { + 0x0005, pci_device_1028_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0006 = { + 0x0006, pci_device_1028_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0007 = { + 0x0007, pci_device_1028_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0008 = { + 0x0008, pci_device_1028_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000a = { + 0x000a, pci_device_1028_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000c = { + 0x000c, pci_device_1028_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000e = { + 0x000e, pci_device_1028_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000f = { + 0x000f, pci_device_1028_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000f, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_102a_0000 = { + 0x0000, pci_device_102a_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102a_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102a_0010 = { + 0x0010, pci_device_102a_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102a_0010, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_102b_0010 = { + 0x0010, pci_device_102b_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0518 = { + 0x0518, pci_device_102b_0518, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0518, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0519 = { + 0x0519, pci_device_102b_0519, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0519, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_051a = { + 0x051a, pci_device_102b_051a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_051a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_051b = { + 0x051b, pci_device_102b_051b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_051b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_051e = { + 0x051e, pci_device_102b_051e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_051e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_051f = { + 0x051f, pci_device_102b_051f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_051f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0520 = { + 0x0520, pci_device_102b_0520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0521 = { + 0x0521, pci_device_102b_0521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0525 = { + 0x0525, pci_device_102b_0525, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0525, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0527 = { + 0x0527, pci_device_102b_0527, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0527, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0d10 = { + 0x0d10, pci_device_102b_0d10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0d10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_1000 = { + 0x1000, pci_device_102b_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_1001 = { + 0x1001, pci_device_102b_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_2007 = { + 0x2007, pci_device_102b_2007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_2007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_2527 = { + 0x2527, pci_device_102b_2527, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_2527, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_4536 = { + 0x4536, pci_device_102b_4536, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_4536, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_6573 = { + 0x6573, pci_device_102b_6573, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_6573, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00b8 = { + 0x00b8, pci_device_102c_00b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00c0 = { + 0x00c0, pci_device_102c_00c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00d0 = { + 0x00d0, pci_device_102c_00d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00d8 = { + 0x00d8, pci_device_102c_00d8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00d8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00dc = { + 0x00dc, pci_device_102c_00dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00e0 = { + 0x00e0, pci_device_102c_00e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00e4 = { + 0x00e4, pci_device_102c_00e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00e5 = { + 0x00e5, pci_device_102c_00e5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00e5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00f0 = { + 0x00f0, pci_device_102c_00f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00f4 = { + 0x00f4, pci_device_102c_00f4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00f4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00f5 = { + 0x00f5, pci_device_102c_00f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_0c30 = { + 0x0c30, pci_device_102c_0c30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_0c30, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_102d_50dc = { + 0x50dc, pci_device_102d_50dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102d_50dc, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_102f_0009 = { + 0x0009, pci_device_102f_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0020 = { + 0x0020, pci_device_102f_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0020, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1031_5601 = { + 0x5601, pci_device_1031_5601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1031_5601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1031_5607 = { + 0x5607, pci_device_1031_5607, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1031_5607, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1031_5631 = { + 0x5631, pci_device_1031_5631, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1031_5631, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1031_6057 = { + 0x6057, pci_device_1031_6057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1031_6057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0001 = { + 0x0001, pci_device_1033_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0002 = { + 0x0002, pci_device_1033_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0003 = { + 0x0003, pci_device_1033_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0004 = { + 0x0004, pci_device_1033_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0005 = { + 0x0005, pci_device_1033_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0006 = { + 0x0006, pci_device_1033_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0007 = { + 0x0007, pci_device_1033_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0008 = { + 0x0008, pci_device_1033_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0009 = { + 0x0009, pci_device_1033_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0016 = { + 0x0016, pci_device_1033_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_001a = { + 0x001a, pci_device_1033_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0021 = { + 0x0021, pci_device_1033_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0029 = { + 0x0029, pci_device_1033_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_002a = { + 0x002a, pci_device_1033_002a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_002a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_002c = { + 0x002c, pci_device_1033_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_002d = { + 0x002d, pci_device_1033_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0035 = { + 0x0035, pci_device_1033_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_003b = { + 0x003b, pci_device_1033_003b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_003b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_003e = { + 0x003e, pci_device_1033_003e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_003e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0046 = { + 0x0046, pci_device_1033_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_005a = { + 0x005a, pci_device_1033_005a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_005a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0063 = { + 0x0063, pci_device_1033_0063, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0063, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0067 = { + 0x0067, pci_device_1033_0067, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0067, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0074 = { + 0x0074, pci_device_1033_0074, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0074, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_009b = { + 0x009b, pci_device_1033_009b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_009b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00a6 = { + 0x00a6, pci_device_1033_00a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00cd = { + 0x00cd, pci_device_1033_00cd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00cd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00e0 = { + 0x00e0, pci_device_1033_00e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00e0, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1036_0000 = { + 0x0000, pci_device_1036_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1036_0000, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1039_0001 = { + 0x0001, pci_device_1039_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0002 = { + 0x0002, pci_device_1039_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0006 = { + 0x0006, pci_device_1039_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0008 = { + 0x0008, pci_device_1039_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0009 = { + 0x0009, pci_device_1039_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0018 = { + 0x0018, pci_device_1039_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0200 = { + 0x0200, pci_device_1039_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0204 = { + 0x0204, pci_device_1039_0204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0205 = { + 0x0205, pci_device_1039_0205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0300 = { + 0x0300, pci_device_1039_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0310 = { + 0x0310, pci_device_1039_0310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0315 = { + 0x0315, pci_device_1039_0315, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0315, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0325 = { + 0x0325, pci_device_1039_0325, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0325, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0330 = { + 0x0330, pci_device_1039_0330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0406 = { + 0x0406, pci_device_1039_0406, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0406, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0496 = { + 0x0496, pci_device_1039_0496, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0496, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0530 = { + 0x0530, pci_device_1039_0530, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0530, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0540 = { + 0x0540, pci_device_1039_0540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0597 = { + 0x0597, pci_device_1039_0597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0601 = { + 0x0601, pci_device_1039_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0620 = { + 0x0620, pci_device_1039_0620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0630 = { + 0x0630, pci_device_1039_0630, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0630, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0633 = { + 0x0633, pci_device_1039_0633, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0633, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0635 = { + 0x0635, pci_device_1039_0635, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0635, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0645 = { + 0x0645, pci_device_1039_0645, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0645, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0646 = { + 0x0646, pci_device_1039_0646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0650 = { + 0x0650, pci_device_1039_0650, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0650, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0651 = { + 0x0651, pci_device_1039_0651, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0651, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0730 = { + 0x0730, pci_device_1039_0730, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0730, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0733 = { + 0x0733, pci_device_1039_0733, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0733, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0735 = { + 0x0735, pci_device_1039_0735, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0735, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0740 = { + 0x0740, pci_device_1039_0740, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0740, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0745 = { + 0x0745, pci_device_1039_0745, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0745, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0900 = { + 0x0900, pci_device_1039_0900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0961 = { + 0x0961, pci_device_1039_0961, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0961, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0962 = { + 0x0962, pci_device_1039_0962, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0962, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_3602 = { + 0x3602, pci_device_1039_3602, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_3602, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5107 = { + 0x5107, pci_device_1039_5107, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5107, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5300 = { + 0x5300, pci_device_1039_5300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5315 = { + 0x5315, pci_device_1039_5315, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5315, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5401 = { + 0x5401, pci_device_1039_5401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5511 = { + 0x5511, pci_device_1039_5511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5513 = { + 0x5513, pci_device_1039_5513, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5513, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5517 = { + 0x5517, pci_device_1039_5517, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5517, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5571 = { + 0x5571, pci_device_1039_5571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5581 = { + 0x5581, pci_device_1039_5581, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5581, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5582 = { + 0x5582, pci_device_1039_5582, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5582, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5591 = { + 0x5591, pci_device_1039_5591, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5591, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5596 = { + 0x5596, pci_device_1039_5596, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5596, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5597 = { + 0x5597, pci_device_1039_5597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5600 = { + 0x5600, pci_device_1039_5600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6204 = { + 0x6204, pci_device_1039_6204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6205 = { + 0x6205, pci_device_1039_6205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6236 = { + 0x6236, pci_device_1039_6236, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6236, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6300 = { + 0x6300, pci_device_1039_6300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6306 = { + 0x6306, pci_device_1039_6306, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6306, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6325 = { + 0x6325, pci_device_1039_6325, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6325, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6326 = { + 0x6326, pci_device_1039_6326, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6326, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7001 = { + 0x7001, pci_device_1039_7001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7002 = { + 0x7002, pci_device_1039_7002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7007 = { + 0x7007, pci_device_1039_7007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7012 = { + 0x7012, pci_device_1039_7012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7013 = { + 0x7013, pci_device_1039_7013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7016 = { + 0x7016, pci_device_1039_7016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7018 = { + 0x7018, pci_device_1039_7018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1005 = { + 0x1005, pci_device_103c_1005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1006 = { + 0x1006, pci_device_103c_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1008 = { + 0x1008, pci_device_103c_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_100a = { + 0x100a, pci_device_103c_100a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_100a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1028 = { + 0x1028, pci_device_103c_1028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1029 = { + 0x1029, pci_device_103c_1029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_102a = { + 0x102a, pci_device_103c_102a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_102a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1030 = { + 0x1030, pci_device_103c_1030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1031 = { + 0x1031, pci_device_103c_1031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1040 = { + 0x1040, pci_device_103c_1040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1041 = { + 0x1041, pci_device_103c_1041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1042 = { + 0x1042, pci_device_103c_1042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1048 = { + 0x1048, pci_device_103c_1048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1064 = { + 0x1064, pci_device_103c_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_108b = { + 0x108b, pci_device_103c_108b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_108b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_10c1 = { + 0x10c1, pci_device_103c_10c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_10c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_10ed = { + 0x10ed, pci_device_103c_10ed, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_10ed, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1200 = { + 0x1200, pci_device_103c_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1219 = { + 0x1219, pci_device_103c_1219, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1219, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_121a = { + 0x121a, pci_device_103c_121a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_121a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_121b = { + 0x121b, pci_device_103c_121b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_121b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_121c = { + 0x121c, pci_device_103c_121c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_121c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1229 = { + 0x1229, pci_device_103c_1229, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1229, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_122a = { + 0x122a, pci_device_103c_122a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_122a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_122e = { + 0x122e, pci_device_103c_122e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_122e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1290 = { + 0x1290, pci_device_103c_1290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_2910 = { + 0x2910, pci_device_103c_2910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_2910, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_2925 = { + 0x2925, pci_device_103c_2925, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_2925, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1042_1000 = { + 0x1000, pci_device_1042_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1042_1001 = { + 0x1001, pci_device_1042_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1042_3000 = { + 0x3000, pci_device_1042_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_3000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1042_3010 = { + 0x3010, pci_device_1042_3010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_3010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1042_3020 = { + 0x3020, pci_device_1042_3020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_3020, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1043_0675 = { + 0x0675, pci_device_1043_0675, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_0675, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_4021 = { + 0x4021, pci_device_1043_4021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_4021, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1044_1012 = { + 0x1012, pci_device_1044_1012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_1012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1044_a400 = { + 0xa400, pci_device_1044_a400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_a400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1044_a500 = { + 0xa500, pci_device_1044_a500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_a500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1044_a501 = { + 0xa501, pci_device_1044_a501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_a501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1044_a511 = { + 0xa511, pci_device_1044_a511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_a511, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1045_a0f8 = { + 0xa0f8, pci_device_1045_a0f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_a0f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c101 = { + 0xc101, pci_device_1045_c101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c178 = { + 0xc178, pci_device_1045_c178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c556 = { + 0xc556, pci_device_1045_c556, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c556, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c557 = { + 0xc557, pci_device_1045_c557, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c557, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c558 = { + 0xc558, pci_device_1045_c558, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c558, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c567 = { + 0xc567, pci_device_1045_c567, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c567, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c568 = { + 0xc568, pci_device_1045_c568, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c568, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c569 = { + 0xc569, pci_device_1045_c569, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c569, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c621 = { + 0xc621, pci_device_1045_c621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c700 = { + 0xc700, pci_device_1045_c700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c701 = { + 0xc701, pci_device_1045_c701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c814 = { + 0xc814, pci_device_1045_c814, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c814, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c822 = { + 0xc822, pci_device_1045_c822, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c822, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c824 = { + 0xc824, pci_device_1045_c824, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c824, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c825 = { + 0xc825, pci_device_1045_c825, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c825, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c832 = { + 0xc832, pci_device_1045_c832, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c832, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c861 = { + 0xc861, pci_device_1045_c861, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c861, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c895 = { + 0xc895, pci_device_1045_c895, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c895, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c935 = { + 0xc935, pci_device_1045_c935, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c935, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_d568 = { + 0xd568, pci_device_1045_d568, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_d568, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_d721 = { + 0xd721, pci_device_1045_d721, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_d721, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1048_0d22 = { + 0x0d22, pci_device_1048_0d22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_0d22, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1048_1000 = { + 0x1000, pci_device_1048_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1048_3000 = { + 0x3000, pci_device_1048_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_3000, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_104a_0008 = { + 0x0008, pci_device_104a_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0009 = { + 0x0009, pci_device_104a_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0010 = { + 0x0010, pci_device_104a_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0210 = { + 0x0210, pci_device_104a_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0981 = { + 0x0981, pci_device_104a_0981, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0981, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_1746 = { + 0x1746, pci_device_104a_1746, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_1746, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_2774 = { + 0x2774, pci_device_104a_2774, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_2774, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_3520 = { + 0x3520, pci_device_104a_3520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_3520, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_104b_0140 = { + 0x0140, pci_device_104b_0140, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104b_0140, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104b_1040 = { + 0x1040, pci_device_104b_1040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104b_1040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104b_8130 = { + 0x8130, pci_device_104b_8130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104b_8130, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_104c_0500 = { + 0x0500, pci_device_104c_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_0508 = { + 0x0508, pci_device_104c_0508, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_0508, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_1000 = { + 0x1000, pci_device_104c_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_104c = { + 0x104c, pci_device_104c_104c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_104c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_3d04 = { + 0x3d04, pci_device_104c_3d04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_3d04, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_3d07 = { + 0x3d07, pci_device_104c_3d07, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_3d07, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8000 = { + 0x8000, pci_device_104c_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8009 = { + 0x8009, pci_device_104c_8009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8017 = { + 0x8017, pci_device_104c_8017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8019 = { + 0x8019, pci_device_104c_8019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8020 = { + 0x8020, pci_device_104c_8020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8021 = { + 0x8021, pci_device_104c_8021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8022 = { + 0x8022, pci_device_104c_8022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8023 = { + 0x8023, pci_device_104c_8023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8024 = { + 0x8024, pci_device_104c_8024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8026 = { + 0x8026, pci_device_104c_8026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8027 = { + 0x8027, pci_device_104c_8027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8400 = { + 0x8400, pci_device_104c_8400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_a001 = { + 0xa001, pci_device_104c_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_a001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_a100 = { + 0xa100, pci_device_104c_a100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_a100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_a102 = { + 0xa102, pci_device_104c_a102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_a102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_a106 = { + 0xa106, pci_device_104c_a106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_a106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac10 = { + 0xac10, pci_device_104c_ac10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac11 = { + 0xac11, pci_device_104c_ac11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac12 = { + 0xac12, pci_device_104c_ac12, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac12, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac13 = { + 0xac13, pci_device_104c_ac13, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac13, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac15 = { + 0xac15, pci_device_104c_ac15, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac15, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac16 = { + 0xac16, pci_device_104c_ac16, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac16, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac17 = { + 0xac17, pci_device_104c_ac17, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac17, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac18 = { + 0xac18, pci_device_104c_ac18, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac18, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac19 = { + 0xac19, pci_device_104c_ac19, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac19, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1a = { + 0xac1a, pci_device_104c_ac1a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1b = { + 0xac1b, pci_device_104c_ac1b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1c = { + 0xac1c, pci_device_104c_ac1c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1d = { + 0xac1d, pci_device_104c_ac1d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1e = { + 0xac1e, pci_device_104c_ac1e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1f = { + 0xac1f, pci_device_104c_ac1f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac20 = { + 0xac20, pci_device_104c_ac20, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac20, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac21 = { + 0xac21, pci_device_104c_ac21, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac21, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac22 = { + 0xac22, pci_device_104c_ac22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac22, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac23 = { + 0xac23, pci_device_104c_ac23, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac23, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac28 = { + 0xac28, pci_device_104c_ac28, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac28, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac30 = { + 0xac30, pci_device_104c_ac30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac30, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac40 = { + 0xac40, pci_device_104c_ac40, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac40, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac41 = { + 0xac41, pci_device_104c_ac41, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac41, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac42 = { + 0xac42, pci_device_104c_ac42, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac42, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac50 = { + 0xac50, pci_device_104c_ac50, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac50, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac51 = { + 0xac51, pci_device_104c_ac51, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac51, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac52 = { + 0xac52, pci_device_104c_ac52, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac52, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac53 = { + 0xac53, pci_device_104c_ac53, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac53, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac55 = { + 0xac55, pci_device_104c_ac55, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac55, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac56 = { + 0xac56, pci_device_104c_ac56, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac56, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac60 = { + 0xac60, pci_device_104c_ac60, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac60, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_fe00 = { + 0xfe00, pci_device_104c_fe00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_fe00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_fe03 = { + 0xfe03, pci_device_104c_fe03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_fe03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_8009 = { + 0x8009, pci_device_104d_8009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_8009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_8039 = { + 0x8039, pci_device_104d_8039, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_8039, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_8056 = { + 0x8056, pci_device_104d_8056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_8056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_808a = { + 0x808a, pci_device_104d_808a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_808a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0017 = { + 0x0017, pci_device_104e_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0107 = { + 0x0107, pci_device_104e_0107, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0107, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0109 = { + 0x0109, pci_device_104e_0109, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0109, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0111 = { + 0x0111, pci_device_104e_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0217 = { + 0x0217, pci_device_104e_0217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0317 = { + 0x0317, pci_device_104e_0317, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0317, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1050_0000 = { + 0x0000, pci_device_1050_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_0001 = { + 0x0001, pci_device_1050_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_0105 = { + 0x0105, pci_device_1050_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_0840 = { + 0x0840, pci_device_1050_0840, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0840, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_0940 = { + 0x0940, pci_device_1050_0940, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0940, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_5a5a = { + 0x5a5a, pci_device_1050_5a5a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_5a5a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_6692 = { + 0x6692, pci_device_1050_6692, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_6692, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_9970 = { + 0x9970, pci_device_1050_9970, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_9970, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1055_9130 = { + 0x9130, pci_device_1055_9130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1055_9130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1055_9460 = { + 0x9460, pci_device_1055_9460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1055_9460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1055_9462 = { + 0x9462, pci_device_1055_9462, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1055_9462, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1055_9463 = { + 0x9463, pci_device_1055_9463, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1055_9463, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1057_0001 = { + 0x0001, pci_device_1057_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0002 = { + 0x0002, pci_device_1057_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0003 = { + 0x0003, pci_device_1057_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0004 = { + 0x0004, pci_device_1057_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0006 = { + 0x0006, pci_device_1057_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0100 = { + 0x0100, pci_device_1057_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0431 = { + 0x0431, pci_device_1057_0431, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0431, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_1801 = { + 0x1801, pci_device_1057_1801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_1801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_18c0 = { + 0x18c0, pci_device_1057_18c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_18c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4801 = { + 0x4801, pci_device_1057_4801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4802 = { + 0x4802, pci_device_1057_4802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4803 = { + 0x4803, pci_device_1057_4803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4806 = { + 0x4806, pci_device_1057_4806, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4806, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4d68 = { + 0x4d68, pci_device_1057_4d68, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4d68, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_5600 = { + 0x5600, pci_device_1057_5600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_5600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_6400 = { + 0x6400, pci_device_1057_6400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_6400, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_105a_0d30 = { + 0x0d30, pci_device_105a_0d30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_0d30, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_0d38 = { + 0x0d38, pci_device_105a_0d38, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_0d38, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_1275 = { + 0x1275, pci_device_105a_1275, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_1275, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3376 = { + 0x3376, pci_device_105a_3376, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3376, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d30 = { + 0x4d30, pci_device_105a_4d30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d30, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d33 = { + 0x4d33, pci_device_105a_4d33, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d33, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d38 = { + 0x4d38, pci_device_105a_4d38, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d38, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d68 = { + 0x4d68, pci_device_105a_4d68, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d68, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d69 = { + 0x4d69, pci_device_105a_4d69, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d69, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_5275 = { + 0x5275, pci_device_105a_5275, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_5275, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_5300 = { + 0x5300, pci_device_105a_5300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_5300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6268 = { + 0x6268, pci_device_105a_6268, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6268, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6269 = { + 0x6269, pci_device_105a_6269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6621 = { + 0x6621, pci_device_105a_6621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_7275 = { + 0x7275, pci_device_105a_7275, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_7275, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_105d_2309 = { + 0x2309, pci_device_105d_2309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105d_2309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105d_2339 = { + 0x2339, pci_device_105d_2339, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105d_2339, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105d_493d = { + 0x493d, pci_device_105d_493d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105d_493d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105d_5348 = { + 0x5348, pci_device_105d_5348, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105d_5348, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1060_0001 = { + 0x0001, pci_device_1060_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0002 = { + 0x0002, pci_device_1060_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0101 = { + 0x0101, pci_device_1060_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0881 = { + 0x0881, pci_device_1060_0881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0886 = { + 0x0886, pci_device_1060_0886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0886, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0891 = { + 0x0891, pci_device_1060_0891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_1001 = { + 0x1001, pci_device_1060_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_673a = { + 0x673a, pci_device_1060_673a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_673a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_673b = { + 0x673b, pci_device_1060_673b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_673b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_8710 = { + 0x8710, pci_device_1060_8710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_8710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_886a = { + 0x886a, pci_device_1060_886a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_886a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_8881 = { + 0x8881, pci_device_1060_8881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_8881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_8886 = { + 0x8886, pci_device_1060_8886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_8886, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_888a = { + 0x888a, pci_device_1060_888a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_888a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_8891 = { + 0x8891, pci_device_1060_8891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_8891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_9017 = { + 0x9017, pci_device_1060_9017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_9017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_9018 = { + 0x9018, pci_device_1060_9018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_9018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_9026 = { + 0x9026, pci_device_1060_9026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_9026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_e881 = { + 0xe881, pci_device_1060_e881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_e881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_e886 = { + 0xe886, pci_device_1060_e886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_e886, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_e88a = { + 0xe88a, pci_device_1060_e88a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_e88a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_e891 = { + 0xe891, pci_device_1060_e891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_e891, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1061_0001 = { + 0x0001, pci_device_1061_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1061_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1061_0002 = { + 0x0002, pci_device_1061_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1061_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1066_0000 = { + 0x0000, pci_device_1066_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0001 = { + 0x0001, pci_device_1066_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0002 = { + 0x0002, pci_device_1066_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0003 = { + 0x0003, pci_device_1066_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0004 = { + 0x0004, pci_device_1066_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0005 = { + 0x0005, pci_device_1066_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_8002 = { + 0x8002, pci_device_1066_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_8002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1067_1002 = { + 0x1002, pci_device_1067_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1067_1002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1069_0001 = { + 0x0001, pci_device_1069_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_0002 = { + 0x0002, pci_device_1069_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_0010 = { + 0x0010, pci_device_1069_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_0050 = { + 0x0050, pci_device_1069_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_ba55 = { + 0xba55, pci_device_1069_ba55, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_ba55, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_ba56 = { + 0xba56, pci_device_1069_ba56, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_ba56, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_106b_0001 = { + 0x0001, pci_device_106b_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0002 = { + 0x0002, pci_device_106b_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0003 = { + 0x0003, pci_device_106b_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0004 = { + 0x0004, pci_device_106b_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0007 = { + 0x0007, pci_device_106b_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_000e = { + 0x000e, pci_device_106b_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_000e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0010 = { + 0x0010, pci_device_106b_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0017 = { + 0x0017, pci_device_106b_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0018 = { + 0x0018, pci_device_106b_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0019 = { + 0x0019, pci_device_106b_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_001e = { + 0x001e, pci_device_106b_001e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_001e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_001f = { + 0x001f, pci_device_106b_001f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_001f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0020 = { + 0x0020, pci_device_106b_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0021 = { + 0x0021, pci_device_106b_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0022 = { + 0x0022, pci_device_106b_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0024 = { + 0x0024, pci_device_106b_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0025 = { + 0x0025, pci_device_106b_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0026 = { + 0x0026, pci_device_106b_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0027 = { + 0x0027, pci_device_106b_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0028 = { + 0x0028, pci_device_106b_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0029 = { + 0x0029, pci_device_106b_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_002d = { + 0x002d, pci_device_106b_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_002e = { + 0x002e, pci_device_106b_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_002f = { + 0x002f, pci_device_106b_002f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_002f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0030 = { + 0x0030, pci_device_106b_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0031 = { + 0x0031, pci_device_106b_0031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0032 = { + 0x0032, pci_device_106b_0032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0033 = { + 0x0033, pci_device_106b_0033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0034 = { + 0x0034, pci_device_106b_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_1645 = { + 0x1645, pci_device_106b_1645, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_1645, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_106c_8801 = { + 0x8801, pci_device_106c_8801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106c_8802 = { + 0x8802, pci_device_106c_8802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106c_8803 = { + 0x8803, pci_device_106c_8803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106c_8804 = { + 0x8804, pci_device_106c_8804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106c_8805 = { + 0x8805, pci_device_106c_8805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8805, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1073_0001 = { + 0x0001, pci_device_1073_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0002 = { + 0x0002, pci_device_1073_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0003 = { + 0x0003, pci_device_1073_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0004 = { + 0x0004, pci_device_1073_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0005 = { + 0x0005, pci_device_1073_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0006 = { + 0x0006, pci_device_1073_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0008 = { + 0x0008, pci_device_1073_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_000a = { + 0x000a, pci_device_1073_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_000c = { + 0x000c, pci_device_1073_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_000d = { + 0x000d, pci_device_1073_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0010 = { + 0x0010, pci_device_1073_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0012 = { + 0x0012, pci_device_1073_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0020 = { + 0x0020, pci_device_1073_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_2000 = { + 0x2000, pci_device_1073_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_2000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1074_4e78 = { + 0x4e78, pci_device_1074_4e78, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1074_4e78, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1077_1016 = { + 0x1016, pci_device_1077_1016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1020 = { + 0x1020, pci_device_1077_1020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1022 = { + 0x1022, pci_device_1077_1022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1080 = { + 0x1080, pci_device_1077_1080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1216 = { + 0x1216, pci_device_1077_1216, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1216, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1240 = { + 0x1240, pci_device_1077_1240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1280 = { + 0x1280, pci_device_1077_1280, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1280, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2020 = { + 0x2020, pci_device_1077_2020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2100 = { + 0x2100, pci_device_1077_2100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2200 = { + 0x2200, pci_device_1077_2200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2300 = { + 0x2300, pci_device_1077_2300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2312 = { + 0x2312, pci_device_1077_2312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2312, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1078_0000 = { + 0x0000, pci_device_1078_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0001 = { + 0x0001, pci_device_1078_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0002 = { + 0x0002, pci_device_1078_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0100 = { + 0x0100, pci_device_1078_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0101 = { + 0x0101, pci_device_1078_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0102 = { + 0x0102, pci_device_1078_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0103 = { + 0x0103, pci_device_1078_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0104 = { + 0x0104, pci_device_1078_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0400 = { + 0x0400, pci_device_1078_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0401 = { + 0x0401, pci_device_1078_0401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0402 = { + 0x0402, pci_device_1078_0402, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0402, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0403 = { + 0x0403, pci_device_1078_0403, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0403, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_107d_0000 = { + 0x0000, pci_device_107d_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107d_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_107e_0001 = { + 0x0001, pci_device_107e_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_0002 = { + 0x0002, pci_device_107e_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_0004 = { + 0x0004, pci_device_107e_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_0005 = { + 0x0005, pci_device_107e_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_0008 = { + 0x0008, pci_device_107e_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9003 = { + 0x9003, pci_device_107e_9003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9007 = { + 0x9007, pci_device_107e_9007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9008 = { + 0x9008, pci_device_107e_9008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_900c = { + 0x900c, pci_device_107e_900c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_900c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_900e = { + 0x900e, pci_device_107e_900e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_900e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9011 = { + 0x9011, pci_device_107e_9011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9013 = { + 0x9013, pci_device_107e_9013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9023 = { + 0x9023, pci_device_107e_9023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9027 = { + 0x9027, pci_device_107e_9027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9031 = { + 0x9031, pci_device_107e_9031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9033 = { + 0x9033, pci_device_107e_9033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9033, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_107f_0802 = { + 0x0802, pci_device_107f_0802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107f_0802, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1080_0600 = { + 0x0600, pci_device_1080_0600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1080_0600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1080_c691 = { + 0xc691, pci_device_1080_c691, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1080_c691, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1080_c693 = { + 0xc693, pci_device_1080_c693, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1080_c693, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1081_0d47 = { + 0x0d47, pci_device_1081_0d47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1081_0d47, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1083_0001 = { + 0x0001, pci_device_1083_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1083_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_108a_0001 = { + 0x0001, pci_device_108a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108a_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108a_0010 = { + 0x0010, pci_device_108a_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108a_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108a_0040 = { + 0x0040, pci_device_108a_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108a_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108a_3000 = { + 0x3000, pci_device_108a_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108a_3000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_108d_0001 = { + 0x0001, pci_device_108d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0002 = { + 0x0002, pci_device_108d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0004 = { + 0x0004, pci_device_108d_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0005 = { + 0x0005, pci_device_108d_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0006 = { + 0x0006, pci_device_108d_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0007 = { + 0x0007, pci_device_108d_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0008 = { + 0x0008, pci_device_108d_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0011 = { + 0x0011, pci_device_108d_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0012 = { + 0x0012, pci_device_108d_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0013 = { + 0x0013, pci_device_108d_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0014 = { + 0x0014, pci_device_108d_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0019 = { + 0x0019, pci_device_108d_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0021 = { + 0x0021, pci_device_108d_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0022 = { + 0x0022, pci_device_108d_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0022, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_108e_0001 = { + 0x0001, pci_device_108e_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1000 = { + 0x1000, pci_device_108e_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1001 = { + 0x1001, pci_device_108e_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1100 = { + 0x1100, pci_device_108e_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1101 = { + 0x1101, pci_device_108e_1101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1102 = { + 0x1102, pci_device_108e_1102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1103 = { + 0x1103, pci_device_108e_1103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_2bad = { + 0x2bad, pci_device_108e_2bad, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_2bad, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_5000 = { + 0x5000, pci_device_108e_5000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_5000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_5043 = { + 0x5043, pci_device_108e_5043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_5043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_8000 = { + 0x8000, pci_device_108e_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_8000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_8001 = { + 0x8001, pci_device_108e_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_8001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_a000 = { + 0xa000, pci_device_108e_a000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_a000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_a001 = { + 0xa001, pci_device_108e_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_a001, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1091_0020 = { + 0x0020, pci_device_1091_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0021 = { + 0x0021, pci_device_1091_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0040 = { + 0x0040, pci_device_1091_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0041 = { + 0x0041, pci_device_1091_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0060 = { + 0x0060, pci_device_1091_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_00e4 = { + 0x00e4, pci_device_1091_00e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_00e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0720 = { + 0x0720, pci_device_1091_0720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0720, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1092_00a0 = { + 0x00a0, pci_device_1092_00a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_00a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_00a8 = { + 0x00a8, pci_device_1092_00a8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_00a8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_0550 = { + 0x0550, pci_device_1092_0550, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_0550, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_08d4 = { + 0x08d4, pci_device_1092_08d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_08d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_094c = { + 0x094c, pci_device_1092_094c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_094c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_1092 = { + 0x1092, pci_device_1092_1092, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_1092, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_6120 = { + 0x6120, pci_device_1092_6120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_6120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_8810 = { + 0x8810, pci_device_1092_8810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_8810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_8811 = { + 0x8811, pci_device_1092_8811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_8811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_8880 = { + 0x8880, pci_device_1092_8880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_8880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_8881 = { + 0x8881, pci_device_1092_8881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_8881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88b0 = { + 0x88b0, pci_device_1092_88b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88b1 = { + 0x88b1, pci_device_1092_88b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88c0 = { + 0x88c0, pci_device_1092_88c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88c1 = { + 0x88c1, pci_device_1092_88c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88d0 = { + 0x88d0, pci_device_1092_88d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88d1 = { + 0x88d1, pci_device_1092_88d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88f0 = { + 0x88f0, pci_device_1092_88f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88f1 = { + 0x88f1, pci_device_1092_88f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_9999 = { + 0x9999, pci_device_1092_9999, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_9999, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1093_0160 = { + 0x0160, pci_device_1093_0160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_0160, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_0162 = { + 0x0162, pci_device_1093_0162, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_0162, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1170 = { + 0x1170, pci_device_1093_1170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1180 = { + 0x1180, pci_device_1093_1180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1190 = { + 0x1190, pci_device_1093_1190, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1190, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1330 = { + 0x1330, pci_device_1093_1330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1350 = { + 0x1350, pci_device_1093_1350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2a60 = { + 0x2a60, pci_device_1093_2a60, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2a60, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b001 = { + 0xb001, pci_device_1093_b001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b011 = { + 0xb011, pci_device_1093_b011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b021 = { + 0xb021, pci_device_1093_b021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b031 = { + 0xb031, pci_device_1093_b031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b041 = { + 0xb041, pci_device_1093_b041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b051 = { + 0xb051, pci_device_1093_b051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b061 = { + 0xb061, pci_device_1093_b061, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b061, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b071 = { + 0xb071, pci_device_1093_b071, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b071, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b081 = { + 0xb081, pci_device_1093_b081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b091 = { + 0xb091, pci_device_1093_b091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_c801 = { + 0xc801, pci_device_1093_c801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_c801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_c831 = { + 0xc831, pci_device_1093_c831, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_c831, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1095_0640 = { + 0x0640, pci_device_1095_0640, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0640, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0643 = { + 0x0643, pci_device_1095_0643, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0643, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0646 = { + 0x0646, pci_device_1095_0646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0647 = { + 0x0647, pci_device_1095_0647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0648 = { + 0x0648, pci_device_1095_0648, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0648, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0649 = { + 0x0649, pci_device_1095_0649, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0649, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0650 = { + 0x0650, pci_device_1095_0650, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0650, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0670 = { + 0x0670, pci_device_1095_0670, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0670, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0673 = { + 0x0673, pci_device_1095_0673, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0673, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0680 = { + 0x0680, pci_device_1095_0680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_3112 = { + 0x3112, pci_device_1095_3112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_3112, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1098_0001 = { + 0x0001, pci_device_1098_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1098_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1098_0002 = { + 0x0002, pci_device_1098_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1098_0002, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_109e_0350 = { + 0x0350, pci_device_109e_0350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0351 = { + 0x0351, pci_device_109e_0351, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0351, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0369 = { + 0x0369, pci_device_109e_0369, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0369, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_036c = { + 0x036c, pci_device_109e_036c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_036c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_036e = { + 0x036e, pci_device_109e_036e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_036e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_036f = { + 0x036f, pci_device_109e_036f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_036f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0370 = { + 0x0370, pci_device_109e_0370, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0370, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0878 = { + 0x0878, pci_device_109e_0878, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0878, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0879 = { + 0x0879, pci_device_109e_0879, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0879, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0880 = { + 0x0880, pci_device_109e_0880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_2115 = { + 0x2115, pci_device_109e_2115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_2115, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_2125 = { + 0x2125, pci_device_109e_2125, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_2125, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_2164 = { + 0x2164, pci_device_109e_2164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_2164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_2165 = { + 0x2165, pci_device_109e_2165, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_2165, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_8230 = { + 0x8230, pci_device_109e_8230, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_8230, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_8472 = { + 0x8472, pci_device_109e_8472, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_8472, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_8474 = { + 0x8474, pci_device_109e_8474, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_8474, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10a5_5449 = { + 0x5449, pci_device_10a5_5449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a5_5449, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10a8_0000 = { + 0x0000, pci_device_10a8_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a8_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10a9_0001 = { + 0x0001, pci_device_10a9_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0002 = { + 0x0002, pci_device_10a9_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0003 = { + 0x0003, pci_device_10a9_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0004 = { + 0x0004, pci_device_10a9_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0005 = { + 0x0005, pci_device_10a9_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0006 = { + 0x0006, pci_device_10a9_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0007 = { + 0x0007, pci_device_10a9_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0008 = { + 0x0008, pci_device_10a9_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0009 = { + 0x0009, pci_device_10a9_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0010 = { + 0x0010, pci_device_10a9_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0011 = { + 0x0011, pci_device_10a9_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0012 = { + 0x0012, pci_device_10a9_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1001 = { + 0x1001, pci_device_10a9_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1002 = { + 0x1002, pci_device_10a9_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1003 = { + 0x1003, pci_device_10a9_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1004 = { + 0x1004, pci_device_10a9_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1005 = { + 0x1005, pci_device_10a9_1005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1006 = { + 0x1006, pci_device_10a9_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1007 = { + 0x1007, pci_device_10a9_1007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1008 = { + 0x1008, pci_device_10a9_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_2001 = { + 0x2001, pci_device_10a9_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_2001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_2002 = { + 0x2002, pci_device_10a9_2002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_2002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_8001 = { + 0x8001, pci_device_10a9_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_8001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_8002 = { + 0x8002, pci_device_10a9_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_8002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10aa_0000 = { + 0x0000, pci_device_10aa_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10aa_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ad_0001 = { + 0x0001, pci_device_10ad_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0003 = { + 0x0003, pci_device_10ad_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0005 = { + 0x0005, pci_device_10ad_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0103 = { + 0x0103, pci_device_10ad_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0105 = { + 0x0105, pci_device_10ad_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0565 = { + 0x0565, pci_device_10ad_0565, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0565, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b3_3106 = { + 0x3106, pci_device_10b3_3106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b3_3106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b3_b106 = { + 0xb106, pci_device_10b3_b106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b3_b106, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b4_1b1d = { + 0x1b1d, pci_device_10b4_1b1d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b4_1b1d, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b5_0001 = { + 0x0001, pci_device_10b5_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1076 = { + 0x1076, pci_device_10b5_1076, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1076, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1077 = { + 0x1077, pci_device_10b5_1077, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1077, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1078 = { + 0x1078, pci_device_10b5_1078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1103 = { + 0x1103, pci_device_10b5_1103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1146 = { + 0x1146, pci_device_10b5_1146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1147 = { + 0x1147, pci_device_10b5_1147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_2724 = { + 0x2724, pci_device_10b5_2724, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_2724, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9030 = { + 0x9030, pci_device_10b5_9030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9036 = { + 0x9036, pci_device_10b5_9036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9050 = { + 0x9050, pci_device_10b5_9050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9054 = { + 0x9054, pci_device_10b5_9054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9060 = { + 0x9060, pci_device_10b5_9060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_906d = { + 0x906d, pci_device_10b5_906d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_906d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_906e = { + 0x906e, pci_device_10b5_906e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_906e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9080 = { + 0x9080, pci_device_10b5_9080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9080, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b6_0001 = { + 0x0001, pci_device_10b6_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0002 = { + 0x0002, pci_device_10b6_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0003 = { + 0x0003, pci_device_10b6_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0004 = { + 0x0004, pci_device_10b6_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0006 = { + 0x0006, pci_device_10b6_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0007 = { + 0x0007, pci_device_10b6_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0009 = { + 0x0009, pci_device_10b6_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_000a = { + 0x000a, pci_device_10b6_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_000b = { + 0x000b, pci_device_10b6_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_000c = { + 0x000c, pci_device_10b6_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_1000 = { + 0x1000, pci_device_10b6_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_1001 = { + 0x1001, pci_device_10b6_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_1001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b7_0001 = { + 0x0001, pci_device_10b7_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_1006 = { + 0x1006, pci_device_10b7_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_1007 = { + 0x1007, pci_device_10b7_1007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_1007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_3390 = { + 0x3390, pci_device_10b7_3390, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_3390, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_3590 = { + 0x3590, pci_device_10b7_3590, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_3590, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_4500 = { + 0x4500, pci_device_10b7_4500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_4500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5055 = { + 0x5055, pci_device_10b7_5055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5057 = { + 0x5057, pci_device_10b7_5057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5157 = { + 0x5157, pci_device_10b7_5157, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5157, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5257 = { + 0x5257, pci_device_10b7_5257, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5257, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5900 = { + 0x5900, pci_device_10b7_5900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5920 = { + 0x5920, pci_device_10b7_5920, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5920, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5950 = { + 0x5950, pci_device_10b7_5950, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5950, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5951 = { + 0x5951, pci_device_10b7_5951, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5951, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5952 = { + 0x5952, pci_device_10b7_5952, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5952, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5970 = { + 0x5970, pci_device_10b7_5970, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5970, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5b57 = { + 0x5b57, pci_device_10b7_5b57, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5b57, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6055 = { + 0x6055, pci_device_10b7_6055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6056 = { + 0x6056, pci_device_10b7_6056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6560 = { + 0x6560, pci_device_10b7_6560, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6560, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6561 = { + 0x6561, pci_device_10b7_6561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6562 = { + 0x6562, pci_device_10b7_6562, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6562, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6563 = { + 0x6563, pci_device_10b7_6563, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6563, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6564 = { + 0x6564, pci_device_10b7_6564, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6564, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7646 = { + 0x7646, pci_device_10b7_7646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7940 = { + 0x7940, pci_device_10b7_7940, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7940, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7980 = { + 0x7980, pci_device_10b7_7980, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7980, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7990 = { + 0x7990, pci_device_10b7_7990, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7990, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_8811 = { + 0x8811, pci_device_10b7_8811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_8811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9000 = { + 0x9000, pci_device_10b7_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9001 = { + 0x9001, pci_device_10b7_9001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9004 = { + 0x9004, pci_device_10b7_9004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9005 = { + 0x9005, pci_device_10b7_9005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9006 = { + 0x9006, pci_device_10b7_9006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_900a = { + 0x900a, pci_device_10b7_900a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_900a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9050 = { + 0x9050, pci_device_10b7_9050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9051 = { + 0x9051, pci_device_10b7_9051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9055 = { + 0x9055, pci_device_10b7_9055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9056 = { + 0x9056, pci_device_10b7_9056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9058 = { + 0x9058, pci_device_10b7_9058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_905a = { + 0x905a, pci_device_10b7_905a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_905a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9200 = { + 0x9200, pci_device_10b7_9200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9201 = { + 0x9201, pci_device_10b7_9201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9300 = { + 0x9300, pci_device_10b7_9300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9800 = { + 0x9800, pci_device_10b7_9800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9805 = { + 0x9805, pci_device_10b7_9805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9900 = { + 0x9900, pci_device_10b7_9900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9902 = { + 0x9902, pci_device_10b7_9902, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9902, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9903 = { + 0x9903, pci_device_10b7_9903, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9903, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9904 = { + 0x9904, pci_device_10b7_9904, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9904, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9905 = { + 0x9905, pci_device_10b7_9905, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9905, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9908 = { + 0x9908, pci_device_10b7_9908, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9908, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9909 = { + 0x9909, pci_device_10b7_9909, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9909, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_990b = { + 0x990b, pci_device_10b7_990b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_990b, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b8_0005 = { + 0x0005, pci_device_10b8_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_0006 = { + 0x0006, pci_device_10b8_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_1000 = { + 0x1000, pci_device_10b8_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_1001 = { + 0x1001, pci_device_10b8_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_a011 = { + 0xa011, pci_device_10b8_a011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_a011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_b106 = { + 0xb106, pci_device_10b8_b106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_b106, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_10b9_0111 = { + 0x0111, pci_device_10b9_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1435 = { + 0x1435, pci_device_10b9_1435, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1435, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1445 = { + 0x1445, pci_device_10b9_1445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1449 = { + 0x1449, pci_device_10b9_1449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1451 = { + 0x1451, pci_device_10b9_1451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1461 = { + 0x1461, pci_device_10b9_1461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1489 = { + 0x1489, pci_device_10b9_1489, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1489, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1511 = { + 0x1511, pci_device_10b9_1511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1512 = { + 0x1512, pci_device_10b9_1512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1512, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1513 = { + 0x1513, pci_device_10b9_1513, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1513, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1521 = { + 0x1521, pci_device_10b9_1521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1523 = { + 0x1523, pci_device_10b9_1523, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1523, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1531 = { + 0x1531, pci_device_10b9_1531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1533 = { + 0x1533, pci_device_10b9_1533, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1533, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1541 = { + 0x1541, pci_device_10b9_1541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1543 = { + 0x1543, pci_device_10b9_1543, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1543, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1563 = { + 0x1563, pci_device_10b9_1563, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1563, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1621 = { + 0x1621, pci_device_10b9_1621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1631 = { + 0x1631, pci_device_10b9_1631, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1631, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1632 = { + 0x1632, pci_device_10b9_1632, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1632, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1641 = { + 0x1641, pci_device_10b9_1641, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1641, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1644 = { + 0x1644, pci_device_10b9_1644, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1644, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1646 = { + 0x1646, pci_device_10b9_1646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1647 = { + 0x1647, pci_device_10b9_1647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1651 = { + 0x1651, pci_device_10b9_1651, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1651, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1671 = { + 0x1671, pci_device_10b9_1671, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1671, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1681 = { + 0x1681, pci_device_10b9_1681, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1681, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1687 = { + 0x1687, pci_device_10b9_1687, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1687, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3141 = { + 0x3141, pci_device_10b9_3141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3141, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3143 = { + 0x3143, pci_device_10b9_3143, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3143, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3145 = { + 0x3145, pci_device_10b9_3145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3147 = { + 0x3147, pci_device_10b9_3147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3149 = { + 0x3149, pci_device_10b9_3149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3151 = { + 0x3151, pci_device_10b9_3151, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3151, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3307 = { + 0x3307, pci_device_10b9_3307, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3307, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3309 = { + 0x3309, pci_device_10b9_3309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5212 = { + 0x5212, pci_device_10b9_5212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5215 = { + 0x5215, pci_device_10b9_5215, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5215, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5217 = { + 0x5217, pci_device_10b9_5217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5219 = { + 0x5219, pci_device_10b9_5219, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5219, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5225 = { + 0x5225, pci_device_10b9_5225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5229 = { + 0x5229, pci_device_10b9_5229, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5229, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5235 = { + 0x5235, pci_device_10b9_5235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5237 = { + 0x5237, pci_device_10b9_5237, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5237, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5239 = { + 0x5239, pci_device_10b9_5239, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5239, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5243 = { + 0x5243, pci_device_10b9_5243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5243, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5247 = { + 0x5247, pci_device_10b9_5247, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5247, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5249 = { + 0x5249, pci_device_10b9_5249, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5249, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5251 = { + 0x5251, pci_device_10b9_5251, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5251, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5253 = { + 0x5253, pci_device_10b9_5253, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5253, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5261 = { + 0x5261, pci_device_10b9_5261, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5261, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5451 = { + 0x5451, pci_device_10b9_5451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5453 = { + 0x5453, pci_device_10b9_5453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5455 = { + 0x5455, pci_device_10b9_5455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5457 = { + 0x5457, pci_device_10b9_5457, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5457, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5459 = { + 0x5459, pci_device_10b9_5459, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5459, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_545a = { + 0x545a, pci_device_10b9_545a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_545a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5471 = { + 0x5471, pci_device_10b9_5471, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5471, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5473 = { + 0x5473, pci_device_10b9_5473, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5473, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_7101 = { + 0x7101, pci_device_10b9_7101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_7101, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ba_0301 = { + 0x0301, pci_device_10ba_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ba_0301, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10bd_0e34 = { + 0x0e34, pci_device_10bd_0e34, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10bd_0e34, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10c3_1100 = { + 0x1100, pci_device_10c3_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c3_1100, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_10c8_0001 = { + 0x0001, pci_device_10c8_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0002 = { + 0x0002, pci_device_10c8_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0003 = { + 0x0003, pci_device_10c8_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0004 = { + 0x0004, pci_device_10c8_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0005 = { + 0x0005, pci_device_10c8_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0006 = { + 0x0006, pci_device_10c8_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0016 = { + 0x0016, pci_device_10c8_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0025 = { + 0x0025, pci_device_10c8_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0083 = { + 0x0083, pci_device_10c8_0083, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0083, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_8005 = { + 0x8005, pci_device_10c8_8005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_8005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_8006 = { + 0x8006, pci_device_10c8_8006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_8006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_8016 = { + 0x8016, pci_device_10c8_8016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_8016, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10cd_1100 = { + 0x1100, pci_device_10cd_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cd_1200 = { + 0x1200, pci_device_10cd_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cd_1300 = { + 0x1300, pci_device_10cd_1300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_1300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cd_2300 = { + 0x2300, pci_device_10cd_2300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_2300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cd_2500 = { + 0x2500, pci_device_10cd_2500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_2500, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10cf_2001 = { + 0x2001, pci_device_10cf_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cf_2001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10d9_0512 = { + 0x0512, pci_device_10d9_0512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_0512, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_0531 = { + 0x0531, pci_device_10d9_0531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_0531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_8625 = { + 0x8625, pci_device_10d9_8625, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_8625, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_8888 = { + 0x8888, pci_device_10d9_8888, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_8888, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10da_0508 = { + 0x0508, pci_device_10da_0508, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10da_0508, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10da_3390 = { + 0x3390, pci_device_10da_3390, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10da_3390, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10dc_0001 = { + 0x0001, pci_device_10dc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10dc_0002 = { + 0x0002, pci_device_10dc_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10dc_0021 = { + 0x0021, pci_device_10dc_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10dc_0022 = { + 0x0022, pci_device_10dc_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10dc_10dc = { + 0x10dc, pci_device_10dc_10dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_10dc, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_10de_0008 = { + 0x0008, pci_device_10de_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0009 = { + 0x0009, pci_device_10de_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0010 = { + 0x0010, pci_device_10de_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0020 = { + 0x0020, pci_device_10de_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0028 = { + 0x0028, pci_device_10de_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0029 = { + 0x0029, pci_device_10de_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002a = { + 0x002a, pci_device_10de_002a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002b = { + 0x002b, pci_device_10de_002b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002c = { + 0x002c, pci_device_10de_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002d = { + 0x002d, pci_device_10de_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002e = { + 0x002e, pci_device_10de_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002f = { + 0x002f, pci_device_10de_002f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0060 = { + 0x0060, pci_device_10de_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0064 = { + 0x0064, pci_device_10de_0064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0065 = { + 0x0065, pci_device_10de_0065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0066 = { + 0x0066, pci_device_10de_0066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0067 = { + 0x0067, pci_device_10de_0067, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0067, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0068 = { + 0x0068, pci_device_10de_0068, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0068, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006a = { + 0x006a, pci_device_10de_006a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006b = { + 0x006b, pci_device_10de_006b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006e = { + 0x006e, pci_device_10de_006e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00a0 = { + 0x00a0, pci_device_10de_00a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0100 = { + 0x0100, pci_device_10de_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0101 = { + 0x0101, pci_device_10de_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0103 = { + 0x0103, pci_device_10de_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0110 = { + 0x0110, pci_device_10de_0110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0111 = { + 0x0111, pci_device_10de_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0112 = { + 0x0112, pci_device_10de_0112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0113 = { + 0x0113, pci_device_10de_0113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0150 = { + 0x0150, pci_device_10de_0150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0150, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0151 = { + 0x0151, pci_device_10de_0151, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0151, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0152 = { + 0x0152, pci_device_10de_0152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0153 = { + 0x0153, pci_device_10de_0153, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0153, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0170 = { + 0x0170, pci_device_10de_0170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0171 = { + 0x0171, pci_device_10de_0171, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0171, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0172 = { + 0x0172, pci_device_10de_0172, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0172, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0173 = { + 0x0173, pci_device_10de_0173, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0173, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0174 = { + 0x0174, pci_device_10de_0174, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0174, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0175 = { + 0x0175, pci_device_10de_0175, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0175, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0176 = { + 0x0176, pci_device_10de_0176, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0176, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0178 = { + 0x0178, pci_device_10de_0178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0179 = { + 0x0179, pci_device_10de_0179, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0179, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_017a = { + 0x017a, pci_device_10de_017a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_017a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_017b = { + 0x017b, pci_device_10de_017b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_017b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_017c = { + 0x017c, pci_device_10de_017c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_017c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0181 = { + 0x0181, pci_device_10de_0181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0182 = { + 0x0182, pci_device_10de_0182, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0182, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0183 = { + 0x0183, pci_device_10de_0183, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0183, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0188 = { + 0x0188, pci_device_10de_0188, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0188, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_018a = { + 0x018a, pci_device_10de_018a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_018a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_018b = { + 0x018b, pci_device_10de_018b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_018b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01a0 = { + 0x01a0, pci_device_10de_01a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01a4 = { + 0x01a4, pci_device_10de_01a4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01a4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ab = { + 0x01ab, pci_device_10de_01ab, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ab, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ac = { + 0x01ac, pci_device_10de_01ac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ad = { + 0x01ad, pci_device_10de_01ad, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ad, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b1 = { + 0x01b1, pci_device_10de_01b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b2 = { + 0x01b2, pci_device_10de_01b2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b4 = { + 0x01b4, pci_device_10de_01b4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b7 = { + 0x01b7, pci_device_10de_01b7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b8 = { + 0x01b8, pci_device_10de_01b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01bc = { + 0x01bc, pci_device_10de_01bc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01bc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01c1 = { + 0x01c1, pci_device_10de_01c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01c2 = { + 0x01c2, pci_device_10de_01c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01c2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01c3 = { + 0x01c3, pci_device_10de_01c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01e8 = { + 0x01e8, pci_device_10de_01e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01f0 = { + 0x01f0, pci_device_10de_01f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0200 = { + 0x0200, pci_device_10de_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0201 = { + 0x0201, pci_device_10de_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0202 = { + 0x0202, pci_device_10de_0202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0203 = { + 0x0203, pci_device_10de_0203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0250 = { + 0x0250, pci_device_10de_0250, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0250, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0251 = { + 0x0251, pci_device_10de_0251, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0251, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0252 = { + 0x0252, pci_device_10de_0252, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0252, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0253 = { + 0x0253, pci_device_10de_0253, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0253, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0258 = { + 0x0258, pci_device_10de_0258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0259 = { + 0x0259, pci_device_10de_0259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_025b = { + 0x025b, pci_device_10de_025b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_025b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0280 = { + 0x0280, pci_device_10de_0280, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0280, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0281 = { + 0x0281, pci_device_10de_0281, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0281, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0282 = { + 0x0282, pci_device_10de_0282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0288 = { + 0x0288, pci_device_10de_0288, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0288, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0289 = { + 0x0289, pci_device_10de_0289, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0289, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0300 = { + 0x0300, pci_device_10de_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0301 = { + 0x0301, pci_device_10de_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0302 = { + 0x0302, pci_device_10de_0302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0308 = { + 0x0308, pci_device_10de_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0309 = { + 0x0309, pci_device_10de_0309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0309, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10df_1ae5 = { + 0x1ae5, pci_device_10df_1ae5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_1ae5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f085 = { + 0xf085, pci_device_10df_f085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f095 = { + 0xf095, pci_device_10df_f095, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f095, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f098 = { + 0xf098, pci_device_10df_f098, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f098, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f700 = { + 0xf700, pci_device_10df_f700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f800 = { + 0xf800, pci_device_10df_f800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f900 = { + 0xf900, pci_device_10df_f900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f980 = { + 0xf980, pci_device_10df_f980, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f980, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_10e0_5026 = { + 0x5026, pci_device_10e0_5026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_5026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_5027 = { + 0x5027, pci_device_10e0_5027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_5027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_5028 = { + 0x5028, pci_device_10e0_5028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_5028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_8849 = { + 0x8849, pci_device_10e0_8849, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_8849, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_8853 = { + 0x8853, pci_device_10e0_8853, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_8853, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_9128 = { + 0x9128, pci_device_10e0_9128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_9128, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10e1_0391 = { + 0x0391, pci_device_10e1_0391, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e1_0391, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e1_690c = { + 0x690c, pci_device_10e1_690c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e1_690c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e1_dc29 = { + 0xdc29, pci_device_10e1_dc29, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e1_dc29, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10e3_0000 = { + 0x0000, pci_device_10e3_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_0860 = { + 0x0860, pci_device_10e3_0860, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_0860, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_0862 = { + 0x0862, pci_device_10e3_0862, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_0862, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10e8_2011 = { + 0x2011, pci_device_10e8_2011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_2011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_4750 = { + 0x4750, pci_device_10e8_4750, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_4750, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_5920 = { + 0x5920, pci_device_10e8_5920, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_5920, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8043 = { + 0x8043, pci_device_10e8_8043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8062 = { + 0x8062, pci_device_10e8_8062, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8062, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_807d = { + 0x807d, pci_device_10e8_807d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_807d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8088 = { + 0x8088, pci_device_10e8_8088, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8088, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8089 = { + 0x8089, pci_device_10e8_8089, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8089, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_809c = { + 0x809c, pci_device_10e8_809c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_809c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_80d7 = { + 0x80d7, pci_device_10e8_80d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_80d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_80d9 = { + 0x80d9, pci_device_10e8_80d9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_80d9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_80da = { + 0x80da, pci_device_10e8_80da, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_80da, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_811a = { + 0x811a, pci_device_10e8_811a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_811a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8170 = { + 0x8170, pci_device_10e8_8170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82db = { + 0x82db, pci_device_10e8_82db, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82db, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_10ea_1680 = { + 0x1680, pci_device_10ea_1680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_1680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_1682 = { + 0x1682, pci_device_10ea_1682, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_1682, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_1683 = { + 0x1683, pci_device_10ea_1683, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_1683, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_2000 = { + 0x2000, pci_device_10ea_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_2010 = { + 0x2010, pci_device_10ea_2010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_2010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_5000 = { + 0x5000, pci_device_10ea_5000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_5000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_5050 = { + 0x5050, pci_device_10ea_5050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_5050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_5202 = { + 0x5202, pci_device_10ea_5202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_5202, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10eb_0101 = { + 0x0101, pci_device_10eb_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10eb_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10eb_8111 = { + 0x8111, pci_device_10eb_8111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10eb_8111, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ec_8029 = { + 0x8029, pci_device_10ec_8029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8129 = { + 0x8129, pci_device_10ec_8129, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8129, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8138 = { + 0x8138, pci_device_10ec_8138, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8138, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8139 = { + 0x8139, pci_device_10ec_8139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8139, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8169 = { + 0x8169, pci_device_10ec_8169, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8169, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8197 = { + 0x8197, pci_device_10ec_8197, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8197, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ed_7310 = { + 0x7310, pci_device_10ed_7310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ed_7310, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ee_3fc0 = { + 0x3fc0, pci_device_10ee_3fc0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc1 = { + 0x3fc1, pci_device_10ee_3fc1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc2 = { + 0x3fc2, pci_device_10ee_3fc2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc3 = { + 0x3fc3, pci_device_10ee_3fc3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc4 = { + 0x3fc4, pci_device_10ee_3fc4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc5 = { + 0x3fc5, pci_device_10ee_3fc5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc5, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ef_8154 = { + 0x8154, pci_device_10ef_8154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ef_8154, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10f5_a001 = { + 0xa001, pci_device_10f5_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10f5_a001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10fa_000c = { + 0x000c, pci_device_10fa_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10fa_000c, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10fb_186f = { + 0x186f, pci_device_10fb_186f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10fb_186f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10fc_0003 = { + 0x0003, pci_device_10fc_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10fc_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10fc_0005 = { + 0x0005, pci_device_10fc_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10fc_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1101_1060 = { + 0x1060, pci_device_1101_1060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_1060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9100 = { + 0x9100, pci_device_1101_9100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9400 = { + 0x9400, pci_device_1101_9400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9401 = { + 0x9401, pci_device_1101_9401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9500 = { + 0x9500, pci_device_1101_9500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9500, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1102_0002 = { + 0x0002, pci_device_1102_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0002, +#else + NULL, +#endif + 0x0401 +}; +static const pciDeviceInfo pci_dev_info_1102_0004 = { + 0x0004, pci_device_1102_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_0006 = { + 0x0006, pci_device_1102_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_4001 = { + 0x4001, pci_device_1102_4001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_4001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_7002 = { + 0x7002, pci_device_1102_7002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_7002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_7003 = { + 0x7003, pci_device_1102_7003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_7003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_7004 = { + 0x7004, pci_device_1102_7004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_7004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_8064 = { + 0x8064, pci_device_1102_8064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_8064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_8938 = { + 0x8938, pci_device_1102_8938, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_8938, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1103_0003 = { + 0x0003, pci_device_1103_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0004 = { + 0x0004, pci_device_1103_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0005 = { + 0x0005, pci_device_1103_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0006 = { + 0x0006, pci_device_1103_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0007 = { + 0x0007, pci_device_1103_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0008 = { + 0x0008, pci_device_1103_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0008, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1105_1105 = { + 0x1105, pci_device_1105_1105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_1105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8300 = { + 0x8300, pci_device_1105_8300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8400 = { + 0x8400, pci_device_1105_8400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8400, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1106_0102 = { + 0x0102, pci_device_1106_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0130 = { + 0x0130, pci_device_1106_0130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0305 = { + 0x0305, pci_device_1106_0305, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0305, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0391 = { + 0x0391, pci_device_1106_0391, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0391, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0501 = { + 0x0501, pci_device_1106_0501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0505 = { + 0x0505, pci_device_1106_0505, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0505, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0561 = { + 0x0561, pci_device_1106_0561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0571 = { + 0x0571, pci_device_1106_0571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0576 = { + 0x0576, pci_device_1106_0576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0576, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0585 = { + 0x0585, pci_device_1106_0585, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0585, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0586 = { + 0x0586, pci_device_1106_0586, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0586, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0595 = { + 0x0595, pci_device_1106_0595, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0595, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0596 = { + 0x0596, pci_device_1106_0596, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0596, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0597 = { + 0x0597, pci_device_1106_0597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0598 = { + 0x0598, pci_device_1106_0598, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0598, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0601 = { + 0x0601, pci_device_1106_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0605 = { + 0x0605, pci_device_1106_0605, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0605, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0680 = { + 0x0680, pci_device_1106_0680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0686 = { + 0x0686, pci_device_1106_0686, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0686, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0691 = { + 0x0691, pci_device_1106_0691, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0691, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0693 = { + 0x0693, pci_device_1106_0693, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0693, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0698 = { + 0x0698, pci_device_1106_0698, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0698, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0926 = { + 0x0926, pci_device_1106_0926, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0926, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1000 = { + 0x1000, pci_device_1106_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1106 = { + 0x1106, pci_device_1106_1106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1571 = { + 0x1571, pci_device_1106_1571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1595 = { + 0x1595, pci_device_1106_1595, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1595, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3038 = { + 0x3038, pci_device_1106_3038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3040 = { + 0x3040, pci_device_1106_3040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3043 = { + 0x3043, pci_device_1106_3043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3044 = { + 0x3044, pci_device_1106_3044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3050 = { + 0x3050, pci_device_1106_3050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3051 = { + 0x3051, pci_device_1106_3051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3057 = { + 0x3057, pci_device_1106_3057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3058 = { + 0x3058, pci_device_1106_3058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3059 = { + 0x3059, pci_device_1106_3059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3065 = { + 0x3065, pci_device_1106_3065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3068 = { + 0x3068, pci_device_1106_3068, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3068, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3074 = { + 0x3074, pci_device_1106_3074, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3074, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3091 = { + 0x3091, pci_device_1106_3091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3099 = { + 0x3099, pci_device_1106_3099, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3099, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3101 = { + 0x3101, pci_device_1106_3101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3102 = { + 0x3102, pci_device_1106_3102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3103 = { + 0x3103, pci_device_1106_3103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3104 = { + 0x3104, pci_device_1106_3104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3106 = { + 0x3106, pci_device_1106_3106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3109 = { + 0x3109, pci_device_1106_3109, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3109, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3112 = { + 0x3112, pci_device_1106_3112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3116 = { + 0x3116, pci_device_1106_3116, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3116, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3122 = { + 0x3122, pci_device_1106_3122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3123 = { + 0x3123, pci_device_1106_3123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3128 = { + 0x3128, pci_device_1106_3128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3128, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3133 = { + 0x3133, pci_device_1106_3133, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3133, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3147 = { + 0x3147, pci_device_1106_3147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3148 = { + 0x3148, pci_device_1106_3148, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3148, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3156 = { + 0x3156, pci_device_1106_3156, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3156, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3168 = { + 0x3168, pci_device_1106_3168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3177 = { + 0x3177, pci_device_1106_3177, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3177, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3189 = { + 0x3189, pci_device_1106_3189, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3189, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5030 = { + 0x5030, pci_device_1106_5030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_6100 = { + 0x6100, pci_device_1106_6100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_6100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8231 = { + 0x8231, pci_device_1106_8231, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8231, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8235 = { + 0x8235, pci_device_1106_8235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8305 = { + 0x8305, pci_device_1106_8305, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8305, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8391 = { + 0x8391, pci_device_1106_8391, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8391, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8501 = { + 0x8501, pci_device_1106_8501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8596 = { + 0x8596, pci_device_1106_8596, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8596, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8597 = { + 0x8597, pci_device_1106_8597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8598 = { + 0x8598, pci_device_1106_8598, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8598, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8601 = { + 0x8601, pci_device_1106_8601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8605 = { + 0x8605, pci_device_1106_8605, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8605, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8691 = { + 0x8691, pci_device_1106_8691, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8691, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8693 = { + 0x8693, pci_device_1106_8693, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8693, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b091 = { + 0xb091, pci_device_1106_b091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b099 = { + 0xb099, pci_device_1106_b099, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b099, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b101 = { + 0xb101, pci_device_1106_b101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b102 = { + 0xb102, pci_device_1106_b102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b103 = { + 0xb103, pci_device_1106_b103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b112 = { + 0xb112, pci_device_1106_b112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b168 = { + 0xb168, pci_device_1106_b168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b168, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1107_0576 = { + 0x0576, pci_device_1107_0576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1107_0576, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1108_0100 = { + 0x0100, pci_device_1108_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0101 = { + 0x0101, pci_device_1108_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0105 = { + 0x0105, pci_device_1108_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0108 = { + 0x0108, pci_device_1108_0108, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0108, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0138 = { + 0x0138, pci_device_1108_0138, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0138, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0139 = { + 0x0139, pci_device_1108_0139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0139, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_013c = { + 0x013c, pci_device_1108_013c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_013c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_013d = { + 0x013d, pci_device_1108_013d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_013d, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1109_1400 = { + 0x1400, pci_device_1109_1400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1109_1400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_110a_0002 = { + 0x0002, pci_device_110a_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_0005 = { + 0x0005, pci_device_110a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_2102 = { + 0x2102, pci_device_110a_2102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_2102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_4942 = { + 0x4942, pci_device_110a_4942, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_4942, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_6120 = { + 0x6120, pci_device_110a_6120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_6120, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_110b_0001 = { + 0x0001, pci_device_110b_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110b_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110b_0004 = { + 0x0004, pci_device_110b_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110b_0004, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1110_6037 = { + 0x6037, pci_device_1110_6037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1110_6037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1110_6073 = { + 0x6073, pci_device_1110_6073, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1110_6073, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1112_2200 = { + 0x2200, pci_device_1112_2200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1112_2200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1112_2300 = { + 0x2300, pci_device_1112_2300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1112_2300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1112_2340 = { + 0x2340, pci_device_1112_2340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1112_2340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1112_2400 = { + 0x2400, pci_device_1112_2400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1112_2400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1113_1211 = { + 0x1211, pci_device_1113_1211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_1211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_1216 = { + 0x1216, pci_device_1113_1216, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_1216, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_1217 = { + 0x1217, pci_device_1113_1217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_1217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_5105 = { + 0x5105, pci_device_1113_5105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_5105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_9211 = { + 0x9211, pci_device_1113_9211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_9211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_9511 = { + 0x9511, pci_device_1113_9511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_9511, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1116_0022 = { + 0x0022, pci_device_1116_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0023 = { + 0x0023, pci_device_1116_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0024 = { + 0x0024, pci_device_1116_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0025 = { + 0x0025, pci_device_1116_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0026 = { + 0x0026, pci_device_1116_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0027 = { + 0x0027, pci_device_1116_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0028 = { + 0x0028, pci_device_1116_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0028, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1117_9500 = { + 0x9500, pci_device_1117_9500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1117_9500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1117_9501 = { + 0x9501, pci_device_1117_9501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1117_9501, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1119_0000 = { + 0x0000, pci_device_1119_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0001 = { + 0x0001, pci_device_1119_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0002 = { + 0x0002, pci_device_1119_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0003 = { + 0x0003, pci_device_1119_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0004 = { + 0x0004, pci_device_1119_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0005 = { + 0x0005, pci_device_1119_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0006 = { + 0x0006, pci_device_1119_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0007 = { + 0x0007, pci_device_1119_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0008 = { + 0x0008, pci_device_1119_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0009 = { + 0x0009, pci_device_1119_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_000a = { + 0x000a, pci_device_1119_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_000b = { + 0x000b, pci_device_1119_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_000c = { + 0x000c, pci_device_1119_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_000d = { + 0x000d, pci_device_1119_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0100 = { + 0x0100, pci_device_1119_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0101 = { + 0x0101, pci_device_1119_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0102 = { + 0x0102, pci_device_1119_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0103 = { + 0x0103, pci_device_1119_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0104 = { + 0x0104, pci_device_1119_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0105 = { + 0x0105, pci_device_1119_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0110 = { + 0x0110, pci_device_1119_0110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0111 = { + 0x0111, pci_device_1119_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0112 = { + 0x0112, pci_device_1119_0112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0113 = { + 0x0113, pci_device_1119_0113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0114 = { + 0x0114, pci_device_1119_0114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0115 = { + 0x0115, pci_device_1119_0115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0115, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0118 = { + 0x0118, pci_device_1119_0118, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0118, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0119 = { + 0x0119, pci_device_1119_0119, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0119, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_011a = { + 0x011a, pci_device_1119_011a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_011a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_011b = { + 0x011b, pci_device_1119_011b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_011b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0120 = { + 0x0120, pci_device_1119_0120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0121 = { + 0x0121, pci_device_1119_0121, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0121, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0122 = { + 0x0122, pci_device_1119_0122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0123 = { + 0x0123, pci_device_1119_0123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0124 = { + 0x0124, pci_device_1119_0124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0124, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0125 = { + 0x0125, pci_device_1119_0125, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0125, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0136 = { + 0x0136, pci_device_1119_0136, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0136, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0137 = { + 0x0137, pci_device_1119_0137, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0137, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0138 = { + 0x0138, pci_device_1119_0138, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0138, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0139 = { + 0x0139, pci_device_1119_0139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0139, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013a = { + 0x013a, pci_device_1119_013a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013b = { + 0x013b, pci_device_1119_013b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013c = { + 0x013c, pci_device_1119_013c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013d = { + 0x013d, pci_device_1119_013d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013e = { + 0x013e, pci_device_1119_013e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013f = { + 0x013f, pci_device_1119_013f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0166 = { + 0x0166, pci_device_1119_0166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0167 = { + 0x0167, pci_device_1119_0167, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0167, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0168 = { + 0x0168, pci_device_1119_0168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0169 = { + 0x0169, pci_device_1119_0169, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0169, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016a = { + 0x016a, pci_device_1119_016a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016b = { + 0x016b, pci_device_1119_016b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016c = { + 0x016c, pci_device_1119_016c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016d = { + 0x016d, pci_device_1119_016d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016e = { + 0x016e, pci_device_1119_016e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016f = { + 0x016f, pci_device_1119_016f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01d6 = { + 0x01d6, pci_device_1119_01d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01d7 = { + 0x01d7, pci_device_1119_01d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01f6 = { + 0x01f6, pci_device_1119_01f6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01f6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01f7 = { + 0x01f7, pci_device_1119_01f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01fc = { + 0x01fc, pci_device_1119_01fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01fd = { + 0x01fd, pci_device_1119_01fd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01fd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01fe = { + 0x01fe, pci_device_1119_01fe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01fe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01ff = { + 0x01ff, pci_device_1119_01ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0210 = { + 0x0210, pci_device_1119_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0211 = { + 0x0211, pci_device_1119_0211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0260 = { + 0x0260, pci_device_1119_0260, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0260, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0261 = { + 0x0261, pci_device_1119_0261, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0261, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0300 = { + 0x0300, pci_device_1119_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0300, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_111a_0000 = { + 0x0000, pci_device_111a_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_0002 = { + 0x0002, pci_device_111a_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_0003 = { + 0x0003, pci_device_111a_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_0005 = { + 0x0005, pci_device_111a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_0007 = { + 0x0007, pci_device_111a_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0007, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_111c_0001 = { + 0x0001, pci_device_111c_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111c_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_111d_0001 = { + 0x0001, pci_device_111d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111d_0003 = { + 0x0003, pci_device_111d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111d_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_111f_4a47 = { + 0x4a47, pci_device_111f_4a47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111f_4a47, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111f_5243 = { + 0x5243, pci_device_111f_5243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111f_5243, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1127_0200 = { + 0x0200, pci_device_1127_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0210 = { + 0x0210, pci_device_1127_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0250 = { + 0x0250, pci_device_1127_0250, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0250, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0300 = { + 0x0300, pci_device_1127_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0310 = { + 0x0310, pci_device_1127_0310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0400 = { + 0x0400, pci_device_1127_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_112f_0000 = { + 0x0000, pci_device_112f_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_112f_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_112f_0001 = { + 0x0001, pci_device_112f_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_112f_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1131_1561 = { + 0x1561, pci_device_1131_1561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_1561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_1562 = { + 0x1562, pci_device_1131_1562, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_1562, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_3400 = { + 0x3400, pci_device_1131_3400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_3400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7130 = { + 0x7130, pci_device_1131_7130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7133 = { + 0x7133, pci_device_1131_7133, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7133, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7134 = { + 0x7134, pci_device_1131_7134, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7134, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7135 = { + 0x7135, pci_device_1131_7135, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7135, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7145 = { + 0x7145, pci_device_1131_7145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7146 = { + 0x7146, pci_device_1131_7146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7146, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1133_7901 = { + 0x7901, pci_device_1133_7901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7902 = { + 0x7902, pci_device_1133_7902, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7902, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7911 = { + 0x7911, pci_device_1133_7911, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7911, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7912 = { + 0x7912, pci_device_1133_7912, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7912, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7941 = { + 0x7941, pci_device_1133_7941, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7941, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7942 = { + 0x7942, pci_device_1133_7942, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7942, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7943 = { + 0x7943, pci_device_1133_7943, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7943, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7944 = { + 0x7944, pci_device_1133_7944, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7944, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_b921 = { + 0xb921, pci_device_1133_b921, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_b921, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_b922 = { + 0xb922, pci_device_1133_b922, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_b922, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_b923 = { + 0xb923, pci_device_1133_b923, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_b923, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e001 = { + 0xe001, pci_device_1133_e001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e002 = { + 0xe002, pci_device_1133_e002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e003 = { + 0xe003, pci_device_1133_e003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e004 = { + 0xe004, pci_device_1133_e004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e005 = { + 0xe005, pci_device_1133_e005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e00b = { + 0xe00b, pci_device_1133_e00b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e00b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e010 = { + 0xe010, pci_device_1133_e010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e012 = { + 0xe012, pci_device_1133_e012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e014 = { + 0xe014, pci_device_1133_e014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e018 = { + 0xe018, pci_device_1133_e018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e018, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1134_0001 = { + 0x0001, pci_device_1134_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1134_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1135_0001 = { + 0x0001, pci_device_1135_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1135_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1138_8905 = { + 0x8905, pci_device_1138_8905, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1138_8905, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1139_0001 = { + 0x0001, pci_device_1139_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1139_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_113c_0000 = { + 0x0000, pci_device_113c_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0001 = { + 0x0001, pci_device_113c_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0911 = { + 0x0911, pci_device_113c_0911, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0911, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0912 = { + 0x0912, pci_device_113c_0912, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0912, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0913 = { + 0x0913, pci_device_113c_0913, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0913, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0914 = { + 0x0914, pci_device_113c_0914, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0914, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_113f_0808 = { + 0x0808, pci_device_113f_0808, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_0808, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_1010 = { + 0x1010, pci_device_113f_1010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_1010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_80c0 = { + 0x80c0, pci_device_113f_80c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_80c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_80c4 = { + 0x80c4, pci_device_113f_80c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_80c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_80c8 = { + 0x80c8, pci_device_113f_80c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_80c8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_8888 = { + 0x8888, pci_device_113f_8888, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_8888, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_9090 = { + 0x9090, pci_device_113f_9090, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_9090, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1142_3210 = { + 0x3210, pci_device_1142_3210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_3210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1142_6422 = { + 0x6422, pci_device_1142_6422, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_6422, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1142_6424 = { + 0x6424, pci_device_1142_6424, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_6424, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1142_6425 = { + 0x6425, pci_device_1142_6425, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_6425, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1142_643d = { + 0x643d, pci_device_1142_643d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_643d, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1144_0001 = { + 0x0001, pci_device_1144_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1144_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1145_8007 = { + 0x8007, pci_device_1145_8007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_8007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f007 = { + 0xf007, pci_device_1145_f007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f010 = { + 0xf010, pci_device_1145_f010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f012 = { + 0xf012, pci_device_1145_f012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f013 = { + 0xf013, pci_device_1145_f013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f015 = { + 0xf015, pci_device_1145_f015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f015, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1148_4000 = { + 0x4000, pci_device_1148_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4200 = { + 0x4200, pci_device_1148_4200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4300 = { + 0x4300, pci_device_1148_4300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4320 = { + 0x4320, pci_device_1148_4320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4400 = { + 0x4400, pci_device_1148_4400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_114a_5579 = { + 0x5579, pci_device_114a_5579, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114a_5579, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114a_5587 = { + 0x5587, pci_device_114a_5587, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114a_5587, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114a_6504 = { + 0x6504, pci_device_114a_6504, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114a_6504, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114a_7587 = { + 0x7587, pci_device_114a_7587, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114a_7587, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_114f_0002 = { + 0x0002, pci_device_114f_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0003 = { + 0x0003, pci_device_114f_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0004 = { + 0x0004, pci_device_114f_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0005 = { + 0x0005, pci_device_114f_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0006 = { + 0x0006, pci_device_114f_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0009 = { + 0x0009, pci_device_114f_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_000a = { + 0x000a, pci_device_114f_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_000c = { + 0x000c, pci_device_114f_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_000d = { + 0x000d, pci_device_114f_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0011 = { + 0x0011, pci_device_114f_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0012 = { + 0x0012, pci_device_114f_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0013 = { + 0x0013, pci_device_114f_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0014 = { + 0x0014, pci_device_114f_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0015 = { + 0x0015, pci_device_114f_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0016 = { + 0x0016, pci_device_114f_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0017 = { + 0x0017, pci_device_114f_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_001a = { + 0x001a, pci_device_114f_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_001b = { + 0x001b, pci_device_114f_001b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_001b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_001d = { + 0x001d, pci_device_114f_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0023 = { + 0x0023, pci_device_114f_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0024 = { + 0x0024, pci_device_114f_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0026 = { + 0x0026, pci_device_114f_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0027 = { + 0x0027, pci_device_114f_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0034 = { + 0x0034, pci_device_114f_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0035 = { + 0x0035, pci_device_114f_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0040 = { + 0x0040, pci_device_114f_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0042 = { + 0x0042, pci_device_114f_0042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0070 = { + 0x0070, pci_device_114f_0070, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0070, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0071 = { + 0x0071, pci_device_114f_0071, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0071, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0072 = { + 0x0072, pci_device_114f_0072, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0072, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0073 = { + 0x0073, pci_device_114f_0073, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0073, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_6001 = { + 0x6001, pci_device_114f_6001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_6001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1158_3011 = { + 0x3011, pci_device_1158_3011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1158_3011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1158_9050 = { + 0x9050, pci_device_1158_9050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1158_9050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1158_9051 = { + 0x9051, pci_device_1158_9051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1158_9051, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1159_0001 = { + 0x0001, pci_device_1159_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1159_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_115d_0003 = { + 0x0003, pci_device_115d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_0005 = { + 0x0005, pci_device_115d_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_0007 = { + 0x0007, pci_device_115d_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_000b = { + 0x000b, pci_device_115d_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_000c = { + 0x000c, pci_device_115d_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_000f = { + 0x000f, pci_device_115d_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_0101 = { + 0x0101, pci_device_115d_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_0103 = { + 0x0103, pci_device_115d_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0103, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1163_0001 = { + 0x0001, pci_device_1163_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1163_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1163_2000 = { + 0x2000, pci_device_1163_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1163_2000, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1165_0001 = { + 0x0001, pci_device_1165_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1165_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1166_0005 = { + 0x0005, pci_device_1166_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0007 = { + 0x0007, pci_device_1166_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0008 = { + 0x0008, pci_device_1166_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0009 = { + 0x0009, pci_device_1166_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0010 = { + 0x0010, pci_device_1166_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0011 = { + 0x0011, pci_device_1166_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0012 = { + 0x0012, pci_device_1166_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0013 = { + 0x0013, pci_device_1166_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0014 = { + 0x0014, pci_device_1166_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0015 = { + 0x0015, pci_device_1166_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0016 = { + 0x0016, pci_device_1166_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0017 = { + 0x0017, pci_device_1166_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0200 = { + 0x0200, pci_device_1166_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0201 = { + 0x0201, pci_device_1166_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0203 = { + 0x0203, pci_device_1166_0203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0211 = { + 0x0211, pci_device_1166_0211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0212 = { + 0x0212, pci_device_1166_0212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0213 = { + 0x0213, pci_device_1166_0213, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0213, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0220 = { + 0x0220, pci_device_1166_0220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0221 = { + 0x0221, pci_device_1166_0221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0221, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0225 = { + 0x0225, pci_device_1166_0225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0227 = { + 0x0227, pci_device_1166_0227, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0227, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_116a_6100 = { + 0x6100, pci_device_116a_6100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_116a_6100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_116a_6800 = { + 0x6800, pci_device_116a_6800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_116a_6800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_116a_7100 = { + 0x7100, pci_device_116a_7100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_116a_7100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_116a_7800 = { + 0x7800, pci_device_116a_7800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_116a_7800, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1178_afa1 = { + 0xafa1, pci_device_1178_afa1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1178_afa1, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1179_0103 = { + 0x0103, pci_device_1179_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0404 = { + 0x0404, pci_device_1179_0404, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0404, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0406 = { + 0x0406, pci_device_1179_0406, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0406, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0407 = { + 0x0407, pci_device_1179_0407, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0407, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0601 = { + 0x0601, pci_device_1179_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0603 = { + 0x0603, pci_device_1179_0603, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0603, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_060a = { + 0x060a, pci_device_1179_060a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_060a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_060f = { + 0x060f, pci_device_1179_060f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_060f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0617 = { + 0x0617, pci_device_1179_0617, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0617, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0618 = { + 0x0618, pci_device_1179_0618, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0618, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0701 = { + 0x0701, pci_device_1179_0701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0804 = { + 0x0804, pci_device_1179_0804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0805 = { + 0x0805, pci_device_1179_0805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0d01 = { + 0x0d01, pci_device_1179_0d01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0d01, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1180_0465 = { + 0x0465, pci_device_1180_0465, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0465, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0466 = { + 0x0466, pci_device_1180_0466, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0466, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0475 = { + 0x0475, pci_device_1180_0475, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0475, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0476 = { + 0x0476, pci_device_1180_0476, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0476, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0477 = { + 0x0477, pci_device_1180_0477, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0477, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0478 = { + 0x0478, pci_device_1180_0478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0522 = { + 0x0522, pci_device_1180_0522, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0522, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0551 = { + 0x0551, pci_device_1180_0551, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0551, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0552 = { + 0x0552, pci_device_1180_0552, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0552, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1186_0100 = { + 0x0100, pci_device_1186_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1002 = { + 0x1002, pci_device_1186_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1300 = { + 0x1300, pci_device_1186_1300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1340 = { + 0x1340, pci_device_1186_1340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1561 = { + 0x1561, pci_device_1186_1561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_4000 = { + 0x4000, pci_device_1186_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_4000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_118c_0014 = { + 0x0014, pci_device_118c_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118c_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118c_1117 = { + 0x1117, pci_device_118c_1117, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118c_1117, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_118d_0001 = { + 0x0001, pci_device_118d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0012 = { + 0x0012, pci_device_118d_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0014 = { + 0x0014, pci_device_118d_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0024 = { + 0x0024, pci_device_118d_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0044 = { + 0x0044, pci_device_118d_0044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0112 = { + 0x0112, pci_device_118d_0112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0114 = { + 0x0114, pci_device_118d_0114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0124 = { + 0x0124, pci_device_118d_0124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0124, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0144 = { + 0x0144, pci_device_118d_0144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0212 = { + 0x0212, pci_device_118d_0212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0214 = { + 0x0214, pci_device_118d_0214, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0214, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0224 = { + 0x0224, pci_device_118d_0224, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0224, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0244 = { + 0x0244, pci_device_118d_0244, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0244, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0312 = { + 0x0312, pci_device_118d_0312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0314 = { + 0x0314, pci_device_118d_0314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0324 = { + 0x0324, pci_device_118d_0324, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0324, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0344 = { + 0x0344, pci_device_118d_0344, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0344, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1190_c731 = { + 0xc731, pci_device_1190_c731, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1190_c731, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1191_0003 = { + 0x0003, pci_device_1191_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0004 = { + 0x0004, pci_device_1191_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0005 = { + 0x0005, pci_device_1191_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0006 = { + 0x0006, pci_device_1191_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0007 = { + 0x0007, pci_device_1191_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0008 = { + 0x0008, pci_device_1191_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0009 = { + 0x0009, pci_device_1191_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8002 = { + 0x8002, pci_device_1191_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8010 = { + 0x8010, pci_device_1191_8010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8020 = { + 0x8020, pci_device_1191_8020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8030 = { + 0x8030, pci_device_1191_8030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8040 = { + 0x8040, pci_device_1191_8040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8050 = { + 0x8050, pci_device_1191_8050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8050, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1193_0001 = { + 0x0001, pci_device_1193_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1193_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1193_0002 = { + 0x0002, pci_device_1193_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1193_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_119b_1221 = { + 0x1221, pci_device_119b_1221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_119b_1221, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_119e_0001 = { + 0x0001, pci_device_119e_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_119e_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_119e_0003 = { + 0x0003, pci_device_119e_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_119e_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11a9_4240 = { + 0x4240, pci_device_11a9_4240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11a9_4240, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11ab_0146 = { + 0x0146, pci_device_11ab_0146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_0146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4611 = { + 0x4611, pci_device_11ab_4611, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4611, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4620 = { + 0x4620, pci_device_11ab_4620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4801 = { + 0x4801, pci_device_11ab_4801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_f003 = { + 0xf003, pci_device_11ab_f003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_f003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11ad_0002 = { + 0x0002, pci_device_11ad_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ad_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ad_c115 = { + 0xc115, pci_device_11ad_c115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ad_c115, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11b0_0002 = { + 0x0002, pci_device_11b0_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b0_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11b0_0292 = { + 0x0292, pci_device_11b0_0292, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b0_0292, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11b0_0960 = { + 0x0960, pci_device_11b0_0960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b0_0960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11b0_c960 = { + 0xc960, pci_device_11b0_c960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b0_c960, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11b8_0001 = { + 0x0001, pci_device_11b8_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b8_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11b9_c0ed = { + 0xc0ed, pci_device_11b9_c0ed, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b9_c0ed, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11bc_0001 = { + 0x0001, pci_device_11bc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11bc_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11c1_0440 = { + 0x0440, pci_device_11c1_0440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0441 = { + 0x0441, pci_device_11c1_0441, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0441, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0442 = { + 0x0442, pci_device_11c1_0442, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0442, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0443 = { + 0x0443, pci_device_11c1_0443, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0443, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0444 = { + 0x0444, pci_device_11c1_0444, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0444, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0445 = { + 0x0445, pci_device_11c1_0445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0446 = { + 0x0446, pci_device_11c1_0446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0447 = { + 0x0447, pci_device_11c1_0447, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0447, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0448 = { + 0x0448, pci_device_11c1_0448, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0448, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0449 = { + 0x0449, pci_device_11c1_0449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044a = { + 0x044a, pci_device_11c1_044a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044b = { + 0x044b, pci_device_11c1_044b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044c = { + 0x044c, pci_device_11c1_044c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044d = { + 0x044d, pci_device_11c1_044d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044e = { + 0x044e, pci_device_11c1_044e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044f = { + 0x044f, pci_device_11c1_044f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0450 = { + 0x0450, pci_device_11c1_0450, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0450, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0451 = { + 0x0451, pci_device_11c1_0451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0452 = { + 0x0452, pci_device_11c1_0452, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0452, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0453 = { + 0x0453, pci_device_11c1_0453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0454 = { + 0x0454, pci_device_11c1_0454, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0454, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0455 = { + 0x0455, pci_device_11c1_0455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0456 = { + 0x0456, pci_device_11c1_0456, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0456, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0457 = { + 0x0457, pci_device_11c1_0457, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0457, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0458 = { + 0x0458, pci_device_11c1_0458, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0458, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0459 = { + 0x0459, pci_device_11c1_0459, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0459, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_045a = { + 0x045a, pci_device_11c1_045a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_045a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_045c = { + 0x045c, pci_device_11c1_045c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_045c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0461 = { + 0x0461, pci_device_11c1_0461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0462 = { + 0x0462, pci_device_11c1_0462, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0462, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0480 = { + 0x0480, pci_device_11c1_0480, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0480, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_5801 = { + 0x5801, pci_device_11c1_5801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_5801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_5802 = { + 0x5802, pci_device_11c1_5802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_5802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_5803 = { + 0x5803, pci_device_11c1_5803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_5803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_5811 = { + 0x5811, pci_device_11c1_5811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_5811, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11c8_0658 = { + 0x0658, pci_device_11c8_0658, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c8_0658, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c8_d665 = { + 0xd665, pci_device_11c8_d665, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c8_d665, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c8_d667 = { + 0xd667, pci_device_11c8_d667, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c8_d667, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11c9_0010 = { + 0x0010, pci_device_11c9_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c9_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c9_0011 = { + 0x0011, pci_device_11c9_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c9_0011, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11cb_2000 = { + 0x2000, pci_device_11cb_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11cb_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11cb_4000 = { + 0x4000, pci_device_11cb_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11cb_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11cb_8000 = { + 0x8000, pci_device_11cb_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11cb_8000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11d1_01f7 = { + 0x01f7, pci_device_11d1_01f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d1_01f7, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11d4_1805 = { + 0x1805, pci_device_11d4_1805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d4_1805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11d4_1889 = { + 0x1889, pci_device_11d4_1889, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d4_1889, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11d5_0115 = { + 0x0115, pci_device_11d5_0115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d5_0115, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11d5_0117 = { + 0x0117, pci_device_11d5_0117, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d5_0117, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11de_6057 = { + 0x6057, pci_device_11de_6057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11de_6057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11de_6120 = { + 0x6120, pci_device_11de_6120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11de_6120, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11e3_5030 = { + 0x5030, pci_device_11e3_5030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11e3_5030, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11f0_4231 = { + 0x4231, pci_device_11f0_4231, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4231, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4232 = { + 0x4232, pci_device_11f0_4232, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4232, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4233 = { + 0x4233, pci_device_11f0_4233, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4233, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4234 = { + 0x4234, pci_device_11f0_4234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4234, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4235 = { + 0x4235, pci_device_11f0_4235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4236 = { + 0x4236, pci_device_11f0_4236, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4236, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4731 = { + 0x4731, pci_device_11f0_4731, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4731, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11f4_2915 = { + 0x2915, pci_device_11f4_2915, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f4_2915, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11f6_0112 = { + 0x0112, pci_device_11f6_0112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_0112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_0113 = { + 0x0113, pci_device_11f6_0113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_0113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_1401 = { + 0x1401, pci_device_11f6_1401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_1401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_2011 = { + 0x2011, pci_device_11f6_2011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_2011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_2201 = { + 0x2201, pci_device_11f6_2201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_2201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_9881 = { + 0x9881, pci_device_11f6_9881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_9881, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11f8_7375 = { + 0x7375, pci_device_11f8_7375, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f8_7375, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11fe_0001 = { + 0x0001, pci_device_11fe_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0002 = { + 0x0002, pci_device_11fe_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0003 = { + 0x0003, pci_device_11fe_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0004 = { + 0x0004, pci_device_11fe_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0005 = { + 0x0005, pci_device_11fe_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0006 = { + 0x0006, pci_device_11fe_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0007 = { + 0x0007, pci_device_11fe_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0008 = { + 0x0008, pci_device_11fe_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0009 = { + 0x0009, pci_device_11fe_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000a = { + 0x000a, pci_device_11fe_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000b = { + 0x000b, pci_device_11fe_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000c = { + 0x000c, pci_device_11fe_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_8015 = { + 0x8015, pci_device_11fe_8015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_8015, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1202_4300 = { + 0x4300, pci_device_1202_4300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1202_4300, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1208_4853 = { + 0x4853, pci_device_1208_4853, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1208_4853, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_120e_0100 = { + 0x0100, pci_device_120e_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0101 = { + 0x0101, pci_device_120e_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0102 = { + 0x0102, pci_device_120e_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0103 = { + 0x0103, pci_device_120e_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0104 = { + 0x0104, pci_device_120e_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0105 = { + 0x0105, pci_device_120e_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0200 = { + 0x0200, pci_device_120e_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0201 = { + 0x0201, pci_device_120e_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0300 = { + 0x0300, pci_device_120e_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0301 = { + 0x0301, pci_device_120e_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0310 = { + 0x0310, pci_device_120e_0310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0311 = { + 0x0311, pci_device_120e_0311, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0311, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0320 = { + 0x0320, pci_device_120e_0320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0321 = { + 0x0321, pci_device_120e_0321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0400 = { + 0x0400, pci_device_120e_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_120f_0001 = { + 0x0001, pci_device_120f_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120f_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1217_6729 = { + 0x6729, pci_device_1217_6729, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6729, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_673a = { + 0x673a, pci_device_1217_673a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_673a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6832 = { + 0x6832, pci_device_1217_6832, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6832, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6836 = { + 0x6836, pci_device_1217_6836, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6836, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6872 = { + 0x6872, pci_device_1217_6872, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6872, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6925 = { + 0x6925, pci_device_1217_6925, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6925, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6933 = { + 0x6933, pci_device_1217_6933, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6933, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6972 = { + 0x6972, pci_device_1217_6972, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6972, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_121a_0001 = { + 0x0001, pci_device_121a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0002 = { + 0x0002, pci_device_121a_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0003 = { + 0x0003, pci_device_121a_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0004 = { + 0x0004, pci_device_121a_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0005 = { + 0x0005, pci_device_121a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0009 = { + 0x0009, pci_device_121a_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0057 = { + 0x0057, pci_device_121a_0057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0057, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1220_1220 = { + 0x1220, pci_device_1220_1220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1220_1220, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1223_0003 = { + 0x0003, pci_device_1223_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_0004 = { + 0x0004, pci_device_1223_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_0005 = { + 0x0005, pci_device_1223_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_0008 = { + 0x0008, pci_device_1223_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_0009 = { + 0x0009, pci_device_1223_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000a = { + 0x000a, pci_device_1223_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000b = { + 0x000b, pci_device_1223_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000c = { + 0x000c, pci_device_1223_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000d = { + 0x000d, pci_device_1223_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000e = { + 0x000e, pci_device_1223_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000e, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_122d_1206 = { + 0x1206, pci_device_122d_1206, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_122d_1206, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_122d_50dc = { + 0x50dc, pci_device_122d_50dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_122d_50dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_122d_80da = { + 0x80da, pci_device_122d_80da, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_122d_80da, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1236_0000 = { + 0x0000, pci_device_1236_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1236_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1236_6401 = { + 0x6401, pci_device_1236_6401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1236_6401, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_123d_0000 = { + 0x0000, pci_device_123d_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123d_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_123d_0002 = { + 0x0002, pci_device_123d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123d_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_123d_0003 = { + 0x0003, pci_device_123d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123d_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_123f_00e4 = { + 0x00e4, pci_device_123f_00e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123f_00e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_123f_8120 = { + 0x8120, pci_device_123f_8120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123f_8120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_123f_8888 = { + 0x8888, pci_device_123f_8888, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123f_8888, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1242_1560 = { + 0x1560, pci_device_1242_1560, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1242_1560, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1242_4643 = { + 0x4643, pci_device_1242_4643, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1242_4643, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1244_0700 = { + 0x0700, pci_device_1244_0700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_0700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_0800 = { + 0x0800, pci_device_1244_0800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_0800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_0a00 = { + 0x0a00, pci_device_1244_0a00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_0a00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_0e00 = { + 0x0e00, pci_device_1244_0e00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_0e00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_1100 = { + 0x1100, pci_device_1244_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_1200 = { + 0x1200, pci_device_1244_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_1200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_124b_0040 = { + 0x0040, pci_device_124b_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124b_0040, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_124d_0000 = { + 0x0000, pci_device_124d_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124d_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_124d_0002 = { + 0x0002, pci_device_124d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124d_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_124d_0003 = { + 0x0003, pci_device_124d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124d_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_124d_0004 = { + 0x0004, pci_device_124d_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124d_0004, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_124f_0041 = { + 0x0041, pci_device_124f_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124f_0041, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1255_1110 = { + 0x1110, pci_device_1255_1110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_1110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1255_1210 = { + 0x1210, pci_device_1255_1210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_1210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1255_2110 = { + 0x2110, pci_device_1255_2110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_2110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1255_2120 = { + 0x2120, pci_device_1255_2120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_2120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1255_2130 = { + 0x2130, pci_device_1255_2130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_2130, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1256_4201 = { + 0x4201, pci_device_1256_4201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1256_4201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1256_4401 = { + 0x4401, pci_device_1256_4401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1256_4401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1256_5201 = { + 0x5201, pci_device_1256_5201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1256_5201, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1259_2560 = { + 0x2560, pci_device_1259_2560, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1259_2560, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_125b_1400 = { + 0x1400, pci_device_125b_1400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125b_1400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_125c_0640 = { + 0x0640, pci_device_125c_0640, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125c_0640, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_125d_0000 = { + 0x0000, pci_device_125d_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1948 = { + 0x1948, pci_device_125d_1948, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1948, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1968 = { + 0x1968, pci_device_125d_1968, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1968, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1969 = { + 0x1969, pci_device_125d_1969, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1969, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1978 = { + 0x1978, pci_device_125d_1978, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1978, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1988 = { + 0x1988, pci_device_125d_1988, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1988, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1989 = { + 0x1989, pci_device_125d_1989, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1989, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1998 = { + 0x1998, pci_device_125d_1998, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1998, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1999 = { + 0x1999, pci_device_125d_1999, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1999, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_199a = { + 0x199a, pci_device_125d_199a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_199a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_199b = { + 0x199b, pci_device_125d_199b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_199b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_2808 = { + 0x2808, pci_device_125d_2808, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_2808, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_2838 = { + 0x2838, pci_device_125d_2838, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_2838, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_2898 = { + 0x2898, pci_device_125d_2898, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_2898, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1260_3873 = { + 0x3873, pci_device_1260_3873, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_3873, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_8130 = { + 0x8130, pci_device_1260_8130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_8130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_8131 = { + 0x8131, pci_device_1260_8131, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_8131, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1266_0001 = { + 0x0001, pci_device_1266_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1266_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1266_1910 = { + 0x1910, pci_device_1266_1910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1266_1910, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1267_5352 = { + 0x5352, pci_device_1267_5352, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1267_5352, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1267_5a4b = { + 0x5a4b, pci_device_1267_5a4b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1267_5a4b, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_126f_0710 = { + 0x0710, pci_device_126f_0710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0712 = { + 0x0712, pci_device_126f_0712, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0712, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0720 = { + 0x0720, pci_device_126f_0720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0720, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0810 = { + 0x0810, pci_device_126f_0810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0811 = { + 0x0811, pci_device_126f_0811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0820 = { + 0x0820, pci_device_126f_0820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0820, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0910 = { + 0x0910, pci_device_126f_0910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0910, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1273_0002 = { + 0x0002, pci_device_1273_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1273_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1274_1371 = { + 0x1371, pci_device_1274_1371, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1274_1371, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1274_5000 = { + 0x5000, pci_device_1274_5000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1274_5000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1274_5880 = { + 0x5880, pci_device_1274_5880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1274_5880, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1278_0701 = { + 0x0701, pci_device_1278_0701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1278_0701, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1279_0295 = { + 0x0295, pci_device_1279_0295, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0295, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0395 = { + 0x0395, pci_device_1279_0395, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0395, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0396 = { + 0x0396, pci_device_1279_0396, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0396, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0397 = { + 0x0397, pci_device_1279_0397, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0397, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_127a_1002 = { + 0x1002, pci_device_127a_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1003 = { + 0x1003, pci_device_127a_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1004 = { + 0x1004, pci_device_127a_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1005 = { + 0x1005, pci_device_127a_1005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1022 = { + 0x1022, pci_device_127a_1022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1023 = { + 0x1023, pci_device_127a_1023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1024 = { + 0x1024, pci_device_127a_1024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1025 = { + 0x1025, pci_device_127a_1025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1026 = { + 0x1026, pci_device_127a_1026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1032 = { + 0x1032, pci_device_127a_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1033 = { + 0x1033, pci_device_127a_1033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1034 = { + 0x1034, pci_device_127a_1034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1035 = { + 0x1035, pci_device_127a_1035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1036 = { + 0x1036, pci_device_127a_1036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1085 = { + 0x1085, pci_device_127a_1085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2005 = { + 0x2005, pci_device_127a_2005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2013 = { + 0x2013, pci_device_127a_2013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2014 = { + 0x2014, pci_device_127a_2014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2015 = { + 0x2015, pci_device_127a_2015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2016 = { + 0x2016, pci_device_127a_2016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_4311 = { + 0x4311, pci_device_127a_4311, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_4311, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_4320 = { + 0x4320, pci_device_127a_4320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_4320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_4321 = { + 0x4321, pci_device_127a_4321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_4321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_4322 = { + 0x4322, pci_device_127a_4322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_4322, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_8234 = { + 0x8234, pci_device_127a_8234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_8234, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1282_9009 = { + 0x9009, pci_device_1282_9009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1282_9009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1282_9100 = { + 0x9100, pci_device_1282_9100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1282_9100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1282_9102 = { + 0x9102, pci_device_1282_9102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1282_9102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1282_9132 = { + 0x9132, pci_device_1282_9132, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1282_9132, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1283_673a = { + 0x673a, pci_device_1283_673a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_673a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8330 = { + 0x8330, pci_device_1283_8330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8888 = { + 0x8888, pci_device_1283_8888, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8888, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8889 = { + 0x8889, pci_device_1283_8889, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8889, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_e886 = { + 0xe886, pci_device_1283_e886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_e886, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1285_0100 = { + 0x0100, pci_device_1285_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1285_0100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1287_001e = { + 0x001e, pci_device_1287_001e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1287_001e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1287_001f = { + 0x001f, pci_device_1287_001f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1287_001f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_128d_0021 = { + 0x0021, pci_device_128d_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128d_0021, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_128e_0008 = { + 0x0008, pci_device_128e_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_128e_0009 = { + 0x0009, pci_device_128e_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_128e_000a = { + 0x000a, pci_device_128e_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_128e_000b = { + 0x000b, pci_device_128e_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_128e_000c = { + 0x000c, pci_device_128e_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_000c, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_129a_0615 = { + 0x0615, pci_device_129a_0615, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_129a_0615, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12ab_3000 = { + 0x3000, pci_device_12ab_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ab_3000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12ae_0001 = { + 0x0001, pci_device_12ae_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ae_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12ae_0002 = { + 0x0002, pci_device_12ae_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ae_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12b9_1006 = { + 0x1006, pci_device_12b9_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12b9_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12b9_1007 = { + 0x1007, pci_device_12b9_1007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12b9_1007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12b9_1008 = { + 0x1008, pci_device_12b9_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12b9_1008, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12be_3041 = { + 0x3041, pci_device_12be_3041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12be_3041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12be_3042 = { + 0x3042, pci_device_12be_3042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12be_3042, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12c3_0058 = { + 0x0058, pci_device_12c3_0058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c3_0058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c3_5598 = { + 0x5598, pci_device_12c3_5598, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c3_5598, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12c5_007e = { + 0x007e, pci_device_12c5_007e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_007e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c5_007f = { + 0x007f, pci_device_12c5_007f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_007f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c5_0081 = { + 0x0081, pci_device_12c5_0081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_0081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c5_0085 = { + 0x0085, pci_device_12c5_0085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_0085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c5_0086 = { + 0x0086, pci_device_12c5_0086, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_0086, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_12d2_0008 = { + 0x0008, pci_device_12d2_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0009 = { + 0x0009, pci_device_12d2_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0018 = { + 0x0018, pci_device_12d2_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0019 = { + 0x0019, pci_device_12d2_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0020 = { + 0x0020, pci_device_12d2_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0028 = { + 0x0028, pci_device_12d2_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0029 = { + 0x0029, pci_device_12d2_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_002c = { + 0x002c, pci_device_12d2_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_00a0 = { + 0x00a0, pci_device_12d2_00a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_00a0, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12e0_0010 = { + 0x0010, pci_device_12e0_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12e0_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12e0_0020 = { + 0x0020, pci_device_12e0_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12e0_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12e0_0030 = { + 0x0030, pci_device_12e0_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12e0_0030, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12eb_0001 = { + 0x0001, pci_device_12eb_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12eb_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12eb_0002 = { + 0x0002, pci_device_12eb_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12eb_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12eb_0003 = { + 0x0003, pci_device_12eb_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12eb_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12eb_8803 = { + 0x8803, pci_device_12eb_8803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12eb_8803, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12f8_0002 = { + 0x0002, pci_device_12f8_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12f8_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1307_0001 = { + 0x0001, pci_device_1307_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_000b = { + 0x000b, pci_device_1307_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_000c = { + 0x000c, pci_device_1307_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_000d = { + 0x000d, pci_device_1307_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_000f = { + 0x000f, pci_device_1307_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0010 = { + 0x0010, pci_device_1307_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0014 = { + 0x0014, pci_device_1307_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0015 = { + 0x0015, pci_device_1307_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0016 = { + 0x0016, pci_device_1307_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0017 = { + 0x0017, pci_device_1307_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0018 = { + 0x0018, pci_device_1307_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0019 = { + 0x0019, pci_device_1307_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001a = { + 0x001a, pci_device_1307_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001b = { + 0x001b, pci_device_1307_001b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001c = { + 0x001c, pci_device_1307_001c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001d = { + 0x001d, pci_device_1307_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001e = { + 0x001e, pci_device_1307_001e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001f = { + 0x001f, pci_device_1307_001f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0020 = { + 0x0020, pci_device_1307_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0021 = { + 0x0021, pci_device_1307_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0022 = { + 0x0022, pci_device_1307_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0023 = { + 0x0023, pci_device_1307_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0024 = { + 0x0024, pci_device_1307_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0025 = { + 0x0025, pci_device_1307_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0026 = { + 0x0026, pci_device_1307_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0027 = { + 0x0027, pci_device_1307_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0028 = { + 0x0028, pci_device_1307_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0029 = { + 0x0029, pci_device_1307_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_002c = { + 0x002c, pci_device_1307_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0033 = { + 0x0033, pci_device_1307_0033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0034 = { + 0x0034, pci_device_1307_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0035 = { + 0x0035, pci_device_1307_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0036 = { + 0x0036, pci_device_1307_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0037 = { + 0x0037, pci_device_1307_0037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_004c = { + 0x004c, pci_device_1307_004c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_004c, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1308_0001 = { + 0x0001, pci_device_1308_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1308_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1317_0981 = { + 0x0981, pci_device_1317_0981, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_0981, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_0985 = { + 0x0985, pci_device_1317_0985, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_0985, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_1985 = { + 0x1985, pci_device_1317_1985, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_1985, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1318_0911 = { + 0x0911, pci_device_1318_0911, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1318_0911, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1319_0801 = { + 0x0801, pci_device_1319_0801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1319_0801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1319_0802 = { + 0x0802, pci_device_1319_0802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1319_0802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1319_1000 = { + 0x1000, pci_device_1319_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1319_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1319_1001 = { + 0x1001, pci_device_1319_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1319_1001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_131f_1000 = { + 0x1000, pci_device_131f_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1001 = { + 0x1001, pci_device_131f_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1002 = { + 0x1002, pci_device_131f_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1010 = { + 0x1010, pci_device_131f_1010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1011 = { + 0x1011, pci_device_131f_1011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1012 = { + 0x1012, pci_device_131f_1012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1020 = { + 0x1020, pci_device_131f_1020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1021 = { + 0x1021, pci_device_131f_1021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1030 = { + 0x1030, pci_device_131f_1030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1031 = { + 0x1031, pci_device_131f_1031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1032 = { + 0x1032, pci_device_131f_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1034 = { + 0x1034, pci_device_131f_1034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1035 = { + 0x1035, pci_device_131f_1035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1036 = { + 0x1036, pci_device_131f_1036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1050 = { + 0x1050, pci_device_131f_1050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1051 = { + 0x1051, pci_device_131f_1051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1052 = { + 0x1052, pci_device_131f_1052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2000 = { + 0x2000, pci_device_131f_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2001 = { + 0x2001, pci_device_131f_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2002 = { + 0x2002, pci_device_131f_2002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2010 = { + 0x2010, pci_device_131f_2010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2011 = { + 0x2011, pci_device_131f_2011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2012 = { + 0x2012, pci_device_131f_2012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2020 = { + 0x2020, pci_device_131f_2020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2021 = { + 0x2021, pci_device_131f_2021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2030 = { + 0x2030, pci_device_131f_2030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2031 = { + 0x2031, pci_device_131f_2031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2032 = { + 0x2032, pci_device_131f_2032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2040 = { + 0x2040, pci_device_131f_2040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2041 = { + 0x2041, pci_device_131f_2041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2042 = { + 0x2042, pci_device_131f_2042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2050 = { + 0x2050, pci_device_131f_2050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2051 = { + 0x2051, pci_device_131f_2051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2052 = { + 0x2052, pci_device_131f_2052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2060 = { + 0x2060, pci_device_131f_2060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2061 = { + 0x2061, pci_device_131f_2061, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2061, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2062 = { + 0x2062, pci_device_131f_2062, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2062, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1332_5415 = { + 0x5415, pci_device_1332_5415, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1332_5415, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_134a_0001 = { + 0x0001, pci_device_134a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134a_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134a_0002 = { + 0x0002, pci_device_134a_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134a_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_134d_7890 = { + 0x7890, pci_device_134d_7890, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7890, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7891 = { + 0x7891, pci_device_134d_7891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7892 = { + 0x7892, pci_device_134d_7892, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7892, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7893 = { + 0x7893, pci_device_134d_7893, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7893, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7894 = { + 0x7894, pci_device_134d_7894, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7894, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7895 = { + 0x7895, pci_device_134d_7895, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7895, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7896 = { + 0x7896, pci_device_134d_7896, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7896, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7897 = { + 0x7897, pci_device_134d_7897, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7897, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1353_0002 = { + 0x0002, pci_device_1353_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1353_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1353_0003 = { + 0x0003, pci_device_1353_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1353_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1353_0004 = { + 0x0004, pci_device_1353_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1353_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1353_0005 = { + 0x0005, pci_device_1353_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1353_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_135c_0010 = { + 0x0010, pci_device_135c_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0020 = { + 0x0020, pci_device_135c_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0030 = { + 0x0030, pci_device_135c_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0040 = { + 0x0040, pci_device_135c_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0050 = { + 0x0050, pci_device_135c_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0060 = { + 0x0060, pci_device_135c_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_00f0 = { + 0x00f0, pci_device_135c_00f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_00f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0170 = { + 0x0170, pci_device_135c_0170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0180 = { + 0x0180, pci_device_135c_0180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0190 = { + 0x0190, pci_device_135c_0190, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0190, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_01a0 = { + 0x01a0, pci_device_135c_01a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_01a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_01b0 = { + 0x01b0, pci_device_135c_01b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_01b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_01c0 = { + 0x01c0, pci_device_135c_01c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_01c0, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_135e_7101 = { + 0x7101, pci_device_135e_7101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7201 = { + 0x7201, pci_device_135e_7201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7202 = { + 0x7202, pci_device_135e_7202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7401 = { + 0x7401, pci_device_135e_7401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7402 = { + 0x7402, pci_device_135e_7402, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7402, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7801 = { + 0x7801, pci_device_135e_7801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_8001 = { + 0x8001, pci_device_135e_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_8001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1385_4100 = { + 0x4100, pci_device_1385_4100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_620a = { + 0x620a, pci_device_1385_620a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_620a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_622a = { + 0x622a, pci_device_1385_622a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_622a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_630a = { + 0x630a, pci_device_1385_630a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_630a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_f311 = { + 0xf311, pci_device_1385_f311, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_f311, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1389_0001 = { + 0x0001, pci_device_1389_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1389_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1393_1040 = { + 0x1040, pci_device_1393_1040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_1040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_1680 = { + 0x1680, pci_device_1393_1680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_1680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_2040 = { + 0x2040, pci_device_1393_2040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_2040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_2180 = { + 0x2180, pci_device_1393_2180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_2180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_3200 = { + 0x3200, pci_device_1393_3200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_3200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1394_0001 = { + 0x0001, pci_device_1394_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1394_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1397_2bd0 = { + 0x2bd0, pci_device_1397_2bd0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1397_2bd0, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_139a_0001 = { + 0x0001, pci_device_139a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_139a_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_139a_0003 = { + 0x0003, pci_device_139a_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_139a_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_139a_0005 = { + 0x0005, pci_device_139a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_139a_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13a3_0005 = { + 0x0005, pci_device_13a3_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0006 = { + 0x0006, pci_device_13a3_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0007 = { + 0x0007, pci_device_13a3_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0012 = { + 0x0012, pci_device_13a3_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0014 = { + 0x0014, pci_device_13a3_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0016 = { + 0x0016, pci_device_13a3_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0017 = { + 0x0017, pci_device_13a3_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0018 = { + 0x0018, pci_device_13a3_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0018, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13a8_0158 = { + 0x0158, pci_device_13a8_0158, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a8_0158, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13c0_0010 = { + 0x0010, pci_device_13c0_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c0_0010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13c1_1000 = { + 0x1000, pci_device_13c1_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c1_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c1_1001 = { + 0x1001, pci_device_13c1_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c1_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c1_1002 = { + 0x1002, pci_device_13c1_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c1_1002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13d0_2103 = { + 0x2103, pci_device_13d0_2103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d0_2103, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13d1_ab02 = { + 0xab02, pci_device_13d1_ab02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d1_ab02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13d1_ab06 = { + 0xab06, pci_device_13d1_ab06, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d1_ab06, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13df_0001 = { + 0x0001, pci_device_13df_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13df_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13f0_0201 = { + 0x0201, pci_device_13f0_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f0_0201, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13f4_1401 = { + 0x1401, pci_device_13f4_1401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f4_1401, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13f6_0100 = { + 0x0100, pci_device_13f6_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f6_0101 = { + 0x0101, pci_device_13f6_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f6_0111 = { + 0x0111, pci_device_13f6_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f6_0211 = { + 0x0211, pci_device_13f6_0211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0211, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13fe_1756 = { + 0x1756, pci_device_13fe_1756, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1756, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1400_1401 = { + 0x1401, pci_device_1400_1401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1400_1401, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1407_0100 = { + 0x0100, pci_device_1407_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0101 = { + 0x0101, pci_device_1407_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0102 = { + 0x0102, pci_device_1407_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0200 = { + 0x0200, pci_device_1407_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0201 = { + 0x0201, pci_device_1407_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0202 = { + 0x0202, pci_device_1407_0202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0500 = { + 0x0500, pci_device_1407_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0600 = { + 0x0600, pci_device_1407_0600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8000 = { + 0x8000, pci_device_1407_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8001 = { + 0x8001, pci_device_1407_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8002 = { + 0x8002, pci_device_1407_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8003 = { + 0x8003, pci_device_1407_8003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8800 = { + 0x8800, pci_device_1407_8800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8800, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1409_7168 = { + 0x7168, pci_device_1409_7168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1409_7168, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1412_1712 = { + 0x1712, pci_device_1412_1712, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1412_1712, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1412_1724 = { + 0x1724, pci_device_1412_1724, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1412_1724, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1415_8403 = { + 0x8403, pci_device_1415_8403, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_8403, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9501 = { + 0x9501, pci_device_1415_9501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_950a = { + 0x950a, pci_device_1415_950a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_950a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_950b = { + 0x950b, pci_device_1415_950b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_950b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9511 = { + 0x9511, pci_device_1415_9511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9521 = { + 0x9521, pci_device_1415_9521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9521, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_144a_7296 = { + 0x7296, pci_device_144a_7296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_7432 = { + 0x7432, pci_device_144a_7432, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7432, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_7433 = { + 0x7433, pci_device_144a_7433, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7433, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_7434 = { + 0x7434, pci_device_144a_7434, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7434, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_7841 = { + 0x7841, pci_device_144a_7841, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7841, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_8133 = { + 0x8133, pci_device_144a_8133, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_8133, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_8554 = { + 0x8554, pci_device_144a_8554, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_8554, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_9111 = { + 0x9111, pci_device_144a_9111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_9111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_9113 = { + 0x9113, pci_device_144a_9113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_9113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_9114 = { + 0x9114, pci_device_144a_9114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_9114, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_145f_0001 = { + 0x0001, pci_device_145f_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_145f_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_148d_1003 = { + 0x1003, pci_device_148d_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_148d_1003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14af_7102 = { + 0x7102, pci_device_14af_7102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14af_7102, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14b3_0000 = { + 0x0000, pci_device_14b3_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b3_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14b5_0200 = { + 0x0200, pci_device_14b5_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0300 = { + 0x0300, pci_device_14b5_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0400 = { + 0x0400, pci_device_14b5_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0600 = { + 0x0600, pci_device_14b5_0600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0800 = { + 0x0800, pci_device_14b5_0800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0900 = { + 0x0900, pci_device_14b5_0900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0a00 = { + 0x0a00, pci_device_14b5_0a00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0a00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0b00 = { + 0x0b00, pci_device_14b5_0b00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0b00, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14b7_0001 = { + 0x0001, pci_device_14b7_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b7_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14b9_0001 = { + 0x0001, pci_device_14b9_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_0340 = { + 0x0340, pci_device_14b9_0340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_0340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_0350 = { + 0x0350, pci_device_14b9_0350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_0350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_4500 = { + 0x4500, pci_device_14b9_4500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_4500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_4800 = { + 0x4800, pci_device_14b9_4800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_4800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_a504 = { + 0xa504, pci_device_14b9_a504, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_a504, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14d2_8001 = { + 0x8001, pci_device_14d2_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8002 = { + 0x8002, pci_device_14d2_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8010 = { + 0x8010, pci_device_14d2_8010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8011 = { + 0x8011, pci_device_14d2_8011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8020 = { + 0x8020, pci_device_14d2_8020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8021 = { + 0x8021, pci_device_14d2_8021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8040 = { + 0x8040, pci_device_14d2_8040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8080 = { + 0x8080, pci_device_14d2_8080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a000 = { + 0xa000, pci_device_14d2_a000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a001 = { + 0xa001, pci_device_14d2_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a003 = { + 0xa003, pci_device_14d2_a003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a004 = { + 0xa004, pci_device_14d2_a004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a005 = { + 0xa005, pci_device_14d2_a005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_e001 = { + 0xe001, pci_device_14d2_e001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_e001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_e010 = { + 0xe010, pci_device_14d2_e010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_e010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_e020 = { + 0xe020, pci_device_14d2_e020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_e020, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14db_2120 = { + 0x2120, pci_device_14db_2120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14db_2120, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14dc_0000 = { + 0x0000, pci_device_14dc_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0001 = { + 0x0001, pci_device_14dc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0002 = { + 0x0002, pci_device_14dc_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0003 = { + 0x0003, pci_device_14dc_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0004 = { + 0x0004, pci_device_14dc_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0005 = { + 0x0005, pci_device_14dc_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0006 = { + 0x0006, pci_device_14dc_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0007 = { + 0x0007, pci_device_14dc_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0008 = { + 0x0008, pci_device_14dc_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0009 = { + 0x0009, pci_device_14dc_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_000a = { + 0x000a, pci_device_14dc_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_000b = { + 0x000b, pci_device_14dc_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_000b, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14e4_1644 = { + 0x1644, pci_device_14e4_1644, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1644, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1645 = { + 0x1645, pci_device_14e4_1645, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1645, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1646 = { + 0x1646, pci_device_14e4_1646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1647 = { + 0x1647, pci_device_14e4_1647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1648 = { + 0x1648, pci_device_14e4_1648, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1648, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_164d = { + 0x164d, pci_device_14e4_164d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_164d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1653 = { + 0x1653, pci_device_14e4_1653, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1653, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_165d = { + 0x165d, pci_device_14e4_165d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_165d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1696 = { + 0x1696, pci_device_14e4_1696, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1696, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16a6 = { + 0x16a6, pci_device_14e4_16a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16a7 = { + 0x16a7, pci_device_14e4_16a7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16a7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16a8 = { + 0x16a8, pci_device_14e4_16a8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16a8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16c6 = { + 0x16c6, pci_device_14e4_16c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16c7 = { + 0x16c7, pci_device_14e4_16c7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16c7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4210 = { + 0x4210, pci_device_14e4_4210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4211 = { + 0x4211, pci_device_14e4_4211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4212 = { + 0x4212, pci_device_14e4_4212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4301 = { + 0x4301, pci_device_14e4_4301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4401 = { + 0x4401, pci_device_14e4_4401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4402 = { + 0x4402, pci_device_14e4_4402, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4402, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4410 = { + 0x4410, pci_device_14e4_4410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4411 = { + 0x4411, pci_device_14e4_4411, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4411, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4412 = { + 0x4412, pci_device_14e4_4412, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4412, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5820 = { + 0x5820, pci_device_14e4_5820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5820, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5821 = { + 0x5821, pci_device_14e4_5821, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5821, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14ea_ab06 = { + 0xab06, pci_device_14ea_ab06, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14ea_ab06, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14f1_1002 = { + 0x1002, pci_device_14f1_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1003 = { + 0x1003, pci_device_14f1_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1004 = { + 0x1004, pci_device_14f1_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1005 = { + 0x1005, pci_device_14f1_1005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1006 = { + 0x1006, pci_device_14f1_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1022 = { + 0x1022, pci_device_14f1_1022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1023 = { + 0x1023, pci_device_14f1_1023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1024 = { + 0x1024, pci_device_14f1_1024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1025 = { + 0x1025, pci_device_14f1_1025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1026 = { + 0x1026, pci_device_14f1_1026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1032 = { + 0x1032, pci_device_14f1_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1033 = { + 0x1033, pci_device_14f1_1033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1034 = { + 0x1034, pci_device_14f1_1034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1035 = { + 0x1035, pci_device_14f1_1035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1036 = { + 0x1036, pci_device_14f1_1036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1052 = { + 0x1052, pci_device_14f1_1052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1053 = { + 0x1053, pci_device_14f1_1053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1054 = { + 0x1054, pci_device_14f1_1054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1055 = { + 0x1055, pci_device_14f1_1055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1056 = { + 0x1056, pci_device_14f1_1056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1057 = { + 0x1057, pci_device_14f1_1057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1059 = { + 0x1059, pci_device_14f1_1059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1063 = { + 0x1063, pci_device_14f1_1063, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1063, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1064 = { + 0x1064, pci_device_14f1_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1065 = { + 0x1065, pci_device_14f1_1065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1066 = { + 0x1066, pci_device_14f1_1066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1433 = { + 0x1433, pci_device_14f1_1433, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1433, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1434 = { + 0x1434, pci_device_14f1_1434, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1434, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1435 = { + 0x1435, pci_device_14f1_1435, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1435, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1436 = { + 0x1436, pci_device_14f1_1436, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1436, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1453 = { + 0x1453, pci_device_14f1_1453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1454 = { + 0x1454, pci_device_14f1_1454, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1454, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1455 = { + 0x1455, pci_device_14f1_1455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1456 = { + 0x1456, pci_device_14f1_1456, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1456, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1610 = { + 0x1610, pci_device_14f1_1610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1611 = { + 0x1611, pci_device_14f1_1611, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1611, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1803 = { + 0x1803, pci_device_14f1_1803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1815 = { + 0x1815, pci_device_14f1_1815, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1815, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2003 = { + 0x2003, pci_device_14f1_2003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2004 = { + 0x2004, pci_device_14f1_2004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2005 = { + 0x2005, pci_device_14f1_2005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2006 = { + 0x2006, pci_device_14f1_2006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2013 = { + 0x2013, pci_device_14f1_2013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2014 = { + 0x2014, pci_device_14f1_2014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2015 = { + 0x2015, pci_device_14f1_2015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2016 = { + 0x2016, pci_device_14f1_2016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2043 = { + 0x2043, pci_device_14f1_2043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2044 = { + 0x2044, pci_device_14f1_2044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2045 = { + 0x2045, pci_device_14f1_2045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2046 = { + 0x2046, pci_device_14f1_2046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2063 = { + 0x2063, pci_device_14f1_2063, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2063, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2064 = { + 0x2064, pci_device_14f1_2064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2065 = { + 0x2065, pci_device_14f1_2065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2066 = { + 0x2066, pci_device_14f1_2066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2093 = { + 0x2093, pci_device_14f1_2093, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2093, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2143 = { + 0x2143, pci_device_14f1_2143, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2143, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2144 = { + 0x2144, pci_device_14f1_2144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2145 = { + 0x2145, pci_device_14f1_2145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2146 = { + 0x2146, pci_device_14f1_2146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2163 = { + 0x2163, pci_device_14f1_2163, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2163, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2164 = { + 0x2164, pci_device_14f1_2164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2165 = { + 0x2165, pci_device_14f1_2165, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2165, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2166 = { + 0x2166, pci_device_14f1_2166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2343 = { + 0x2343, pci_device_14f1_2343, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2343, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2344 = { + 0x2344, pci_device_14f1_2344, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2344, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2345 = { + 0x2345, pci_device_14f1_2345, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2345, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2346 = { + 0x2346, pci_device_14f1_2346, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2346, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2363 = { + 0x2363, pci_device_14f1_2363, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2363, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2364 = { + 0x2364, pci_device_14f1_2364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2365 = { + 0x2365, pci_device_14f1_2365, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2365, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2366 = { + 0x2366, pci_device_14f1_2366, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2366, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2443 = { + 0x2443, pci_device_14f1_2443, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2443, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2444 = { + 0x2444, pci_device_14f1_2444, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2444, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2445 = { + 0x2445, pci_device_14f1_2445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2446 = { + 0x2446, pci_device_14f1_2446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2463 = { + 0x2463, pci_device_14f1_2463, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2463, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2464 = { + 0x2464, pci_device_14f1_2464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2465 = { + 0x2465, pci_device_14f1_2465, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2465, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2466 = { + 0x2466, pci_device_14f1_2466, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2466, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2f00 = { + 0x2f00, pci_device_14f1_2f00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2f00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8234 = { + 0x8234, pci_device_14f1_8234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8234, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1507_0001 = { + 0x0001, pci_device_1507_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_0002 = { + 0x0002, pci_device_1507_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_0003 = { + 0x0003, pci_device_1507_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_0100 = { + 0x0100, pci_device_1507_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_0431 = { + 0x0431, pci_device_1507_0431, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0431, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_4801 = { + 0x4801, pci_device_1507_4801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_4801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_4802 = { + 0x4802, pci_device_1507_4802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_4802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_4803 = { + 0x4803, pci_device_1507_4803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_4803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_4806 = { + 0x4806, pci_device_1507_4806, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_4806, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1516_0803 = { + 0x0803, pci_device_1516_0803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1516_0803, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_151a_1002 = { + 0x1002, pci_device_151a_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151a_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_151a_1004 = { + 0x1004, pci_device_151a_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151a_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_151a_1008 = { + 0x1008, pci_device_151a_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151a_1008, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_151f_0000 = { + 0x0000, pci_device_151f_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151f_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1522_0100 = { + 0x0100, pci_device_1522_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1522_0100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1524_1211 = { + 0x1211, pci_device_1524_1211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1225 = { + 0x1225, pci_device_1524_1225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1410 = { + 0x1410, pci_device_1524_1410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1420 = { + 0x1420, pci_device_1524_1420, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1420, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1543_3052 = { + 0x3052, pci_device_1543_3052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1543_3052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1543_4c22 = { + 0x4c22, pci_device_1543_4c22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1543_4c22, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1571_a001 = { + 0xa001, pci_device_1571_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a002 = { + 0xa002, pci_device_1571_a002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a003 = { + 0xa003, pci_device_1571_a003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a004 = { + 0xa004, pci_device_1571_a004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a005 = { + 0xa005, pci_device_1571_a005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a006 = { + 0xa006, pci_device_1571_a006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a007 = { + 0xa007, pci_device_1571_a007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a008 = { + 0xa008, pci_device_1571_a008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a009 = { + 0xa009, pci_device_1571_a009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a00a = { + 0xa00a, pci_device_1571_a00a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a00a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a00b = { + 0xa00b, pci_device_1571_a00b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a00b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a00c = { + 0xa00c, pci_device_1571_a00c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a00c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a00d = { + 0xa00d, pci_device_1571_a00d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a00d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a201 = { + 0xa201, pci_device_1571_a201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a202 = { + 0xa202, pci_device_1571_a202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a203 = { + 0xa203, pci_device_1571_a203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a204 = { + 0xa204, pci_device_1571_a204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a205 = { + 0xa205, pci_device_1571_a205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a206 = { + 0xa206, pci_device_1571_a206, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a206, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_157c_8001 = { + 0x8001, pci_device_157c_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_157c_8001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1592_0781 = { + 0x0781, pci_device_1592_0781, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0781, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0782 = { + 0x0782, pci_device_1592_0782, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0782, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0783 = { + 0x0783, pci_device_1592_0783, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0783, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0785 = { + 0x0785, pci_device_1592_0785, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0785, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0786 = { + 0x0786, pci_device_1592_0786, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0786, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0787 = { + 0x0787, pci_device_1592_0787, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0787, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0788 = { + 0x0788, pci_device_1592_0788, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0788, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_078a = { + 0x078a, pci_device_1592_078a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_078a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15a2_0001 = { + 0x0001, pci_device_15a2_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15a2_0001, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_15ad_0710 = { + 0x0710, pci_device_15ad_0710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15ad_0710, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15b3_5274 = { + 0x5274, pci_device_15b3_5274, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_5274, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15bc_2929 = { + 0x2929, pci_device_15bc_2929, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15bc_2929, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15c7_0349 = { + 0x0349, pci_device_15c7_0349, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15c7_0349, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15dc_0001 = { + 0x0001, pci_device_15dc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15dc_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15e8_0130 = { + 0x0130, pci_device_15e8_0130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15e8_0130, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1619_0400 = { + 0x0400, pci_device_1619_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_0400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_0440 = { + 0x0440, pci_device_1619_0440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_0440, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1629_1003 = { + 0x1003, pci_device_1629_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1629_1003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1629_2002 = { + 0x2002, pci_device_1629_2002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1629_2002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1638_1100 = { + 0x1100, pci_device_1638_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1638_1100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_163c_5449 = { + 0x5449, pci_device_163c_5449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_163c_5449, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_165a_c100 = { + 0xc100, pci_device_165a_c100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_165a_c100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_165a_d200 = { + 0xd200, pci_device_165a_d200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_165a_d200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_165a_d300 = { + 0xd300, pci_device_165a_d300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_165a_d300, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16ab_1102 = { + 0x1102, pci_device_16ab_1102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ab_1102, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16ec_3685 = { + 0x3685, pci_device_16ec_3685, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ec_3685, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_173b_03e8 = { + 0x03e8, pci_device_173b_03e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_173b_03e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_173b_03ea = { + 0x03ea, pci_device_173b_03ea, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_173b_03ea, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1743_8139 = { + 0x8139, pci_device_1743_8139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1743_8139, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1796_0001 = { + 0x0001, pci_device_1796_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0002 = { + 0x0002, pci_device_1796_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0003 = { + 0x0003, pci_device_1796_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0004 = { + 0x0004, pci_device_1796_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0005 = { + 0x0005, pci_device_1796_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0006 = { + 0x0006, pci_device_1796_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0006, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17cc_2280 = { + 0x2280, pci_device_17cc_2280, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17cc_2280, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1813_4000 = { + 0x4000, pci_device_1813_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1813_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1813_4100 = { + 0x4100, pci_device_1813_4100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1813_4100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1888_0301 = { + 0x0301, pci_device_1888_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1888_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1888_0601 = { + 0x0601, pci_device_1888_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1888_0601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1888_0710 = { + 0x0710, pci_device_1888_0710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1888_0710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1888_0720 = { + 0x0720, pci_device_1888_0720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1888_0720, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1a08_0000 = { + 0x0000, pci_device_1a08_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1a08_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1c1c_0001 = { + 0x0001, pci_device_1c1c_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1c1c_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1d44_a400 = { + 0xa400, pci_device_1d44_a400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1d44_a400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1de1_0391 = { + 0x0391, pci_device_1de1_0391, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1de1_0391, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1de1_2020 = { + 0x2020, pci_device_1de1_2020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1de1_2020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1de1_690c = { + 0x690c, pci_device_1de1_690c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1de1_690c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1de1_dc29 = { + 0xdc29, pci_device_1de1_dc29, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1de1_dc29, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_2348_2010 = { + 0x2010, pci_device_2348_2010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_2348_2010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_3388_0013 = { + 0x0013, pci_device_3388_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_0014 = { + 0x0014, pci_device_3388_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_0021 = { + 0x0021, pci_device_3388_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_8011 = { + 0x8011, pci_device_3388_8011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_8011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_8012 = { + 0x8012, pci_device_3388_8012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_8012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_8013 = { + 0x8013, pci_device_3388_8013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_8013, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_3d3d_0001 = { + 0x0001, pci_device_3d3d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0002 = { + 0x0002, pci_device_3d3d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0003 = { + 0x0003, pci_device_3d3d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0004 = { + 0x0004, pci_device_3d3d_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0005 = { + 0x0005, pci_device_3d3d_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0006 = { + 0x0006, pci_device_3d3d_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0007 = { + 0x0007, pci_device_3d3d_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0008 = { + 0x0008, pci_device_3d3d_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0009 = { + 0x0009, pci_device_3d3d_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_000a = { + 0x000a, pci_device_3d3d_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_000c = { + 0x000c, pci_device_3d3d_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0100 = { + 0x0100, pci_device_3d3d_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_1004 = { + 0x1004, pci_device_3d3d_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_3d04 = { + 0x3d04, pci_device_3d3d_3d04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_3d04, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_ffff = { + 0xffff, pci_device_3d3d_ffff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_ffff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_0300 = { + 0x0300, pci_device_4005_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_0308 = { + 0x0308, pci_device_4005_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_0309 = { + 0x0309, pci_device_4005_0309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_0309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_1064 = { + 0x1064, pci_device_4005_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2064 = { + 0x2064, pci_device_4005_2064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2128 = { + 0x2128, pci_device_4005_2128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2128, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2301 = { + 0x2301, pci_device_4005_2301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2302 = { + 0x2302, pci_device_4005_2302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2303 = { + 0x2303, pci_device_4005_2303, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2303, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2364 = { + 0x2364, pci_device_4005_2364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2464 = { + 0x2464, pci_device_4005_2464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2501 = { + 0x2501, pci_device_4005_2501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_4000 = { + 0x4000, pci_device_4005_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_4710 = { + 0x4710, pci_device_4005_4710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_4710, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4033_1360 = { + 0x1360, pci_device_4033_1360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4033_1360, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_416c_0100 = { + 0x0100, pci_device_416c_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_416c_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_416c_0200 = { + 0x0200, pci_device_416c_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_416c_0200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4444_0803 = { + 0x0803, pci_device_4444_0803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4444_0803, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4916_1960 = { + 0x1960, pci_device_4916_1960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4916_1960, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4a14_5000 = { + 0x5000, pci_device_4a14_5000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4a14_5000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4d51_0200 = { + 0x0200, pci_device_4d51_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4d51_0200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4ddc_0100 = { + 0x0100, pci_device_4ddc_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0801 = { + 0x0801, pci_device_4ddc_0801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0802 = { + 0x0802, pci_device_4ddc_0802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0811 = { + 0x0811, pci_device_4ddc_0811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0812 = { + 0x0812, pci_device_4ddc_0812, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0812, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0881 = { + 0x0881, pci_device_4ddc_0881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0882 = { + 0x0882, pci_device_4ddc_0882, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0882, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0891 = { + 0x0891, pci_device_4ddc_0891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0892 = { + 0x0892, pci_device_4ddc_0892, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0892, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0901 = { + 0x0901, pci_device_4ddc_0901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0902 = { + 0x0902, pci_device_4ddc_0902, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0902, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0903 = { + 0x0903, pci_device_4ddc_0903, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0903, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0904 = { + 0x0904, pci_device_4ddc_0904, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0904, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0b01 = { + 0x0b01, pci_device_4ddc_0b01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0b01, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0b02 = { + 0x0b02, pci_device_4ddc_0b02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0b02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0b03 = { + 0x0b03, pci_device_4ddc_0b03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0b03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0b04 = { + 0x0b04, pci_device_4ddc_0b04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0b04, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5046_1001 = { + 0x1001, pci_device_5046_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5046_1001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5053_2010 = { + 0x2010, pci_device_5053_2010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5053_2010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5145_3031 = { + 0x3031, pci_device_5145_3031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5145_3031, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5301_0001 = { + 0x0001, pci_device_5301_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5301_0001, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_5333_0551 = { + 0x0551, pci_device_5333_0551, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_0551, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_5631 = { + 0x5631, pci_device_5333_5631, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_5631, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8800 = { + 0x8800, pci_device_5333_8800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8801 = { + 0x8801, pci_device_5333_8801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8810 = { + 0x8810, pci_device_5333_8810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8811 = { + 0x8811, pci_device_5333_8811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8812 = { + 0x8812, pci_device_5333_8812, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8812, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8813 = { + 0x8813, pci_device_5333_8813, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8813, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8814 = { + 0x8814, pci_device_5333_8814, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8814, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8815 = { + 0x8815, pci_device_5333_8815, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8815, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_883d = { + 0x883d, pci_device_5333_883d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_883d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8870 = { + 0x8870, pci_device_5333_8870, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8870, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8880 = { + 0x8880, pci_device_5333_8880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8881 = { + 0x8881, pci_device_5333_8881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8882 = { + 0x8882, pci_device_5333_8882, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8882, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8883 = { + 0x8883, pci_device_5333_8883, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8883, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88b0 = { + 0x88b0, pci_device_5333_88b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88b1 = { + 0x88b1, pci_device_5333_88b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88b2 = { + 0x88b2, pci_device_5333_88b2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88b2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88b3 = { + 0x88b3, pci_device_5333_88b3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88b3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88c0 = { + 0x88c0, pci_device_5333_88c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88c1 = { + 0x88c1, pci_device_5333_88c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88c2 = { + 0x88c2, pci_device_5333_88c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88c2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88c3 = { + 0x88c3, pci_device_5333_88c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88d0 = { + 0x88d0, pci_device_5333_88d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88d1 = { + 0x88d1, pci_device_5333_88d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88d2 = { + 0x88d2, pci_device_5333_88d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88d3 = { + 0x88d3, pci_device_5333_88d3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88d3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88f0 = { + 0x88f0, pci_device_5333_88f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88f1 = { + 0x88f1, pci_device_5333_88f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88f2 = { + 0x88f2, pci_device_5333_88f2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88f2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88f3 = { + 0x88f3, pci_device_5333_88f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8900 = { + 0x8900, pci_device_5333_8900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8901 = { + 0x8901, pci_device_5333_8901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8902 = { + 0x8902, pci_device_5333_8902, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8902, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8903 = { + 0x8903, pci_device_5333_8903, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8903, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8904 = { + 0x8904, pci_device_5333_8904, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8904, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8905 = { + 0x8905, pci_device_5333_8905, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8905, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8906 = { + 0x8906, pci_device_5333_8906, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8906, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8907 = { + 0x8907, pci_device_5333_8907, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8907, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8908 = { + 0x8908, pci_device_5333_8908, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8908, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8909 = { + 0x8909, pci_device_5333_8909, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8909, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890a = { + 0x890a, pci_device_5333_890a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890b = { + 0x890b, pci_device_5333_890b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890c = { + 0x890c, pci_device_5333_890c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890d = { + 0x890d, pci_device_5333_890d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890e = { + 0x890e, pci_device_5333_890e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890f = { + 0x890f, pci_device_5333_890f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a01 = { + 0x8a01, pci_device_5333_8a01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a01, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a10 = { + 0x8a10, pci_device_5333_8a10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a13 = { + 0x8a13, pci_device_5333_8a13, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a13, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a20 = { + 0x8a20, pci_device_5333_8a20, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a20, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a21 = { + 0x8a21, pci_device_5333_8a21, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a21, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a22 = { + 0x8a22, pci_device_5333_8a22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a22, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a23 = { + 0x8a23, pci_device_5333_8a23, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a23, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a25 = { + 0x8a25, pci_device_5333_8a25, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a25, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a26 = { + 0x8a26, pci_device_5333_8a26, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a26, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c00 = { + 0x8c00, pci_device_5333_8c00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c01 = { + 0x8c01, pci_device_5333_8c01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c01, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c02 = { + 0x8c02, pci_device_5333_8c02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c03 = { + 0x8c03, pci_device_5333_8c03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c10 = { + 0x8c10, pci_device_5333_8c10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c11 = { + 0x8c11, pci_device_5333_8c11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c12 = { + 0x8c12, pci_device_5333_8c12, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c12, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c13 = { + 0x8c13, pci_device_5333_8c13, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c13, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c22 = { + 0x8c22, pci_device_5333_8c22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c22, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c24 = { + 0x8c24, pci_device_5333_8c24, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c24, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c26 = { + 0x8c26, pci_device_5333_8c26, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c26, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2a = { + 0x8c2a, pci_device_5333_8c2a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2b = { + 0x8c2b, pci_device_5333_8c2b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2c = { + 0x8c2c, pci_device_5333_8c2c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2d = { + 0x8c2d, pci_device_5333_8c2d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2e = { + 0x8c2e, pci_device_5333_8c2e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2f = { + 0x8c2f, pci_device_5333_8c2f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8d01 = { + 0x8d01, pci_device_5333_8d01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8d01, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8d02 = { + 0x8d02, pci_device_5333_8d02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8d02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8d03 = { + 0x8d03, pci_device_5333_8d03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8d03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8d04 = { + 0x8d04, pci_device_5333_8d04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8d04, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_9102 = { + 0x9102, pci_device_5333_9102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_9102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_ca00 = { + 0xca00, pci_device_5333_ca00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_ca00, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5455_4458 = { + 0x4458, pci_device_5455_4458, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5455_4458, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5544_0001 = { + 0x0001, pci_device_5544_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5544_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5555_0003 = { + 0x0003, pci_device_5555_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5555_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_6374_6773 = { + 0x6773, pci_device_6374_6773, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6374_6773, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_6666_0001 = { + 0x0001, pci_device_6666_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6666_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_6666_0002 = { + 0x0002, pci_device_6666_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6666_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_8008_0010 = { + 0x0010, pci_device_8008_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8008_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8008_0011 = { + 0x0011, pci_device_8008_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8008_0011, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_8086_0007 = { + 0x0007, pci_device_8086_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0008 = { + 0x0008, pci_device_8086_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0039 = { + 0x0039, pci_device_8086_0039, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0039, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0122 = { + 0x0122, pci_device_8086_0122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0482 = { + 0x0482, pci_device_8086_0482, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0482, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0483 = { + 0x0483, pci_device_8086_0483, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0483, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0484 = { + 0x0484, pci_device_8086_0484, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0484, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0486 = { + 0x0486, pci_device_8086_0486, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0486, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_04a3 = { + 0x04a3, pci_device_8086_04a3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_04a3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_04d0 = { + 0x04d0, pci_device_8086_04d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_04d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0600 = { + 0x0600, pci_device_8086_0600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0960 = { + 0x0960, pci_device_8086_0960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0962 = { + 0x0962, pci_device_8086_0962, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0962, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0964 = { + 0x0964, pci_device_8086_0964, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0964, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1000 = { + 0x1000, pci_device_8086_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1001 = { + 0x1001, pci_device_8086_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1002 = { + 0x1002, pci_device_8086_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1004 = { + 0x1004, pci_device_8086_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1008 = { + 0x1008, pci_device_8086_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1009 = { + 0x1009, pci_device_8086_1009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100c = { + 0x100c, pci_device_8086_100c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100d = { + 0x100d, pci_device_8086_100d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100e = { + 0x100e, pci_device_8086_100e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100f = { + 0x100f, pci_device_8086_100f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1010 = { + 0x1010, pci_device_8086_1010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1011 = { + 0x1011, pci_device_8086_1011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1012 = { + 0x1012, pci_device_8086_1012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1015 = { + 0x1015, pci_device_8086_1015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1029 = { + 0x1029, pci_device_8086_1029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1030 = { + 0x1030, pci_device_8086_1030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1031 = { + 0x1031, pci_device_8086_1031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1032 = { + 0x1032, pci_device_8086_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1033 = { + 0x1033, pci_device_8086_1033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1034 = { + 0x1034, pci_device_8086_1034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1035 = { + 0x1035, pci_device_8086_1035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1036 = { + 0x1036, pci_device_8086_1036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1037 = { + 0x1037, pci_device_8086_1037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1038 = { + 0x1038, pci_device_8086_1038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1039 = { + 0x1039, pci_device_8086_1039, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1039, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103a = { + 0x103a, pci_device_8086_103a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103b = { + 0x103b, pci_device_8086_103b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103c = { + 0x103c, pci_device_8086_103c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103d = { + 0x103d, pci_device_8086_103d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103e = { + 0x103e, pci_device_8086_103e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1040 = { + 0x1040, pci_device_8086_1040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1059 = { + 0x1059, pci_device_8086_1059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1130 = { + 0x1130, pci_device_8086_1130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1131 = { + 0x1131, pci_device_8086_1131, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1131, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1132 = { + 0x1132, pci_device_8086_1132, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1132, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1161 = { + 0x1161, pci_device_8086_1161, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1161, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1162 = { + 0x1162, pci_device_8086_1162, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1162, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1200 = { + 0x1200, pci_device_8086_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1209 = { + 0x1209, pci_device_8086_1209, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1209, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1221 = { + 0x1221, pci_device_8086_1221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1221, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1222 = { + 0x1222, pci_device_8086_1222, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1222, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1223 = { + 0x1223, pci_device_8086_1223, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1223, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1225 = { + 0x1225, pci_device_8086_1225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1226 = { + 0x1226, pci_device_8086_1226, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1226, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1227 = { + 0x1227, pci_device_8086_1227, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1227, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1228 = { + 0x1228, pci_device_8086_1228, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1228, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1229 = { + 0x1229, pci_device_8086_1229, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1229, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_122d = { + 0x122d, pci_device_8086_122d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_122d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_122e = { + 0x122e, pci_device_8086_122e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_122e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1230 = { + 0x1230, pci_device_8086_1230, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1230, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1231 = { + 0x1231, pci_device_8086_1231, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1231, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1234 = { + 0x1234, pci_device_8086_1234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1234, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1235 = { + 0x1235, pci_device_8086_1235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1237 = { + 0x1237, pci_device_8086_1237, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1237, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1239 = { + 0x1239, pci_device_8086_1239, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1239, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123b = { + 0x123b, pci_device_8086_123b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123c = { + 0x123c, pci_device_8086_123c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123d = { + 0x123d, pci_device_8086_123d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123f = { + 0x123f, pci_device_8086_123f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1240 = { + 0x1240, pci_device_8086_1240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_124b = { + 0x124b, pci_device_8086_124b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_124b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1250 = { + 0x1250, pci_device_8086_1250, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1250, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1360 = { + 0x1360, pci_device_8086_1360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1361 = { + 0x1361, pci_device_8086_1361, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1361, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1460 = { + 0x1460, pci_device_8086_1460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1461 = { + 0x1461, pci_device_8086_1461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1462 = { + 0x1462, pci_device_8086_1462, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1462, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1960 = { + 0x1960, pci_device_8086_1960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1962 = { + 0x1962, pci_device_8086_1962, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1962, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a21 = { + 0x1a21, pci_device_8086_1a21, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a21, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a23 = { + 0x1a23, pci_device_8086_1a23, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a23, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a24 = { + 0x1a24, pci_device_8086_1a24, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a24, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a30 = { + 0x1a30, pci_device_8086_1a30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a30, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a31 = { + 0x1a31, pci_device_8086_1a31, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a31, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2410 = { + 0x2410, pci_device_8086_2410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2411 = { + 0x2411, pci_device_8086_2411, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2411, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2412 = { + 0x2412, pci_device_8086_2412, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2412, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2413 = { + 0x2413, pci_device_8086_2413, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2413, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2415 = { + 0x2415, pci_device_8086_2415, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2415, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2416 = { + 0x2416, pci_device_8086_2416, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2416, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2418 = { + 0x2418, pci_device_8086_2418, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2418, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2420 = { + 0x2420, pci_device_8086_2420, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2420, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2421 = { + 0x2421, pci_device_8086_2421, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2421, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2422 = { + 0x2422, pci_device_8086_2422, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2422, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2423 = { + 0x2423, pci_device_8086_2423, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2423, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2425 = { + 0x2425, pci_device_8086_2425, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2425, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2426 = { + 0x2426, pci_device_8086_2426, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2426, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2428 = { + 0x2428, pci_device_8086_2428, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2428, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2440 = { + 0x2440, pci_device_8086_2440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2442 = { + 0x2442, pci_device_8086_2442, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2442, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2443 = { + 0x2443, pci_device_8086_2443, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2443, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2444 = { + 0x2444, pci_device_8086_2444, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2444, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2445 = { + 0x2445, pci_device_8086_2445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2446 = { + 0x2446, pci_device_8086_2446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2448 = { + 0x2448, pci_device_8086_2448, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2448, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2449 = { + 0x2449, pci_device_8086_2449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_244a = { + 0x244a, pci_device_8086_244a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_244a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_244b = { + 0x244b, pci_device_8086_244b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_244b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_244c = { + 0x244c, pci_device_8086_244c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_244c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_244e = { + 0x244e, pci_device_8086_244e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_244e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2450 = { + 0x2450, pci_device_8086_2450, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2450, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2452 = { + 0x2452, pci_device_8086_2452, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2452, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2453 = { + 0x2453, pci_device_8086_2453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2459 = { + 0x2459, pci_device_8086_2459, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2459, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_245b = { + 0x245b, pci_device_8086_245b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_245b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_245d = { + 0x245d, pci_device_8086_245d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_245d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_245e = { + 0x245e, pci_device_8086_245e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_245e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2480 = { + 0x2480, pci_device_8086_2480, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2480, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2482 = { + 0x2482, pci_device_8086_2482, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2482, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2483 = { + 0x2483, pci_device_8086_2483, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2483, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2484 = { + 0x2484, pci_device_8086_2484, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2484, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2485 = { + 0x2485, pci_device_8086_2485, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2485, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2486 = { + 0x2486, pci_device_8086_2486, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2486, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2487 = { + 0x2487, pci_device_8086_2487, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2487, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_248a = { + 0x248a, pci_device_8086_248a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_248a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_248b = { + 0x248b, pci_device_8086_248b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_248b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_248c = { + 0x248c, pci_device_8086_248c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_248c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c0 = { + 0x24c0, pci_device_8086_24c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c2 = { + 0x24c2, pci_device_8086_24c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c3 = { + 0x24c3, pci_device_8086_24c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c4 = { + 0x24c4, pci_device_8086_24c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c5 = { + 0x24c5, pci_device_8086_24c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c6 = { + 0x24c6, pci_device_8086_24c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c7 = { + 0x24c7, pci_device_8086_24c7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24cb = { + 0x24cb, pci_device_8086_24cb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24cb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24cd = { + 0x24cd, pci_device_8086_24cd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24cd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2500 = { + 0x2500, pci_device_8086_2500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2501 = { + 0x2501, pci_device_8086_2501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_250b = { + 0x250b, pci_device_8086_250b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_250b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_250f = { + 0x250f, pci_device_8086_250f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_250f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2520 = { + 0x2520, pci_device_8086_2520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2521 = { + 0x2521, pci_device_8086_2521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2530 = { + 0x2530, pci_device_8086_2530, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2530, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2531 = { + 0x2531, pci_device_8086_2531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2532 = { + 0x2532, pci_device_8086_2532, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2532, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2533 = { + 0x2533, pci_device_8086_2533, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2533, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2534 = { + 0x2534, pci_device_8086_2534, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2534, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2540 = { + 0x2540, pci_device_8086_2540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2541 = { + 0x2541, pci_device_8086_2541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2543 = { + 0x2543, pci_device_8086_2543, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2543, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2544 = { + 0x2544, pci_device_8086_2544, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2544, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2545 = { + 0x2545, pci_device_8086_2545, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2545, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2546 = { + 0x2546, pci_device_8086_2546, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2546, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2547 = { + 0x2547, pci_device_8086_2547, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2547, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2548 = { + 0x2548, pci_device_8086_2548, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2548, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2560 = { + 0x2560, pci_device_8086_2560, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2560, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2561 = { + 0x2561, pci_device_8086_2561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2562 = { + 0x2562, pci_device_8086_2562, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2562, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2570 = { + 0x2570, pci_device_8086_2570, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2570, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2572 = { + 0x2572, pci_device_8086_2572, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2572, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3092 = { + 0x3092, pci_device_8086_3092, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3092, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3575 = { + 0x3575, pci_device_8086_3575, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3575, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3576 = { + 0x3576, pci_device_8086_3576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3576, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3577 = { + 0x3577, pci_device_8086_3577, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3577, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3578 = { + 0x3578, pci_device_8086_3578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3580 = { + 0x3580, pci_device_8086_3580, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3580, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3582 = { + 0x3582, pci_device_8086_3582, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3582, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_5200 = { + 0x5200, pci_device_8086_5200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_5200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_5201 = { + 0x5201, pci_device_8086_5201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_5201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_530d = { + 0x530d, pci_device_8086_530d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_530d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7000 = { + 0x7000, pci_device_8086_7000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7010 = { + 0x7010, pci_device_8086_7010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7020 = { + 0x7020, pci_device_8086_7020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7030 = { + 0x7030, pci_device_8086_7030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7100 = { + 0x7100, pci_device_8086_7100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7110 = { + 0x7110, pci_device_8086_7110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7111 = { + 0x7111, pci_device_8086_7111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7112 = { + 0x7112, pci_device_8086_7112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7113 = { + 0x7113, pci_device_8086_7113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7120 = { + 0x7120, pci_device_8086_7120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7121 = { + 0x7121, pci_device_8086_7121, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7121, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7122 = { + 0x7122, pci_device_8086_7122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7123 = { + 0x7123, pci_device_8086_7123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7124 = { + 0x7124, pci_device_8086_7124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7124, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7125 = { + 0x7125, pci_device_8086_7125, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7125, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7126 = { + 0x7126, pci_device_8086_7126, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7126, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7128 = { + 0x7128, pci_device_8086_7128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7128, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_712a = { + 0x712a, pci_device_8086_712a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_712a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7180 = { + 0x7180, pci_device_8086_7180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7181 = { + 0x7181, pci_device_8086_7181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7190 = { + 0x7190, pci_device_8086_7190, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7190, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7191 = { + 0x7191, pci_device_8086_7191, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7191, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7192 = { + 0x7192, pci_device_8086_7192, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7192, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7194 = { + 0x7194, pci_device_8086_7194, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7194, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7195 = { + 0x7195, pci_device_8086_7195, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7195, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7196 = { + 0x7196, pci_device_8086_7196, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7196, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7198 = { + 0x7198, pci_device_8086_7198, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7198, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7199 = { + 0x7199, pci_device_8086_7199, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7199, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_719a = { + 0x719a, pci_device_8086_719a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_719a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_719b = { + 0x719b, pci_device_8086_719b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_719b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_71a0 = { + 0x71a0, pci_device_8086_71a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_71a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_71a1 = { + 0x71a1, pci_device_8086_71a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_71a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_71a2 = { + 0x71a2, pci_device_8086_71a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_71a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7600 = { + 0x7600, pci_device_8086_7600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7601 = { + 0x7601, pci_device_8086_7601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7602 = { + 0x7602, pci_device_8086_7602, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7602, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7603 = { + 0x7603, pci_device_8086_7603, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7603, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7800 = { + 0x7800, pci_device_8086_7800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84c4 = { + 0x84c4, pci_device_8086_84c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84c5 = { + 0x84c5, pci_device_8086_84c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84ca = { + 0x84ca, pci_device_8086_84ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84cb = { + 0x84cb, pci_device_8086_84cb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84cb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e0 = { + 0x84e0, pci_device_8086_84e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e1 = { + 0x84e1, pci_device_8086_84e1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e2 = { + 0x84e2, pci_device_8086_84e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e3 = { + 0x84e3, pci_device_8086_84e3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e4 = { + 0x84e4, pci_device_8086_84e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e6 = { + 0x84e6, pci_device_8086_84e6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84ea = { + 0x84ea, pci_device_8086_84ea, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84ea, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9621 = { + 0x9621, pci_device_8086_9621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9622 = { + 0x9622, pci_device_8086_9622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9641 = { + 0x9641, pci_device_8086_9641, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9641, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_96a1 = { + 0x96a1, pci_device_8086_96a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_96a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_b152 = { + 0xb152, pci_device_8086_b152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_b152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_b154 = { + 0xb154, pci_device_8086_b154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_b154, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_b555 = { + 0xb555, pci_device_8086_b555, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_b555, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_ffff = { + 0xffff, pci_device_8086_ffff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_ffff, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_8800_2008 = { + 0x2008, pci_device_8800_2008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8800_2008, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_8e2e_3000 = { + 0x3000, pci_device_8e2e_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8e2e_3000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_9004_1078 = { + 0x1078, pci_device_9004_1078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_1078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_1160 = { + 0x1160, pci_device_9004_1160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_1160, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_2178 = { + 0x2178, pci_device_9004_2178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_2178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_3860 = { + 0x3860, pci_device_9004_3860, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_3860, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_3b78 = { + 0x3b78, pci_device_9004_3b78, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_3b78, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5075 = { + 0x5075, pci_device_9004_5075, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5075, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5078 = { + 0x5078, pci_device_9004_5078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5175 = { + 0x5175, pci_device_9004_5175, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5175, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5178 = { + 0x5178, pci_device_9004_5178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5275 = { + 0x5275, pci_device_9004_5275, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5275, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5278 = { + 0x5278, pci_device_9004_5278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5375 = { + 0x5375, pci_device_9004_5375, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5375, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5378 = { + 0x5378, pci_device_9004_5378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5475 = { + 0x5475, pci_device_9004_5475, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5475, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5478 = { + 0x5478, pci_device_9004_5478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5575 = { + 0x5575, pci_device_9004_5575, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5575, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5578 = { + 0x5578, pci_device_9004_5578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5647 = { + 0x5647, pci_device_9004_5647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5675 = { + 0x5675, pci_device_9004_5675, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5675, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5678 = { + 0x5678, pci_device_9004_5678, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5678, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5775 = { + 0x5775, pci_device_9004_5775, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5775, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5778 = { + 0x5778, pci_device_9004_5778, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5778, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5800 = { + 0x5800, pci_device_9004_5800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5900 = { + 0x5900, pci_device_9004_5900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5905 = { + 0x5905, pci_device_9004_5905, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5905, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6038 = { + 0x6038, pci_device_9004_6038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6075 = { + 0x6075, pci_device_9004_6075, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6075, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6078 = { + 0x6078, pci_device_9004_6078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6178 = { + 0x6178, pci_device_9004_6178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6278 = { + 0x6278, pci_device_9004_6278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6378 = { + 0x6378, pci_device_9004_6378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6478 = { + 0x6478, pci_device_9004_6478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6578 = { + 0x6578, pci_device_9004_6578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6678 = { + 0x6678, pci_device_9004_6678, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6678, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6778 = { + 0x6778, pci_device_9004_6778, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6778, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6915 = { + 0x6915, pci_device_9004_6915, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6915, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7078 = { + 0x7078, pci_device_9004_7078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7178 = { + 0x7178, pci_device_9004_7178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7278 = { + 0x7278, pci_device_9004_7278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7378 = { + 0x7378, pci_device_9004_7378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7478 = { + 0x7478, pci_device_9004_7478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7578 = { + 0x7578, pci_device_9004_7578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7678 = { + 0x7678, pci_device_9004_7678, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7678, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7778 = { + 0x7778, pci_device_9004_7778, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7778, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7810 = { + 0x7810, pci_device_9004_7810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7815 = { + 0x7815, pci_device_9004_7815, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7815, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7850 = { + 0x7850, pci_device_9004_7850, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7850, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7855 = { + 0x7855, pci_device_9004_7855, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7855, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7860 = { + 0x7860, pci_device_9004_7860, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7860, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7870 = { + 0x7870, pci_device_9004_7870, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7870, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7871 = { + 0x7871, pci_device_9004_7871, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7871, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7872 = { + 0x7872, pci_device_9004_7872, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7872, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7873 = { + 0x7873, pci_device_9004_7873, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7873, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7874 = { + 0x7874, pci_device_9004_7874, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7874, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7880 = { + 0x7880, pci_device_9004_7880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7890 = { + 0x7890, pci_device_9004_7890, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7890, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7891 = { + 0x7891, pci_device_9004_7891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7892 = { + 0x7892, pci_device_9004_7892, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7892, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7893 = { + 0x7893, pci_device_9004_7893, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7893, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7894 = { + 0x7894, pci_device_9004_7894, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7894, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7895 = { + 0x7895, pci_device_9004_7895, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7895, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7896 = { + 0x7896, pci_device_9004_7896, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7896, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7897 = { + 0x7897, pci_device_9004_7897, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7897, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8078 = { + 0x8078, pci_device_9004_8078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8178 = { + 0x8178, pci_device_9004_8178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8278 = { + 0x8278, pci_device_9004_8278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8378 = { + 0x8378, pci_device_9004_8378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8478 = { + 0x8478, pci_device_9004_8478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8578 = { + 0x8578, pci_device_9004_8578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8678 = { + 0x8678, pci_device_9004_8678, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8678, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8778 = { + 0x8778, pci_device_9004_8778, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8778, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8878 = { + 0x8878, pci_device_9004_8878, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8878, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8b78 = { + 0x8b78, pci_device_9004_8b78, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8b78, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_ec78 = { + 0xec78, pci_device_9004_ec78, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_ec78, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_9005_0010 = { + 0x0010, pci_device_9005_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0011 = { + 0x0011, pci_device_9005_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0013 = { + 0x0013, pci_device_9005_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_001f = { + 0x001f, pci_device_9005_001f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_001f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0020 = { + 0x0020, pci_device_9005_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_002f = { + 0x002f, pci_device_9005_002f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_002f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0030 = { + 0x0030, pci_device_9005_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_003f = { + 0x003f, pci_device_9005_003f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_003f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0050 = { + 0x0050, pci_device_9005_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0051 = { + 0x0051, pci_device_9005_0051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0053 = { + 0x0053, pci_device_9005_0053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_005f = { + 0x005f, pci_device_9005_005f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_005f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0080 = { + 0x0080, pci_device_9005_0080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0081 = { + 0x0081, pci_device_9005_0081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0083 = { + 0x0083, pci_device_9005_0083, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0083, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_008f = { + 0x008f, pci_device_9005_008f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_008f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_00c0 = { + 0x00c0, pci_device_9005_00c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_00c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_00c1 = { + 0x00c1, pci_device_9005_00c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_00c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_00c3 = { + 0x00c3, pci_device_9005_00c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_00c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_00c5 = { + 0x00c5, pci_device_9005_00c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_00c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_00cf = { + 0x00cf, pci_device_9005_00cf, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_00cf, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0250 = { + 0x0250, pci_device_9005_0250, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0250, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0285 = { + 0x0285, pci_device_9005_0285, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0285, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8000 = { + 0x8000, pci_device_9005_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_800f = { + 0x800f, pci_device_9005_800f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_800f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8010 = { + 0x8010, pci_device_9005_8010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8011 = { + 0x8011, pci_device_9005_8011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8012 = { + 0x8012, pci_device_9005_8012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8013 = { + 0x8013, pci_device_9005_8013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8014 = { + 0x8014, pci_device_9005_8014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_801e = { + 0x801e, pci_device_9005_801e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_801e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_801f = { + 0x801f, pci_device_9005_801f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_801f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8090 = { + 0x8090, pci_device_9005_8090, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8090, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8091 = { + 0x8091, pci_device_9005_8091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8092 = { + 0x8092, pci_device_9005_8092, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8092, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8093 = { + 0x8093, pci_device_9005_8093, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8093, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8094 = { + 0x8094, pci_device_9005_8094, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8094, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_809e = { + 0x809e, pci_device_9005_809e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_809e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_809f = { + 0x809f, pci_device_9005_809f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_809f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_907f_2015 = { + 0x2015, pci_device_907f_2015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_907f_2015, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_9412_6565 = { + 0x6565, pci_device_9412_6565, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9412_6565, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_9699_6565 = { + 0x6565, pci_device_9699_6565, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9699_6565, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_9710_9815 = { + 0x9815, pci_device_9710_9815, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9710_9815, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9710_9835 = { + 0x9835, pci_device_9710_9835, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9710_9835, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_cddd_0101 = { + 0x0101, pci_device_cddd_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_cddd_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_cddd_0200 = { + 0x0200, pci_device_cddd_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_cddd_0200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_d4d4_0601 = { + 0x0601, pci_device_d4d4_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_d4d4_0601, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_e000_e000 = { + 0xe000, pci_device_e000_e000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_e000_e000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_e159_0001 = { + 0x0001, pci_device_e159_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_e159_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_e159_0002 = { + 0x0002, pci_device_e159_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_e159_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_ea60_9896 = { + 0x9896, pci_device_ea60_9896, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea60_9896, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea60_9897 = { + 0x9897, pci_device_ea60_9897, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea60_9897, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea60_9898 = { + 0x9898, pci_device_ea60_9898, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea60_9898, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_eace_3100 = { + 0x3100, pci_device_eace_3100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_3100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_3200 = { + 0x3200, pci_device_eace_3200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_3200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_320e = { + 0x320e, pci_device_eace_320e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_320e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_340e = { + 0x340e, pci_device_eace_340e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_340e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_341e = { + 0x341e, pci_device_eace_341e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_341e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_3500 = { + 0x3500, pci_device_eace_3500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_3500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_351c = { + 0x351c, pci_device_eace_351c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_351c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_4100 = { + 0x4100, pci_device_eace_4100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_4100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_4110 = { + 0x4110, pci_device_eace_4110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_4110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_4220 = { + 0x4220, pci_device_eace_4220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_4220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_422e = { + 0x422e, pci_device_eace_422e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_422e, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_ec80_ec00 = { + 0xec00, pci_device_ec80_ec00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ec80_ec00, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_ecc0_0050 = { + 0x0050, pci_device_ecc0_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ecc0_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ecc0_0051 = { + 0x0051, pci_device_ecc0_0051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ecc0_0051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ecc0_0060 = { + 0x0060, pci_device_ecc0_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ecc0_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ecc0_0070 = { + 0x0070, pci_device_ecc0_0070, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ecc0_0070, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ecc0_0071 = { + 0x0071, pci_device_ecc0_0071, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ecc0_0071, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ecc0_0072 = { + 0x0072, pci_device_ecc0_0072, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ecc0_0072, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ecc0_0080 = { + 0x0080, pci_device_ecc0_0080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ecc0_0080, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_edd8_a091 = { + 0xa091, pci_device_edd8_a091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_edd8_a091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_edd8_a099 = { + 0xa099, pci_device_edd8_a099, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_edd8_a099, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_edd8_a0a1 = { + 0xa0a1, pci_device_edd8_a0a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_edd8_a0a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_edd8_a0a9 = { + 0xa0a9, pci_device_edd8_a0a9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_edd8_a0a9, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_f1d0_cafe = { + 0xcafe, pci_device_f1d0_cafe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_f1d0_cafe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_f1d0_efac = { + 0xefac, pci_device_f1d0_efac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_f1d0_efac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_f1d0_facd = { + 0xfacd, pci_device_f1d0_facd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_f1d0_facd, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_feda_a0fa = { + 0xa0fa, pci_device_feda_a0fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_feda_a0fa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_feda_a10e = { + 0xa10e, pci_device_feda_a10e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_feda_a10e, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_fffe_0710 = { + 0x0710, pci_device_fffe_0710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_fffe_0710, +#else + NULL, +#endif + 0 +}; +#endif +#define pci_dev_list_0000 NULL +#define pci_dev_list_001a NULL +#define pci_dev_list_0033 NULL +#define pci_dev_list_003d NULL +#define pci_dev_list_0059 NULL +#define pci_dev_list_0070 NULL +#define pci_dev_list_0100 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0675[] = { + &pci_dev_info_0675_1700, + &pci_dev_info_0675_1702, + NULL +}; +#endif +#define pci_dev_list_0925 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_09c1[] = { + &pci_dev_info_09c1_0704, + NULL +}; +#endif +#define pci_dev_list_0a89 NULL +static const pciDeviceInfo *pci_dev_list_0e11[] = { + &pci_dev_info_0e11_0001, + &pci_dev_info_0e11_0002, + &pci_dev_info_0e11_0049, + &pci_dev_info_0e11_004a, + &pci_dev_info_0e11_0508, + &pci_dev_info_0e11_1000, + &pci_dev_info_0e11_2000, + &pci_dev_info_0e11_3032, + &pci_dev_info_0e11_3033, + &pci_dev_info_0e11_3034, + &pci_dev_info_0e11_4000, + &pci_dev_info_0e11_6010, + &pci_dev_info_0e11_7020, + &pci_dev_info_0e11_a0ec, + &pci_dev_info_0e11_a0f0, + &pci_dev_info_0e11_a0f3, + &pci_dev_info_0e11_a0f7, + &pci_dev_info_0e11_a0f8, + &pci_dev_info_0e11_a0fc, + &pci_dev_info_0e11_ae10, + &pci_dev_info_0e11_ae29, + &pci_dev_info_0e11_ae2a, + &pci_dev_info_0e11_ae2b, + &pci_dev_info_0e11_ae31, + &pci_dev_info_0e11_ae32, + &pci_dev_info_0e11_ae33, + &pci_dev_info_0e11_ae34, + &pci_dev_info_0e11_ae35, + &pci_dev_info_0e11_ae40, + &pci_dev_info_0e11_ae43, + &pci_dev_info_0e11_ae69, + &pci_dev_info_0e11_ae6c, + &pci_dev_info_0e11_ae6d, + &pci_dev_info_0e11_b011, + &pci_dev_info_0e11_b012, + &pci_dev_info_0e11_b01e, + &pci_dev_info_0e11_b01f, + &pci_dev_info_0e11_b02f, + &pci_dev_info_0e11_b030, + &pci_dev_info_0e11_b04a, + &pci_dev_info_0e11_b060, + &pci_dev_info_0e11_b0c6, + &pci_dev_info_0e11_b0c7, + &pci_dev_info_0e11_b0d7, + &pci_dev_info_0e11_b0dd, + &pci_dev_info_0e11_b0de, + &pci_dev_info_0e11_b0df, + &pci_dev_info_0e11_b0e0, + &pci_dev_info_0e11_b0e1, + &pci_dev_info_0e11_b123, + &pci_dev_info_0e11_b134, + &pci_dev_info_0e11_b13c, + &pci_dev_info_0e11_b144, + &pci_dev_info_0e11_b163, + &pci_dev_info_0e11_b164, + &pci_dev_info_0e11_b178, + &pci_dev_info_0e11_b1a4, + &pci_dev_info_0e11_f130, + &pci_dev_info_0e11_f150, + NULL +}; +#define pci_dev_list_0e55 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1000[] = { + &pci_dev_info_1000_0001, + &pci_dev_info_1000_0002, + &pci_dev_info_1000_0003, + &pci_dev_info_1000_0004, + &pci_dev_info_1000_0005, + &pci_dev_info_1000_0006, + &pci_dev_info_1000_000a, + &pci_dev_info_1000_000b, + &pci_dev_info_1000_000c, + &pci_dev_info_1000_000d, + &pci_dev_info_1000_000f, + &pci_dev_info_1000_0010, + &pci_dev_info_1000_0012, + &pci_dev_info_1000_0013, + &pci_dev_info_1000_0020, + &pci_dev_info_1000_0021, + &pci_dev_info_1000_0030, + &pci_dev_info_1000_0040, + &pci_dev_info_1000_008f, + &pci_dev_info_1000_0621, + &pci_dev_info_1000_0622, + &pci_dev_info_1000_0623, + &pci_dev_info_1000_0624, + &pci_dev_info_1000_0625, + &pci_dev_info_1000_0626, + &pci_dev_info_1000_0627, + &pci_dev_info_1000_0628, + &pci_dev_info_1000_0629, + &pci_dev_info_1000_0701, + &pci_dev_info_1000_0702, + &pci_dev_info_1000_0901, + &pci_dev_info_1000_1000, + &pci_dev_info_1000_1960, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1001[] = { + &pci_dev_info_1001_0010, + &pci_dev_info_1001_0011, + &pci_dev_info_1001_0012, + &pci_dev_info_1001_0013, + &pci_dev_info_1001_0014, + &pci_dev_info_1001_0015, + &pci_dev_info_1001_0016, + &pci_dev_info_1001_0017, + &pci_dev_info_1001_9100, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_1002[] = { + &pci_dev_info_1002_4144, + &pci_dev_info_1002_4145, + &pci_dev_info_1002_4146, + &pci_dev_info_1002_4147, + &pci_dev_info_1002_4158, + &pci_dev_info_1002_4242, + &pci_dev_info_1002_4336, + &pci_dev_info_1002_4337, + &pci_dev_info_1002_4354, + &pci_dev_info_1002_4358, + &pci_dev_info_1002_4554, + &pci_dev_info_1002_4654, + &pci_dev_info_1002_4742, + &pci_dev_info_1002_4744, + &pci_dev_info_1002_4747, + &pci_dev_info_1002_4749, + &pci_dev_info_1002_474c, + &pci_dev_info_1002_474d, + &pci_dev_info_1002_474e, + &pci_dev_info_1002_474f, + &pci_dev_info_1002_4750, + &pci_dev_info_1002_4751, + &pci_dev_info_1002_4752, + &pci_dev_info_1002_4753, + &pci_dev_info_1002_4754, + &pci_dev_info_1002_4755, + &pci_dev_info_1002_4756, + &pci_dev_info_1002_4757, + &pci_dev_info_1002_4758, + &pci_dev_info_1002_4759, + &pci_dev_info_1002_475a, + &pci_dev_info_1002_4964, + &pci_dev_info_1002_4965, + &pci_dev_info_1002_4966, + &pci_dev_info_1002_4967, + &pci_dev_info_1002_496e, + &pci_dev_info_1002_4c42, + &pci_dev_info_1002_4c44, + &pci_dev_info_1002_4c45, + &pci_dev_info_1002_4c46, + &pci_dev_info_1002_4c47, + &pci_dev_info_1002_4c49, + &pci_dev_info_1002_4c4d, + &pci_dev_info_1002_4c4e, + &pci_dev_info_1002_4c50, + &pci_dev_info_1002_4c51, + &pci_dev_info_1002_4c52, + &pci_dev_info_1002_4c53, + &pci_dev_info_1002_4c54, + &pci_dev_info_1002_4c57, + &pci_dev_info_1002_4c58, + &pci_dev_info_1002_4c59, + &pci_dev_info_1002_4c5a, + &pci_dev_info_1002_4c64, + &pci_dev_info_1002_4c65, + &pci_dev_info_1002_4c66, + &pci_dev_info_1002_4c67, + &pci_dev_info_1002_4d46, + &pci_dev_info_1002_4d4c, + &pci_dev_info_1002_4e44, + &pci_dev_info_1002_4e45, + &pci_dev_info_1002_4e46, + &pci_dev_info_1002_4e47, + &pci_dev_info_1002_4e64, + &pci_dev_info_1002_4e65, + &pci_dev_info_1002_4e66, + &pci_dev_info_1002_4e67, + &pci_dev_info_1002_5041, + &pci_dev_info_1002_5042, + &pci_dev_info_1002_5043, + &pci_dev_info_1002_5044, + &pci_dev_info_1002_5045, + &pci_dev_info_1002_5046, + &pci_dev_info_1002_5047, + &pci_dev_info_1002_5048, + &pci_dev_info_1002_5049, + &pci_dev_info_1002_504a, + &pci_dev_info_1002_504b, + &pci_dev_info_1002_504c, + &pci_dev_info_1002_504d, + &pci_dev_info_1002_504e, + &pci_dev_info_1002_504f, + &pci_dev_info_1002_5050, + &pci_dev_info_1002_5051, + &pci_dev_info_1002_5052, + &pci_dev_info_1002_5053, + &pci_dev_info_1002_5054, + &pci_dev_info_1002_5055, + &pci_dev_info_1002_5056, + &pci_dev_info_1002_5057, + &pci_dev_info_1002_5058, + &pci_dev_info_1002_5144, + &pci_dev_info_1002_5145, + &pci_dev_info_1002_5146, + &pci_dev_info_1002_5147, + &pci_dev_info_1002_5148, + &pci_dev_info_1002_5149, + &pci_dev_info_1002_514a, + &pci_dev_info_1002_514b, + &pci_dev_info_1002_514c, + &pci_dev_info_1002_514d, + &pci_dev_info_1002_514e, + &pci_dev_info_1002_514f, + &pci_dev_info_1002_5157, + &pci_dev_info_1002_5158, + &pci_dev_info_1002_5159, + &pci_dev_info_1002_515a, + &pci_dev_info_1002_5168, + &pci_dev_info_1002_5169, + &pci_dev_info_1002_516a, + &pci_dev_info_1002_516b, + &pci_dev_info_1002_516c, + &pci_dev_info_1002_5245, + &pci_dev_info_1002_5246, + &pci_dev_info_1002_5247, + &pci_dev_info_1002_524b, + &pci_dev_info_1002_524c, + &pci_dev_info_1002_5345, + &pci_dev_info_1002_5346, + &pci_dev_info_1002_5347, + &pci_dev_info_1002_5348, + &pci_dev_info_1002_534b, + &pci_dev_info_1002_534c, + &pci_dev_info_1002_534d, + &pci_dev_info_1002_534e, + &pci_dev_info_1002_5354, + &pci_dev_info_1002_5446, + &pci_dev_info_1002_544c, + &pci_dev_info_1002_5452, + &pci_dev_info_1002_5453, + &pci_dev_info_1002_5454, + &pci_dev_info_1002_5455, + &pci_dev_info_1002_5654, + &pci_dev_info_1002_5655, + &pci_dev_info_1002_5656, + &pci_dev_info_1002_700f, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1003[] = { + &pci_dev_info_1003_0201, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1004[] = { + &pci_dev_info_1004_0005, + &pci_dev_info_1004_0006, + &pci_dev_info_1004_0007, + &pci_dev_info_1004_0008, + &pci_dev_info_1004_0009, + &pci_dev_info_1004_000c, + &pci_dev_info_1004_000d, + &pci_dev_info_1004_0101, + &pci_dev_info_1004_0102, + &pci_dev_info_1004_0103, + &pci_dev_info_1004_0104, + &pci_dev_info_1004_0105, + &pci_dev_info_1004_0200, + &pci_dev_info_1004_0280, + &pci_dev_info_1004_0304, + &pci_dev_info_1004_0305, + &pci_dev_info_1004_0306, + &pci_dev_info_1004_0307, + &pci_dev_info_1004_0308, + &pci_dev_info_1004_0702, + &pci_dev_info_1004_0703, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_1005[] = { + &pci_dev_info_1005_2064, + &pci_dev_info_1005_2128, + &pci_dev_info_1005_2301, + &pci_dev_info_1005_2302, + &pci_dev_info_1005_2364, + &pci_dev_info_1005_2464, + &pci_dev_info_1005_2501, + NULL +}; +#define pci_dev_list_1006 NULL +#define pci_dev_list_1007 NULL +#define pci_dev_list_1008 NULL +#define pci_dev_list_100a NULL +static const pciDeviceInfo *pci_dev_list_100b[] = { + &pci_dev_info_100b_0001, + &pci_dev_info_100b_0002, + &pci_dev_info_100b_000e, + &pci_dev_info_100b_000f, + &pci_dev_info_100b_0011, + &pci_dev_info_100b_0012, + &pci_dev_info_100b_0020, + &pci_dev_info_100b_0022, + &pci_dev_info_100b_0500, + &pci_dev_info_100b_0501, + &pci_dev_info_100b_0502, + &pci_dev_info_100b_0503, + &pci_dev_info_100b_0504, + &pci_dev_info_100b_0505, + &pci_dev_info_100b_d001, + NULL +}; +static const pciDeviceInfo *pci_dev_list_100c[] = { + &pci_dev_info_100c_3202, + &pci_dev_info_100c_3205, + &pci_dev_info_100c_3206, + &pci_dev_info_100c_3207, + &pci_dev_info_100c_3208, + &pci_dev_info_100c_4702, + NULL +}; +#define pci_dev_list_100d NULL +static const pciDeviceInfo *pci_dev_list_100e[] = { + &pci_dev_info_100e_9000, + &pci_dev_info_100e_9001, + &pci_dev_info_100e_9002, + &pci_dev_info_100e_9100, + NULL +}; +#define pci_dev_list_1010 NULL +static const pciDeviceInfo *pci_dev_list_1011[] = { + &pci_dev_info_1011_0001, + &pci_dev_info_1011_0002, + &pci_dev_info_1011_0004, + &pci_dev_info_1011_0007, + &pci_dev_info_1011_0008, + &pci_dev_info_1011_0009, + &pci_dev_info_1011_000a, + &pci_dev_info_1011_000d, + &pci_dev_info_1011_000f, + &pci_dev_info_1011_0014, + &pci_dev_info_1011_0016, + &pci_dev_info_1011_0019, + &pci_dev_info_1011_001a, + &pci_dev_info_1011_0021, + &pci_dev_info_1011_0022, + &pci_dev_info_1011_0023, + &pci_dev_info_1011_0024, + &pci_dev_info_1011_0025, + &pci_dev_info_1011_0026, + &pci_dev_info_1011_0034, + &pci_dev_info_1011_0045, + &pci_dev_info_1011_0046, + &pci_dev_info_1011_1065, + NULL +}; +#define pci_dev_list_1012 NULL +static const pciDeviceInfo *pci_dev_list_1013[] = { + &pci_dev_info_1013_0038, + &pci_dev_info_1013_0040, + &pci_dev_info_1013_004c, + &pci_dev_info_1013_00a0, + &pci_dev_info_1013_00a2, + &pci_dev_info_1013_00a4, + &pci_dev_info_1013_00a8, + &pci_dev_info_1013_00ac, + &pci_dev_info_1013_00b0, + &pci_dev_info_1013_00b8, + &pci_dev_info_1013_00bc, + &pci_dev_info_1013_00d0, + &pci_dev_info_1013_00d2, + &pci_dev_info_1013_00d4, + &pci_dev_info_1013_00d5, + &pci_dev_info_1013_00d6, + &pci_dev_info_1013_00e8, + &pci_dev_info_1013_1100, + &pci_dev_info_1013_1110, + &pci_dev_info_1013_1112, + &pci_dev_info_1013_1113, + &pci_dev_info_1013_1200, + &pci_dev_info_1013_1202, + &pci_dev_info_1013_1204, + &pci_dev_info_1013_4400, + &pci_dev_info_1013_6001, + &pci_dev_info_1013_6003, + &pci_dev_info_1013_6004, + &pci_dev_info_1013_6005, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1014[] = { + &pci_dev_info_1014_0002, + &pci_dev_info_1014_0005, + &pci_dev_info_1014_0007, + &pci_dev_info_1014_000a, + &pci_dev_info_1014_0017, + &pci_dev_info_1014_0018, + &pci_dev_info_1014_001b, + &pci_dev_info_1014_001c, + &pci_dev_info_1014_001d, + &pci_dev_info_1014_0020, + &pci_dev_info_1014_0022, + &pci_dev_info_1014_002d, + &pci_dev_info_1014_002e, + &pci_dev_info_1014_0036, + &pci_dev_info_1014_003a, + &pci_dev_info_1014_003e, + &pci_dev_info_1014_0045, + &pci_dev_info_1014_0046, + &pci_dev_info_1014_0047, + &pci_dev_info_1014_0048, + &pci_dev_info_1014_0049, + &pci_dev_info_1014_004e, + &pci_dev_info_1014_004f, + &pci_dev_info_1014_0050, + &pci_dev_info_1014_0053, + &pci_dev_info_1014_0057, + &pci_dev_info_1014_005c, + &pci_dev_info_1014_007c, + &pci_dev_info_1014_007d, + &pci_dev_info_1014_0090, + &pci_dev_info_1014_0095, + &pci_dev_info_1014_0096, + &pci_dev_info_1014_00a5, + &pci_dev_info_1014_00a6, + &pci_dev_info_1014_00b7, + &pci_dev_info_1014_00be, + &pci_dev_info_1014_00dc, + &pci_dev_info_1014_00fc, + &pci_dev_info_1014_0105, + &pci_dev_info_1014_010f, + &pci_dev_info_1014_0142, + &pci_dev_info_1014_0144, + &pci_dev_info_1014_0156, + &pci_dev_info_1014_01a7, + &pci_dev_info_1014_01bd, + &pci_dev_info_1014_0302, + &pci_dev_info_1014_ffff, + NULL +}; +#endif +#define pci_dev_list_1015 NULL +#define pci_dev_list_1016 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1017[] = { + &pci_dev_info_1017_5343, + NULL +}; +#endif +#define pci_dev_list_1018 NULL +#define pci_dev_list_1019 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_101a[] = { + &pci_dev_info_101a_0005, + NULL +}; +#endif +#define pci_dev_list_101b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_101c[] = { + &pci_dev_info_101c_0193, + &pci_dev_info_101c_0196, + &pci_dev_info_101c_0197, + &pci_dev_info_101c_0296, + &pci_dev_info_101c_3193, + &pci_dev_info_101c_3197, + &pci_dev_info_101c_3296, + &pci_dev_info_101c_4296, + &pci_dev_info_101c_9710, + &pci_dev_info_101c_9712, + &pci_dev_info_101c_c24a, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_101e[] = { + &pci_dev_info_101e_1960, + &pci_dev_info_101e_9010, + &pci_dev_info_101e_9030, + &pci_dev_info_101e_9031, + &pci_dev_info_101e_9032, + &pci_dev_info_101e_9033, + &pci_dev_info_101e_9040, + &pci_dev_info_101e_9060, + &pci_dev_info_101e_9063, + NULL +}; +#endif +#define pci_dev_list_101f NULL +#define pci_dev_list_1020 NULL +#define pci_dev_list_1021 NULL +static const pciDeviceInfo *pci_dev_list_1022[] = { + &pci_dev_info_1022_1100, + &pci_dev_info_1022_1101, + &pci_dev_info_1022_1102, + &pci_dev_info_1022_1103, + &pci_dev_info_1022_2000, + &pci_dev_info_1022_2001, + &pci_dev_info_1022_2020, + &pci_dev_info_1022_2040, + &pci_dev_info_1022_3000, + &pci_dev_info_1022_7006, + &pci_dev_info_1022_7007, + &pci_dev_info_1022_700c, + &pci_dev_info_1022_700d, + &pci_dev_info_1022_700e, + &pci_dev_info_1022_700f, + &pci_dev_info_1022_7400, + &pci_dev_info_1022_7401, + &pci_dev_info_1022_7403, + &pci_dev_info_1022_7404, + &pci_dev_info_1022_7408, + &pci_dev_info_1022_7409, + &pci_dev_info_1022_740b, + &pci_dev_info_1022_740c, + &pci_dev_info_1022_7410, + &pci_dev_info_1022_7411, + &pci_dev_info_1022_7413, + &pci_dev_info_1022_7414, + &pci_dev_info_1022_7440, + &pci_dev_info_1022_7441, + &pci_dev_info_1022_7443, + &pci_dev_info_1022_7445, + &pci_dev_info_1022_7446, + &pci_dev_info_1022_7448, + &pci_dev_info_1022_7449, + &pci_dev_info_1022_7450, + &pci_dev_info_1022_7451, + &pci_dev_info_1022_7454, + &pci_dev_info_1022_7455, + &pci_dev_info_1022_7460, + &pci_dev_info_1022_7461, + &pci_dev_info_1022_7462, + &pci_dev_info_1022_7464, + &pci_dev_info_1022_7468, + &pci_dev_info_1022_7469, + &pci_dev_info_1022_746a, + &pci_dev_info_1022_746b, + &pci_dev_info_1022_746d, + &pci_dev_info_1022_746e, + NULL +}; +static const pciDeviceInfo *pci_dev_list_1023[] = { + &pci_dev_info_1023_0194, + &pci_dev_info_1023_2000, + &pci_dev_info_1023_2001, + &pci_dev_info_1023_8400, + &pci_dev_info_1023_8420, + &pci_dev_info_1023_8500, + &pci_dev_info_1023_8520, + &pci_dev_info_1023_8620, + &pci_dev_info_1023_8820, + &pci_dev_info_1023_9320, + &pci_dev_info_1023_9350, + &pci_dev_info_1023_9360, + &pci_dev_info_1023_9382, + &pci_dev_info_1023_9383, + &pci_dev_info_1023_9385, + &pci_dev_info_1023_9386, + &pci_dev_info_1023_9388, + &pci_dev_info_1023_9397, + &pci_dev_info_1023_939a, + &pci_dev_info_1023_9420, + &pci_dev_info_1023_9430, + &pci_dev_info_1023_9440, + &pci_dev_info_1023_9460, + &pci_dev_info_1023_9470, + &pci_dev_info_1023_9520, + &pci_dev_info_1023_9525, + &pci_dev_info_1023_9540, + &pci_dev_info_1023_9660, + &pci_dev_info_1023_9680, + &pci_dev_info_1023_9682, + &pci_dev_info_1023_9683, + &pci_dev_info_1023_9685, + &pci_dev_info_1023_9750, + &pci_dev_info_1023_9753, + &pci_dev_info_1023_9754, + &pci_dev_info_1023_9759, + &pci_dev_info_1023_9783, + &pci_dev_info_1023_9785, + &pci_dev_info_1023_9850, + &pci_dev_info_1023_9880, + &pci_dev_info_1023_9910, + &pci_dev_info_1023_9930, + NULL +}; +#define pci_dev_list_1024 NULL +static const pciDeviceInfo *pci_dev_list_1025[] = { + &pci_dev_info_1025_1435, + &pci_dev_info_1025_1445, + &pci_dev_info_1025_1449, + &pci_dev_info_1025_1451, + &pci_dev_info_1025_1461, + &pci_dev_info_1025_1489, + &pci_dev_info_1025_1511, + &pci_dev_info_1025_1512, + &pci_dev_info_1025_1513, + &pci_dev_info_1025_1521, + &pci_dev_info_1025_1523, + &pci_dev_info_1025_1531, + &pci_dev_info_1025_1533, + &pci_dev_info_1025_1535, + &pci_dev_info_1025_1541, + &pci_dev_info_1025_1542, + &pci_dev_info_1025_1543, + &pci_dev_info_1025_1561, + &pci_dev_info_1025_1621, + &pci_dev_info_1025_1631, + &pci_dev_info_1025_1641, + &pci_dev_info_1025_1647, + &pci_dev_info_1025_3141, + &pci_dev_info_1025_3143, + &pci_dev_info_1025_3145, + &pci_dev_info_1025_3147, + &pci_dev_info_1025_3149, + &pci_dev_info_1025_3151, + &pci_dev_info_1025_3307, + &pci_dev_info_1025_3309, + &pci_dev_info_1025_3321, + &pci_dev_info_1025_5212, + &pci_dev_info_1025_5215, + &pci_dev_info_1025_5217, + &pci_dev_info_1025_5219, + &pci_dev_info_1025_5225, + &pci_dev_info_1025_5229, + &pci_dev_info_1025_5235, + &pci_dev_info_1025_5237, + &pci_dev_info_1025_5240, + &pci_dev_info_1025_5241, + &pci_dev_info_1025_5242, + &pci_dev_info_1025_5243, + &pci_dev_info_1025_5244, + &pci_dev_info_1025_5247, + &pci_dev_info_1025_5251, + &pci_dev_info_1025_5427, + &pci_dev_info_1025_5451, + &pci_dev_info_1025_5453, + &pci_dev_info_1025_7101, + NULL +}; +static const pciDeviceInfo *pci_dev_list_1028[] = { + &pci_dev_info_1028_0001, + &pci_dev_info_1028_0002, + &pci_dev_info_1028_0003, + &pci_dev_info_1028_0004, + &pci_dev_info_1028_0005, + &pci_dev_info_1028_0006, + &pci_dev_info_1028_0007, + &pci_dev_info_1028_0008, + &pci_dev_info_1028_000a, + &pci_dev_info_1028_000c, + &pci_dev_info_1028_000e, + &pci_dev_info_1028_000f, + NULL +}; +#define pci_dev_list_1029 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_102a[] = { + &pci_dev_info_102a_0000, + &pci_dev_info_102a_0010, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_102b[] = { + &pci_dev_info_102b_0010, + &pci_dev_info_102b_0518, + &pci_dev_info_102b_0519, + &pci_dev_info_102b_051a, + &pci_dev_info_102b_051b, + &pci_dev_info_102b_051e, + &pci_dev_info_102b_051f, + &pci_dev_info_102b_0520, + &pci_dev_info_102b_0521, + &pci_dev_info_102b_0525, + &pci_dev_info_102b_0527, + &pci_dev_info_102b_0d10, + &pci_dev_info_102b_1000, + &pci_dev_info_102b_1001, + &pci_dev_info_102b_2007, + &pci_dev_info_102b_2527, + &pci_dev_info_102b_4536, + &pci_dev_info_102b_6573, + NULL +}; +static const pciDeviceInfo *pci_dev_list_102c[] = { + &pci_dev_info_102c_00b8, + &pci_dev_info_102c_00c0, + &pci_dev_info_102c_00d0, + &pci_dev_info_102c_00d8, + &pci_dev_info_102c_00dc, + &pci_dev_info_102c_00e0, + &pci_dev_info_102c_00e4, + &pci_dev_info_102c_00e5, + &pci_dev_info_102c_00f0, + &pci_dev_info_102c_00f4, + &pci_dev_info_102c_00f5, + &pci_dev_info_102c_0c30, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_102d[] = { + &pci_dev_info_102d_50dc, + NULL +}; +#endif +#define pci_dev_list_102e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_102f[] = { + &pci_dev_info_102f_0009, + &pci_dev_info_102f_0020, + NULL +}; +#endif +#define pci_dev_list_1030 NULL +static const pciDeviceInfo *pci_dev_list_1031[] = { + &pci_dev_info_1031_5601, + &pci_dev_info_1031_5607, + &pci_dev_info_1031_5631, + &pci_dev_info_1031_6057, + NULL +}; +#define pci_dev_list_1032 NULL +static const pciDeviceInfo *pci_dev_list_1033[] = { + &pci_dev_info_1033_0001, + &pci_dev_info_1033_0002, + &pci_dev_info_1033_0003, + &pci_dev_info_1033_0004, + &pci_dev_info_1033_0005, + &pci_dev_info_1033_0006, + &pci_dev_info_1033_0007, + &pci_dev_info_1033_0008, + &pci_dev_info_1033_0009, + &pci_dev_info_1033_0016, + &pci_dev_info_1033_001a, + &pci_dev_info_1033_0021, + &pci_dev_info_1033_0029, + &pci_dev_info_1033_002a, + &pci_dev_info_1033_002c, + &pci_dev_info_1033_002d, + &pci_dev_info_1033_0035, + &pci_dev_info_1033_003b, + &pci_dev_info_1033_003e, + &pci_dev_info_1033_0046, + &pci_dev_info_1033_005a, + &pci_dev_info_1033_0063, + &pci_dev_info_1033_0067, + &pci_dev_info_1033_0074, + &pci_dev_info_1033_009b, + &pci_dev_info_1033_00a6, + &pci_dev_info_1033_00cd, + &pci_dev_info_1033_00e0, + NULL +}; +#define pci_dev_list_1034 NULL +#define pci_dev_list_1035 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1036[] = { + &pci_dev_info_1036_0000, + NULL +}; +#endif +#define pci_dev_list_1037 NULL +#define pci_dev_list_1038 NULL +static const pciDeviceInfo *pci_dev_list_1039[] = { + &pci_dev_info_1039_0001, + &pci_dev_info_1039_0002, + &pci_dev_info_1039_0006, + &pci_dev_info_1039_0008, + &pci_dev_info_1039_0009, + &pci_dev_info_1039_0018, + &pci_dev_info_1039_0200, + &pci_dev_info_1039_0204, + &pci_dev_info_1039_0205, + &pci_dev_info_1039_0300, + &pci_dev_info_1039_0310, + &pci_dev_info_1039_0315, + &pci_dev_info_1039_0325, + &pci_dev_info_1039_0330, + &pci_dev_info_1039_0406, + &pci_dev_info_1039_0496, + &pci_dev_info_1039_0530, + &pci_dev_info_1039_0540, + &pci_dev_info_1039_0597, + &pci_dev_info_1039_0601, + &pci_dev_info_1039_0620, + &pci_dev_info_1039_0630, + &pci_dev_info_1039_0633, + &pci_dev_info_1039_0635, + &pci_dev_info_1039_0645, + &pci_dev_info_1039_0646, + &pci_dev_info_1039_0650, + &pci_dev_info_1039_0651, + &pci_dev_info_1039_0730, + &pci_dev_info_1039_0733, + &pci_dev_info_1039_0735, + &pci_dev_info_1039_0740, + &pci_dev_info_1039_0745, + &pci_dev_info_1039_0900, + &pci_dev_info_1039_0961, + &pci_dev_info_1039_0962, + &pci_dev_info_1039_3602, + &pci_dev_info_1039_5107, + &pci_dev_info_1039_5300, + &pci_dev_info_1039_5315, + &pci_dev_info_1039_5401, + &pci_dev_info_1039_5511, + &pci_dev_info_1039_5513, + &pci_dev_info_1039_5517, + &pci_dev_info_1039_5571, + &pci_dev_info_1039_5581, + &pci_dev_info_1039_5582, + &pci_dev_info_1039_5591, + &pci_dev_info_1039_5596, + &pci_dev_info_1039_5597, + &pci_dev_info_1039_5600, + &pci_dev_info_1039_6204, + &pci_dev_info_1039_6205, + &pci_dev_info_1039_6236, + &pci_dev_info_1039_6300, + &pci_dev_info_1039_6306, + &pci_dev_info_1039_6325, + &pci_dev_info_1039_6326, + &pci_dev_info_1039_7001, + &pci_dev_info_1039_7002, + &pci_dev_info_1039_7007, + &pci_dev_info_1039_7012, + &pci_dev_info_1039_7013, + &pci_dev_info_1039_7016, + &pci_dev_info_1039_7018, + NULL +}; +#define pci_dev_list_103a NULL +#define pci_dev_list_103b NULL +static const pciDeviceInfo *pci_dev_list_103c[] = { + &pci_dev_info_103c_1005, + &pci_dev_info_103c_1006, + &pci_dev_info_103c_1008, + &pci_dev_info_103c_100a, + &pci_dev_info_103c_1028, + &pci_dev_info_103c_1029, + &pci_dev_info_103c_102a, + &pci_dev_info_103c_1030, + &pci_dev_info_103c_1031, + &pci_dev_info_103c_1040, + &pci_dev_info_103c_1041, + &pci_dev_info_103c_1042, + &pci_dev_info_103c_1048, + &pci_dev_info_103c_1064, + &pci_dev_info_103c_108b, + &pci_dev_info_103c_10c1, + &pci_dev_info_103c_10ed, + &pci_dev_info_103c_1200, + &pci_dev_info_103c_1219, + &pci_dev_info_103c_121a, + &pci_dev_info_103c_121b, + &pci_dev_info_103c_121c, + &pci_dev_info_103c_1229, + &pci_dev_info_103c_122a, + &pci_dev_info_103c_122e, + &pci_dev_info_103c_1290, + &pci_dev_info_103c_2910, + &pci_dev_info_103c_2925, + NULL +}; +#define pci_dev_list_103e NULL +#define pci_dev_list_103f NULL +#define pci_dev_list_1040 NULL +#define pci_dev_list_1041 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1042[] = { + &pci_dev_info_1042_1000, + &pci_dev_info_1042_1001, + &pci_dev_info_1042_3000, + &pci_dev_info_1042_3010, + &pci_dev_info_1042_3020, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1043[] = { + &pci_dev_info_1043_0675, + &pci_dev_info_1043_4021, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1044[] = { + &pci_dev_info_1044_1012, + &pci_dev_info_1044_a400, + &pci_dev_info_1044_a500, + &pci_dev_info_1044_a501, + &pci_dev_info_1044_a511, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1045[] = { + &pci_dev_info_1045_a0f8, + &pci_dev_info_1045_c101, + &pci_dev_info_1045_c178, + &pci_dev_info_1045_c556, + &pci_dev_info_1045_c557, + &pci_dev_info_1045_c558, + &pci_dev_info_1045_c567, + &pci_dev_info_1045_c568, + &pci_dev_info_1045_c569, + &pci_dev_info_1045_c621, + &pci_dev_info_1045_c700, + &pci_dev_info_1045_c701, + &pci_dev_info_1045_c814, + &pci_dev_info_1045_c822, + &pci_dev_info_1045_c824, + &pci_dev_info_1045_c825, + &pci_dev_info_1045_c832, + &pci_dev_info_1045_c861, + &pci_dev_info_1045_c895, + &pci_dev_info_1045_c935, + &pci_dev_info_1045_d568, + &pci_dev_info_1045_d721, + NULL +}; +#endif +#define pci_dev_list_1046 NULL +#define pci_dev_list_1047 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1048[] = { + &pci_dev_info_1048_0d22, + &pci_dev_info_1048_1000, + &pci_dev_info_1048_3000, + NULL +}; +#endif +#define pci_dev_list_1049 NULL +static const pciDeviceInfo *pci_dev_list_104a[] = { + &pci_dev_info_104a_0008, + &pci_dev_info_104a_0009, + &pci_dev_info_104a_0010, + &pci_dev_info_104a_0210, + &pci_dev_info_104a_0981, + &pci_dev_info_104a_1746, + &pci_dev_info_104a_2774, + &pci_dev_info_104a_3520, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_104b[] = { + &pci_dev_info_104b_0140, + &pci_dev_info_104b_1040, + &pci_dev_info_104b_8130, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_104c[] = { + &pci_dev_info_104c_0500, + &pci_dev_info_104c_0508, + &pci_dev_info_104c_1000, + &pci_dev_info_104c_104c, + &pci_dev_info_104c_3d04, + &pci_dev_info_104c_3d07, + &pci_dev_info_104c_8000, + &pci_dev_info_104c_8009, + &pci_dev_info_104c_8017, + &pci_dev_info_104c_8019, + &pci_dev_info_104c_8020, + &pci_dev_info_104c_8021, + &pci_dev_info_104c_8022, + &pci_dev_info_104c_8023, + &pci_dev_info_104c_8024, + &pci_dev_info_104c_8026, + &pci_dev_info_104c_8027, + &pci_dev_info_104c_8400, + &pci_dev_info_104c_a001, + &pci_dev_info_104c_a100, + &pci_dev_info_104c_a102, + &pci_dev_info_104c_a106, + &pci_dev_info_104c_ac10, + &pci_dev_info_104c_ac11, + &pci_dev_info_104c_ac12, + &pci_dev_info_104c_ac13, + &pci_dev_info_104c_ac15, + &pci_dev_info_104c_ac16, + &pci_dev_info_104c_ac17, + &pci_dev_info_104c_ac18, + &pci_dev_info_104c_ac19, + &pci_dev_info_104c_ac1a, + &pci_dev_info_104c_ac1b, + &pci_dev_info_104c_ac1c, + &pci_dev_info_104c_ac1d, + &pci_dev_info_104c_ac1e, + &pci_dev_info_104c_ac1f, + &pci_dev_info_104c_ac20, + &pci_dev_info_104c_ac21, + &pci_dev_info_104c_ac22, + &pci_dev_info_104c_ac23, + &pci_dev_info_104c_ac28, + &pci_dev_info_104c_ac30, + &pci_dev_info_104c_ac40, + &pci_dev_info_104c_ac41, + &pci_dev_info_104c_ac42, + &pci_dev_info_104c_ac50, + &pci_dev_info_104c_ac51, + &pci_dev_info_104c_ac52, + &pci_dev_info_104c_ac53, + &pci_dev_info_104c_ac55, + &pci_dev_info_104c_ac56, + &pci_dev_info_104c_ac60, + &pci_dev_info_104c_fe00, + &pci_dev_info_104c_fe03, + NULL +}; +static const pciDeviceInfo *pci_dev_list_104d[] = { + &pci_dev_info_104d_8009, + &pci_dev_info_104d_8039, + &pci_dev_info_104d_8056, + &pci_dev_info_104d_808a, + NULL +}; +static const pciDeviceInfo *pci_dev_list_104e[] = { + &pci_dev_info_104e_0017, + &pci_dev_info_104e_0107, + &pci_dev_info_104e_0109, + &pci_dev_info_104e_0111, + &pci_dev_info_104e_0217, + &pci_dev_info_104e_0317, + NULL +}; +#define pci_dev_list_104f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1050[] = { + &pci_dev_info_1050_0000, + &pci_dev_info_1050_0001, + &pci_dev_info_1050_0105, + &pci_dev_info_1050_0840, + &pci_dev_info_1050_0940, + &pci_dev_info_1050_5a5a, + &pci_dev_info_1050_6692, + &pci_dev_info_1050_9970, + NULL +}; +#endif +#define pci_dev_list_1051 NULL +#define pci_dev_list_1052 NULL +#define pci_dev_list_1053 NULL +#define pci_dev_list_1054 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1055[] = { + &pci_dev_info_1055_9130, + &pci_dev_info_1055_9460, + &pci_dev_info_1055_9462, + &pci_dev_info_1055_9463, + NULL +}; +#endif +#define pci_dev_list_1056 NULL +static const pciDeviceInfo *pci_dev_list_1057[] = { + &pci_dev_info_1057_0001, + &pci_dev_info_1057_0002, + &pci_dev_info_1057_0003, + &pci_dev_info_1057_0004, + &pci_dev_info_1057_0006, + &pci_dev_info_1057_0100, + &pci_dev_info_1057_0431, + &pci_dev_info_1057_1801, + &pci_dev_info_1057_18c0, + &pci_dev_info_1057_4801, + &pci_dev_info_1057_4802, + &pci_dev_info_1057_4803, + &pci_dev_info_1057_4806, + &pci_dev_info_1057_4d68, + &pci_dev_info_1057_5600, + &pci_dev_info_1057_6400, + NULL +}; +#define pci_dev_list_1058 NULL +#define pci_dev_list_1059 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_105a[] = { + &pci_dev_info_105a_0d30, + &pci_dev_info_105a_0d38, + &pci_dev_info_105a_1275, + &pci_dev_info_105a_3376, + &pci_dev_info_105a_4d30, + &pci_dev_info_105a_4d33, + &pci_dev_info_105a_4d38, + &pci_dev_info_105a_4d68, + &pci_dev_info_105a_4d69, + &pci_dev_info_105a_5275, + &pci_dev_info_105a_5300, + &pci_dev_info_105a_6268, + &pci_dev_info_105a_6269, + &pci_dev_info_105a_6621, + &pci_dev_info_105a_7275, + NULL +}; +#endif +#define pci_dev_list_105b NULL +#define pci_dev_list_105c NULL +static const pciDeviceInfo *pci_dev_list_105d[] = { + &pci_dev_info_105d_2309, + &pci_dev_info_105d_2339, + &pci_dev_info_105d_493d, + &pci_dev_info_105d_5348, + NULL +}; +#define pci_dev_list_105e NULL +#define pci_dev_list_105f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1060[] = { + &pci_dev_info_1060_0001, + &pci_dev_info_1060_0002, + &pci_dev_info_1060_0101, + &pci_dev_info_1060_0881, + &pci_dev_info_1060_0886, + &pci_dev_info_1060_0891, + &pci_dev_info_1060_1001, + &pci_dev_info_1060_673a, + &pci_dev_info_1060_673b, + &pci_dev_info_1060_8710, + &pci_dev_info_1060_886a, + &pci_dev_info_1060_8881, + &pci_dev_info_1060_8886, + &pci_dev_info_1060_888a, + &pci_dev_info_1060_8891, + &pci_dev_info_1060_9017, + &pci_dev_info_1060_9018, + &pci_dev_info_1060_9026, + &pci_dev_info_1060_e881, + &pci_dev_info_1060_e886, + &pci_dev_info_1060_e88a, + &pci_dev_info_1060_e891, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1061[] = { + &pci_dev_info_1061_0001, + &pci_dev_info_1061_0002, + NULL +}; +#endif +#define pci_dev_list_1062 NULL +#define pci_dev_list_1063 NULL +#define pci_dev_list_1064 NULL +#define pci_dev_list_1065 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1066[] = { + &pci_dev_info_1066_0000, + &pci_dev_info_1066_0001, + &pci_dev_info_1066_0002, + &pci_dev_info_1066_0003, + &pci_dev_info_1066_0004, + &pci_dev_info_1066_0005, + &pci_dev_info_1066_8002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1067[] = { + &pci_dev_info_1067_1002, + NULL +}; +#endif +#define pci_dev_list_1068 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1069[] = { + &pci_dev_info_1069_0001, + &pci_dev_info_1069_0002, + &pci_dev_info_1069_0010, + &pci_dev_info_1069_0050, + &pci_dev_info_1069_ba55, + &pci_dev_info_1069_ba56, + NULL +}; +#endif +#define pci_dev_list_106a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_106b[] = { + &pci_dev_info_106b_0001, + &pci_dev_info_106b_0002, + &pci_dev_info_106b_0003, + &pci_dev_info_106b_0004, + &pci_dev_info_106b_0007, + &pci_dev_info_106b_000e, + &pci_dev_info_106b_0010, + &pci_dev_info_106b_0017, + &pci_dev_info_106b_0018, + &pci_dev_info_106b_0019, + &pci_dev_info_106b_001e, + &pci_dev_info_106b_001f, + &pci_dev_info_106b_0020, + &pci_dev_info_106b_0021, + &pci_dev_info_106b_0022, + &pci_dev_info_106b_0024, + &pci_dev_info_106b_0025, + &pci_dev_info_106b_0026, + &pci_dev_info_106b_0027, + &pci_dev_info_106b_0028, + &pci_dev_info_106b_0029, + &pci_dev_info_106b_002d, + &pci_dev_info_106b_002e, + &pci_dev_info_106b_002f, + &pci_dev_info_106b_0030, + &pci_dev_info_106b_0031, + &pci_dev_info_106b_0032, + &pci_dev_info_106b_0033, + &pci_dev_info_106b_0034, + &pci_dev_info_106b_1645, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_106c[] = { + &pci_dev_info_106c_8801, + &pci_dev_info_106c_8802, + &pci_dev_info_106c_8803, + &pci_dev_info_106c_8804, + &pci_dev_info_106c_8805, + NULL +}; +#endif +#define pci_dev_list_106d NULL +#define pci_dev_list_106e NULL +#define pci_dev_list_106f NULL +#define pci_dev_list_1070 NULL +#define pci_dev_list_1071 NULL +#define pci_dev_list_1072 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1073[] = { + &pci_dev_info_1073_0001, + &pci_dev_info_1073_0002, + &pci_dev_info_1073_0003, + &pci_dev_info_1073_0004, + &pci_dev_info_1073_0005, + &pci_dev_info_1073_0006, + &pci_dev_info_1073_0008, + &pci_dev_info_1073_000a, + &pci_dev_info_1073_000c, + &pci_dev_info_1073_000d, + &pci_dev_info_1073_0010, + &pci_dev_info_1073_0012, + &pci_dev_info_1073_0020, + &pci_dev_info_1073_2000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1074[] = { + &pci_dev_info_1074_4e78, + NULL +}; +#endif +#define pci_dev_list_1075 NULL +#define pci_dev_list_1076 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1077[] = { + &pci_dev_info_1077_1016, + &pci_dev_info_1077_1020, + &pci_dev_info_1077_1022, + &pci_dev_info_1077_1080, + &pci_dev_info_1077_1216, + &pci_dev_info_1077_1240, + &pci_dev_info_1077_1280, + &pci_dev_info_1077_2020, + &pci_dev_info_1077_2100, + &pci_dev_info_1077_2200, + &pci_dev_info_1077_2300, + &pci_dev_info_1077_2312, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_1078[] = { + &pci_dev_info_1078_0000, + &pci_dev_info_1078_0001, + &pci_dev_info_1078_0002, + &pci_dev_info_1078_0100, + &pci_dev_info_1078_0101, + &pci_dev_info_1078_0102, + &pci_dev_info_1078_0103, + &pci_dev_info_1078_0104, + &pci_dev_info_1078_0400, + &pci_dev_info_1078_0401, + &pci_dev_info_1078_0402, + &pci_dev_info_1078_0403, + NULL +}; +#define pci_dev_list_1079 NULL +#define pci_dev_list_107a NULL +#define pci_dev_list_107b NULL +#define pci_dev_list_107c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_107d[] = { + &pci_dev_info_107d_0000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_107e[] = { + &pci_dev_info_107e_0001, + &pci_dev_info_107e_0002, + &pci_dev_info_107e_0004, + &pci_dev_info_107e_0005, + &pci_dev_info_107e_0008, + &pci_dev_info_107e_9003, + &pci_dev_info_107e_9007, + &pci_dev_info_107e_9008, + &pci_dev_info_107e_900c, + &pci_dev_info_107e_900e, + &pci_dev_info_107e_9011, + &pci_dev_info_107e_9013, + &pci_dev_info_107e_9023, + &pci_dev_info_107e_9027, + &pci_dev_info_107e_9031, + &pci_dev_info_107e_9033, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_107f[] = { + &pci_dev_info_107f_0802, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1080[] = { + &pci_dev_info_1080_0600, + &pci_dev_info_1080_c691, + &pci_dev_info_1080_c693, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1081[] = { + &pci_dev_info_1081_0d47, + NULL +}; +#endif +#define pci_dev_list_1082 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1083[] = { + &pci_dev_info_1083_0001, + NULL +}; +#endif +#define pci_dev_list_1084 NULL +#define pci_dev_list_1085 NULL +#define pci_dev_list_1086 NULL +#define pci_dev_list_1087 NULL +#define pci_dev_list_1088 NULL +#define pci_dev_list_1089 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_108a[] = { + &pci_dev_info_108a_0001, + &pci_dev_info_108a_0010, + &pci_dev_info_108a_0040, + &pci_dev_info_108a_3000, + NULL +}; +#endif +#define pci_dev_list_108c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_108d[] = { + &pci_dev_info_108d_0001, + &pci_dev_info_108d_0002, + &pci_dev_info_108d_0004, + &pci_dev_info_108d_0005, + &pci_dev_info_108d_0006, + &pci_dev_info_108d_0007, + &pci_dev_info_108d_0008, + &pci_dev_info_108d_0011, + &pci_dev_info_108d_0012, + &pci_dev_info_108d_0013, + &pci_dev_info_108d_0014, + &pci_dev_info_108d_0019, + &pci_dev_info_108d_0021, + &pci_dev_info_108d_0022, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_108e[] = { + &pci_dev_info_108e_0001, + &pci_dev_info_108e_1000, + &pci_dev_info_108e_1001, + &pci_dev_info_108e_1100, + &pci_dev_info_108e_1101, + &pci_dev_info_108e_1102, + &pci_dev_info_108e_1103, + &pci_dev_info_108e_2bad, + &pci_dev_info_108e_5000, + &pci_dev_info_108e_5043, + &pci_dev_info_108e_8000, + &pci_dev_info_108e_8001, + &pci_dev_info_108e_a000, + &pci_dev_info_108e_a001, + NULL +}; +#define pci_dev_list_108f NULL +#define pci_dev_list_1090 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1091[] = { + &pci_dev_info_1091_0020, + &pci_dev_info_1091_0021, + &pci_dev_info_1091_0040, + &pci_dev_info_1091_0041, + &pci_dev_info_1091_0060, + &pci_dev_info_1091_00e4, + &pci_dev_info_1091_0720, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_1092[] = { + &pci_dev_info_1092_00a0, + &pci_dev_info_1092_00a8, + &pci_dev_info_1092_0550, + &pci_dev_info_1092_08d4, + &pci_dev_info_1092_094c, + &pci_dev_info_1092_1092, + &pci_dev_info_1092_6120, + &pci_dev_info_1092_8810, + &pci_dev_info_1092_8811, + &pci_dev_info_1092_8880, + &pci_dev_info_1092_8881, + &pci_dev_info_1092_88b0, + &pci_dev_info_1092_88b1, + &pci_dev_info_1092_88c0, + &pci_dev_info_1092_88c1, + &pci_dev_info_1092_88d0, + &pci_dev_info_1092_88d1, + &pci_dev_info_1092_88f0, + &pci_dev_info_1092_88f1, + &pci_dev_info_1092_9999, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1093[] = { + &pci_dev_info_1093_0160, + &pci_dev_info_1093_0162, + &pci_dev_info_1093_1170, + &pci_dev_info_1093_1180, + &pci_dev_info_1093_1190, + &pci_dev_info_1093_1330, + &pci_dev_info_1093_1350, + &pci_dev_info_1093_2a60, + &pci_dev_info_1093_b001, + &pci_dev_info_1093_b011, + &pci_dev_info_1093_b021, + &pci_dev_info_1093_b031, + &pci_dev_info_1093_b041, + &pci_dev_info_1093_b051, + &pci_dev_info_1093_b061, + &pci_dev_info_1093_b071, + &pci_dev_info_1093_b081, + &pci_dev_info_1093_b091, + &pci_dev_info_1093_c801, + &pci_dev_info_1093_c831, + NULL +}; +#endif +#define pci_dev_list_1094 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1095[] = { + &pci_dev_info_1095_0640, + &pci_dev_info_1095_0643, + &pci_dev_info_1095_0646, + &pci_dev_info_1095_0647, + &pci_dev_info_1095_0648, + &pci_dev_info_1095_0649, + &pci_dev_info_1095_0650, + &pci_dev_info_1095_0670, + &pci_dev_info_1095_0673, + &pci_dev_info_1095_0680, + &pci_dev_info_1095_3112, + NULL +}; +#endif +#define pci_dev_list_1096 NULL +#define pci_dev_list_1097 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1098[] = { + &pci_dev_info_1098_0001, + &pci_dev_info_1098_0002, + NULL +}; +#endif +#define pci_dev_list_1099 NULL +#define pci_dev_list_109a NULL +#define pci_dev_list_109b NULL +#define pci_dev_list_109c NULL +#define pci_dev_list_109d NULL +static const pciDeviceInfo *pci_dev_list_109e[] = { + &pci_dev_info_109e_0350, + &pci_dev_info_109e_0351, + &pci_dev_info_109e_0369, + &pci_dev_info_109e_036c, + &pci_dev_info_109e_036e, + &pci_dev_info_109e_036f, + &pci_dev_info_109e_0370, + &pci_dev_info_109e_0878, + &pci_dev_info_109e_0879, + &pci_dev_info_109e_0880, + &pci_dev_info_109e_2115, + &pci_dev_info_109e_2125, + &pci_dev_info_109e_2164, + &pci_dev_info_109e_2165, + &pci_dev_info_109e_8230, + &pci_dev_info_109e_8472, + &pci_dev_info_109e_8474, + NULL +}; +#define pci_dev_list_109f NULL +#define pci_dev_list_10a0 NULL +#define pci_dev_list_10a1 NULL +#define pci_dev_list_10a2 NULL +#define pci_dev_list_10a3 NULL +#define pci_dev_list_10a4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10a5[] = { + &pci_dev_info_10a5_5449, + NULL +}; +#endif +#define pci_dev_list_10a6 NULL +#define pci_dev_list_10a7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10a8[] = { + &pci_dev_info_10a8_0000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10a9[] = { + &pci_dev_info_10a9_0001, + &pci_dev_info_10a9_0002, + &pci_dev_info_10a9_0003, + &pci_dev_info_10a9_0004, + &pci_dev_info_10a9_0005, + &pci_dev_info_10a9_0006, + &pci_dev_info_10a9_0007, + &pci_dev_info_10a9_0008, + &pci_dev_info_10a9_0009, + &pci_dev_info_10a9_0010, + &pci_dev_info_10a9_0011, + &pci_dev_info_10a9_0012, + &pci_dev_info_10a9_1001, + &pci_dev_info_10a9_1002, + &pci_dev_info_10a9_1003, + &pci_dev_info_10a9_1004, + &pci_dev_info_10a9_1005, + &pci_dev_info_10a9_1006, + &pci_dev_info_10a9_1007, + &pci_dev_info_10a9_1008, + &pci_dev_info_10a9_2001, + &pci_dev_info_10a9_2002, + &pci_dev_info_10a9_8001, + &pci_dev_info_10a9_8002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10aa[] = { + &pci_dev_info_10aa_0000, + NULL +}; +#endif +#define pci_dev_list_10ab NULL +#define pci_dev_list_10ac NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ad[] = { + &pci_dev_info_10ad_0001, + &pci_dev_info_10ad_0003, + &pci_dev_info_10ad_0005, + &pci_dev_info_10ad_0103, + &pci_dev_info_10ad_0105, + &pci_dev_info_10ad_0565, + NULL +}; +#endif +#define pci_dev_list_10ae NULL +#define pci_dev_list_10af NULL +#define pci_dev_list_10b0 NULL +#define pci_dev_list_10b1 NULL +#define pci_dev_list_10b2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b3[] = { + &pci_dev_info_10b3_3106, + &pci_dev_info_10b3_b106, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b4[] = { + &pci_dev_info_10b4_1b1d, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b5[] = { + &pci_dev_info_10b5_0001, + &pci_dev_info_10b5_1076, + &pci_dev_info_10b5_1077, + &pci_dev_info_10b5_1078, + &pci_dev_info_10b5_1103, + &pci_dev_info_10b5_1146, + &pci_dev_info_10b5_1147, + &pci_dev_info_10b5_2724, + &pci_dev_info_10b5_9030, + &pci_dev_info_10b5_9036, + &pci_dev_info_10b5_9050, + &pci_dev_info_10b5_9054, + &pci_dev_info_10b5_9060, + &pci_dev_info_10b5_906d, + &pci_dev_info_10b5_906e, + &pci_dev_info_10b5_9080, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b6[] = { + &pci_dev_info_10b6_0001, + &pci_dev_info_10b6_0002, + &pci_dev_info_10b6_0003, + &pci_dev_info_10b6_0004, + &pci_dev_info_10b6_0006, + &pci_dev_info_10b6_0007, + &pci_dev_info_10b6_0009, + &pci_dev_info_10b6_000a, + &pci_dev_info_10b6_000b, + &pci_dev_info_10b6_000c, + &pci_dev_info_10b6_1000, + &pci_dev_info_10b6_1001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b7[] = { + &pci_dev_info_10b7_0001, + &pci_dev_info_10b7_1006, + &pci_dev_info_10b7_1007, + &pci_dev_info_10b7_3390, + &pci_dev_info_10b7_3590, + &pci_dev_info_10b7_4500, + &pci_dev_info_10b7_5055, + &pci_dev_info_10b7_5057, + &pci_dev_info_10b7_5157, + &pci_dev_info_10b7_5257, + &pci_dev_info_10b7_5900, + &pci_dev_info_10b7_5920, + &pci_dev_info_10b7_5950, + &pci_dev_info_10b7_5951, + &pci_dev_info_10b7_5952, + &pci_dev_info_10b7_5970, + &pci_dev_info_10b7_5b57, + &pci_dev_info_10b7_6055, + &pci_dev_info_10b7_6056, + &pci_dev_info_10b7_6560, + &pci_dev_info_10b7_6561, + &pci_dev_info_10b7_6562, + &pci_dev_info_10b7_6563, + &pci_dev_info_10b7_6564, + &pci_dev_info_10b7_7646, + &pci_dev_info_10b7_7940, + &pci_dev_info_10b7_7980, + &pci_dev_info_10b7_7990, + &pci_dev_info_10b7_8811, + &pci_dev_info_10b7_9000, + &pci_dev_info_10b7_9001, + &pci_dev_info_10b7_9004, + &pci_dev_info_10b7_9005, + &pci_dev_info_10b7_9006, + &pci_dev_info_10b7_900a, + &pci_dev_info_10b7_9050, + &pci_dev_info_10b7_9051, + &pci_dev_info_10b7_9055, + &pci_dev_info_10b7_9056, + &pci_dev_info_10b7_9058, + &pci_dev_info_10b7_905a, + &pci_dev_info_10b7_9200, + &pci_dev_info_10b7_9201, + &pci_dev_info_10b7_9300, + &pci_dev_info_10b7_9800, + &pci_dev_info_10b7_9805, + &pci_dev_info_10b7_9900, + &pci_dev_info_10b7_9902, + &pci_dev_info_10b7_9903, + &pci_dev_info_10b7_9904, + &pci_dev_info_10b7_9905, + &pci_dev_info_10b7_9908, + &pci_dev_info_10b7_9909, + &pci_dev_info_10b7_990b, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b8[] = { + &pci_dev_info_10b8_0005, + &pci_dev_info_10b8_0006, + &pci_dev_info_10b8_1000, + &pci_dev_info_10b8_1001, + &pci_dev_info_10b8_a011, + &pci_dev_info_10b8_b106, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_10b9[] = { + &pci_dev_info_10b9_0111, + &pci_dev_info_10b9_1435, + &pci_dev_info_10b9_1445, + &pci_dev_info_10b9_1449, + &pci_dev_info_10b9_1451, + &pci_dev_info_10b9_1461, + &pci_dev_info_10b9_1489, + &pci_dev_info_10b9_1511, + &pci_dev_info_10b9_1512, + &pci_dev_info_10b9_1513, + &pci_dev_info_10b9_1521, + &pci_dev_info_10b9_1523, + &pci_dev_info_10b9_1531, + &pci_dev_info_10b9_1533, + &pci_dev_info_10b9_1541, + &pci_dev_info_10b9_1543, + &pci_dev_info_10b9_1563, + &pci_dev_info_10b9_1621, + &pci_dev_info_10b9_1631, + &pci_dev_info_10b9_1632, + &pci_dev_info_10b9_1641, + &pci_dev_info_10b9_1644, + &pci_dev_info_10b9_1646, + &pci_dev_info_10b9_1647, + &pci_dev_info_10b9_1651, + &pci_dev_info_10b9_1671, + &pci_dev_info_10b9_1681, + &pci_dev_info_10b9_1687, + &pci_dev_info_10b9_3141, + &pci_dev_info_10b9_3143, + &pci_dev_info_10b9_3145, + &pci_dev_info_10b9_3147, + &pci_dev_info_10b9_3149, + &pci_dev_info_10b9_3151, + &pci_dev_info_10b9_3307, + &pci_dev_info_10b9_3309, + &pci_dev_info_10b9_5212, + &pci_dev_info_10b9_5215, + &pci_dev_info_10b9_5217, + &pci_dev_info_10b9_5219, + &pci_dev_info_10b9_5225, + &pci_dev_info_10b9_5229, + &pci_dev_info_10b9_5235, + &pci_dev_info_10b9_5237, + &pci_dev_info_10b9_5239, + &pci_dev_info_10b9_5243, + &pci_dev_info_10b9_5247, + &pci_dev_info_10b9_5249, + &pci_dev_info_10b9_5251, + &pci_dev_info_10b9_5253, + &pci_dev_info_10b9_5261, + &pci_dev_info_10b9_5451, + &pci_dev_info_10b9_5453, + &pci_dev_info_10b9_5455, + &pci_dev_info_10b9_5457, + &pci_dev_info_10b9_5459, + &pci_dev_info_10b9_545a, + &pci_dev_info_10b9_5471, + &pci_dev_info_10b9_5473, + &pci_dev_info_10b9_7101, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ba[] = { + &pci_dev_info_10ba_0301, + NULL +}; +#endif +#define pci_dev_list_10bb NULL +#define pci_dev_list_10bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10bd[] = { + &pci_dev_info_10bd_0e34, + NULL +}; +#endif +#define pci_dev_list_10be NULL +#define pci_dev_list_10bf NULL +#define pci_dev_list_10c0 NULL +#define pci_dev_list_10c1 NULL +#define pci_dev_list_10c2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10c3[] = { + &pci_dev_info_10c3_1100, + NULL +}; +#endif +#define pci_dev_list_10c4 NULL +#define pci_dev_list_10c5 NULL +#define pci_dev_list_10c6 NULL +#define pci_dev_list_10c7 NULL +static const pciDeviceInfo *pci_dev_list_10c8[] = { + &pci_dev_info_10c8_0001, + &pci_dev_info_10c8_0002, + &pci_dev_info_10c8_0003, + &pci_dev_info_10c8_0004, + &pci_dev_info_10c8_0005, + &pci_dev_info_10c8_0006, + &pci_dev_info_10c8_0016, + &pci_dev_info_10c8_0025, + &pci_dev_info_10c8_0083, + &pci_dev_info_10c8_8005, + &pci_dev_info_10c8_8006, + &pci_dev_info_10c8_8016, + NULL +}; +#define pci_dev_list_10c9 NULL +#define pci_dev_list_10ca NULL +#define pci_dev_list_10cb NULL +#define pci_dev_list_10cc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10cd[] = { + &pci_dev_info_10cd_1100, + &pci_dev_info_10cd_1200, + &pci_dev_info_10cd_1300, + &pci_dev_info_10cd_2300, + &pci_dev_info_10cd_2500, + NULL +}; +#endif +#define pci_dev_list_10ce NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10cf[] = { + &pci_dev_info_10cf_2001, + NULL +}; +#endif +#define pci_dev_list_10d0 NULL +#define pci_dev_list_10d1 NULL +#define pci_dev_list_10d2 NULL +#define pci_dev_list_10d3 NULL +#define pci_dev_list_10d4 NULL +#define pci_dev_list_10d5 NULL +#define pci_dev_list_10d6 NULL +#define pci_dev_list_10d7 NULL +#define pci_dev_list_10d8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10d9[] = { + &pci_dev_info_10d9_0512, + &pci_dev_info_10d9_0531, + &pci_dev_info_10d9_8625, + &pci_dev_info_10d9_8888, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10da[] = { + &pci_dev_info_10da_0508, + &pci_dev_info_10da_3390, + NULL +}; +#endif +#define pci_dev_list_10db NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10dc[] = { + &pci_dev_info_10dc_0001, + &pci_dev_info_10dc_0002, + &pci_dev_info_10dc_0021, + &pci_dev_info_10dc_0022, + &pci_dev_info_10dc_10dc, + NULL +}; +#endif +#define pci_dev_list_10dd NULL +static const pciDeviceInfo *pci_dev_list_10de[] = { + &pci_dev_info_10de_0008, + &pci_dev_info_10de_0009, + &pci_dev_info_10de_0010, + &pci_dev_info_10de_0020, + &pci_dev_info_10de_0028, + &pci_dev_info_10de_0029, + &pci_dev_info_10de_002a, + &pci_dev_info_10de_002b, + &pci_dev_info_10de_002c, + &pci_dev_info_10de_002d, + &pci_dev_info_10de_002e, + &pci_dev_info_10de_002f, + &pci_dev_info_10de_0060, + &pci_dev_info_10de_0064, + &pci_dev_info_10de_0065, + &pci_dev_info_10de_0066, + &pci_dev_info_10de_0067, + &pci_dev_info_10de_0068, + &pci_dev_info_10de_006a, + &pci_dev_info_10de_006b, + &pci_dev_info_10de_006e, + &pci_dev_info_10de_00a0, + &pci_dev_info_10de_0100, + &pci_dev_info_10de_0101, + &pci_dev_info_10de_0103, + &pci_dev_info_10de_0110, + &pci_dev_info_10de_0111, + &pci_dev_info_10de_0112, + &pci_dev_info_10de_0113, + &pci_dev_info_10de_0150, + &pci_dev_info_10de_0151, + &pci_dev_info_10de_0152, + &pci_dev_info_10de_0153, + &pci_dev_info_10de_0170, + &pci_dev_info_10de_0171, + &pci_dev_info_10de_0172, + &pci_dev_info_10de_0173, + &pci_dev_info_10de_0174, + &pci_dev_info_10de_0175, + &pci_dev_info_10de_0176, + &pci_dev_info_10de_0178, + &pci_dev_info_10de_0179, + &pci_dev_info_10de_017a, + &pci_dev_info_10de_017b, + &pci_dev_info_10de_017c, + &pci_dev_info_10de_0181, + &pci_dev_info_10de_0182, + &pci_dev_info_10de_0183, + &pci_dev_info_10de_0188, + &pci_dev_info_10de_018a, + &pci_dev_info_10de_018b, + &pci_dev_info_10de_01a0, + &pci_dev_info_10de_01a4, + &pci_dev_info_10de_01ab, + &pci_dev_info_10de_01ac, + &pci_dev_info_10de_01ad, + &pci_dev_info_10de_01b1, + &pci_dev_info_10de_01b2, + &pci_dev_info_10de_01b4, + &pci_dev_info_10de_01b7, + &pci_dev_info_10de_01b8, + &pci_dev_info_10de_01bc, + &pci_dev_info_10de_01c1, + &pci_dev_info_10de_01c2, + &pci_dev_info_10de_01c3, + &pci_dev_info_10de_01e8, + &pci_dev_info_10de_01f0, + &pci_dev_info_10de_0200, + &pci_dev_info_10de_0201, + &pci_dev_info_10de_0202, + &pci_dev_info_10de_0203, + &pci_dev_info_10de_0250, + &pci_dev_info_10de_0251, + &pci_dev_info_10de_0252, + &pci_dev_info_10de_0253, + &pci_dev_info_10de_0258, + &pci_dev_info_10de_0259, + &pci_dev_info_10de_025b, + &pci_dev_info_10de_0280, + &pci_dev_info_10de_0281, + &pci_dev_info_10de_0282, + &pci_dev_info_10de_0288, + &pci_dev_info_10de_0289, + &pci_dev_info_10de_0300, + &pci_dev_info_10de_0301, + &pci_dev_info_10de_0302, + &pci_dev_info_10de_0308, + &pci_dev_info_10de_0309, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10df[] = { + &pci_dev_info_10df_1ae5, + &pci_dev_info_10df_f085, + &pci_dev_info_10df_f095, + &pci_dev_info_10df_f098, + &pci_dev_info_10df_f700, + &pci_dev_info_10df_f800, + &pci_dev_info_10df_f900, + &pci_dev_info_10df_f980, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_10e0[] = { + &pci_dev_info_10e0_5026, + &pci_dev_info_10e0_5027, + &pci_dev_info_10e0_5028, + &pci_dev_info_10e0_8849, + &pci_dev_info_10e0_8853, + &pci_dev_info_10e0_9128, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10e1[] = { + &pci_dev_info_10e1_0391, + &pci_dev_info_10e1_690c, + &pci_dev_info_10e1_dc29, + NULL +}; +#endif +#define pci_dev_list_10e2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10e3[] = { + &pci_dev_info_10e3_0000, + &pci_dev_info_10e3_0860, + &pci_dev_info_10e3_0862, + NULL +}; +#endif +#define pci_dev_list_10e4 NULL +#define pci_dev_list_10e5 NULL +#define pci_dev_list_10e6 NULL +#define pci_dev_list_10e7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10e8[] = { + &pci_dev_info_10e8_2011, + &pci_dev_info_10e8_4750, + &pci_dev_info_10e8_5920, + &pci_dev_info_10e8_8043, + &pci_dev_info_10e8_8062, + &pci_dev_info_10e8_807d, + &pci_dev_info_10e8_8088, + &pci_dev_info_10e8_8089, + &pci_dev_info_10e8_809c, + &pci_dev_info_10e8_80d7, + &pci_dev_info_10e8_80d9, + &pci_dev_info_10e8_80da, + &pci_dev_info_10e8_811a, + &pci_dev_info_10e8_8170, + &pci_dev_info_10e8_82db, + NULL +}; +#endif +#define pci_dev_list_10e9 NULL +static const pciDeviceInfo *pci_dev_list_10ea[] = { + &pci_dev_info_10ea_1680, + &pci_dev_info_10ea_1682, + &pci_dev_info_10ea_1683, + &pci_dev_info_10ea_2000, + &pci_dev_info_10ea_2010, + &pci_dev_info_10ea_5000, + &pci_dev_info_10ea_5050, + &pci_dev_info_10ea_5202, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10eb[] = { + &pci_dev_info_10eb_0101, + &pci_dev_info_10eb_8111, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ec[] = { + &pci_dev_info_10ec_8029, + &pci_dev_info_10ec_8129, + &pci_dev_info_10ec_8138, + &pci_dev_info_10ec_8139, + &pci_dev_info_10ec_8169, + &pci_dev_info_10ec_8197, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ed[] = { + &pci_dev_info_10ed_7310, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ee[] = { + &pci_dev_info_10ee_3fc0, + &pci_dev_info_10ee_3fc1, + &pci_dev_info_10ee_3fc2, + &pci_dev_info_10ee_3fc3, + &pci_dev_info_10ee_3fc4, + &pci_dev_info_10ee_3fc5, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ef[] = { + &pci_dev_info_10ef_8154, + NULL +}; +#endif +#define pci_dev_list_10f0 NULL +#define pci_dev_list_10f1 NULL +#define pci_dev_list_10f2 NULL +#define pci_dev_list_10f3 NULL +#define pci_dev_list_10f4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10f5[] = { + &pci_dev_info_10f5_a001, + NULL +}; +#endif +#define pci_dev_list_10f6 NULL +#define pci_dev_list_10f7 NULL +#define pci_dev_list_10f8 NULL +#define pci_dev_list_10f9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10fa[] = { + &pci_dev_info_10fa_000c, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10fb[] = { + &pci_dev_info_10fb_186f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10fc[] = { + &pci_dev_info_10fc_0003, + &pci_dev_info_10fc_0005, + NULL +}; +#endif +#define pci_dev_list_10fd NULL +#define pci_dev_list_10fe NULL +#define pci_dev_list_10ff NULL +#define pci_dev_list_1100 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1101[] = { + &pci_dev_info_1101_1060, + &pci_dev_info_1101_9100, + &pci_dev_info_1101_9400, + &pci_dev_info_1101_9401, + &pci_dev_info_1101_9500, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1102[] = { + &pci_dev_info_1102_0002, + &pci_dev_info_1102_0004, + &pci_dev_info_1102_0006, + &pci_dev_info_1102_4001, + &pci_dev_info_1102_7002, + &pci_dev_info_1102_7003, + &pci_dev_info_1102_7004, + &pci_dev_info_1102_8064, + &pci_dev_info_1102_8938, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1103[] = { + &pci_dev_info_1103_0003, + &pci_dev_info_1103_0004, + &pci_dev_info_1103_0005, + &pci_dev_info_1103_0006, + &pci_dev_info_1103_0007, + &pci_dev_info_1103_0008, + NULL +}; +#endif +#define pci_dev_list_1104 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1105[] = { + &pci_dev_info_1105_1105, + &pci_dev_info_1105_8300, + &pci_dev_info_1105_8400, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_1106[] = { + &pci_dev_info_1106_0102, + &pci_dev_info_1106_0130, + &pci_dev_info_1106_0305, + &pci_dev_info_1106_0391, + &pci_dev_info_1106_0501, + &pci_dev_info_1106_0505, + &pci_dev_info_1106_0561, + &pci_dev_info_1106_0571, + &pci_dev_info_1106_0576, + &pci_dev_info_1106_0585, + &pci_dev_info_1106_0586, + &pci_dev_info_1106_0595, + &pci_dev_info_1106_0596, + &pci_dev_info_1106_0597, + &pci_dev_info_1106_0598, + &pci_dev_info_1106_0601, + &pci_dev_info_1106_0605, + &pci_dev_info_1106_0680, + &pci_dev_info_1106_0686, + &pci_dev_info_1106_0691, + &pci_dev_info_1106_0693, + &pci_dev_info_1106_0698, + &pci_dev_info_1106_0926, + &pci_dev_info_1106_1000, + &pci_dev_info_1106_1106, + &pci_dev_info_1106_1571, + &pci_dev_info_1106_1595, + &pci_dev_info_1106_3038, + &pci_dev_info_1106_3040, + &pci_dev_info_1106_3043, + &pci_dev_info_1106_3044, + &pci_dev_info_1106_3050, + &pci_dev_info_1106_3051, + &pci_dev_info_1106_3057, + &pci_dev_info_1106_3058, + &pci_dev_info_1106_3059, + &pci_dev_info_1106_3065, + &pci_dev_info_1106_3068, + &pci_dev_info_1106_3074, + &pci_dev_info_1106_3091, + &pci_dev_info_1106_3099, + &pci_dev_info_1106_3101, + &pci_dev_info_1106_3102, + &pci_dev_info_1106_3103, + &pci_dev_info_1106_3104, + &pci_dev_info_1106_3106, + &pci_dev_info_1106_3109, + &pci_dev_info_1106_3112, + &pci_dev_info_1106_3116, + &pci_dev_info_1106_3122, + &pci_dev_info_1106_3123, + &pci_dev_info_1106_3128, + &pci_dev_info_1106_3133, + &pci_dev_info_1106_3147, + &pci_dev_info_1106_3148, + &pci_dev_info_1106_3156, + &pci_dev_info_1106_3168, + &pci_dev_info_1106_3177, + &pci_dev_info_1106_3189, + &pci_dev_info_1106_5030, + &pci_dev_info_1106_6100, + &pci_dev_info_1106_8231, + &pci_dev_info_1106_8235, + &pci_dev_info_1106_8305, + &pci_dev_info_1106_8391, + &pci_dev_info_1106_8501, + &pci_dev_info_1106_8596, + &pci_dev_info_1106_8597, + &pci_dev_info_1106_8598, + &pci_dev_info_1106_8601, + &pci_dev_info_1106_8605, + &pci_dev_info_1106_8691, + &pci_dev_info_1106_8693, + &pci_dev_info_1106_b091, + &pci_dev_info_1106_b099, + &pci_dev_info_1106_b101, + &pci_dev_info_1106_b102, + &pci_dev_info_1106_b103, + &pci_dev_info_1106_b112, + &pci_dev_info_1106_b168, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1107[] = { + &pci_dev_info_1107_0576, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1108[] = { + &pci_dev_info_1108_0100, + &pci_dev_info_1108_0101, + &pci_dev_info_1108_0105, + &pci_dev_info_1108_0108, + &pci_dev_info_1108_0138, + &pci_dev_info_1108_0139, + &pci_dev_info_1108_013c, + &pci_dev_info_1108_013d, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1109[] = { + &pci_dev_info_1109_1400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_110a[] = { + &pci_dev_info_110a_0002, + &pci_dev_info_110a_0005, + &pci_dev_info_110a_2102, + &pci_dev_info_110a_4942, + &pci_dev_info_110a_6120, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_110b[] = { + &pci_dev_info_110b_0001, + &pci_dev_info_110b_0004, + NULL +}; +#endif +#define pci_dev_list_110c NULL +#define pci_dev_list_110d NULL +#define pci_dev_list_110e NULL +#define pci_dev_list_110f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1110[] = { + &pci_dev_info_1110_6037, + &pci_dev_info_1110_6073, + NULL +}; +#endif +#define pci_dev_list_1111 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1112[] = { + &pci_dev_info_1112_2200, + &pci_dev_info_1112_2300, + &pci_dev_info_1112_2340, + &pci_dev_info_1112_2400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1113[] = { + &pci_dev_info_1113_1211, + &pci_dev_info_1113_1216, + &pci_dev_info_1113_1217, + &pci_dev_info_1113_5105, + &pci_dev_info_1113_9211, + &pci_dev_info_1113_9511, + NULL +}; +#endif +#define pci_dev_list_1114 NULL +#define pci_dev_list_1115 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1116[] = { + &pci_dev_info_1116_0022, + &pci_dev_info_1116_0023, + &pci_dev_info_1116_0024, + &pci_dev_info_1116_0025, + &pci_dev_info_1116_0026, + &pci_dev_info_1116_0027, + &pci_dev_info_1116_0028, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1117[] = { + &pci_dev_info_1117_9500, + &pci_dev_info_1117_9501, + NULL +}; +#endif +#define pci_dev_list_1118 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1119[] = { + &pci_dev_info_1119_0000, + &pci_dev_info_1119_0001, + &pci_dev_info_1119_0002, + &pci_dev_info_1119_0003, + &pci_dev_info_1119_0004, + &pci_dev_info_1119_0005, + &pci_dev_info_1119_0006, + &pci_dev_info_1119_0007, + &pci_dev_info_1119_0008, + &pci_dev_info_1119_0009, + &pci_dev_info_1119_000a, + &pci_dev_info_1119_000b, + &pci_dev_info_1119_000c, + &pci_dev_info_1119_000d, + &pci_dev_info_1119_0100, + &pci_dev_info_1119_0101, + &pci_dev_info_1119_0102, + &pci_dev_info_1119_0103, + &pci_dev_info_1119_0104, + &pci_dev_info_1119_0105, + &pci_dev_info_1119_0110, + &pci_dev_info_1119_0111, + &pci_dev_info_1119_0112, + &pci_dev_info_1119_0113, + &pci_dev_info_1119_0114, + &pci_dev_info_1119_0115, + &pci_dev_info_1119_0118, + &pci_dev_info_1119_0119, + &pci_dev_info_1119_011a, + &pci_dev_info_1119_011b, + &pci_dev_info_1119_0120, + &pci_dev_info_1119_0121, + &pci_dev_info_1119_0122, + &pci_dev_info_1119_0123, + &pci_dev_info_1119_0124, + &pci_dev_info_1119_0125, + &pci_dev_info_1119_0136, + &pci_dev_info_1119_0137, + &pci_dev_info_1119_0138, + &pci_dev_info_1119_0139, + &pci_dev_info_1119_013a, + &pci_dev_info_1119_013b, + &pci_dev_info_1119_013c, + &pci_dev_info_1119_013d, + &pci_dev_info_1119_013e, + &pci_dev_info_1119_013f, + &pci_dev_info_1119_0166, + &pci_dev_info_1119_0167, + &pci_dev_info_1119_0168, + &pci_dev_info_1119_0169, + &pci_dev_info_1119_016a, + &pci_dev_info_1119_016b, + &pci_dev_info_1119_016c, + &pci_dev_info_1119_016d, + &pci_dev_info_1119_016e, + &pci_dev_info_1119_016f, + &pci_dev_info_1119_01d6, + &pci_dev_info_1119_01d7, + &pci_dev_info_1119_01f6, + &pci_dev_info_1119_01f7, + &pci_dev_info_1119_01fc, + &pci_dev_info_1119_01fd, + &pci_dev_info_1119_01fe, + &pci_dev_info_1119_01ff, + &pci_dev_info_1119_0210, + &pci_dev_info_1119_0211, + &pci_dev_info_1119_0260, + &pci_dev_info_1119_0261, + &pci_dev_info_1119_0300, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_111a[] = { + &pci_dev_info_111a_0000, + &pci_dev_info_111a_0002, + &pci_dev_info_111a_0003, + &pci_dev_info_111a_0005, + &pci_dev_info_111a_0007, + NULL +}; +#endif +#define pci_dev_list_111b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_111c[] = { + &pci_dev_info_111c_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_111d[] = { + &pci_dev_info_111d_0001, + &pci_dev_info_111d_0003, + NULL +}; +#endif +#define pci_dev_list_111e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_111f[] = { + &pci_dev_info_111f_4a47, + &pci_dev_info_111f_5243, + NULL +}; +#endif +#define pci_dev_list_1120 NULL +#define pci_dev_list_1121 NULL +#define pci_dev_list_1122 NULL +#define pci_dev_list_1123 NULL +#define pci_dev_list_1124 NULL +#define pci_dev_list_1125 NULL +#define pci_dev_list_1126 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1127[] = { + &pci_dev_info_1127_0200, + &pci_dev_info_1127_0210, + &pci_dev_info_1127_0250, + &pci_dev_info_1127_0300, + &pci_dev_info_1127_0310, + &pci_dev_info_1127_0400, + NULL +}; +#endif +#define pci_dev_list_1129 NULL +#define pci_dev_list_112a NULL +#define pci_dev_list_112b NULL +#define pci_dev_list_112c NULL +#define pci_dev_list_112d NULL +#define pci_dev_list_112e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_112f[] = { + &pci_dev_info_112f_0000, + &pci_dev_info_112f_0001, + NULL +}; +#endif +#define pci_dev_list_1130 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1131[] = { + &pci_dev_info_1131_1561, + &pci_dev_info_1131_1562, + &pci_dev_info_1131_3400, + &pci_dev_info_1131_7130, + &pci_dev_info_1131_7133, + &pci_dev_info_1131_7134, + &pci_dev_info_1131_7135, + &pci_dev_info_1131_7145, + &pci_dev_info_1131_7146, + NULL +}; +#endif +#define pci_dev_list_1132 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1133[] = { + &pci_dev_info_1133_7901, + &pci_dev_info_1133_7902, + &pci_dev_info_1133_7911, + &pci_dev_info_1133_7912, + &pci_dev_info_1133_7941, + &pci_dev_info_1133_7942, + &pci_dev_info_1133_7943, + &pci_dev_info_1133_7944, + &pci_dev_info_1133_b921, + &pci_dev_info_1133_b922, + &pci_dev_info_1133_b923, + &pci_dev_info_1133_e001, + &pci_dev_info_1133_e002, + &pci_dev_info_1133_e003, + &pci_dev_info_1133_e004, + &pci_dev_info_1133_e005, + &pci_dev_info_1133_e00b, + &pci_dev_info_1133_e010, + &pci_dev_info_1133_e012, + &pci_dev_info_1133_e014, + &pci_dev_info_1133_e018, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1134[] = { + &pci_dev_info_1134_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1135[] = { + &pci_dev_info_1135_0001, + NULL +}; +#endif +#define pci_dev_list_1136 NULL +#define pci_dev_list_1137 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1138[] = { + &pci_dev_info_1138_8905, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1139[] = { + &pci_dev_info_1139_0001, + NULL +}; +#endif +#define pci_dev_list_113a NULL +#define pci_dev_list_113b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_113c[] = { + &pci_dev_info_113c_0000, + &pci_dev_info_113c_0001, + &pci_dev_info_113c_0911, + &pci_dev_info_113c_0912, + &pci_dev_info_113c_0913, + &pci_dev_info_113c_0914, + NULL +}; +#endif +#define pci_dev_list_113d NULL +#define pci_dev_list_113e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_113f[] = { + &pci_dev_info_113f_0808, + &pci_dev_info_113f_1010, + &pci_dev_info_113f_80c0, + &pci_dev_info_113f_80c4, + &pci_dev_info_113f_80c8, + &pci_dev_info_113f_8888, + &pci_dev_info_113f_9090, + NULL +}; +#endif +#define pci_dev_list_1140 NULL +#define pci_dev_list_1141 NULL +static const pciDeviceInfo *pci_dev_list_1142[] = { + &pci_dev_info_1142_3210, + &pci_dev_info_1142_6422, + &pci_dev_info_1142_6424, + &pci_dev_info_1142_6425, + &pci_dev_info_1142_643d, + NULL +}; +#define pci_dev_list_1143 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1144[] = { + &pci_dev_info_1144_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1145[] = { + &pci_dev_info_1145_8007, + &pci_dev_info_1145_f007, + &pci_dev_info_1145_f010, + &pci_dev_info_1145_f012, + &pci_dev_info_1145_f013, + &pci_dev_info_1145_f015, + NULL +}; +#endif +#define pci_dev_list_1146 NULL +#define pci_dev_list_1147 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1148[] = { + &pci_dev_info_1148_4000, + &pci_dev_info_1148_4200, + &pci_dev_info_1148_4300, + &pci_dev_info_1148_4320, + &pci_dev_info_1148_4400, + NULL +}; +#endif +#define pci_dev_list_1149 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_114a[] = { + &pci_dev_info_114a_5579, + &pci_dev_info_114a_5587, + &pci_dev_info_114a_6504, + &pci_dev_info_114a_7587, + NULL +}; +#endif +#define pci_dev_list_114b NULL +#define pci_dev_list_114c NULL +#define pci_dev_list_114d NULL +#define pci_dev_list_114e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_114f[] = { + &pci_dev_info_114f_0002, + &pci_dev_info_114f_0003, + &pci_dev_info_114f_0004, + &pci_dev_info_114f_0005, + &pci_dev_info_114f_0006, + &pci_dev_info_114f_0009, + &pci_dev_info_114f_000a, + &pci_dev_info_114f_000c, + &pci_dev_info_114f_000d, + &pci_dev_info_114f_0011, + &pci_dev_info_114f_0012, + &pci_dev_info_114f_0013, + &pci_dev_info_114f_0014, + &pci_dev_info_114f_0015, + &pci_dev_info_114f_0016, + &pci_dev_info_114f_0017, + &pci_dev_info_114f_001a, + &pci_dev_info_114f_001b, + &pci_dev_info_114f_001d, + &pci_dev_info_114f_0023, + &pci_dev_info_114f_0024, + &pci_dev_info_114f_0026, + &pci_dev_info_114f_0027, + &pci_dev_info_114f_0034, + &pci_dev_info_114f_0035, + &pci_dev_info_114f_0040, + &pci_dev_info_114f_0042, + &pci_dev_info_114f_0070, + &pci_dev_info_114f_0071, + &pci_dev_info_114f_0072, + &pci_dev_info_114f_0073, + &pci_dev_info_114f_6001, + NULL +}; +#endif +#define pci_dev_list_1150 NULL +#define pci_dev_list_1151 NULL +#define pci_dev_list_1152 NULL +#define pci_dev_list_1153 NULL +#define pci_dev_list_1154 NULL +#define pci_dev_list_1155 NULL +#define pci_dev_list_1156 NULL +#define pci_dev_list_1157 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1158[] = { + &pci_dev_info_1158_3011, + &pci_dev_info_1158_9050, + &pci_dev_info_1158_9051, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1159[] = { + &pci_dev_info_1159_0001, + NULL +}; +#endif +#define pci_dev_list_115a NULL +#define pci_dev_list_115b NULL +#define pci_dev_list_115c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_115d[] = { + &pci_dev_info_115d_0003, + &pci_dev_info_115d_0005, + &pci_dev_info_115d_0007, + &pci_dev_info_115d_000b, + &pci_dev_info_115d_000c, + &pci_dev_info_115d_000f, + &pci_dev_info_115d_0101, + &pci_dev_info_115d_0103, + NULL +}; +#endif +#define pci_dev_list_115e NULL +#define pci_dev_list_115f NULL +#define pci_dev_list_1160 NULL +#define pci_dev_list_1161 NULL +#define pci_dev_list_1162 NULL +static const pciDeviceInfo *pci_dev_list_1163[] = { + &pci_dev_info_1163_0001, + &pci_dev_info_1163_2000, + NULL +}; +#define pci_dev_list_1164 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1165[] = { + &pci_dev_info_1165_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1166[] = { + &pci_dev_info_1166_0005, + &pci_dev_info_1166_0007, + &pci_dev_info_1166_0008, + &pci_dev_info_1166_0009, + &pci_dev_info_1166_0010, + &pci_dev_info_1166_0011, + &pci_dev_info_1166_0012, + &pci_dev_info_1166_0013, + &pci_dev_info_1166_0014, + &pci_dev_info_1166_0015, + &pci_dev_info_1166_0016, + &pci_dev_info_1166_0017, + &pci_dev_info_1166_0200, + &pci_dev_info_1166_0201, + &pci_dev_info_1166_0203, + &pci_dev_info_1166_0211, + &pci_dev_info_1166_0212, + &pci_dev_info_1166_0213, + &pci_dev_info_1166_0220, + &pci_dev_info_1166_0221, + &pci_dev_info_1166_0225, + &pci_dev_info_1166_0227, + NULL +}; +#endif +#define pci_dev_list_1167 NULL +#define pci_dev_list_1168 NULL +#define pci_dev_list_1169 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_116a[] = { + &pci_dev_info_116a_6100, + &pci_dev_info_116a_6800, + &pci_dev_info_116a_7100, + &pci_dev_info_116a_7800, + NULL +}; +#endif +#define pci_dev_list_116b NULL +#define pci_dev_list_116c NULL +#define pci_dev_list_116d NULL +#define pci_dev_list_116e NULL +#define pci_dev_list_116f NULL +#define pci_dev_list_1170 NULL +#define pci_dev_list_1171 NULL +#define pci_dev_list_1172 NULL +#define pci_dev_list_1173 NULL +#define pci_dev_list_1174 NULL +#define pci_dev_list_1175 NULL +#define pci_dev_list_1176 NULL +#define pci_dev_list_1177 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1178[] = { + &pci_dev_info_1178_afa1, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1179[] = { + &pci_dev_info_1179_0103, + &pci_dev_info_1179_0404, + &pci_dev_info_1179_0406, + &pci_dev_info_1179_0407, + &pci_dev_info_1179_0601, + &pci_dev_info_1179_0603, + &pci_dev_info_1179_060a, + &pci_dev_info_1179_060f, + &pci_dev_info_1179_0617, + &pci_dev_info_1179_0618, + &pci_dev_info_1179_0701, + &pci_dev_info_1179_0804, + &pci_dev_info_1179_0805, + &pci_dev_info_1179_0d01, + NULL +}; +#endif +#define pci_dev_list_117a NULL +#define pci_dev_list_117b NULL +#define pci_dev_list_117c NULL +#define pci_dev_list_117d NULL +#define pci_dev_list_117e NULL +#define pci_dev_list_117f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1180[] = { + &pci_dev_info_1180_0465, + &pci_dev_info_1180_0466, + &pci_dev_info_1180_0475, + &pci_dev_info_1180_0476, + &pci_dev_info_1180_0477, + &pci_dev_info_1180_0478, + &pci_dev_info_1180_0522, + &pci_dev_info_1180_0551, + &pci_dev_info_1180_0552, + NULL +}; +#endif +#define pci_dev_list_1181 NULL +#define pci_dev_list_1183 NULL +#define pci_dev_list_1184 NULL +#define pci_dev_list_1185 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1186[] = { + &pci_dev_info_1186_0100, + &pci_dev_info_1186_1002, + &pci_dev_info_1186_1300, + &pci_dev_info_1186_1340, + &pci_dev_info_1186_1561, + &pci_dev_info_1186_4000, + NULL +}; +#endif +#define pci_dev_list_1187 NULL +#define pci_dev_list_1188 NULL +#define pci_dev_list_1189 NULL +#define pci_dev_list_118a NULL +#define pci_dev_list_118b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_118c[] = { + &pci_dev_info_118c_0014, + &pci_dev_info_118c_1117, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_118d[] = { + &pci_dev_info_118d_0001, + &pci_dev_info_118d_0012, + &pci_dev_info_118d_0014, + &pci_dev_info_118d_0024, + &pci_dev_info_118d_0044, + &pci_dev_info_118d_0112, + &pci_dev_info_118d_0114, + &pci_dev_info_118d_0124, + &pci_dev_info_118d_0144, + &pci_dev_info_118d_0212, + &pci_dev_info_118d_0214, + &pci_dev_info_118d_0224, + &pci_dev_info_118d_0244, + &pci_dev_info_118d_0312, + &pci_dev_info_118d_0314, + &pci_dev_info_118d_0324, + &pci_dev_info_118d_0344, + NULL +}; +#endif +#define pci_dev_list_118e NULL +#define pci_dev_list_118f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1190[] = { + &pci_dev_info_1190_c731, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1191[] = { + &pci_dev_info_1191_0003, + &pci_dev_info_1191_0004, + &pci_dev_info_1191_0005, + &pci_dev_info_1191_0006, + &pci_dev_info_1191_0007, + &pci_dev_info_1191_0008, + &pci_dev_info_1191_0009, + &pci_dev_info_1191_8002, + &pci_dev_info_1191_8010, + &pci_dev_info_1191_8020, + &pci_dev_info_1191_8030, + &pci_dev_info_1191_8040, + &pci_dev_info_1191_8050, + NULL +}; +#endif +#define pci_dev_list_1192 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1193[] = { + &pci_dev_info_1193_0001, + &pci_dev_info_1193_0002, + NULL +}; +#endif +#define pci_dev_list_1194 NULL +#define pci_dev_list_1195 NULL +#define pci_dev_list_1196 NULL +#define pci_dev_list_1197 NULL +#define pci_dev_list_1198 NULL +#define pci_dev_list_1199 NULL +#define pci_dev_list_119a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_119b[] = { + &pci_dev_info_119b_1221, + NULL +}; +#endif +#define pci_dev_list_119c NULL +#define pci_dev_list_119d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_119e[] = { + &pci_dev_info_119e_0001, + &pci_dev_info_119e_0003, + NULL +}; +#endif +#define pci_dev_list_119f NULL +#define pci_dev_list_11a0 NULL +#define pci_dev_list_11a1 NULL +#define pci_dev_list_11a2 NULL +#define pci_dev_list_11a3 NULL +#define pci_dev_list_11a4 NULL +#define pci_dev_list_11a5 NULL +#define pci_dev_list_11a6 NULL +#define pci_dev_list_11a7 NULL +#define pci_dev_list_11a8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11a9[] = { + &pci_dev_info_11a9_4240, + NULL +}; +#endif +#define pci_dev_list_11aa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11ab[] = { + &pci_dev_info_11ab_0146, + &pci_dev_info_11ab_4611, + &pci_dev_info_11ab_4620, + &pci_dev_info_11ab_4801, + &pci_dev_info_11ab_f003, + NULL +}; +#endif +#define pci_dev_list_11ac NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11ad[] = { + &pci_dev_info_11ad_0002, + &pci_dev_info_11ad_c115, + NULL +}; +#endif +#define pci_dev_list_11ae NULL +#define pci_dev_list_11af NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11b0[] = { + &pci_dev_info_11b0_0002, + &pci_dev_info_11b0_0292, + &pci_dev_info_11b0_0960, + &pci_dev_info_11b0_c960, + NULL +}; +#endif +#define pci_dev_list_11b1 NULL +#define pci_dev_list_11b2 NULL +#define pci_dev_list_11b3 NULL +#define pci_dev_list_11b4 NULL +#define pci_dev_list_11b5 NULL +#define pci_dev_list_11b6 NULL +#define pci_dev_list_11b7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11b8[] = { + &pci_dev_info_11b8_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11b9[] = { + &pci_dev_info_11b9_c0ed, + NULL +}; +#endif +#define pci_dev_list_11ba NULL +#define pci_dev_list_11bb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11bc[] = { + &pci_dev_info_11bc_0001, + NULL +}; +#endif +#define pci_dev_list_11bd NULL +#define pci_dev_list_11be NULL +#define pci_dev_list_11bf NULL +#define pci_dev_list_11c0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11c1[] = { + &pci_dev_info_11c1_0440, + &pci_dev_info_11c1_0441, + &pci_dev_info_11c1_0442, + &pci_dev_info_11c1_0443, + &pci_dev_info_11c1_0444, + &pci_dev_info_11c1_0445, + &pci_dev_info_11c1_0446, + &pci_dev_info_11c1_0447, + &pci_dev_info_11c1_0448, + &pci_dev_info_11c1_0449, + &pci_dev_info_11c1_044a, + &pci_dev_info_11c1_044b, + &pci_dev_info_11c1_044c, + &pci_dev_info_11c1_044d, + &pci_dev_info_11c1_044e, + &pci_dev_info_11c1_044f, + &pci_dev_info_11c1_0450, + &pci_dev_info_11c1_0451, + &pci_dev_info_11c1_0452, + &pci_dev_info_11c1_0453, + &pci_dev_info_11c1_0454, + &pci_dev_info_11c1_0455, + &pci_dev_info_11c1_0456, + &pci_dev_info_11c1_0457, + &pci_dev_info_11c1_0458, + &pci_dev_info_11c1_0459, + &pci_dev_info_11c1_045a, + &pci_dev_info_11c1_045c, + &pci_dev_info_11c1_0461, + &pci_dev_info_11c1_0462, + &pci_dev_info_11c1_0480, + &pci_dev_info_11c1_5801, + &pci_dev_info_11c1_5802, + &pci_dev_info_11c1_5803, + &pci_dev_info_11c1_5811, + NULL +}; +#endif +#define pci_dev_list_11c2 NULL +#define pci_dev_list_11c3 NULL +#define pci_dev_list_11c4 NULL +#define pci_dev_list_11c5 NULL +#define pci_dev_list_11c6 NULL +#define pci_dev_list_11c7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11c8[] = { + &pci_dev_info_11c8_0658, + &pci_dev_info_11c8_d665, + &pci_dev_info_11c8_d667, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11c9[] = { + &pci_dev_info_11c9_0010, + &pci_dev_info_11c9_0011, + NULL +}; +#endif +#define pci_dev_list_11ca NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11cb[] = { + &pci_dev_info_11cb_2000, + &pci_dev_info_11cb_4000, + &pci_dev_info_11cb_8000, + NULL +}; +#endif +#define pci_dev_list_11cc NULL +#define pci_dev_list_11cd NULL +#define pci_dev_list_11ce NULL +#define pci_dev_list_11cf NULL +#define pci_dev_list_11d0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11d1[] = { + &pci_dev_info_11d1_01f7, + NULL +}; +#endif +#define pci_dev_list_11d2 NULL +#define pci_dev_list_11d3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11d4[] = { + &pci_dev_info_11d4_1805, + &pci_dev_info_11d4_1889, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11d5[] = { + &pci_dev_info_11d5_0115, + &pci_dev_info_11d5_0117, + NULL +}; +#endif +#define pci_dev_list_11d6 NULL +#define pci_dev_list_11d7 NULL +#define pci_dev_list_11d8 NULL +#define pci_dev_list_11d9 NULL +#define pci_dev_list_11da NULL +#define pci_dev_list_11db NULL +#define pci_dev_list_11dc NULL +#define pci_dev_list_11dd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11de[] = { + &pci_dev_info_11de_6057, + &pci_dev_info_11de_6120, + NULL +}; +#endif +#define pci_dev_list_11df NULL +#define pci_dev_list_11e0 NULL +#define pci_dev_list_11e1 NULL +#define pci_dev_list_11e2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11e3[] = { + &pci_dev_info_11e3_5030, + NULL +}; +#endif +#define pci_dev_list_11e4 NULL +#define pci_dev_list_11e5 NULL +#define pci_dev_list_11e6 NULL +#define pci_dev_list_11e7 NULL +#define pci_dev_list_11e8 NULL +#define pci_dev_list_11e9 NULL +#define pci_dev_list_11ea NULL +#define pci_dev_list_11eb NULL +#define pci_dev_list_11ec NULL +#define pci_dev_list_11ed NULL +#define pci_dev_list_11ee NULL +#define pci_dev_list_11ef NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11f0[] = { + &pci_dev_info_11f0_4231, + &pci_dev_info_11f0_4232, + &pci_dev_info_11f0_4233, + &pci_dev_info_11f0_4234, + &pci_dev_info_11f0_4235, + &pci_dev_info_11f0_4236, + &pci_dev_info_11f0_4731, + NULL +}; +#endif +#define pci_dev_list_11f1 NULL +#define pci_dev_list_11f2 NULL +#define pci_dev_list_11f3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11f4[] = { + &pci_dev_info_11f4_2915, + NULL +}; +#endif +#define pci_dev_list_11f5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11f6[] = { + &pci_dev_info_11f6_0112, + &pci_dev_info_11f6_0113, + &pci_dev_info_11f6_1401, + &pci_dev_info_11f6_2011, + &pci_dev_info_11f6_2201, + &pci_dev_info_11f6_9881, + NULL +}; +#endif +#define pci_dev_list_11f7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11f8[] = { + &pci_dev_info_11f8_7375, + NULL +}; +#endif +#define pci_dev_list_11f9 NULL +#define pci_dev_list_11fa NULL +#define pci_dev_list_11fb NULL +#define pci_dev_list_11fc NULL +#define pci_dev_list_11fd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11fe[] = { + &pci_dev_info_11fe_0001, + &pci_dev_info_11fe_0002, + &pci_dev_info_11fe_0003, + &pci_dev_info_11fe_0004, + &pci_dev_info_11fe_0005, + &pci_dev_info_11fe_0006, + &pci_dev_info_11fe_0007, + &pci_dev_info_11fe_0008, + &pci_dev_info_11fe_0009, + &pci_dev_info_11fe_000a, + &pci_dev_info_11fe_000b, + &pci_dev_info_11fe_000c, + &pci_dev_info_11fe_8015, + NULL +}; +#endif +#define pci_dev_list_11ff NULL +#define pci_dev_list_1200 NULL +#define pci_dev_list_1201 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1202[] = { + &pci_dev_info_1202_4300, + NULL +}; +#endif +#define pci_dev_list_1203 NULL +#define pci_dev_list_1204 NULL +#define pci_dev_list_1205 NULL +#define pci_dev_list_1206 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1208[] = { + &pci_dev_info_1208_4853, + NULL +}; +#endif +#define pci_dev_list_1209 NULL +#define pci_dev_list_120a NULL +#define pci_dev_list_120b NULL +#define pci_dev_list_120c NULL +#define pci_dev_list_120d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_120e[] = { + &pci_dev_info_120e_0100, + &pci_dev_info_120e_0101, + &pci_dev_info_120e_0102, + &pci_dev_info_120e_0103, + &pci_dev_info_120e_0104, + &pci_dev_info_120e_0105, + &pci_dev_info_120e_0200, + &pci_dev_info_120e_0201, + &pci_dev_info_120e_0300, + &pci_dev_info_120e_0301, + &pci_dev_info_120e_0310, + &pci_dev_info_120e_0311, + &pci_dev_info_120e_0320, + &pci_dev_info_120e_0321, + &pci_dev_info_120e_0400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_120f[] = { + &pci_dev_info_120f_0001, + NULL +}; +#endif +#define pci_dev_list_1210 NULL +#define pci_dev_list_1211 NULL +#define pci_dev_list_1212 NULL +#define pci_dev_list_1213 NULL +#define pci_dev_list_1214 NULL +#define pci_dev_list_1215 NULL +#define pci_dev_list_1216 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1217[] = { + &pci_dev_info_1217_6729, + &pci_dev_info_1217_673a, + &pci_dev_info_1217_6832, + &pci_dev_info_1217_6836, + &pci_dev_info_1217_6872, + &pci_dev_info_1217_6925, + &pci_dev_info_1217_6933, + &pci_dev_info_1217_6972, + NULL +}; +#endif +#define pci_dev_list_1218 NULL +#define pci_dev_list_1219 NULL +static const pciDeviceInfo *pci_dev_list_121a[] = { + &pci_dev_info_121a_0001, + &pci_dev_info_121a_0002, + &pci_dev_info_121a_0003, + &pci_dev_info_121a_0004, + &pci_dev_info_121a_0005, + &pci_dev_info_121a_0009, + &pci_dev_info_121a_0057, + NULL +}; +#define pci_dev_list_121b NULL +#define pci_dev_list_121c NULL +#define pci_dev_list_121d NULL +#define pci_dev_list_121e NULL +#define pci_dev_list_121f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1220[] = { + &pci_dev_info_1220_1220, + NULL +}; +#endif +#define pci_dev_list_1221 NULL +#define pci_dev_list_1222 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1223[] = { + &pci_dev_info_1223_0003, + &pci_dev_info_1223_0004, + &pci_dev_info_1223_0005, + &pci_dev_info_1223_0008, + &pci_dev_info_1223_0009, + &pci_dev_info_1223_000a, + &pci_dev_info_1223_000b, + &pci_dev_info_1223_000c, + &pci_dev_info_1223_000d, + &pci_dev_info_1223_000e, + NULL +}; +#endif +#define pci_dev_list_1224 NULL +#define pci_dev_list_1225 NULL +#define pci_dev_list_1227 NULL +#define pci_dev_list_1228 NULL +#define pci_dev_list_1229 NULL +#define pci_dev_list_122a NULL +#define pci_dev_list_122b NULL +#define pci_dev_list_122c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_122d[] = { + &pci_dev_info_122d_1206, + &pci_dev_info_122d_50dc, + &pci_dev_info_122d_80da, + NULL +}; +#endif +#define pci_dev_list_122e NULL +#define pci_dev_list_122f NULL +#define pci_dev_list_1230 NULL +#define pci_dev_list_1231 NULL +#define pci_dev_list_1232 NULL +#define pci_dev_list_1233 NULL +#define pci_dev_list_1234 NULL +#define pci_dev_list_1235 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1236[] = { + &pci_dev_info_1236_0000, + &pci_dev_info_1236_6401, + NULL +}; +#endif +#define pci_dev_list_1237 NULL +#define pci_dev_list_1238 NULL +#define pci_dev_list_1239 NULL +#define pci_dev_list_123a NULL +#define pci_dev_list_123b NULL +#define pci_dev_list_123c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_123d[] = { + &pci_dev_info_123d_0000, + &pci_dev_info_123d_0002, + &pci_dev_info_123d_0003, + NULL +}; +#endif +#define pci_dev_list_123e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_123f[] = { + &pci_dev_info_123f_00e4, + &pci_dev_info_123f_8120, + &pci_dev_info_123f_8888, + NULL +}; +#endif +#define pci_dev_list_1240 NULL +#define pci_dev_list_1241 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1242[] = { + &pci_dev_info_1242_1560, + &pci_dev_info_1242_4643, + NULL +}; +#endif +#define pci_dev_list_1243 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1244[] = { + &pci_dev_info_1244_0700, + &pci_dev_info_1244_0800, + &pci_dev_info_1244_0a00, + &pci_dev_info_1244_0e00, + &pci_dev_info_1244_1100, + &pci_dev_info_1244_1200, + NULL +}; +#endif +#define pci_dev_list_1245 NULL +#define pci_dev_list_1246 NULL +#define pci_dev_list_1247 NULL +#define pci_dev_list_1248 NULL +#define pci_dev_list_1249 NULL +#define pci_dev_list_124a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_124b[] = { + &pci_dev_info_124b_0040, + NULL +}; +#endif +#define pci_dev_list_124c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_124d[] = { + &pci_dev_info_124d_0000, + &pci_dev_info_124d_0002, + &pci_dev_info_124d_0003, + &pci_dev_info_124d_0004, + NULL +}; +#endif +#define pci_dev_list_124e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_124f[] = { + &pci_dev_info_124f_0041, + NULL +}; +#endif +#define pci_dev_list_1250 NULL +#define pci_dev_list_1251 NULL +#define pci_dev_list_1253 NULL +#define pci_dev_list_1254 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1255[] = { + &pci_dev_info_1255_1110, + &pci_dev_info_1255_1210, + &pci_dev_info_1255_2110, + &pci_dev_info_1255_2120, + &pci_dev_info_1255_2130, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1256[] = { + &pci_dev_info_1256_4201, + &pci_dev_info_1256_4401, + &pci_dev_info_1256_5201, + NULL +}; +#endif +#define pci_dev_list_1257 NULL +#define pci_dev_list_1258 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1259[] = { + &pci_dev_info_1259_2560, + NULL +}; +#endif +#define pci_dev_list_125a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_125b[] = { + &pci_dev_info_125b_1400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_125c[] = { + &pci_dev_info_125c_0640, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_125d[] = { + &pci_dev_info_125d_0000, + &pci_dev_info_125d_1948, + &pci_dev_info_125d_1968, + &pci_dev_info_125d_1969, + &pci_dev_info_125d_1978, + &pci_dev_info_125d_1988, + &pci_dev_info_125d_1989, + &pci_dev_info_125d_1998, + &pci_dev_info_125d_1999, + &pci_dev_info_125d_199a, + &pci_dev_info_125d_199b, + &pci_dev_info_125d_2808, + &pci_dev_info_125d_2838, + &pci_dev_info_125d_2898, + NULL +}; +#endif +#define pci_dev_list_125e NULL +#define pci_dev_list_125f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1260[] = { + &pci_dev_info_1260_3873, + &pci_dev_info_1260_8130, + &pci_dev_info_1260_8131, + NULL +}; +#endif +#define pci_dev_list_1261 NULL +#define pci_dev_list_1262 NULL +#define pci_dev_list_1263 NULL +#define pci_dev_list_1264 NULL +#define pci_dev_list_1265 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1266[] = { + &pci_dev_info_1266_0001, + &pci_dev_info_1266_1910, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1267[] = { + &pci_dev_info_1267_5352, + &pci_dev_info_1267_5a4b, + NULL +}; +#endif +#define pci_dev_list_1268 NULL +#define pci_dev_list_1269 NULL +#define pci_dev_list_126a NULL +#define pci_dev_list_126b NULL +#define pci_dev_list_126c NULL +#define pci_dev_list_126d NULL +#define pci_dev_list_126e NULL +static const pciDeviceInfo *pci_dev_list_126f[] = { + &pci_dev_info_126f_0710, + &pci_dev_info_126f_0712, + &pci_dev_info_126f_0720, + &pci_dev_info_126f_0810, + &pci_dev_info_126f_0811, + &pci_dev_info_126f_0820, + &pci_dev_info_126f_0910, + NULL +}; +#define pci_dev_list_1270 NULL +#define pci_dev_list_1271 NULL +#define pci_dev_list_1272 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1273[] = { + &pci_dev_info_1273_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1274[] = { + &pci_dev_info_1274_1371, + &pci_dev_info_1274_5000, + &pci_dev_info_1274_5880, + NULL +}; +#endif +#define pci_dev_list_1275 NULL +#define pci_dev_list_1276 NULL +#define pci_dev_list_1277 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1278[] = { + &pci_dev_info_1278_0701, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1279[] = { + &pci_dev_info_1279_0295, + &pci_dev_info_1279_0395, + &pci_dev_info_1279_0396, + &pci_dev_info_1279_0397, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_127a[] = { + &pci_dev_info_127a_1002, + &pci_dev_info_127a_1003, + &pci_dev_info_127a_1004, + &pci_dev_info_127a_1005, + &pci_dev_info_127a_1022, + &pci_dev_info_127a_1023, + &pci_dev_info_127a_1024, + &pci_dev_info_127a_1025, + &pci_dev_info_127a_1026, + &pci_dev_info_127a_1032, + &pci_dev_info_127a_1033, + &pci_dev_info_127a_1034, + &pci_dev_info_127a_1035, + &pci_dev_info_127a_1036, + &pci_dev_info_127a_1085, + &pci_dev_info_127a_2005, + &pci_dev_info_127a_2013, + &pci_dev_info_127a_2014, + &pci_dev_info_127a_2015, + &pci_dev_info_127a_2016, + &pci_dev_info_127a_4311, + &pci_dev_info_127a_4320, + &pci_dev_info_127a_4321, + &pci_dev_info_127a_4322, + &pci_dev_info_127a_8234, + NULL +}; +#endif +#define pci_dev_list_127b NULL +#define pci_dev_list_127c NULL +#define pci_dev_list_127d NULL +#define pci_dev_list_127e NULL +#define pci_dev_list_127f NULL +#define pci_dev_list_1280 NULL +#define pci_dev_list_1281 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1282[] = { + &pci_dev_info_1282_9009, + &pci_dev_info_1282_9100, + &pci_dev_info_1282_9102, + &pci_dev_info_1282_9132, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1283[] = { + &pci_dev_info_1283_673a, + &pci_dev_info_1283_8330, + &pci_dev_info_1283_8888, + &pci_dev_info_1283_8889, + &pci_dev_info_1283_e886, + NULL +}; +#endif +#define pci_dev_list_1284 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1285[] = { + &pci_dev_info_1285_0100, + NULL +}; +#endif +#define pci_dev_list_1286 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1287[] = { + &pci_dev_info_1287_001e, + &pci_dev_info_1287_001f, + NULL +}; +#endif +#define pci_dev_list_1288 NULL +#define pci_dev_list_1289 NULL +#define pci_dev_list_128a NULL +#define pci_dev_list_128b NULL +#define pci_dev_list_128c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_128d[] = { + &pci_dev_info_128d_0021, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_128e[] = { + &pci_dev_info_128e_0008, + &pci_dev_info_128e_0009, + &pci_dev_info_128e_000a, + &pci_dev_info_128e_000b, + &pci_dev_info_128e_000c, + NULL +}; +#endif +#define pci_dev_list_128f NULL +#define pci_dev_list_1290 NULL +#define pci_dev_list_1291 NULL +#define pci_dev_list_1292 NULL +#define pci_dev_list_1293 NULL +#define pci_dev_list_1294 NULL +#define pci_dev_list_1295 NULL +#define pci_dev_list_1296 NULL +#define pci_dev_list_1297 NULL +#define pci_dev_list_1298 NULL +#define pci_dev_list_1299 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_129a[] = { + &pci_dev_info_129a_0615, + NULL +}; +#endif +#define pci_dev_list_129b NULL +#define pci_dev_list_129c NULL +#define pci_dev_list_129d NULL +#define pci_dev_list_129e NULL +#define pci_dev_list_129f NULL +#define pci_dev_list_12a0 NULL +#define pci_dev_list_12a1 NULL +#define pci_dev_list_12a2 NULL +#define pci_dev_list_12a3 NULL +#define pci_dev_list_12a4 NULL +#define pci_dev_list_12a5 NULL +#define pci_dev_list_12a6 NULL +#define pci_dev_list_12a7 NULL +#define pci_dev_list_12a8 NULL +#define pci_dev_list_12a9 NULL +#define pci_dev_list_12aa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12ab[] = { + &pci_dev_info_12ab_3000, + NULL +}; +#endif +#define pci_dev_list_12ac NULL +#define pci_dev_list_12ad NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12ae[] = { + &pci_dev_info_12ae_0001, + &pci_dev_info_12ae_0002, + NULL +}; +#endif +#define pci_dev_list_12af NULL +#define pci_dev_list_12b0 NULL +#define pci_dev_list_12b1 NULL +#define pci_dev_list_12b2 NULL +#define pci_dev_list_12b3 NULL +#define pci_dev_list_12b4 NULL +#define pci_dev_list_12b5 NULL +#define pci_dev_list_12b6 NULL +#define pci_dev_list_12b7 NULL +#define pci_dev_list_12b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12b9[] = { + &pci_dev_info_12b9_1006, + &pci_dev_info_12b9_1007, + &pci_dev_info_12b9_1008, + NULL +}; +#endif +#define pci_dev_list_12ba NULL +#define pci_dev_list_12bb NULL +#define pci_dev_list_12bc NULL +#define pci_dev_list_12bd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12be[] = { + &pci_dev_info_12be_3041, + &pci_dev_info_12be_3042, + NULL +}; +#endif +#define pci_dev_list_12bf NULL +#define pci_dev_list_12c0 NULL +#define pci_dev_list_12c1 NULL +#define pci_dev_list_12c2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12c3[] = { + &pci_dev_info_12c3_0058, + &pci_dev_info_12c3_5598, + NULL +}; +#endif +#define pci_dev_list_12c4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12c5[] = { + &pci_dev_info_12c5_007e, + &pci_dev_info_12c5_007f, + &pci_dev_info_12c5_0081, + &pci_dev_info_12c5_0085, + &pci_dev_info_12c5_0086, + NULL +}; +#endif +#define pci_dev_list_12c6 NULL +#define pci_dev_list_12c7 NULL +#define pci_dev_list_12c8 NULL +#define pci_dev_list_12c9 NULL +#define pci_dev_list_12ca NULL +#define pci_dev_list_12cb NULL +#define pci_dev_list_12cc NULL +#define pci_dev_list_12cd NULL +#define pci_dev_list_12ce NULL +#define pci_dev_list_12cf NULL +#define pci_dev_list_12d0 NULL +#define pci_dev_list_12d1 NULL +static const pciDeviceInfo *pci_dev_list_12d2[] = { + &pci_dev_info_12d2_0008, + &pci_dev_info_12d2_0009, + &pci_dev_info_12d2_0018, + &pci_dev_info_12d2_0019, + &pci_dev_info_12d2_0020, + &pci_dev_info_12d2_0028, + &pci_dev_info_12d2_0029, + &pci_dev_info_12d2_002c, + &pci_dev_info_12d2_00a0, + NULL +}; +#define pci_dev_list_12d3 NULL +#define pci_dev_list_12d4 NULL +#define pci_dev_list_12d5 NULL +#define pci_dev_list_12d6 NULL +#define pci_dev_list_12d7 NULL +#define pci_dev_list_12d8 NULL +#define pci_dev_list_12d9 NULL +#define pci_dev_list_12da NULL +#define pci_dev_list_12db NULL +#define pci_dev_list_12dc NULL +#define pci_dev_list_12dd NULL +#define pci_dev_list_12de NULL +#define pci_dev_list_12df NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12e0[] = { + &pci_dev_info_12e0_0010, + &pci_dev_info_12e0_0020, + &pci_dev_info_12e0_0030, + NULL +}; +#endif +#define pci_dev_list_12e1 NULL +#define pci_dev_list_12e2 NULL +#define pci_dev_list_12e3 NULL +#define pci_dev_list_12e4 NULL +#define pci_dev_list_12e5 NULL +#define pci_dev_list_12e6 NULL +#define pci_dev_list_12e7 NULL +#define pci_dev_list_12e8 NULL +#define pci_dev_list_12e9 NULL +#define pci_dev_list_12ea NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12eb[] = { + &pci_dev_info_12eb_0001, + &pci_dev_info_12eb_0002, + &pci_dev_info_12eb_0003, + &pci_dev_info_12eb_8803, + NULL +}; +#endif +#define pci_dev_list_12ec NULL +#define pci_dev_list_12ed NULL +#define pci_dev_list_12ee NULL +#define pci_dev_list_12ef NULL +#define pci_dev_list_12f0 NULL +#define pci_dev_list_12f1 NULL +#define pci_dev_list_12f2 NULL +#define pci_dev_list_12f3 NULL +#define pci_dev_list_12f4 NULL +#define pci_dev_list_12f5 NULL +#define pci_dev_list_12f6 NULL +#define pci_dev_list_12f7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12f8[] = { + &pci_dev_info_12f8_0002, + NULL +}; +#endif +#define pci_dev_list_12f9 NULL +#define pci_dev_list_12fb NULL +#define pci_dev_list_12fc NULL +#define pci_dev_list_12fd NULL +#define pci_dev_list_12fe NULL +#define pci_dev_list_12ff NULL +#define pci_dev_list_1300 NULL +#define pci_dev_list_1302 NULL +#define pci_dev_list_1303 NULL +#define pci_dev_list_1304 NULL +#define pci_dev_list_1305 NULL +#define pci_dev_list_1306 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1307[] = { + &pci_dev_info_1307_0001, + &pci_dev_info_1307_000b, + &pci_dev_info_1307_000c, + &pci_dev_info_1307_000d, + &pci_dev_info_1307_000f, + &pci_dev_info_1307_0010, + &pci_dev_info_1307_0014, + &pci_dev_info_1307_0015, + &pci_dev_info_1307_0016, + &pci_dev_info_1307_0017, + &pci_dev_info_1307_0018, + &pci_dev_info_1307_0019, + &pci_dev_info_1307_001a, + &pci_dev_info_1307_001b, + &pci_dev_info_1307_001c, + &pci_dev_info_1307_001d, + &pci_dev_info_1307_001e, + &pci_dev_info_1307_001f, + &pci_dev_info_1307_0020, + &pci_dev_info_1307_0021, + &pci_dev_info_1307_0022, + &pci_dev_info_1307_0023, + &pci_dev_info_1307_0024, + &pci_dev_info_1307_0025, + &pci_dev_info_1307_0026, + &pci_dev_info_1307_0027, + &pci_dev_info_1307_0028, + &pci_dev_info_1307_0029, + &pci_dev_info_1307_002c, + &pci_dev_info_1307_0033, + &pci_dev_info_1307_0034, + &pci_dev_info_1307_0035, + &pci_dev_info_1307_0036, + &pci_dev_info_1307_0037, + &pci_dev_info_1307_004c, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1308[] = { + &pci_dev_info_1308_0001, + NULL +}; +#endif +#define pci_dev_list_1309 NULL +#define pci_dev_list_130a NULL +#define pci_dev_list_130b NULL +#define pci_dev_list_130c NULL +#define pci_dev_list_130d NULL +#define pci_dev_list_130e NULL +#define pci_dev_list_130f NULL +#define pci_dev_list_1310 NULL +#define pci_dev_list_1311 NULL +#define pci_dev_list_1312 NULL +#define pci_dev_list_1313 NULL +#define pci_dev_list_1316 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1317[] = { + &pci_dev_info_1317_0981, + &pci_dev_info_1317_0985, + &pci_dev_info_1317_1985, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1318[] = { + &pci_dev_info_1318_0911, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1319[] = { + &pci_dev_info_1319_0801, + &pci_dev_info_1319_0802, + &pci_dev_info_1319_1000, + &pci_dev_info_1319_1001, + NULL +}; +#endif +#define pci_dev_list_131a NULL +#define pci_dev_list_131c NULL +#define pci_dev_list_131d NULL +#define pci_dev_list_131e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_131f[] = { + &pci_dev_info_131f_1000, + &pci_dev_info_131f_1001, + &pci_dev_info_131f_1002, + &pci_dev_info_131f_1010, + &pci_dev_info_131f_1011, + &pci_dev_info_131f_1012, + &pci_dev_info_131f_1020, + &pci_dev_info_131f_1021, + &pci_dev_info_131f_1030, + &pci_dev_info_131f_1031, + &pci_dev_info_131f_1032, + &pci_dev_info_131f_1034, + &pci_dev_info_131f_1035, + &pci_dev_info_131f_1036, + &pci_dev_info_131f_1050, + &pci_dev_info_131f_1051, + &pci_dev_info_131f_1052, + &pci_dev_info_131f_2000, + &pci_dev_info_131f_2001, + &pci_dev_info_131f_2002, + &pci_dev_info_131f_2010, + &pci_dev_info_131f_2011, + &pci_dev_info_131f_2012, + &pci_dev_info_131f_2020, + &pci_dev_info_131f_2021, + &pci_dev_info_131f_2030, + &pci_dev_info_131f_2031, + &pci_dev_info_131f_2032, + &pci_dev_info_131f_2040, + &pci_dev_info_131f_2041, + &pci_dev_info_131f_2042, + &pci_dev_info_131f_2050, + &pci_dev_info_131f_2051, + &pci_dev_info_131f_2052, + &pci_dev_info_131f_2060, + &pci_dev_info_131f_2061, + &pci_dev_info_131f_2062, + NULL +}; +#endif +#define pci_dev_list_1320 NULL +#define pci_dev_list_1321 NULL +#define pci_dev_list_1322 NULL +#define pci_dev_list_1323 NULL +#define pci_dev_list_1324 NULL +#define pci_dev_list_1325 NULL +#define pci_dev_list_1326 NULL +#define pci_dev_list_1327 NULL +#define pci_dev_list_1328 NULL +#define pci_dev_list_1329 NULL +#define pci_dev_list_132a NULL +#define pci_dev_list_132b NULL +#define pci_dev_list_132c NULL +#define pci_dev_list_132d NULL +#define pci_dev_list_1330 NULL +#define pci_dev_list_1331 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1332[] = { + &pci_dev_info_1332_5415, + NULL +}; +#endif +#define pci_dev_list_1334 NULL +#define pci_dev_list_1335 NULL +#define pci_dev_list_1337 NULL +#define pci_dev_list_1338 NULL +#define pci_dev_list_133a NULL +#define pci_dev_list_133b NULL +#define pci_dev_list_133c NULL +#define pci_dev_list_133d NULL +#define pci_dev_list_133e NULL +#define pci_dev_list_133f NULL +#define pci_dev_list_1340 NULL +#define pci_dev_list_1341 NULL +#define pci_dev_list_1342 NULL +#define pci_dev_list_1343 NULL +#define pci_dev_list_1344 NULL +#define pci_dev_list_1345 NULL +#define pci_dev_list_1347 NULL +#define pci_dev_list_1349 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_134a[] = { + &pci_dev_info_134a_0001, + &pci_dev_info_134a_0002, + NULL +}; +#endif +#define pci_dev_list_134b NULL +#define pci_dev_list_134c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_134d[] = { + &pci_dev_info_134d_7890, + &pci_dev_info_134d_7891, + &pci_dev_info_134d_7892, + &pci_dev_info_134d_7893, + &pci_dev_info_134d_7894, + &pci_dev_info_134d_7895, + &pci_dev_info_134d_7896, + &pci_dev_info_134d_7897, + NULL +}; +#endif +#define pci_dev_list_134e NULL +#define pci_dev_list_134f NULL +#define pci_dev_list_1350 NULL +#define pci_dev_list_1351 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1353[] = { + &pci_dev_info_1353_0002, + &pci_dev_info_1353_0003, + &pci_dev_info_1353_0004, + &pci_dev_info_1353_0005, + NULL +}; +#endif +#define pci_dev_list_1354 NULL +#define pci_dev_list_1355 NULL +#define pci_dev_list_1356 NULL +#define pci_dev_list_1359 NULL +#define pci_dev_list_135a NULL +#define pci_dev_list_135b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_135c[] = { + &pci_dev_info_135c_0010, + &pci_dev_info_135c_0020, + &pci_dev_info_135c_0030, + &pci_dev_info_135c_0040, + &pci_dev_info_135c_0050, + &pci_dev_info_135c_0060, + &pci_dev_info_135c_00f0, + &pci_dev_info_135c_0170, + &pci_dev_info_135c_0180, + &pci_dev_info_135c_0190, + &pci_dev_info_135c_01a0, + &pci_dev_info_135c_01b0, + &pci_dev_info_135c_01c0, + NULL +}; +#endif +#define pci_dev_list_135d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_135e[] = { + &pci_dev_info_135e_7101, + &pci_dev_info_135e_7201, + &pci_dev_info_135e_7202, + &pci_dev_info_135e_7401, + &pci_dev_info_135e_7402, + &pci_dev_info_135e_7801, + &pci_dev_info_135e_8001, + NULL +}; +#endif +#define pci_dev_list_135f NULL +#define pci_dev_list_1360 NULL +#define pci_dev_list_1361 NULL +#define pci_dev_list_1362 NULL +#define pci_dev_list_1363 NULL +#define pci_dev_list_1364 NULL +#define pci_dev_list_1365 NULL +#define pci_dev_list_1366 NULL +#define pci_dev_list_1367 NULL +#define pci_dev_list_1368 NULL +#define pci_dev_list_1369 NULL +#define pci_dev_list_136a NULL +#define pci_dev_list_136b NULL +#define pci_dev_list_136c NULL +#define pci_dev_list_136d NULL +#define pci_dev_list_136f NULL +#define pci_dev_list_1370 NULL +#define pci_dev_list_1371 NULL +#define pci_dev_list_1373 NULL +#define pci_dev_list_1374 NULL +#define pci_dev_list_1375 NULL +#define pci_dev_list_1376 NULL +#define pci_dev_list_1377 NULL +#define pci_dev_list_1378 NULL +#define pci_dev_list_1379 NULL +#define pci_dev_list_137a NULL +#define pci_dev_list_137b NULL +#define pci_dev_list_137c NULL +#define pci_dev_list_137d NULL +#define pci_dev_list_137e NULL +#define pci_dev_list_137f NULL +#define pci_dev_list_1380 NULL +#define pci_dev_list_1381 NULL +#define pci_dev_list_1382 NULL +#define pci_dev_list_1383 NULL +#define pci_dev_list_1384 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1385[] = { + &pci_dev_info_1385_4100, + &pci_dev_info_1385_620a, + &pci_dev_info_1385_622a, + &pci_dev_info_1385_630a, + &pci_dev_info_1385_f311, + NULL +}; +#endif +#define pci_dev_list_1386 NULL +#define pci_dev_list_1387 NULL +#define pci_dev_list_1388 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1389[] = { + &pci_dev_info_1389_0001, + NULL +}; +#endif +#define pci_dev_list_138a NULL +#define pci_dev_list_138b NULL +#define pci_dev_list_138c NULL +#define pci_dev_list_138d NULL +#define pci_dev_list_138e NULL +#define pci_dev_list_138f NULL +#define pci_dev_list_1390 NULL +#define pci_dev_list_1391 NULL +#define pci_dev_list_1392 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1393[] = { + &pci_dev_info_1393_1040, + &pci_dev_info_1393_1680, + &pci_dev_info_1393_2040, + &pci_dev_info_1393_2180, + &pci_dev_info_1393_3200, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1394[] = { + &pci_dev_info_1394_0001, + NULL +}; +#endif +#define pci_dev_list_1395 NULL +#define pci_dev_list_1396 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1397[] = { + &pci_dev_info_1397_2bd0, + NULL +}; +#endif +#define pci_dev_list_1398 NULL +#define pci_dev_list_1399 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_139a[] = { + &pci_dev_info_139a_0001, + &pci_dev_info_139a_0003, + &pci_dev_info_139a_0005, + NULL +}; +#endif +#define pci_dev_list_139b NULL +#define pci_dev_list_139c NULL +#define pci_dev_list_139d NULL +#define pci_dev_list_139e NULL +#define pci_dev_list_139f NULL +#define pci_dev_list_13a0 NULL +#define pci_dev_list_13a1 NULL +#define pci_dev_list_13a2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13a3[] = { + &pci_dev_info_13a3_0005, + &pci_dev_info_13a3_0006, + &pci_dev_info_13a3_0007, + &pci_dev_info_13a3_0012, + &pci_dev_info_13a3_0014, + &pci_dev_info_13a3_0016, + &pci_dev_info_13a3_0017, + &pci_dev_info_13a3_0018, + NULL +}; +#endif +#define pci_dev_list_13a4 NULL +#define pci_dev_list_13a5 NULL +#define pci_dev_list_13a6 NULL +#define pci_dev_list_13a7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13a8[] = { + &pci_dev_info_13a8_0158, + NULL +}; +#endif +#define pci_dev_list_13a9 NULL +#define pci_dev_list_13aa NULL +#define pci_dev_list_13ab NULL +#define pci_dev_list_13ac NULL +#define pci_dev_list_13ad NULL +#define pci_dev_list_13ae NULL +#define pci_dev_list_13af NULL +#define pci_dev_list_13b0 NULL +#define pci_dev_list_13b1 NULL +#define pci_dev_list_13b2 NULL +#define pci_dev_list_13b3 NULL +#define pci_dev_list_13b4 NULL +#define pci_dev_list_13b5 NULL +#define pci_dev_list_13b6 NULL +#define pci_dev_list_13b7 NULL +#define pci_dev_list_13b8 NULL +#define pci_dev_list_13b9 NULL +#define pci_dev_list_13ba NULL +#define pci_dev_list_13bb NULL +#define pci_dev_list_13bc NULL +#define pci_dev_list_13bd NULL +#define pci_dev_list_13be NULL +#define pci_dev_list_13bf NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13c0[] = { + &pci_dev_info_13c0_0010, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13c1[] = { + &pci_dev_info_13c1_1000, + &pci_dev_info_13c1_1001, + &pci_dev_info_13c1_1002, + NULL +}; +#endif +#define pci_dev_list_13c2 NULL +#define pci_dev_list_13c3 NULL +#define pci_dev_list_13c4 NULL +#define pci_dev_list_13c5 NULL +#define pci_dev_list_13c6 NULL +#define pci_dev_list_13c7 NULL +#define pci_dev_list_13c8 NULL +#define pci_dev_list_13c9 NULL +#define pci_dev_list_13ca NULL +#define pci_dev_list_13cb NULL +#define pci_dev_list_13cc NULL +#define pci_dev_list_13cd NULL +#define pci_dev_list_13ce NULL +#define pci_dev_list_13cf NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13d0[] = { + &pci_dev_info_13d0_2103, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13d1[] = { + &pci_dev_info_13d1_ab02, + &pci_dev_info_13d1_ab06, + NULL +}; +#endif +#define pci_dev_list_13d2 NULL +#define pci_dev_list_13d3 NULL +#define pci_dev_list_13d4 NULL +#define pci_dev_list_13d5 NULL +#define pci_dev_list_13d6 NULL +#define pci_dev_list_13d7 NULL +#define pci_dev_list_13d8 NULL +#define pci_dev_list_13d9 NULL +#define pci_dev_list_13da NULL +#define pci_dev_list_13db NULL +#define pci_dev_list_13dc NULL +#define pci_dev_list_13dd NULL +#define pci_dev_list_13de NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13df[] = { + &pci_dev_info_13df_0001, + NULL +}; +#endif +#define pci_dev_list_13e0 NULL +#define pci_dev_list_13e1 NULL +#define pci_dev_list_13e2 NULL +#define pci_dev_list_13e3 NULL +#define pci_dev_list_13e4 NULL +#define pci_dev_list_13e5 NULL +#define pci_dev_list_13e6 NULL +#define pci_dev_list_13e7 NULL +#define pci_dev_list_13e8 NULL +#define pci_dev_list_13e9 NULL +#define pci_dev_list_13ea NULL +#define pci_dev_list_13eb NULL +#define pci_dev_list_13ec NULL +#define pci_dev_list_13ed NULL +#define pci_dev_list_13ee NULL +#define pci_dev_list_13ef NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13f0[] = { + &pci_dev_info_13f0_0201, + NULL +}; +#endif +#define pci_dev_list_13f1 NULL +#define pci_dev_list_13f2 NULL +#define pci_dev_list_13f3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13f4[] = { + &pci_dev_info_13f4_1401, + NULL +}; +#endif +#define pci_dev_list_13f5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13f6[] = { + &pci_dev_info_13f6_0100, + &pci_dev_info_13f6_0101, + &pci_dev_info_13f6_0111, + &pci_dev_info_13f6_0211, + NULL +}; +#endif +#define pci_dev_list_13f7 NULL +#define pci_dev_list_13f8 NULL +#define pci_dev_list_13f9 NULL +#define pci_dev_list_13fa NULL +#define pci_dev_list_13fb NULL +#define pci_dev_list_13fc NULL +#define pci_dev_list_13fd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13fe[] = { + &pci_dev_info_13fe_1756, + NULL +}; +#endif +#define pci_dev_list_13ff NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1400[] = { + &pci_dev_info_1400_1401, + NULL +}; +#endif +#define pci_dev_list_1401 NULL +#define pci_dev_list_1402 NULL +#define pci_dev_list_1403 NULL +#define pci_dev_list_1404 NULL +#define pci_dev_list_1405 NULL +#define pci_dev_list_1406 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1407[] = { + &pci_dev_info_1407_0100, + &pci_dev_info_1407_0101, + &pci_dev_info_1407_0102, + &pci_dev_info_1407_0200, + &pci_dev_info_1407_0201, + &pci_dev_info_1407_0202, + &pci_dev_info_1407_0500, + &pci_dev_info_1407_0600, + &pci_dev_info_1407_8000, + &pci_dev_info_1407_8001, + &pci_dev_info_1407_8002, + &pci_dev_info_1407_8003, + &pci_dev_info_1407_8800, + NULL +}; +#endif +#define pci_dev_list_1408 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1409[] = { + &pci_dev_info_1409_7168, + NULL +}; +#endif +#define pci_dev_list_140a NULL +#define pci_dev_list_140b NULL +#define pci_dev_list_140c NULL +#define pci_dev_list_140d NULL +#define pci_dev_list_140e NULL +#define pci_dev_list_140f NULL +#define pci_dev_list_1410 NULL +#define pci_dev_list_1411 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1412[] = { + &pci_dev_info_1412_1712, + &pci_dev_info_1412_1724, + NULL +}; +#endif +#define pci_dev_list_1413 NULL +#define pci_dev_list_1414 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1415[] = { + &pci_dev_info_1415_8403, + &pci_dev_info_1415_9501, + &pci_dev_info_1415_950a, + &pci_dev_info_1415_950b, + &pci_dev_info_1415_9511, + &pci_dev_info_1415_9521, + NULL +}; +#endif +#define pci_dev_list_1416 NULL +#define pci_dev_list_1417 NULL +#define pci_dev_list_1418 NULL +#define pci_dev_list_1419 NULL +#define pci_dev_list_141a NULL +#define pci_dev_list_141b NULL +#define pci_dev_list_141d NULL +#define pci_dev_list_141e NULL +#define pci_dev_list_141f NULL +#define pci_dev_list_1420 NULL +#define pci_dev_list_1421 NULL +#define pci_dev_list_1422 NULL +#define pci_dev_list_1423 NULL +#define pci_dev_list_1424 NULL +#define pci_dev_list_1425 NULL +#define pci_dev_list_1426 NULL +#define pci_dev_list_1427 NULL +#define pci_dev_list_1428 NULL +#define pci_dev_list_1429 NULL +#define pci_dev_list_142a NULL +#define pci_dev_list_142b NULL +#define pci_dev_list_142c NULL +#define pci_dev_list_142d NULL +#define pci_dev_list_142e NULL +#define pci_dev_list_142f NULL +#define pci_dev_list_1430 NULL +#define pci_dev_list_1431 NULL +#define pci_dev_list_1432 NULL +#define pci_dev_list_1433 NULL +#define pci_dev_list_1435 NULL +#define pci_dev_list_1436 NULL +#define pci_dev_list_1437 NULL +#define pci_dev_list_1438 NULL +#define pci_dev_list_1439 NULL +#define pci_dev_list_143a NULL +#define pci_dev_list_143b NULL +#define pci_dev_list_143c NULL +#define pci_dev_list_143d NULL +#define pci_dev_list_143e NULL +#define pci_dev_list_143f NULL +#define pci_dev_list_1440 NULL +#define pci_dev_list_1441 NULL +#define pci_dev_list_1442 NULL +#define pci_dev_list_1443 NULL +#define pci_dev_list_1444 NULL +#define pci_dev_list_1445 NULL +#define pci_dev_list_1446 NULL +#define pci_dev_list_1447 NULL +#define pci_dev_list_1448 NULL +#define pci_dev_list_1449 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_144a[] = { + &pci_dev_info_144a_7296, + &pci_dev_info_144a_7432, + &pci_dev_info_144a_7433, + &pci_dev_info_144a_7434, + &pci_dev_info_144a_7841, + &pci_dev_info_144a_8133, + &pci_dev_info_144a_8554, + &pci_dev_info_144a_9111, + &pci_dev_info_144a_9113, + &pci_dev_info_144a_9114, + NULL +}; +#endif +#define pci_dev_list_144b NULL +#define pci_dev_list_144c NULL +#define pci_dev_list_144d NULL +#define pci_dev_list_144e NULL +#define pci_dev_list_144f NULL +#define pci_dev_list_1450 NULL +#define pci_dev_list_1451 NULL +#define pci_dev_list_1453 NULL +#define pci_dev_list_1454 NULL +#define pci_dev_list_1455 NULL +#define pci_dev_list_1456 NULL +#define pci_dev_list_1457 NULL +#define pci_dev_list_1458 NULL +#define pci_dev_list_1459 NULL +#define pci_dev_list_145a NULL +#define pci_dev_list_145b NULL +#define pci_dev_list_145c NULL +#define pci_dev_list_145d NULL +#define pci_dev_list_145e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_145f[] = { + &pci_dev_info_145f_0001, + NULL +}; +#endif +#define pci_dev_list_1460 NULL +#define pci_dev_list_1461 NULL +#define pci_dev_list_1462 NULL +#define pci_dev_list_1463 NULL +#define pci_dev_list_1464 NULL +#define pci_dev_list_1465 NULL +#define pci_dev_list_1466 NULL +#define pci_dev_list_1467 NULL +#define pci_dev_list_1468 NULL +#define pci_dev_list_1469 NULL +#define pci_dev_list_146a NULL +#define pci_dev_list_146b NULL +#define pci_dev_list_146c NULL +#define pci_dev_list_146d NULL +#define pci_dev_list_146e NULL +#define pci_dev_list_146f NULL +#define pci_dev_list_1470 NULL +#define pci_dev_list_1471 NULL +#define pci_dev_list_1472 NULL +#define pci_dev_list_1473 NULL +#define pci_dev_list_1474 NULL +#define pci_dev_list_1475 NULL +#define pci_dev_list_1476 NULL +#define pci_dev_list_1477 NULL +#define pci_dev_list_1478 NULL +#define pci_dev_list_1479 NULL +#define pci_dev_list_147a NULL +#define pci_dev_list_147b NULL +#define pci_dev_list_147c NULL +#define pci_dev_list_147d NULL +#define pci_dev_list_147e NULL +#define pci_dev_list_147f NULL +#define pci_dev_list_1480 NULL +#define pci_dev_list_1481 NULL +#define pci_dev_list_1482 NULL +#define pci_dev_list_1483 NULL +#define pci_dev_list_1484 NULL +#define pci_dev_list_1485 NULL +#define pci_dev_list_1486 NULL +#define pci_dev_list_1487 NULL +#define pci_dev_list_1488 NULL +#define pci_dev_list_1489 NULL +#define pci_dev_list_148a NULL +#define pci_dev_list_148b NULL +#define pci_dev_list_148c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_148d[] = { + &pci_dev_info_148d_1003, + NULL +}; +#endif +#define pci_dev_list_148e NULL +#define pci_dev_list_148f NULL +#define pci_dev_list_1490 NULL +#define pci_dev_list_1491 NULL +#define pci_dev_list_1492 NULL +#define pci_dev_list_1493 NULL +#define pci_dev_list_1494 NULL +#define pci_dev_list_1495 NULL +#define pci_dev_list_1496 NULL +#define pci_dev_list_1497 NULL +#define pci_dev_list_1498 NULL +#define pci_dev_list_1499 NULL +#define pci_dev_list_149a NULL +#define pci_dev_list_149b NULL +#define pci_dev_list_149c NULL +#define pci_dev_list_149d NULL +#define pci_dev_list_149e NULL +#define pci_dev_list_149f NULL +#define pci_dev_list_14a0 NULL +#define pci_dev_list_14a1 NULL +#define pci_dev_list_14a2 NULL +#define pci_dev_list_14a3 NULL +#define pci_dev_list_14a4 NULL +#define pci_dev_list_14a5 NULL +#define pci_dev_list_14a6 NULL +#define pci_dev_list_14a7 NULL +#define pci_dev_list_14a8 NULL +#define pci_dev_list_14a9 NULL +#define pci_dev_list_14aa NULL +#define pci_dev_list_14ab NULL +#define pci_dev_list_14ac NULL +#define pci_dev_list_14ad NULL +#define pci_dev_list_14ae NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14af[] = { + &pci_dev_info_14af_7102, + NULL +}; +#endif +#define pci_dev_list_14b0 NULL +#define pci_dev_list_14b1 NULL +#define pci_dev_list_14b2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14b3[] = { + &pci_dev_info_14b3_0000, + NULL +}; +#endif +#define pci_dev_list_14b4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14b5[] = { + &pci_dev_info_14b5_0200, + &pci_dev_info_14b5_0300, + &pci_dev_info_14b5_0400, + &pci_dev_info_14b5_0600, + &pci_dev_info_14b5_0800, + &pci_dev_info_14b5_0900, + &pci_dev_info_14b5_0a00, + &pci_dev_info_14b5_0b00, + NULL +}; +#endif +#define pci_dev_list_14b6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14b7[] = { + &pci_dev_info_14b7_0001, + NULL +}; +#endif +#define pci_dev_list_14b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14b9[] = { + &pci_dev_info_14b9_0001, + &pci_dev_info_14b9_0340, + &pci_dev_info_14b9_0350, + &pci_dev_info_14b9_4500, + &pci_dev_info_14b9_4800, + &pci_dev_info_14b9_a504, + NULL +}; +#endif +#define pci_dev_list_14ba NULL +#define pci_dev_list_14bb NULL +#define pci_dev_list_14bc NULL +#define pci_dev_list_14bd NULL +#define pci_dev_list_14be NULL +#define pci_dev_list_14bf NULL +#define pci_dev_list_14c0 NULL +#define pci_dev_list_14c1 NULL +#define pci_dev_list_14c2 NULL +#define pci_dev_list_14c3 NULL +#define pci_dev_list_14c4 NULL +#define pci_dev_list_14c5 NULL +#define pci_dev_list_14c6 NULL +#define pci_dev_list_14c7 NULL +#define pci_dev_list_14c8 NULL +#define pci_dev_list_14c9 NULL +#define pci_dev_list_14ca NULL +#define pci_dev_list_14cb NULL +#define pci_dev_list_14cc NULL +#define pci_dev_list_14cd NULL +#define pci_dev_list_14ce NULL +#define pci_dev_list_14cf NULL +#define pci_dev_list_14d0 NULL +#define pci_dev_list_14d1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14d2[] = { + &pci_dev_info_14d2_8001, + &pci_dev_info_14d2_8002, + &pci_dev_info_14d2_8010, + &pci_dev_info_14d2_8011, + &pci_dev_info_14d2_8020, + &pci_dev_info_14d2_8021, + &pci_dev_info_14d2_8040, + &pci_dev_info_14d2_8080, + &pci_dev_info_14d2_a000, + &pci_dev_info_14d2_a001, + &pci_dev_info_14d2_a003, + &pci_dev_info_14d2_a004, + &pci_dev_info_14d2_a005, + &pci_dev_info_14d2_e001, + &pci_dev_info_14d2_e010, + &pci_dev_info_14d2_e020, + NULL +}; +#endif +#define pci_dev_list_14d3 NULL +#define pci_dev_list_14d4 NULL +#define pci_dev_list_14d5 NULL +#define pci_dev_list_14d6 NULL +#define pci_dev_list_14d7 NULL +#define pci_dev_list_14d8 NULL +#define pci_dev_list_14d9 NULL +#define pci_dev_list_14da NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14db[] = { + &pci_dev_info_14db_2120, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14dc[] = { + &pci_dev_info_14dc_0000, + &pci_dev_info_14dc_0001, + &pci_dev_info_14dc_0002, + &pci_dev_info_14dc_0003, + &pci_dev_info_14dc_0004, + &pci_dev_info_14dc_0005, + &pci_dev_info_14dc_0006, + &pci_dev_info_14dc_0007, + &pci_dev_info_14dc_0008, + &pci_dev_info_14dc_0009, + &pci_dev_info_14dc_000a, + &pci_dev_info_14dc_000b, + NULL +}; +#endif +#define pci_dev_list_14dd NULL +#define pci_dev_list_14de NULL +#define pci_dev_list_14df NULL +#define pci_dev_list_14e1 NULL +#define pci_dev_list_14e2 NULL +#define pci_dev_list_14e3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14e4[] = { + &pci_dev_info_14e4_1644, + &pci_dev_info_14e4_1645, + &pci_dev_info_14e4_1646, + &pci_dev_info_14e4_1647, + &pci_dev_info_14e4_1648, + &pci_dev_info_14e4_164d, + &pci_dev_info_14e4_1653, + &pci_dev_info_14e4_165d, + &pci_dev_info_14e4_1696, + &pci_dev_info_14e4_16a6, + &pci_dev_info_14e4_16a7, + &pci_dev_info_14e4_16a8, + &pci_dev_info_14e4_16c6, + &pci_dev_info_14e4_16c7, + &pci_dev_info_14e4_4210, + &pci_dev_info_14e4_4211, + &pci_dev_info_14e4_4212, + &pci_dev_info_14e4_4301, + &pci_dev_info_14e4_4401, + &pci_dev_info_14e4_4402, + &pci_dev_info_14e4_4410, + &pci_dev_info_14e4_4411, + &pci_dev_info_14e4_4412, + &pci_dev_info_14e4_5820, + &pci_dev_info_14e4_5821, + NULL +}; +#endif +#define pci_dev_list_14e5 NULL +#define pci_dev_list_14e6 NULL +#define pci_dev_list_14e7 NULL +#define pci_dev_list_14e8 NULL +#define pci_dev_list_14e9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14ea[] = { + &pci_dev_info_14ea_ab06, + NULL +}; +#endif +#define pci_dev_list_14eb NULL +#define pci_dev_list_14ec NULL +#define pci_dev_list_14ed NULL +#define pci_dev_list_14ee NULL +#define pci_dev_list_14ef NULL +#define pci_dev_list_14f0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14f1[] = { + &pci_dev_info_14f1_1002, + &pci_dev_info_14f1_1003, + &pci_dev_info_14f1_1004, + &pci_dev_info_14f1_1005, + &pci_dev_info_14f1_1006, + &pci_dev_info_14f1_1022, + &pci_dev_info_14f1_1023, + &pci_dev_info_14f1_1024, + &pci_dev_info_14f1_1025, + &pci_dev_info_14f1_1026, + &pci_dev_info_14f1_1032, + &pci_dev_info_14f1_1033, + &pci_dev_info_14f1_1034, + &pci_dev_info_14f1_1035, + &pci_dev_info_14f1_1036, + &pci_dev_info_14f1_1052, + &pci_dev_info_14f1_1053, + &pci_dev_info_14f1_1054, + &pci_dev_info_14f1_1055, + &pci_dev_info_14f1_1056, + &pci_dev_info_14f1_1057, + &pci_dev_info_14f1_1059, + &pci_dev_info_14f1_1063, + &pci_dev_info_14f1_1064, + &pci_dev_info_14f1_1065, + &pci_dev_info_14f1_1066, + &pci_dev_info_14f1_1433, + &pci_dev_info_14f1_1434, + &pci_dev_info_14f1_1435, + &pci_dev_info_14f1_1436, + &pci_dev_info_14f1_1453, + &pci_dev_info_14f1_1454, + &pci_dev_info_14f1_1455, + &pci_dev_info_14f1_1456, + &pci_dev_info_14f1_1610, + &pci_dev_info_14f1_1611, + &pci_dev_info_14f1_1803, + &pci_dev_info_14f1_1815, + &pci_dev_info_14f1_2003, + &pci_dev_info_14f1_2004, + &pci_dev_info_14f1_2005, + &pci_dev_info_14f1_2006, + &pci_dev_info_14f1_2013, + &pci_dev_info_14f1_2014, + &pci_dev_info_14f1_2015, + &pci_dev_info_14f1_2016, + &pci_dev_info_14f1_2043, + &pci_dev_info_14f1_2044, + &pci_dev_info_14f1_2045, + &pci_dev_info_14f1_2046, + &pci_dev_info_14f1_2063, + &pci_dev_info_14f1_2064, + &pci_dev_info_14f1_2065, + &pci_dev_info_14f1_2066, + &pci_dev_info_14f1_2093, + &pci_dev_info_14f1_2143, + &pci_dev_info_14f1_2144, + &pci_dev_info_14f1_2145, + &pci_dev_info_14f1_2146, + &pci_dev_info_14f1_2163, + &pci_dev_info_14f1_2164, + &pci_dev_info_14f1_2165, + &pci_dev_info_14f1_2166, + &pci_dev_info_14f1_2343, + &pci_dev_info_14f1_2344, + &pci_dev_info_14f1_2345, + &pci_dev_info_14f1_2346, + &pci_dev_info_14f1_2363, + &pci_dev_info_14f1_2364, + &pci_dev_info_14f1_2365, + &pci_dev_info_14f1_2366, + &pci_dev_info_14f1_2443, + &pci_dev_info_14f1_2444, + &pci_dev_info_14f1_2445, + &pci_dev_info_14f1_2446, + &pci_dev_info_14f1_2463, + &pci_dev_info_14f1_2464, + &pci_dev_info_14f1_2465, + &pci_dev_info_14f1_2466, + &pci_dev_info_14f1_2f00, + &pci_dev_info_14f1_8234, + NULL +}; +#endif +#define pci_dev_list_14f2 NULL +#define pci_dev_list_14f3 NULL +#define pci_dev_list_14f4 NULL +#define pci_dev_list_14f5 NULL +#define pci_dev_list_14f6 NULL +#define pci_dev_list_14f7 NULL +#define pci_dev_list_14f8 NULL +#define pci_dev_list_14f9 NULL +#define pci_dev_list_14fa NULL +#define pci_dev_list_14fb NULL +#define pci_dev_list_14fc NULL +#define pci_dev_list_14fd NULL +#define pci_dev_list_14fe NULL +#define pci_dev_list_14ff NULL +#define pci_dev_list_1500 NULL +#define pci_dev_list_1501 NULL +#define pci_dev_list_1502 NULL +#define pci_dev_list_1503 NULL +#define pci_dev_list_1504 NULL +#define pci_dev_list_1505 NULL +#define pci_dev_list_1506 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1507[] = { + &pci_dev_info_1507_0001, + &pci_dev_info_1507_0002, + &pci_dev_info_1507_0003, + &pci_dev_info_1507_0100, + &pci_dev_info_1507_0431, + &pci_dev_info_1507_4801, + &pci_dev_info_1507_4802, + &pci_dev_info_1507_4803, + &pci_dev_info_1507_4806, + NULL +}; +#endif +#define pci_dev_list_1508 NULL +#define pci_dev_list_1509 NULL +#define pci_dev_list_150a NULL +#define pci_dev_list_150b NULL +#define pci_dev_list_150c NULL +#define pci_dev_list_150d NULL +#define pci_dev_list_150e NULL +#define pci_dev_list_150f NULL +#define pci_dev_list_1510 NULL +#define pci_dev_list_1511 NULL +#define pci_dev_list_1512 NULL +#define pci_dev_list_1513 NULL +#define pci_dev_list_1514 NULL +#define pci_dev_list_1515 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1516[] = { + &pci_dev_info_1516_0803, + NULL +}; +#endif +#define pci_dev_list_1517 NULL +#define pci_dev_list_1518 NULL +#define pci_dev_list_1519 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_151a[] = { + &pci_dev_info_151a_1002, + &pci_dev_info_151a_1004, + &pci_dev_info_151a_1008, + NULL +}; +#endif +#define pci_dev_list_151b NULL +#define pci_dev_list_151c NULL +#define pci_dev_list_151d NULL +#define pci_dev_list_151e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_151f[] = { + &pci_dev_info_151f_0000, + NULL +}; +#endif +#define pci_dev_list_1520 NULL +#define pci_dev_list_1521 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1522[] = { + &pci_dev_info_1522_0100, + NULL +}; +#endif +#define pci_dev_list_1523 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1524[] = { + &pci_dev_info_1524_1211, + &pci_dev_info_1524_1225, + &pci_dev_info_1524_1410, + &pci_dev_info_1524_1420, + NULL +}; +#endif +#define pci_dev_list_1525 NULL +#define pci_dev_list_1526 NULL +#define pci_dev_list_1527 NULL +#define pci_dev_list_1528 NULL +#define pci_dev_list_1529 NULL +#define pci_dev_list_152a NULL +#define pci_dev_list_152b NULL +#define pci_dev_list_152c NULL +#define pci_dev_list_152d NULL +#define pci_dev_list_152e NULL +#define pci_dev_list_152f NULL +#define pci_dev_list_1530 NULL +#define pci_dev_list_1531 NULL +#define pci_dev_list_1532 NULL +#define pci_dev_list_1533 NULL +#define pci_dev_list_1534 NULL +#define pci_dev_list_1535 NULL +#define pci_dev_list_1537 NULL +#define pci_dev_list_1538 NULL +#define pci_dev_list_1539 NULL +#define pci_dev_list_153a NULL +#define pci_dev_list_153b NULL +#define pci_dev_list_153c NULL +#define pci_dev_list_153d NULL +#define pci_dev_list_153e NULL +#define pci_dev_list_153f NULL +#define pci_dev_list_1540 NULL +#define pci_dev_list_1541 NULL +#define pci_dev_list_1542 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1543[] = { + &pci_dev_info_1543_3052, + &pci_dev_info_1543_4c22, + NULL +}; +#endif +#define pci_dev_list_1544 NULL +#define pci_dev_list_1545 NULL +#define pci_dev_list_1546 NULL +#define pci_dev_list_1547 NULL +#define pci_dev_list_1548 NULL +#define pci_dev_list_1549 NULL +#define pci_dev_list_154a NULL +#define pci_dev_list_154b NULL +#define pci_dev_list_154c NULL +#define pci_dev_list_154d NULL +#define pci_dev_list_154e NULL +#define pci_dev_list_154f NULL +#define pci_dev_list_1550 NULL +#define pci_dev_list_1551 NULL +#define pci_dev_list_1552 NULL +#define pci_dev_list_1553 NULL +#define pci_dev_list_1554 NULL +#define pci_dev_list_1555 NULL +#define pci_dev_list_1556 NULL +#define pci_dev_list_1557 NULL +#define pci_dev_list_1558 NULL +#define pci_dev_list_1559 NULL +#define pci_dev_list_155a NULL +#define pci_dev_list_155b NULL +#define pci_dev_list_155c NULL +#define pci_dev_list_155d NULL +#define pci_dev_list_155e NULL +#define pci_dev_list_155f NULL +#define pci_dev_list_1560 NULL +#define pci_dev_list_1561 NULL +#define pci_dev_list_1562 NULL +#define pci_dev_list_1563 NULL +#define pci_dev_list_1564 NULL +#define pci_dev_list_1565 NULL +#define pci_dev_list_1566 NULL +#define pci_dev_list_1567 NULL +#define pci_dev_list_1568 NULL +#define pci_dev_list_1569 NULL +#define pci_dev_list_156a NULL +#define pci_dev_list_156b NULL +#define pci_dev_list_156c NULL +#define pci_dev_list_156d NULL +#define pci_dev_list_156e NULL +#define pci_dev_list_156f NULL +#define pci_dev_list_1570 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1571[] = { + &pci_dev_info_1571_a001, + &pci_dev_info_1571_a002, + &pci_dev_info_1571_a003, + &pci_dev_info_1571_a004, + &pci_dev_info_1571_a005, + &pci_dev_info_1571_a006, + &pci_dev_info_1571_a007, + &pci_dev_info_1571_a008, + &pci_dev_info_1571_a009, + &pci_dev_info_1571_a00a, + &pci_dev_info_1571_a00b, + &pci_dev_info_1571_a00c, + &pci_dev_info_1571_a00d, + &pci_dev_info_1571_a201, + &pci_dev_info_1571_a202, + &pci_dev_info_1571_a203, + &pci_dev_info_1571_a204, + &pci_dev_info_1571_a205, + &pci_dev_info_1571_a206, + NULL +}; +#endif +#define pci_dev_list_1572 NULL +#define pci_dev_list_1573 NULL +#define pci_dev_list_1574 NULL +#define pci_dev_list_1575 NULL +#define pci_dev_list_1576 NULL +#define pci_dev_list_1578 NULL +#define pci_dev_list_1579 NULL +#define pci_dev_list_157a NULL +#define pci_dev_list_157b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_157c[] = { + &pci_dev_info_157c_8001, + NULL +}; +#endif +#define pci_dev_list_157d NULL +#define pci_dev_list_157e NULL +#define pci_dev_list_157f NULL +#define pci_dev_list_1580 NULL +#define pci_dev_list_1581 NULL +#define pci_dev_list_1582 NULL +#define pci_dev_list_1583 NULL +#define pci_dev_list_1584 NULL +#define pci_dev_list_1585 NULL +#define pci_dev_list_1586 NULL +#define pci_dev_list_1587 NULL +#define pci_dev_list_1588 NULL +#define pci_dev_list_1589 NULL +#define pci_dev_list_158a NULL +#define pci_dev_list_158b NULL +#define pci_dev_list_158c NULL +#define pci_dev_list_158d NULL +#define pci_dev_list_158e NULL +#define pci_dev_list_158f NULL +#define pci_dev_list_1590 NULL +#define pci_dev_list_1591 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1592[] = { + &pci_dev_info_1592_0781, + &pci_dev_info_1592_0782, + &pci_dev_info_1592_0783, + &pci_dev_info_1592_0785, + &pci_dev_info_1592_0786, + &pci_dev_info_1592_0787, + &pci_dev_info_1592_0788, + &pci_dev_info_1592_078a, + NULL +}; +#endif +#define pci_dev_list_1593 NULL +#define pci_dev_list_1594 NULL +#define pci_dev_list_1595 NULL +#define pci_dev_list_1596 NULL +#define pci_dev_list_1597 NULL +#define pci_dev_list_1598 NULL +#define pci_dev_list_1599 NULL +#define pci_dev_list_159a NULL +#define pci_dev_list_159b NULL +#define pci_dev_list_159c NULL +#define pci_dev_list_159d NULL +#define pci_dev_list_159e NULL +#define pci_dev_list_159f NULL +#define pci_dev_list_15a0 NULL +#define pci_dev_list_15a1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15a2[] = { + &pci_dev_info_15a2_0001, + NULL +}; +#endif +#define pci_dev_list_15a3 NULL +#define pci_dev_list_15a4 NULL +#define pci_dev_list_15a5 NULL +#define pci_dev_list_15a6 NULL +#define pci_dev_list_15a7 NULL +#define pci_dev_list_15a8 NULL +#define pci_dev_list_15aa NULL +#define pci_dev_list_15ab NULL +#define pci_dev_list_15ac NULL +static const pciDeviceInfo *pci_dev_list_15ad[] = { + &pci_dev_info_15ad_0710, + NULL +}; +#define pci_dev_list_15ae NULL +#define pci_dev_list_15b0 NULL +#define pci_dev_list_15b1 NULL +#define pci_dev_list_15b2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15b3[] = { + &pci_dev_info_15b3_5274, + NULL +}; +#endif +#define pci_dev_list_15b4 NULL +#define pci_dev_list_15b5 NULL +#define pci_dev_list_15b6 NULL +#define pci_dev_list_15b7 NULL +#define pci_dev_list_15b8 NULL +#define pci_dev_list_15b9 NULL +#define pci_dev_list_15ba NULL +#define pci_dev_list_15bb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15bc[] = { + &pci_dev_info_15bc_2929, + NULL +}; +#endif +#define pci_dev_list_15bd NULL +#define pci_dev_list_15be NULL +#define pci_dev_list_15bf NULL +#define pci_dev_list_15c0 NULL +#define pci_dev_list_15c1 NULL +#define pci_dev_list_15c2 NULL +#define pci_dev_list_15c3 NULL +#define pci_dev_list_15c4 NULL +#define pci_dev_list_15c5 NULL +#define pci_dev_list_15c6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15c7[] = { + &pci_dev_info_15c7_0349, + NULL +}; +#endif +#define pci_dev_list_15c8 NULL +#define pci_dev_list_15c9 NULL +#define pci_dev_list_15ca NULL +#define pci_dev_list_15cb NULL +#define pci_dev_list_15cc NULL +#define pci_dev_list_15cd NULL +#define pci_dev_list_15ce NULL +#define pci_dev_list_15cf NULL +#define pci_dev_list_15d1 NULL +#define pci_dev_list_15d2 NULL +#define pci_dev_list_15d3 NULL +#define pci_dev_list_15d4 NULL +#define pci_dev_list_15d5 NULL +#define pci_dev_list_15d6 NULL +#define pci_dev_list_15d7 NULL +#define pci_dev_list_15d8 NULL +#define pci_dev_list_15d9 NULL +#define pci_dev_list_15da NULL +#define pci_dev_list_15db NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15dc[] = { + &pci_dev_info_15dc_0001, + NULL +}; +#endif +#define pci_dev_list_15dd NULL +#define pci_dev_list_15de NULL +#define pci_dev_list_15df NULL +#define pci_dev_list_15e0 NULL +#define pci_dev_list_15e1 NULL +#define pci_dev_list_15e2 NULL +#define pci_dev_list_15e3 NULL +#define pci_dev_list_15e4 NULL +#define pci_dev_list_15e5 NULL +#define pci_dev_list_15e6 NULL +#define pci_dev_list_15e7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15e8[] = { + &pci_dev_info_15e8_0130, + NULL +}; +#endif +#define pci_dev_list_15e9 NULL +#define pci_dev_list_15ea NULL +#define pci_dev_list_15eb NULL +#define pci_dev_list_15ec NULL +#define pci_dev_list_15ed NULL +#define pci_dev_list_15ee NULL +#define pci_dev_list_15ef NULL +#define pci_dev_list_15f0 NULL +#define pci_dev_list_15f1 NULL +#define pci_dev_list_15f2 NULL +#define pci_dev_list_15f3 NULL +#define pci_dev_list_15f4 NULL +#define pci_dev_list_15f5 NULL +#define pci_dev_list_15f6 NULL +#define pci_dev_list_15f7 NULL +#define pci_dev_list_15f8 NULL +#define pci_dev_list_15f9 NULL +#define pci_dev_list_15fa NULL +#define pci_dev_list_15fb NULL +#define pci_dev_list_15fc NULL +#define pci_dev_list_15fd NULL +#define pci_dev_list_15fe NULL +#define pci_dev_list_15ff NULL +#define pci_dev_list_1600 NULL +#define pci_dev_list_1601 NULL +#define pci_dev_list_1602 NULL +#define pci_dev_list_1603 NULL +#define pci_dev_list_1604 NULL +#define pci_dev_list_1605 NULL +#define pci_dev_list_1606 NULL +#define pci_dev_list_1607 NULL +#define pci_dev_list_1608 NULL +#define pci_dev_list_1609 NULL +#define pci_dev_list_1612 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1619[] = { + &pci_dev_info_1619_0400, + &pci_dev_info_1619_0440, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1629[] = { + &pci_dev_info_1629_1003, + &pci_dev_info_1629_2002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1638[] = { + &pci_dev_info_1638_1100, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_163c[] = { + &pci_dev_info_163c_5449, + NULL +}; +#endif +#define pci_dev_list_1657 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_165a[] = { + &pci_dev_info_165a_c100, + &pci_dev_info_165a_d200, + &pci_dev_info_165a_d300, + NULL +}; +#endif +#define pci_dev_list_165d NULL +#define pci_dev_list_1661 NULL +#define pci_dev_list_1668 NULL +#define pci_dev_list_1681 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16ab[] = { + &pci_dev_info_16ab_1102, + NULL +}; +#endif +#define pci_dev_list_16be NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16ec[] = { + &pci_dev_info_16ec_3685, + NULL +}; +#endif +#define pci_dev_list_16f6 NULL +#define pci_dev_list_1705 NULL +#define pci_dev_list_170b NULL +#define pci_dev_list_170c NULL +#define pci_dev_list_172a NULL +#define pci_dev_list_1737 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_173b[] = { + &pci_dev_info_173b_03e8, + &pci_dev_info_173b_03ea, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1743[] = { + &pci_dev_info_1743_8139, + NULL +}; +#endif +#define pci_dev_list_174b NULL +#define pci_dev_list_175e NULL +#define pci_dev_list_1787 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1796[] = { + &pci_dev_info_1796_0001, + &pci_dev_info_1796_0002, + &pci_dev_info_1796_0003, + &pci_dev_info_1796_0004, + &pci_dev_info_1796_0005, + &pci_dev_info_1796_0006, + NULL +}; +#endif +#define pci_dev_list_1799 NULL +#define pci_dev_list_17af NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17cc[] = { + &pci_dev_info_17cc_2280, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1813[] = { + &pci_dev_info_1813_4000, + &pci_dev_info_1813_4100, + NULL +}; +#endif +#define pci_dev_list_1851 NULL +#define pci_dev_list_1852 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1888[] = { + &pci_dev_info_1888_0301, + &pci_dev_info_1888_0601, + &pci_dev_info_1888_0710, + &pci_dev_info_1888_0720, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1a08[] = { + &pci_dev_info_1a08_0000, + NULL +}; +#endif +#define pci_dev_list_1b13 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1c1c[] = { + &pci_dev_info_1c1c_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1d44[] = { + &pci_dev_info_1d44_a400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1de1[] = { + &pci_dev_info_1de1_0391, + &pci_dev_info_1de1_2020, + &pci_dev_info_1de1_690c, + &pci_dev_info_1de1_dc29, + NULL +}; +#endif +#define pci_dev_list_2000 NULL +#define pci_dev_list_2001 NULL +#define pci_dev_list_2003 NULL +#define pci_dev_list_2004 NULL +#define pci_dev_list_21c3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_2348[] = { + &pci_dev_info_2348_2010, + NULL +}; +#endif +#define pci_dev_list_2646 NULL +#define pci_dev_list_270b NULL +#define pci_dev_list_270f NULL +#define pci_dev_list_2711 NULL +#define pci_dev_list_2a15 NULL +#define pci_dev_list_3000 NULL +#define pci_dev_list_3142 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_3388[] = { + &pci_dev_info_3388_0013, + &pci_dev_info_3388_0014, + &pci_dev_info_3388_0021, + &pci_dev_info_3388_8011, + &pci_dev_info_3388_8012, + &pci_dev_info_3388_8013, + NULL +}; +#endif +#define pci_dev_list_3411 NULL +#define pci_dev_list_3513 NULL +#define pci_dev_list_38ef NULL +static const pciDeviceInfo *pci_dev_list_3d3d[] = { + &pci_dev_info_3d3d_0001, + &pci_dev_info_3d3d_0002, + &pci_dev_info_3d3d_0003, + &pci_dev_info_3d3d_0004, + &pci_dev_info_3d3d_0005, + &pci_dev_info_3d3d_0006, + &pci_dev_info_3d3d_0007, + &pci_dev_info_3d3d_0008, + &pci_dev_info_3d3d_0009, + &pci_dev_info_3d3d_000a, + &pci_dev_info_3d3d_000c, + &pci_dev_info_3d3d_0100, + &pci_dev_info_3d3d_1004, + &pci_dev_info_3d3d_3d04, + &pci_dev_info_3d3d_ffff, + NULL +}; +static const pciDeviceInfo *pci_dev_list_4005[] = { + &pci_dev_info_4005_0300, + &pci_dev_info_4005_0308, + &pci_dev_info_4005_0309, + &pci_dev_info_4005_1064, + &pci_dev_info_4005_2064, + &pci_dev_info_4005_2128, + &pci_dev_info_4005_2301, + &pci_dev_info_4005_2302, + &pci_dev_info_4005_2303, + &pci_dev_info_4005_2364, + &pci_dev_info_4005_2464, + &pci_dev_info_4005_2501, + &pci_dev_info_4005_4000, + &pci_dev_info_4005_4710, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4033[] = { + &pci_dev_info_4033_1360, + NULL +}; +#endif +#define pci_dev_list_4143 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_416c[] = { + &pci_dev_info_416c_0100, + &pci_dev_info_416c_0200, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4444[] = { + &pci_dev_info_4444_0803, + NULL +}; +#endif +#define pci_dev_list_4468 NULL +#define pci_dev_list_4594 NULL +#define pci_dev_list_45fb NULL +#define pci_dev_list_4680 NULL +#define pci_dev_list_4843 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4916[] = { + &pci_dev_info_4916_1960, + NULL +}; +#endif +#define pci_dev_list_4943 NULL +#define pci_dev_list_4978 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4a14[] = { + &pci_dev_info_4a14_5000, + NULL +}; +#endif +#define pci_dev_list_4b10 NULL +#define pci_dev_list_4c48 NULL +#define pci_dev_list_4c53 NULL +#define pci_dev_list_4ca1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4d51[] = { + &pci_dev_info_4d51_0200, + NULL +}; +#endif +#define pci_dev_list_4d54 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4ddc[] = { + &pci_dev_info_4ddc_0100, + &pci_dev_info_4ddc_0801, + &pci_dev_info_4ddc_0802, + &pci_dev_info_4ddc_0811, + &pci_dev_info_4ddc_0812, + &pci_dev_info_4ddc_0881, + &pci_dev_info_4ddc_0882, + &pci_dev_info_4ddc_0891, + &pci_dev_info_4ddc_0892, + &pci_dev_info_4ddc_0901, + &pci_dev_info_4ddc_0902, + &pci_dev_info_4ddc_0903, + &pci_dev_info_4ddc_0904, + &pci_dev_info_4ddc_0b01, + &pci_dev_info_4ddc_0b02, + &pci_dev_info_4ddc_0b03, + &pci_dev_info_4ddc_0b04, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5046[] = { + &pci_dev_info_5046_1001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5053[] = { + &pci_dev_info_5053_2010, + NULL +}; +#endif +#define pci_dev_list_5136 NULL +#define pci_dev_list_5143 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5145[] = { + &pci_dev_info_5145_3031, + NULL +}; +#endif +#define pci_dev_list_5168 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5301[] = { + &pci_dev_info_5301_0001, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_5333[] = { + &pci_dev_info_5333_0551, + &pci_dev_info_5333_5631, + &pci_dev_info_5333_8800, + &pci_dev_info_5333_8801, + &pci_dev_info_5333_8810, + &pci_dev_info_5333_8811, + &pci_dev_info_5333_8812, + &pci_dev_info_5333_8813, + &pci_dev_info_5333_8814, + &pci_dev_info_5333_8815, + &pci_dev_info_5333_883d, + &pci_dev_info_5333_8870, + &pci_dev_info_5333_8880, + &pci_dev_info_5333_8881, + &pci_dev_info_5333_8882, + &pci_dev_info_5333_8883, + &pci_dev_info_5333_88b0, + &pci_dev_info_5333_88b1, + &pci_dev_info_5333_88b2, + &pci_dev_info_5333_88b3, + &pci_dev_info_5333_88c0, + &pci_dev_info_5333_88c1, + &pci_dev_info_5333_88c2, + &pci_dev_info_5333_88c3, + &pci_dev_info_5333_88d0, + &pci_dev_info_5333_88d1, + &pci_dev_info_5333_88d2, + &pci_dev_info_5333_88d3, + &pci_dev_info_5333_88f0, + &pci_dev_info_5333_88f1, + &pci_dev_info_5333_88f2, + &pci_dev_info_5333_88f3, + &pci_dev_info_5333_8900, + &pci_dev_info_5333_8901, + &pci_dev_info_5333_8902, + &pci_dev_info_5333_8903, + &pci_dev_info_5333_8904, + &pci_dev_info_5333_8905, + &pci_dev_info_5333_8906, + &pci_dev_info_5333_8907, + &pci_dev_info_5333_8908, + &pci_dev_info_5333_8909, + &pci_dev_info_5333_890a, + &pci_dev_info_5333_890b, + &pci_dev_info_5333_890c, + &pci_dev_info_5333_890d, + &pci_dev_info_5333_890e, + &pci_dev_info_5333_890f, + &pci_dev_info_5333_8a01, + &pci_dev_info_5333_8a10, + &pci_dev_info_5333_8a13, + &pci_dev_info_5333_8a20, + &pci_dev_info_5333_8a21, + &pci_dev_info_5333_8a22, + &pci_dev_info_5333_8a23, + &pci_dev_info_5333_8a25, + &pci_dev_info_5333_8a26, + &pci_dev_info_5333_8c00, + &pci_dev_info_5333_8c01, + &pci_dev_info_5333_8c02, + &pci_dev_info_5333_8c03, + &pci_dev_info_5333_8c10, + &pci_dev_info_5333_8c11, + &pci_dev_info_5333_8c12, + &pci_dev_info_5333_8c13, + &pci_dev_info_5333_8c22, + &pci_dev_info_5333_8c24, + &pci_dev_info_5333_8c26, + &pci_dev_info_5333_8c2a, + &pci_dev_info_5333_8c2b, + &pci_dev_info_5333_8c2c, + &pci_dev_info_5333_8c2d, + &pci_dev_info_5333_8c2e, + &pci_dev_info_5333_8c2f, + &pci_dev_info_5333_8d01, + &pci_dev_info_5333_8d02, + &pci_dev_info_5333_8d03, + &pci_dev_info_5333_8d04, + &pci_dev_info_5333_9102, + &pci_dev_info_5333_ca00, + NULL +}; +#define pci_dev_list_544c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5455[] = { + &pci_dev_info_5455_4458, + NULL +}; +#endif +#define pci_dev_list_5519 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5544[] = { + &pci_dev_info_5544_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5555[] = { + &pci_dev_info_5555_0003, + NULL +}; +#endif +#define pci_dev_list_5654 NULL +#define pci_dev_list_5700 NULL +#define pci_dev_list_6356 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_6374[] = { + &pci_dev_info_6374_6773, + NULL +}; +#endif +#define pci_dev_list_6409 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_6666[] = { + &pci_dev_info_6666_0001, + &pci_dev_info_6666_0002, + NULL +}; +#endif +#define pci_dev_list_7604 NULL +#define pci_dev_list_7bde NULL +#define pci_dev_list_7fed NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_8008[] = { + &pci_dev_info_8008_0010, + &pci_dev_info_8008_0011, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_8086[] = { + &pci_dev_info_8086_0007, + &pci_dev_info_8086_0008, + &pci_dev_info_8086_0039, + &pci_dev_info_8086_0122, + &pci_dev_info_8086_0482, + &pci_dev_info_8086_0483, + &pci_dev_info_8086_0484, + &pci_dev_info_8086_0486, + &pci_dev_info_8086_04a3, + &pci_dev_info_8086_04d0, + &pci_dev_info_8086_0600, + &pci_dev_info_8086_0960, + &pci_dev_info_8086_0962, + &pci_dev_info_8086_0964, + &pci_dev_info_8086_1000, + &pci_dev_info_8086_1001, + &pci_dev_info_8086_1002, + &pci_dev_info_8086_1004, + &pci_dev_info_8086_1008, + &pci_dev_info_8086_1009, + &pci_dev_info_8086_100c, + &pci_dev_info_8086_100d, + &pci_dev_info_8086_100e, + &pci_dev_info_8086_100f, + &pci_dev_info_8086_1010, + &pci_dev_info_8086_1011, + &pci_dev_info_8086_1012, + &pci_dev_info_8086_1015, + &pci_dev_info_8086_1029, + &pci_dev_info_8086_1030, + &pci_dev_info_8086_1031, + &pci_dev_info_8086_1032, + &pci_dev_info_8086_1033, + &pci_dev_info_8086_1034, + &pci_dev_info_8086_1035, + &pci_dev_info_8086_1036, + &pci_dev_info_8086_1037, + &pci_dev_info_8086_1038, + &pci_dev_info_8086_1039, + &pci_dev_info_8086_103a, + &pci_dev_info_8086_103b, + &pci_dev_info_8086_103c, + &pci_dev_info_8086_103d, + &pci_dev_info_8086_103e, + &pci_dev_info_8086_1040, + &pci_dev_info_8086_1059, + &pci_dev_info_8086_1130, + &pci_dev_info_8086_1131, + &pci_dev_info_8086_1132, + &pci_dev_info_8086_1161, + &pci_dev_info_8086_1162, + &pci_dev_info_8086_1200, + &pci_dev_info_8086_1209, + &pci_dev_info_8086_1221, + &pci_dev_info_8086_1222, + &pci_dev_info_8086_1223, + &pci_dev_info_8086_1225, + &pci_dev_info_8086_1226, + &pci_dev_info_8086_1227, + &pci_dev_info_8086_1228, + &pci_dev_info_8086_1229, + &pci_dev_info_8086_122d, + &pci_dev_info_8086_122e, + &pci_dev_info_8086_1230, + &pci_dev_info_8086_1231, + &pci_dev_info_8086_1234, + &pci_dev_info_8086_1235, + &pci_dev_info_8086_1237, + &pci_dev_info_8086_1239, + &pci_dev_info_8086_123b, + &pci_dev_info_8086_123c, + &pci_dev_info_8086_123d, + &pci_dev_info_8086_123f, + &pci_dev_info_8086_1240, + &pci_dev_info_8086_124b, + &pci_dev_info_8086_1250, + &pci_dev_info_8086_1360, + &pci_dev_info_8086_1361, + &pci_dev_info_8086_1460, + &pci_dev_info_8086_1461, + &pci_dev_info_8086_1462, + &pci_dev_info_8086_1960, + &pci_dev_info_8086_1962, + &pci_dev_info_8086_1a21, + &pci_dev_info_8086_1a23, + &pci_dev_info_8086_1a24, + &pci_dev_info_8086_1a30, + &pci_dev_info_8086_1a31, + &pci_dev_info_8086_2410, + &pci_dev_info_8086_2411, + &pci_dev_info_8086_2412, + &pci_dev_info_8086_2413, + &pci_dev_info_8086_2415, + &pci_dev_info_8086_2416, + &pci_dev_info_8086_2418, + &pci_dev_info_8086_2420, + &pci_dev_info_8086_2421, + &pci_dev_info_8086_2422, + &pci_dev_info_8086_2423, + &pci_dev_info_8086_2425, + &pci_dev_info_8086_2426, + &pci_dev_info_8086_2428, + &pci_dev_info_8086_2440, + &pci_dev_info_8086_2442, + &pci_dev_info_8086_2443, + &pci_dev_info_8086_2444, + &pci_dev_info_8086_2445, + &pci_dev_info_8086_2446, + &pci_dev_info_8086_2448, + &pci_dev_info_8086_2449, + &pci_dev_info_8086_244a, + &pci_dev_info_8086_244b, + &pci_dev_info_8086_244c, + &pci_dev_info_8086_244e, + &pci_dev_info_8086_2450, + &pci_dev_info_8086_2452, + &pci_dev_info_8086_2453, + &pci_dev_info_8086_2459, + &pci_dev_info_8086_245b, + &pci_dev_info_8086_245d, + &pci_dev_info_8086_245e, + &pci_dev_info_8086_2480, + &pci_dev_info_8086_2482, + &pci_dev_info_8086_2483, + &pci_dev_info_8086_2484, + &pci_dev_info_8086_2485, + &pci_dev_info_8086_2486, + &pci_dev_info_8086_2487, + &pci_dev_info_8086_248a, + &pci_dev_info_8086_248b, + &pci_dev_info_8086_248c, + &pci_dev_info_8086_24c0, + &pci_dev_info_8086_24c2, + &pci_dev_info_8086_24c3, + &pci_dev_info_8086_24c4, + &pci_dev_info_8086_24c5, + &pci_dev_info_8086_24c6, + &pci_dev_info_8086_24c7, + &pci_dev_info_8086_24cb, + &pci_dev_info_8086_24cd, + &pci_dev_info_8086_2500, + &pci_dev_info_8086_2501, + &pci_dev_info_8086_250b, + &pci_dev_info_8086_250f, + &pci_dev_info_8086_2520, + &pci_dev_info_8086_2521, + &pci_dev_info_8086_2530, + &pci_dev_info_8086_2531, + &pci_dev_info_8086_2532, + &pci_dev_info_8086_2533, + &pci_dev_info_8086_2534, + &pci_dev_info_8086_2540, + &pci_dev_info_8086_2541, + &pci_dev_info_8086_2543, + &pci_dev_info_8086_2544, + &pci_dev_info_8086_2545, + &pci_dev_info_8086_2546, + &pci_dev_info_8086_2547, + &pci_dev_info_8086_2548, + &pci_dev_info_8086_2560, + &pci_dev_info_8086_2561, + &pci_dev_info_8086_2562, + &pci_dev_info_8086_2570, + &pci_dev_info_8086_2572, + &pci_dev_info_8086_3092, + &pci_dev_info_8086_3575, + &pci_dev_info_8086_3576, + &pci_dev_info_8086_3577, + &pci_dev_info_8086_3578, + &pci_dev_info_8086_3580, + &pci_dev_info_8086_3582, + &pci_dev_info_8086_5200, + &pci_dev_info_8086_5201, + &pci_dev_info_8086_530d, + &pci_dev_info_8086_7000, + &pci_dev_info_8086_7010, + &pci_dev_info_8086_7020, + &pci_dev_info_8086_7030, + &pci_dev_info_8086_7100, + &pci_dev_info_8086_7110, + &pci_dev_info_8086_7111, + &pci_dev_info_8086_7112, + &pci_dev_info_8086_7113, + &pci_dev_info_8086_7120, + &pci_dev_info_8086_7121, + &pci_dev_info_8086_7122, + &pci_dev_info_8086_7123, + &pci_dev_info_8086_7124, + &pci_dev_info_8086_7125, + &pci_dev_info_8086_7126, + &pci_dev_info_8086_7128, + &pci_dev_info_8086_712a, + &pci_dev_info_8086_7180, + &pci_dev_info_8086_7181, + &pci_dev_info_8086_7190, + &pci_dev_info_8086_7191, + &pci_dev_info_8086_7192, + &pci_dev_info_8086_7194, + &pci_dev_info_8086_7195, + &pci_dev_info_8086_7196, + &pci_dev_info_8086_7198, + &pci_dev_info_8086_7199, + &pci_dev_info_8086_719a, + &pci_dev_info_8086_719b, + &pci_dev_info_8086_71a0, + &pci_dev_info_8086_71a1, + &pci_dev_info_8086_71a2, + &pci_dev_info_8086_7600, + &pci_dev_info_8086_7601, + &pci_dev_info_8086_7602, + &pci_dev_info_8086_7603, + &pci_dev_info_8086_7800, + &pci_dev_info_8086_84c4, + &pci_dev_info_8086_84c5, + &pci_dev_info_8086_84ca, + &pci_dev_info_8086_84cb, + &pci_dev_info_8086_84e0, + &pci_dev_info_8086_84e1, + &pci_dev_info_8086_84e2, + &pci_dev_info_8086_84e3, + &pci_dev_info_8086_84e4, + &pci_dev_info_8086_84e6, + &pci_dev_info_8086_84ea, + &pci_dev_info_8086_9621, + &pci_dev_info_8086_9622, + &pci_dev_info_8086_9641, + &pci_dev_info_8086_96a1, + &pci_dev_info_8086_b152, + &pci_dev_info_8086_b154, + &pci_dev_info_8086_b555, + &pci_dev_info_8086_ffff, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_8800[] = { + &pci_dev_info_8800_2008, + NULL +}; +#endif +#define pci_dev_list_8866 NULL +#define pci_dev_list_8888 NULL +#define pci_dev_list_8e0e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_8e2e[] = { + &pci_dev_info_8e2e_3000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_9004[] = { + &pci_dev_info_9004_1078, + &pci_dev_info_9004_1160, + &pci_dev_info_9004_2178, + &pci_dev_info_9004_3860, + &pci_dev_info_9004_3b78, + &pci_dev_info_9004_5075, + &pci_dev_info_9004_5078, + &pci_dev_info_9004_5175, + &pci_dev_info_9004_5178, + &pci_dev_info_9004_5275, + &pci_dev_info_9004_5278, + &pci_dev_info_9004_5375, + &pci_dev_info_9004_5378, + &pci_dev_info_9004_5475, + &pci_dev_info_9004_5478, + &pci_dev_info_9004_5575, + &pci_dev_info_9004_5578, + &pci_dev_info_9004_5647, + &pci_dev_info_9004_5675, + &pci_dev_info_9004_5678, + &pci_dev_info_9004_5775, + &pci_dev_info_9004_5778, + &pci_dev_info_9004_5800, + &pci_dev_info_9004_5900, + &pci_dev_info_9004_5905, + &pci_dev_info_9004_6038, + &pci_dev_info_9004_6075, + &pci_dev_info_9004_6078, + &pci_dev_info_9004_6178, + &pci_dev_info_9004_6278, + &pci_dev_info_9004_6378, + &pci_dev_info_9004_6478, + &pci_dev_info_9004_6578, + &pci_dev_info_9004_6678, + &pci_dev_info_9004_6778, + &pci_dev_info_9004_6915, + &pci_dev_info_9004_7078, + &pci_dev_info_9004_7178, + &pci_dev_info_9004_7278, + &pci_dev_info_9004_7378, + &pci_dev_info_9004_7478, + &pci_dev_info_9004_7578, + &pci_dev_info_9004_7678, + &pci_dev_info_9004_7778, + &pci_dev_info_9004_7810, + &pci_dev_info_9004_7815, + &pci_dev_info_9004_7850, + &pci_dev_info_9004_7855, + &pci_dev_info_9004_7860, + &pci_dev_info_9004_7870, + &pci_dev_info_9004_7871, + &pci_dev_info_9004_7872, + &pci_dev_info_9004_7873, + &pci_dev_info_9004_7874, + &pci_dev_info_9004_7880, + &pci_dev_info_9004_7890, + &pci_dev_info_9004_7891, + &pci_dev_info_9004_7892, + &pci_dev_info_9004_7893, + &pci_dev_info_9004_7894, + &pci_dev_info_9004_7895, + &pci_dev_info_9004_7896, + &pci_dev_info_9004_7897, + &pci_dev_info_9004_8078, + &pci_dev_info_9004_8178, + &pci_dev_info_9004_8278, + &pci_dev_info_9004_8378, + &pci_dev_info_9004_8478, + &pci_dev_info_9004_8578, + &pci_dev_info_9004_8678, + &pci_dev_info_9004_8778, + &pci_dev_info_9004_8878, + &pci_dev_info_9004_8b78, + &pci_dev_info_9004_ec78, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_9005[] = { + &pci_dev_info_9005_0010, + &pci_dev_info_9005_0011, + &pci_dev_info_9005_0013, + &pci_dev_info_9005_001f, + &pci_dev_info_9005_0020, + &pci_dev_info_9005_002f, + &pci_dev_info_9005_0030, + &pci_dev_info_9005_003f, + &pci_dev_info_9005_0050, + &pci_dev_info_9005_0051, + &pci_dev_info_9005_0053, + &pci_dev_info_9005_005f, + &pci_dev_info_9005_0080, + &pci_dev_info_9005_0081, + &pci_dev_info_9005_0083, + &pci_dev_info_9005_008f, + &pci_dev_info_9005_00c0, + &pci_dev_info_9005_00c1, + &pci_dev_info_9005_00c3, + &pci_dev_info_9005_00c5, + &pci_dev_info_9005_00cf, + &pci_dev_info_9005_0250, + &pci_dev_info_9005_0285, + &pci_dev_info_9005_8000, + &pci_dev_info_9005_800f, + &pci_dev_info_9005_8010, + &pci_dev_info_9005_8011, + &pci_dev_info_9005_8012, + &pci_dev_info_9005_8013, + &pci_dev_info_9005_8014, + &pci_dev_info_9005_801e, + &pci_dev_info_9005_801f, + &pci_dev_info_9005_8090, + &pci_dev_info_9005_8091, + &pci_dev_info_9005_8092, + &pci_dev_info_9005_8093, + &pci_dev_info_9005_8094, + &pci_dev_info_9005_809e, + &pci_dev_info_9005_809f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_907f[] = { + &pci_dev_info_907f_2015, + NULL +}; +#endif +#define pci_dev_list_919a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_9412[] = { + &pci_dev_info_9412_6565, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_9699[] = { + &pci_dev_info_9699_6565, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_9710[] = { + &pci_dev_info_9710_9815, + &pci_dev_info_9710_9835, + NULL +}; +#endif +#define pci_dev_list_a0a0 NULL +#define pci_dev_list_a0f1 NULL +#define pci_dev_list_a200 NULL +#define pci_dev_list_a259 NULL +#define pci_dev_list_a25b NULL +#define pci_dev_list_a304 NULL +#define pci_dev_list_a727 NULL +#define pci_dev_list_aa42 NULL +#define pci_dev_list_ac1e NULL +#define pci_dev_list_b1b3 NULL +#define pci_dev_list_bd11 NULL +#define pci_dev_list_c001 NULL +#define pci_dev_list_c0a9 NULL +#define pci_dev_list_c0de NULL +#define pci_dev_list_c0fe NULL +#define pci_dev_list_ca50 NULL +#define pci_dev_list_cafe NULL +#define pci_dev_list_cccc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_cddd[] = { + &pci_dev_info_cddd_0101, + &pci_dev_info_cddd_0200, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_d4d4[] = { + &pci_dev_info_d4d4_0601, + NULL +}; +#endif +#define pci_dev_list_d531 NULL +#define pci_dev_list_d84d NULL +#define pci_dev_list_dead NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_e000[] = { + &pci_dev_info_e000_e000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_e159[] = { + &pci_dev_info_e159_0001, + &pci_dev_info_e159_0002, + NULL +}; +#endif +#define pci_dev_list_e4bf NULL +#define pci_dev_list_ea01 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_ea60[] = { + &pci_dev_info_ea60_9896, + &pci_dev_info_ea60_9897, + &pci_dev_info_ea60_9898, + NULL +}; +#endif +#define pci_dev_list_eabb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_eace[] = { + &pci_dev_info_eace_3100, + &pci_dev_info_eace_3200, + &pci_dev_info_eace_320e, + &pci_dev_info_eace_340e, + &pci_dev_info_eace_341e, + &pci_dev_info_eace_3500, + &pci_dev_info_eace_351c, + &pci_dev_info_eace_4100, + &pci_dev_info_eace_4110, + &pci_dev_info_eace_4220, + &pci_dev_info_eace_422e, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_ec80[] = { + &pci_dev_info_ec80_ec00, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_ecc0[] = { + &pci_dev_info_ecc0_0050, + &pci_dev_info_ecc0_0051, + &pci_dev_info_ecc0_0060, + &pci_dev_info_ecc0_0070, + &pci_dev_info_ecc0_0071, + &pci_dev_info_ecc0_0072, + &pci_dev_info_ecc0_0080, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_edd8[] = { + &pci_dev_info_edd8_a091, + &pci_dev_info_edd8_a099, + &pci_dev_info_edd8_a0a1, + &pci_dev_info_edd8_a0a9, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_f1d0[] = { + &pci_dev_info_f1d0_cafe, + &pci_dev_info_f1d0_efac, + &pci_dev_info_f1d0_facd, + NULL +}; +#endif +#define pci_dev_list_fa57 NULL +#define pci_dev_list_febd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_feda[] = { + &pci_dev_info_feda_a0fa, + &pci_dev_info_feda_a10e, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_fffe[] = { + &pci_dev_info_fffe_0710, + NULL +}; +#endif +#define pci_dev_list_ffff NULL + +static const pciVendorInfo pciVendorInfoList[] = { +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0000, pci_vendor_0000, pci_dev_list_0000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x001a, pci_vendor_001a, pci_dev_list_001a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0033, pci_vendor_0033, pci_dev_list_0033}, +#endif + {0x003d, pci_vendor_003d, pci_dev_list_003d}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0059, pci_vendor_0059, pci_dev_list_0059}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0070, pci_vendor_0070, pci_dev_list_0070}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0100, pci_vendor_0100, pci_dev_list_0100}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0675, pci_vendor_0675, pci_dev_list_0675}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0925, pci_vendor_0925, pci_dev_list_0925}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x09c1, pci_vendor_09c1, pci_dev_list_09c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0a89, pci_vendor_0a89, pci_dev_list_0a89}, +#endif + {0x0e11, pci_vendor_0e11, pci_dev_list_0e11}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0e55, pci_vendor_0e55, pci_dev_list_0e55}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1000, pci_vendor_1000, pci_dev_list_1000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1001, pci_vendor_1001, pci_dev_list_1001}, +#endif + {0x1002, pci_vendor_1002, pci_dev_list_1002}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1003, pci_vendor_1003, pci_dev_list_1003}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1004, pci_vendor_1004, pci_dev_list_1004}, +#endif + {0x1005, pci_vendor_1005, pci_dev_list_1005}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1006, pci_vendor_1006, pci_dev_list_1006}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1007, pci_vendor_1007, pci_dev_list_1007}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1008, pci_vendor_1008, pci_dev_list_1008}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x100a, pci_vendor_100a, pci_dev_list_100a}, +#endif + {0x100b, pci_vendor_100b, pci_dev_list_100b}, + {0x100c, pci_vendor_100c, pci_dev_list_100c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x100d, pci_vendor_100d, pci_dev_list_100d}, +#endif + {0x100e, pci_vendor_100e, pci_dev_list_100e}, + {0x1010, pci_vendor_1010, pci_dev_list_1010}, + {0x1011, pci_vendor_1011, pci_dev_list_1011}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1012, pci_vendor_1012, pci_dev_list_1012}, +#endif + {0x1013, pci_vendor_1013, pci_dev_list_1013}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1014, pci_vendor_1014, pci_dev_list_1014}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1015, pci_vendor_1015, pci_dev_list_1015}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1016, pci_vendor_1016, pci_dev_list_1016}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1017, pci_vendor_1017, pci_dev_list_1017}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1018, pci_vendor_1018, pci_dev_list_1018}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1019, pci_vendor_1019, pci_dev_list_1019}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101a, pci_vendor_101a, pci_dev_list_101a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101b, pci_vendor_101b, pci_dev_list_101b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101c, pci_vendor_101c, pci_dev_list_101c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101e, pci_vendor_101e, pci_dev_list_101e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101f, pci_vendor_101f, pci_dev_list_101f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1020, pci_vendor_1020, pci_dev_list_1020}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1021, pci_vendor_1021, pci_dev_list_1021}, +#endif + {0x1022, pci_vendor_1022, pci_dev_list_1022}, + {0x1023, pci_vendor_1023, pci_dev_list_1023}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1024, pci_vendor_1024, pci_dev_list_1024}, +#endif + {0x1025, pci_vendor_1025, pci_dev_list_1025}, + {0x1028, pci_vendor_1028, pci_dev_list_1028}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1029, pci_vendor_1029, pci_dev_list_1029}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102a, pci_vendor_102a, pci_dev_list_102a}, +#endif + {0x102b, pci_vendor_102b, pci_dev_list_102b}, + {0x102c, pci_vendor_102c, pci_dev_list_102c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102d, pci_vendor_102d, pci_dev_list_102d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102e, pci_vendor_102e, pci_dev_list_102e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102f, pci_vendor_102f, pci_dev_list_102f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1030, pci_vendor_1030, pci_dev_list_1030}, +#endif + {0x1031, pci_vendor_1031, pci_dev_list_1031}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1032, pci_vendor_1032, pci_dev_list_1032}, +#endif + {0x1033, pci_vendor_1033, pci_dev_list_1033}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1034, pci_vendor_1034, pci_dev_list_1034}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1035, pci_vendor_1035, pci_dev_list_1035}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1036, pci_vendor_1036, pci_dev_list_1036}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1037, pci_vendor_1037, pci_dev_list_1037}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1038, pci_vendor_1038, pci_dev_list_1038}, +#endif + {0x1039, pci_vendor_1039, pci_dev_list_1039}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103a, pci_vendor_103a, pci_dev_list_103a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103b, pci_vendor_103b, pci_dev_list_103b}, +#endif + {0x103c, pci_vendor_103c, pci_dev_list_103c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103e, pci_vendor_103e, pci_dev_list_103e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103f, pci_vendor_103f, pci_dev_list_103f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1040, pci_vendor_1040, pci_dev_list_1040}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1041, pci_vendor_1041, pci_dev_list_1041}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1042, pci_vendor_1042, pci_dev_list_1042}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1043, pci_vendor_1043, pci_dev_list_1043}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1044, pci_vendor_1044, pci_dev_list_1044}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1045, pci_vendor_1045, pci_dev_list_1045}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1046, pci_vendor_1046, pci_dev_list_1046}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1047, pci_vendor_1047, pci_dev_list_1047}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1048, pci_vendor_1048, pci_dev_list_1048}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1049, pci_vendor_1049, pci_dev_list_1049}, +#endif + {0x104a, pci_vendor_104a, pci_dev_list_104a}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x104b, pci_vendor_104b, pci_dev_list_104b}, +#endif + {0x104c, pci_vendor_104c, pci_dev_list_104c}, + {0x104d, pci_vendor_104d, pci_dev_list_104d}, + {0x104e, pci_vendor_104e, pci_dev_list_104e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x104f, pci_vendor_104f, pci_dev_list_104f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1050, pci_vendor_1050, pci_dev_list_1050}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1051, pci_vendor_1051, pci_dev_list_1051}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1052, pci_vendor_1052, pci_dev_list_1052}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1053, pci_vendor_1053, pci_dev_list_1053}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1054, pci_vendor_1054, pci_dev_list_1054}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1055, pci_vendor_1055, pci_dev_list_1055}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1056, pci_vendor_1056, pci_dev_list_1056}, +#endif + {0x1057, pci_vendor_1057, pci_dev_list_1057}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1058, pci_vendor_1058, pci_dev_list_1058}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1059, pci_vendor_1059, pci_dev_list_1059}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105a, pci_vendor_105a, pci_dev_list_105a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105b, pci_vendor_105b, pci_dev_list_105b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105c, pci_vendor_105c, pci_dev_list_105c}, +#endif + {0x105d, pci_vendor_105d, pci_dev_list_105d}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105e, pci_vendor_105e, pci_dev_list_105e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105f, pci_vendor_105f, pci_dev_list_105f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1060, pci_vendor_1060, pci_dev_list_1060}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1061, pci_vendor_1061, pci_dev_list_1061}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1062, pci_vendor_1062, pci_dev_list_1062}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1063, pci_vendor_1063, pci_dev_list_1063}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1064, pci_vendor_1064, pci_dev_list_1064}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1065, pci_vendor_1065, pci_dev_list_1065}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1066, pci_vendor_1066, pci_dev_list_1066}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1067, pci_vendor_1067, pci_dev_list_1067}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1068, pci_vendor_1068, pci_dev_list_1068}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1069, pci_vendor_1069, pci_dev_list_1069}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106a, pci_vendor_106a, pci_dev_list_106a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106b, pci_vendor_106b, pci_dev_list_106b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106c, pci_vendor_106c, pci_dev_list_106c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106d, pci_vendor_106d, pci_dev_list_106d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106e, pci_vendor_106e, pci_dev_list_106e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106f, pci_vendor_106f, pci_dev_list_106f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1070, pci_vendor_1070, pci_dev_list_1070}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1071, pci_vendor_1071, pci_dev_list_1071}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1072, pci_vendor_1072, pci_dev_list_1072}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1073, pci_vendor_1073, pci_dev_list_1073}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1074, pci_vendor_1074, pci_dev_list_1074}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1075, pci_vendor_1075, pci_dev_list_1075}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1076, pci_vendor_1076, pci_dev_list_1076}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1077, pci_vendor_1077, pci_dev_list_1077}, +#endif + {0x1078, pci_vendor_1078, pci_dev_list_1078}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1079, pci_vendor_1079, pci_dev_list_1079}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107a, pci_vendor_107a, pci_dev_list_107a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107b, pci_vendor_107b, pci_dev_list_107b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107c, pci_vendor_107c, pci_dev_list_107c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107d, pci_vendor_107d, pci_dev_list_107d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107e, pci_vendor_107e, pci_dev_list_107e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107f, pci_vendor_107f, pci_dev_list_107f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1080, pci_vendor_1080, pci_dev_list_1080}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1081, pci_vendor_1081, pci_dev_list_1081}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1082, pci_vendor_1082, pci_dev_list_1082}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1083, pci_vendor_1083, pci_dev_list_1083}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1084, pci_vendor_1084, pci_dev_list_1084}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1085, pci_vendor_1085, pci_dev_list_1085}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1086, pci_vendor_1086, pci_dev_list_1086}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1087, pci_vendor_1087, pci_dev_list_1087}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1088, pci_vendor_1088, pci_dev_list_1088}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1089, pci_vendor_1089, pci_dev_list_1089}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108a, pci_vendor_108a, pci_dev_list_108a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108c, pci_vendor_108c, pci_dev_list_108c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108d, pci_vendor_108d, pci_dev_list_108d}, +#endif + {0x108e, pci_vendor_108e, pci_dev_list_108e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108f, pci_vendor_108f, pci_dev_list_108f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1090, pci_vendor_1090, pci_dev_list_1090}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1091, pci_vendor_1091, pci_dev_list_1091}, +#endif + {0x1092, pci_vendor_1092, pci_dev_list_1092}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1093, pci_vendor_1093, pci_dev_list_1093}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1094, pci_vendor_1094, pci_dev_list_1094}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1095, pci_vendor_1095, pci_dev_list_1095}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1096, pci_vendor_1096, pci_dev_list_1096}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1097, pci_vendor_1097, pci_dev_list_1097}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1098, pci_vendor_1098, pci_dev_list_1098}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1099, pci_vendor_1099, pci_dev_list_1099}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109a, pci_vendor_109a, pci_dev_list_109a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109b, pci_vendor_109b, pci_dev_list_109b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109c, pci_vendor_109c, pci_dev_list_109c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109d, pci_vendor_109d, pci_dev_list_109d}, +#endif + {0x109e, pci_vendor_109e, pci_dev_list_109e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109f, pci_vendor_109f, pci_dev_list_109f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a0, pci_vendor_10a0, pci_dev_list_10a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a1, pci_vendor_10a1, pci_dev_list_10a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a2, pci_vendor_10a2, pci_dev_list_10a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a3, pci_vendor_10a3, pci_dev_list_10a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a4, pci_vendor_10a4, pci_dev_list_10a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a5, pci_vendor_10a5, pci_dev_list_10a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a6, pci_vendor_10a6, pci_dev_list_10a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a7, pci_vendor_10a7, pci_dev_list_10a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a8, pci_vendor_10a8, pci_dev_list_10a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a9, pci_vendor_10a9, pci_dev_list_10a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10aa, pci_vendor_10aa, pci_dev_list_10aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ab, pci_vendor_10ab, pci_dev_list_10ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ac, pci_vendor_10ac, pci_dev_list_10ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ad, pci_vendor_10ad, pci_dev_list_10ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ae, pci_vendor_10ae, pci_dev_list_10ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10af, pci_vendor_10af, pci_dev_list_10af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b0, pci_vendor_10b0, pci_dev_list_10b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b1, pci_vendor_10b1, pci_dev_list_10b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b2, pci_vendor_10b2, pci_dev_list_10b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b3, pci_vendor_10b3, pci_dev_list_10b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b4, pci_vendor_10b4, pci_dev_list_10b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b5, pci_vendor_10b5, pci_dev_list_10b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b6, pci_vendor_10b6, pci_dev_list_10b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b7, pci_vendor_10b7, pci_dev_list_10b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b8, pci_vendor_10b8, pci_dev_list_10b8}, +#endif + {0x10b9, pci_vendor_10b9, pci_dev_list_10b9}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ba, pci_vendor_10ba, pci_dev_list_10ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bb, pci_vendor_10bb, pci_dev_list_10bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bc, pci_vendor_10bc, pci_dev_list_10bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bd, pci_vendor_10bd, pci_dev_list_10bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10be, pci_vendor_10be, pci_dev_list_10be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bf, pci_vendor_10bf, pci_dev_list_10bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c0, pci_vendor_10c0, pci_dev_list_10c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c1, pci_vendor_10c1, pci_dev_list_10c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c2, pci_vendor_10c2, pci_dev_list_10c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c3, pci_vendor_10c3, pci_dev_list_10c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c4, pci_vendor_10c4, pci_dev_list_10c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c5, pci_vendor_10c5, pci_dev_list_10c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c6, pci_vendor_10c6, pci_dev_list_10c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c7, pci_vendor_10c7, pci_dev_list_10c7}, +#endif + {0x10c8, pci_vendor_10c8, pci_dev_list_10c8}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c9, pci_vendor_10c9, pci_dev_list_10c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ca, pci_vendor_10ca, pci_dev_list_10ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cb, pci_vendor_10cb, pci_dev_list_10cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cc, pci_vendor_10cc, pci_dev_list_10cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cd, pci_vendor_10cd, pci_dev_list_10cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ce, pci_vendor_10ce, pci_dev_list_10ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cf, pci_vendor_10cf, pci_dev_list_10cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d0, pci_vendor_10d0, pci_dev_list_10d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d1, pci_vendor_10d1, pci_dev_list_10d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d2, pci_vendor_10d2, pci_dev_list_10d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d3, pci_vendor_10d3, pci_dev_list_10d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d4, pci_vendor_10d4, pci_dev_list_10d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d5, pci_vendor_10d5, pci_dev_list_10d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d6, pci_vendor_10d6, pci_dev_list_10d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d7, pci_vendor_10d7, pci_dev_list_10d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d8, pci_vendor_10d8, pci_dev_list_10d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d9, pci_vendor_10d9, pci_dev_list_10d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10da, pci_vendor_10da, pci_dev_list_10da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10db, pci_vendor_10db, pci_dev_list_10db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10dc, pci_vendor_10dc, pci_dev_list_10dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10dd, pci_vendor_10dd, pci_dev_list_10dd}, +#endif + {0x10de, pci_vendor_10de, pci_dev_list_10de}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10df, pci_vendor_10df, pci_dev_list_10df}, +#endif + {0x10e0, pci_vendor_10e0, pci_dev_list_10e0}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e1, pci_vendor_10e1, pci_dev_list_10e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e2, pci_vendor_10e2, pci_dev_list_10e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e3, pci_vendor_10e3, pci_dev_list_10e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e4, pci_vendor_10e4, pci_dev_list_10e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e5, pci_vendor_10e5, pci_dev_list_10e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e6, pci_vendor_10e6, pci_dev_list_10e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e7, pci_vendor_10e7, pci_dev_list_10e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e8, pci_vendor_10e8, pci_dev_list_10e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e9, pci_vendor_10e9, pci_dev_list_10e9}, +#endif + {0x10ea, pci_vendor_10ea, pci_dev_list_10ea}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10eb, pci_vendor_10eb, pci_dev_list_10eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ec, pci_vendor_10ec, pci_dev_list_10ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ed, pci_vendor_10ed, pci_dev_list_10ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ee, pci_vendor_10ee, pci_dev_list_10ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ef, pci_vendor_10ef, pci_dev_list_10ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f0, pci_vendor_10f0, pci_dev_list_10f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f1, pci_vendor_10f1, pci_dev_list_10f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f2, pci_vendor_10f2, pci_dev_list_10f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f3, pci_vendor_10f3, pci_dev_list_10f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f4, pci_vendor_10f4, pci_dev_list_10f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f5, pci_vendor_10f5, pci_dev_list_10f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f6, pci_vendor_10f6, pci_dev_list_10f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f7, pci_vendor_10f7, pci_dev_list_10f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f8, pci_vendor_10f8, pci_dev_list_10f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f9, pci_vendor_10f9, pci_dev_list_10f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fa, pci_vendor_10fa, pci_dev_list_10fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fb, pci_vendor_10fb, pci_dev_list_10fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fc, pci_vendor_10fc, pci_dev_list_10fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fd, pci_vendor_10fd, pci_dev_list_10fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fe, pci_vendor_10fe, pci_dev_list_10fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ff, pci_vendor_10ff, pci_dev_list_10ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1100, pci_vendor_1100, pci_dev_list_1100}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1101, pci_vendor_1101, pci_dev_list_1101}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1102, pci_vendor_1102, pci_dev_list_1102}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1103, pci_vendor_1103, pci_dev_list_1103}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1104, pci_vendor_1104, pci_dev_list_1104}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1105, pci_vendor_1105, pci_dev_list_1105}, +#endif + {0x1106, pci_vendor_1106, pci_dev_list_1106}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1107, pci_vendor_1107, pci_dev_list_1107}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1108, pci_vendor_1108, pci_dev_list_1108}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1109, pci_vendor_1109, pci_dev_list_1109}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110a, pci_vendor_110a, pci_dev_list_110a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110b, pci_vendor_110b, pci_dev_list_110b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110c, pci_vendor_110c, pci_dev_list_110c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110d, pci_vendor_110d, pci_dev_list_110d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110e, pci_vendor_110e, pci_dev_list_110e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110f, pci_vendor_110f, pci_dev_list_110f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1110, pci_vendor_1110, pci_dev_list_1110}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1111, pci_vendor_1111, pci_dev_list_1111}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1112, pci_vendor_1112, pci_dev_list_1112}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1113, pci_vendor_1113, pci_dev_list_1113}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1114, pci_vendor_1114, pci_dev_list_1114}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1115, pci_vendor_1115, pci_dev_list_1115}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1116, pci_vendor_1116, pci_dev_list_1116}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1117, pci_vendor_1117, pci_dev_list_1117}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1118, pci_vendor_1118, pci_dev_list_1118}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1119, pci_vendor_1119, pci_dev_list_1119}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111a, pci_vendor_111a, pci_dev_list_111a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111b, pci_vendor_111b, pci_dev_list_111b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111c, pci_vendor_111c, pci_dev_list_111c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111d, pci_vendor_111d, pci_dev_list_111d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111e, pci_vendor_111e, pci_dev_list_111e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111f, pci_vendor_111f, pci_dev_list_111f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1120, pci_vendor_1120, pci_dev_list_1120}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1121, pci_vendor_1121, pci_dev_list_1121}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1122, pci_vendor_1122, pci_dev_list_1122}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1123, pci_vendor_1123, pci_dev_list_1123}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1124, pci_vendor_1124, pci_dev_list_1124}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1125, pci_vendor_1125, pci_dev_list_1125}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1126, pci_vendor_1126, pci_dev_list_1126}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1127, pci_vendor_1127, pci_dev_list_1127}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1129, pci_vendor_1129, pci_dev_list_1129}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112a, pci_vendor_112a, pci_dev_list_112a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112b, pci_vendor_112b, pci_dev_list_112b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112c, pci_vendor_112c, pci_dev_list_112c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112d, pci_vendor_112d, pci_dev_list_112d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112e, pci_vendor_112e, pci_dev_list_112e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112f, pci_vendor_112f, pci_dev_list_112f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1130, pci_vendor_1130, pci_dev_list_1130}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1131, pci_vendor_1131, pci_dev_list_1131}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1132, pci_vendor_1132, pci_dev_list_1132}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1133, pci_vendor_1133, pci_dev_list_1133}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1134, pci_vendor_1134, pci_dev_list_1134}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1135, pci_vendor_1135, pci_dev_list_1135}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1136, pci_vendor_1136, pci_dev_list_1136}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1137, pci_vendor_1137, pci_dev_list_1137}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1138, pci_vendor_1138, pci_dev_list_1138}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1139, pci_vendor_1139, pci_dev_list_1139}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113a, pci_vendor_113a, pci_dev_list_113a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113b, pci_vendor_113b, pci_dev_list_113b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113c, pci_vendor_113c, pci_dev_list_113c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113d, pci_vendor_113d, pci_dev_list_113d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113e, pci_vendor_113e, pci_dev_list_113e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113f, pci_vendor_113f, pci_dev_list_113f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1140, pci_vendor_1140, pci_dev_list_1140}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1141, pci_vendor_1141, pci_dev_list_1141}, +#endif + {0x1142, pci_vendor_1142, pci_dev_list_1142}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1143, pci_vendor_1143, pci_dev_list_1143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1144, pci_vendor_1144, pci_dev_list_1144}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1145, pci_vendor_1145, pci_dev_list_1145}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1146, pci_vendor_1146, pci_dev_list_1146}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1147, pci_vendor_1147, pci_dev_list_1147}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1148, pci_vendor_1148, pci_dev_list_1148}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1149, pci_vendor_1149, pci_dev_list_1149}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114a, pci_vendor_114a, pci_dev_list_114a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114b, pci_vendor_114b, pci_dev_list_114b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114c, pci_vendor_114c, pci_dev_list_114c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114d, pci_vendor_114d, pci_dev_list_114d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114e, pci_vendor_114e, pci_dev_list_114e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114f, pci_vendor_114f, pci_dev_list_114f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1150, pci_vendor_1150, pci_dev_list_1150}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1151, pci_vendor_1151, pci_dev_list_1151}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1152, pci_vendor_1152, pci_dev_list_1152}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1153, pci_vendor_1153, pci_dev_list_1153}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1154, pci_vendor_1154, pci_dev_list_1154}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1155, pci_vendor_1155, pci_dev_list_1155}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1156, pci_vendor_1156, pci_dev_list_1156}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1157, pci_vendor_1157, pci_dev_list_1157}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1158, pci_vendor_1158, pci_dev_list_1158}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1159, pci_vendor_1159, pci_dev_list_1159}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115a, pci_vendor_115a, pci_dev_list_115a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115b, pci_vendor_115b, pci_dev_list_115b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115c, pci_vendor_115c, pci_dev_list_115c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115d, pci_vendor_115d, pci_dev_list_115d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115e, pci_vendor_115e, pci_dev_list_115e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115f, pci_vendor_115f, pci_dev_list_115f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1160, pci_vendor_1160, pci_dev_list_1160}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1161, pci_vendor_1161, pci_dev_list_1161}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1162, pci_vendor_1162, pci_dev_list_1162}, +#endif + {0x1163, pci_vendor_1163, pci_dev_list_1163}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1164, pci_vendor_1164, pci_dev_list_1164}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1165, pci_vendor_1165, pci_dev_list_1165}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1166, pci_vendor_1166, pci_dev_list_1166}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1167, pci_vendor_1167, pci_dev_list_1167}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1168, pci_vendor_1168, pci_dev_list_1168}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1169, pci_vendor_1169, pci_dev_list_1169}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116a, pci_vendor_116a, pci_dev_list_116a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116b, pci_vendor_116b, pci_dev_list_116b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116c, pci_vendor_116c, pci_dev_list_116c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116d, pci_vendor_116d, pci_dev_list_116d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116e, pci_vendor_116e, pci_dev_list_116e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116f, pci_vendor_116f, pci_dev_list_116f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1170, pci_vendor_1170, pci_dev_list_1170}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1171, pci_vendor_1171, pci_dev_list_1171}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1172, pci_vendor_1172, pci_dev_list_1172}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1173, pci_vendor_1173, pci_dev_list_1173}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1174, pci_vendor_1174, pci_dev_list_1174}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1175, pci_vendor_1175, pci_dev_list_1175}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1176, pci_vendor_1176, pci_dev_list_1176}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1177, pci_vendor_1177, pci_dev_list_1177}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1178, pci_vendor_1178, pci_dev_list_1178}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1179, pci_vendor_1179, pci_dev_list_1179}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117a, pci_vendor_117a, pci_dev_list_117a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117b, pci_vendor_117b, pci_dev_list_117b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117c, pci_vendor_117c, pci_dev_list_117c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117d, pci_vendor_117d, pci_dev_list_117d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117e, pci_vendor_117e, pci_dev_list_117e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117f, pci_vendor_117f, pci_dev_list_117f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1180, pci_vendor_1180, pci_dev_list_1180}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1181, pci_vendor_1181, pci_dev_list_1181}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1183, pci_vendor_1183, pci_dev_list_1183}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1184, pci_vendor_1184, pci_dev_list_1184}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1185, pci_vendor_1185, pci_dev_list_1185}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1186, pci_vendor_1186, pci_dev_list_1186}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1187, pci_vendor_1187, pci_dev_list_1187}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1188, pci_vendor_1188, pci_dev_list_1188}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1189, pci_vendor_1189, pci_dev_list_1189}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118a, pci_vendor_118a, pci_dev_list_118a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118b, pci_vendor_118b, pci_dev_list_118b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118c, pci_vendor_118c, pci_dev_list_118c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118d, pci_vendor_118d, pci_dev_list_118d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118e, pci_vendor_118e, pci_dev_list_118e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118f, pci_vendor_118f, pci_dev_list_118f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1190, pci_vendor_1190, pci_dev_list_1190}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1191, pci_vendor_1191, pci_dev_list_1191}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1192, pci_vendor_1192, pci_dev_list_1192}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1193, pci_vendor_1193, pci_dev_list_1193}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1194, pci_vendor_1194, pci_dev_list_1194}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1195, pci_vendor_1195, pci_dev_list_1195}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1196, pci_vendor_1196, pci_dev_list_1196}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1197, pci_vendor_1197, pci_dev_list_1197}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1198, pci_vendor_1198, pci_dev_list_1198}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1199, pci_vendor_1199, pci_dev_list_1199}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119a, pci_vendor_119a, pci_dev_list_119a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119b, pci_vendor_119b, pci_dev_list_119b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119c, pci_vendor_119c, pci_dev_list_119c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119d, pci_vendor_119d, pci_dev_list_119d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119e, pci_vendor_119e, pci_dev_list_119e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119f, pci_vendor_119f, pci_dev_list_119f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a0, pci_vendor_11a0, pci_dev_list_11a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a1, pci_vendor_11a1, pci_dev_list_11a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a2, pci_vendor_11a2, pci_dev_list_11a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a3, pci_vendor_11a3, pci_dev_list_11a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a4, pci_vendor_11a4, pci_dev_list_11a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a5, pci_vendor_11a5, pci_dev_list_11a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a6, pci_vendor_11a6, pci_dev_list_11a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a7, pci_vendor_11a7, pci_dev_list_11a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a8, pci_vendor_11a8, pci_dev_list_11a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a9, pci_vendor_11a9, pci_dev_list_11a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11aa, pci_vendor_11aa, pci_dev_list_11aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ab, pci_vendor_11ab, pci_dev_list_11ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ac, pci_vendor_11ac, pci_dev_list_11ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ad, pci_vendor_11ad, pci_dev_list_11ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ae, pci_vendor_11ae, pci_dev_list_11ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11af, pci_vendor_11af, pci_dev_list_11af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b0, pci_vendor_11b0, pci_dev_list_11b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b1, pci_vendor_11b1, pci_dev_list_11b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b2, pci_vendor_11b2, pci_dev_list_11b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b3, pci_vendor_11b3, pci_dev_list_11b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b4, pci_vendor_11b4, pci_dev_list_11b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b5, pci_vendor_11b5, pci_dev_list_11b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b6, pci_vendor_11b6, pci_dev_list_11b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b7, pci_vendor_11b7, pci_dev_list_11b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b8, pci_vendor_11b8, pci_dev_list_11b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b9, pci_vendor_11b9, pci_dev_list_11b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ba, pci_vendor_11ba, pci_dev_list_11ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bb, pci_vendor_11bb, pci_dev_list_11bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bc, pci_vendor_11bc, pci_dev_list_11bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bd, pci_vendor_11bd, pci_dev_list_11bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11be, pci_vendor_11be, pci_dev_list_11be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bf, pci_vendor_11bf, pci_dev_list_11bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c0, pci_vendor_11c0, pci_dev_list_11c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c1, pci_vendor_11c1, pci_dev_list_11c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c2, pci_vendor_11c2, pci_dev_list_11c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c3, pci_vendor_11c3, pci_dev_list_11c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c4, pci_vendor_11c4, pci_dev_list_11c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c5, pci_vendor_11c5, pci_dev_list_11c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c6, pci_vendor_11c6, pci_dev_list_11c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c7, pci_vendor_11c7, pci_dev_list_11c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c8, pci_vendor_11c8, pci_dev_list_11c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c9, pci_vendor_11c9, pci_dev_list_11c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ca, pci_vendor_11ca, pci_dev_list_11ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cb, pci_vendor_11cb, pci_dev_list_11cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cc, pci_vendor_11cc, pci_dev_list_11cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cd, pci_vendor_11cd, pci_dev_list_11cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ce, pci_vendor_11ce, pci_dev_list_11ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cf, pci_vendor_11cf, pci_dev_list_11cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d0, pci_vendor_11d0, pci_dev_list_11d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d1, pci_vendor_11d1, pci_dev_list_11d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d2, pci_vendor_11d2, pci_dev_list_11d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d3, pci_vendor_11d3, pci_dev_list_11d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d4, pci_vendor_11d4, pci_dev_list_11d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d5, pci_vendor_11d5, pci_dev_list_11d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d6, pci_vendor_11d6, pci_dev_list_11d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d7, pci_vendor_11d7, pci_dev_list_11d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d8, pci_vendor_11d8, pci_dev_list_11d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d9, pci_vendor_11d9, pci_dev_list_11d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11da, pci_vendor_11da, pci_dev_list_11da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11db, pci_vendor_11db, pci_dev_list_11db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11dc, pci_vendor_11dc, pci_dev_list_11dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11dd, pci_vendor_11dd, pci_dev_list_11dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11de, pci_vendor_11de, pci_dev_list_11de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11df, pci_vendor_11df, pci_dev_list_11df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e0, pci_vendor_11e0, pci_dev_list_11e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e1, pci_vendor_11e1, pci_dev_list_11e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e2, pci_vendor_11e2, pci_dev_list_11e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e3, pci_vendor_11e3, pci_dev_list_11e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e4, pci_vendor_11e4, pci_dev_list_11e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e5, pci_vendor_11e5, pci_dev_list_11e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e6, pci_vendor_11e6, pci_dev_list_11e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e7, pci_vendor_11e7, pci_dev_list_11e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e8, pci_vendor_11e8, pci_dev_list_11e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e9, pci_vendor_11e9, pci_dev_list_11e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ea, pci_vendor_11ea, pci_dev_list_11ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11eb, pci_vendor_11eb, pci_dev_list_11eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ec, pci_vendor_11ec, pci_dev_list_11ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ed, pci_vendor_11ed, pci_dev_list_11ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ee, pci_vendor_11ee, pci_dev_list_11ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ef, pci_vendor_11ef, pci_dev_list_11ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f0, pci_vendor_11f0, pci_dev_list_11f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f1, pci_vendor_11f1, pci_dev_list_11f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f2, pci_vendor_11f2, pci_dev_list_11f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f3, pci_vendor_11f3, pci_dev_list_11f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f4, pci_vendor_11f4, pci_dev_list_11f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f5, pci_vendor_11f5, pci_dev_list_11f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f6, pci_vendor_11f6, pci_dev_list_11f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f7, pci_vendor_11f7, pci_dev_list_11f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f8, pci_vendor_11f8, pci_dev_list_11f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f9, pci_vendor_11f9, pci_dev_list_11f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fa, pci_vendor_11fa, pci_dev_list_11fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fb, pci_vendor_11fb, pci_dev_list_11fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fc, pci_vendor_11fc, pci_dev_list_11fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fd, pci_vendor_11fd, pci_dev_list_11fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fe, pci_vendor_11fe, pci_dev_list_11fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ff, pci_vendor_11ff, pci_dev_list_11ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1200, pci_vendor_1200, pci_dev_list_1200}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1201, pci_vendor_1201, pci_dev_list_1201}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1202, pci_vendor_1202, pci_dev_list_1202}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1203, pci_vendor_1203, pci_dev_list_1203}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1204, pci_vendor_1204, pci_dev_list_1204}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1205, pci_vendor_1205, pci_dev_list_1205}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1206, pci_vendor_1206, pci_dev_list_1206}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1208, pci_vendor_1208, pci_dev_list_1208}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1209, pci_vendor_1209, pci_dev_list_1209}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120a, pci_vendor_120a, pci_dev_list_120a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120b, pci_vendor_120b, pci_dev_list_120b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120c, pci_vendor_120c, pci_dev_list_120c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120d, pci_vendor_120d, pci_dev_list_120d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120e, pci_vendor_120e, pci_dev_list_120e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120f, pci_vendor_120f, pci_dev_list_120f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1210, pci_vendor_1210, pci_dev_list_1210}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1211, pci_vendor_1211, pci_dev_list_1211}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1212, pci_vendor_1212, pci_dev_list_1212}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1213, pci_vendor_1213, pci_dev_list_1213}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1214, pci_vendor_1214, pci_dev_list_1214}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1215, pci_vendor_1215, pci_dev_list_1215}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1216, pci_vendor_1216, pci_dev_list_1216}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1217, pci_vendor_1217, pci_dev_list_1217}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1218, pci_vendor_1218, pci_dev_list_1218}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1219, pci_vendor_1219, pci_dev_list_1219}, +#endif + {0x121a, pci_vendor_121a, pci_dev_list_121a}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121b, pci_vendor_121b, pci_dev_list_121b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121c, pci_vendor_121c, pci_dev_list_121c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121d, pci_vendor_121d, pci_dev_list_121d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121e, pci_vendor_121e, pci_dev_list_121e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121f, pci_vendor_121f, pci_dev_list_121f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1220, pci_vendor_1220, pci_dev_list_1220}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1221, pci_vendor_1221, pci_dev_list_1221}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1222, pci_vendor_1222, pci_dev_list_1222}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1223, pci_vendor_1223, pci_dev_list_1223}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1224, pci_vendor_1224, pci_dev_list_1224}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1225, pci_vendor_1225, pci_dev_list_1225}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1227, pci_vendor_1227, pci_dev_list_1227}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1228, pci_vendor_1228, pci_dev_list_1228}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1229, pci_vendor_1229, pci_dev_list_1229}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122a, pci_vendor_122a, pci_dev_list_122a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122b, pci_vendor_122b, pci_dev_list_122b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122c, pci_vendor_122c, pci_dev_list_122c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122d, pci_vendor_122d, pci_dev_list_122d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122e, pci_vendor_122e, pci_dev_list_122e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122f, pci_vendor_122f, pci_dev_list_122f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1230, pci_vendor_1230, pci_dev_list_1230}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1231, pci_vendor_1231, pci_dev_list_1231}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1232, pci_vendor_1232, pci_dev_list_1232}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1233, pci_vendor_1233, pci_dev_list_1233}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1234, pci_vendor_1234, pci_dev_list_1234}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1235, pci_vendor_1235, pci_dev_list_1235}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1236, pci_vendor_1236, pci_dev_list_1236}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1237, pci_vendor_1237, pci_dev_list_1237}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1238, pci_vendor_1238, pci_dev_list_1238}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1239, pci_vendor_1239, pci_dev_list_1239}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123a, pci_vendor_123a, pci_dev_list_123a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123b, pci_vendor_123b, pci_dev_list_123b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123c, pci_vendor_123c, pci_dev_list_123c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123d, pci_vendor_123d, pci_dev_list_123d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123e, pci_vendor_123e, pci_dev_list_123e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123f, pci_vendor_123f, pci_dev_list_123f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1240, pci_vendor_1240, pci_dev_list_1240}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1241, pci_vendor_1241, pci_dev_list_1241}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1242, pci_vendor_1242, pci_dev_list_1242}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1243, pci_vendor_1243, pci_dev_list_1243}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1244, pci_vendor_1244, pci_dev_list_1244}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1245, pci_vendor_1245, pci_dev_list_1245}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1246, pci_vendor_1246, pci_dev_list_1246}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1247, pci_vendor_1247, pci_dev_list_1247}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1248, pci_vendor_1248, pci_dev_list_1248}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1249, pci_vendor_1249, pci_dev_list_1249}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124a, pci_vendor_124a, pci_dev_list_124a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124b, pci_vendor_124b, pci_dev_list_124b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124c, pci_vendor_124c, pci_dev_list_124c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124d, pci_vendor_124d, pci_dev_list_124d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124e, pci_vendor_124e, pci_dev_list_124e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124f, pci_vendor_124f, pci_dev_list_124f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1250, pci_vendor_1250, pci_dev_list_1250}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1251, pci_vendor_1251, pci_dev_list_1251}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1253, pci_vendor_1253, pci_dev_list_1253}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1254, pci_vendor_1254, pci_dev_list_1254}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1255, pci_vendor_1255, pci_dev_list_1255}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1256, pci_vendor_1256, pci_dev_list_1256}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1257, pci_vendor_1257, pci_dev_list_1257}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1258, pci_vendor_1258, pci_dev_list_1258}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1259, pci_vendor_1259, pci_dev_list_1259}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125a, pci_vendor_125a, pci_dev_list_125a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125b, pci_vendor_125b, pci_dev_list_125b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125c, pci_vendor_125c, pci_dev_list_125c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125d, pci_vendor_125d, pci_dev_list_125d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125e, pci_vendor_125e, pci_dev_list_125e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125f, pci_vendor_125f, pci_dev_list_125f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1260, pci_vendor_1260, pci_dev_list_1260}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1261, pci_vendor_1261, pci_dev_list_1261}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1262, pci_vendor_1262, pci_dev_list_1262}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1263, pci_vendor_1263, pci_dev_list_1263}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1264, pci_vendor_1264, pci_dev_list_1264}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1265, pci_vendor_1265, pci_dev_list_1265}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1266, pci_vendor_1266, pci_dev_list_1266}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1267, pci_vendor_1267, pci_dev_list_1267}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1268, pci_vendor_1268, pci_dev_list_1268}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1269, pci_vendor_1269, pci_dev_list_1269}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126a, pci_vendor_126a, pci_dev_list_126a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126b, pci_vendor_126b, pci_dev_list_126b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126c, pci_vendor_126c, pci_dev_list_126c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126d, pci_vendor_126d, pci_dev_list_126d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126e, pci_vendor_126e, pci_dev_list_126e}, +#endif + {0x126f, pci_vendor_126f, pci_dev_list_126f}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1270, pci_vendor_1270, pci_dev_list_1270}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1271, pci_vendor_1271, pci_dev_list_1271}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1272, pci_vendor_1272, pci_dev_list_1272}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1273, pci_vendor_1273, pci_dev_list_1273}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1274, pci_vendor_1274, pci_dev_list_1274}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1275, pci_vendor_1275, pci_dev_list_1275}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1276, pci_vendor_1276, pci_dev_list_1276}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1277, pci_vendor_1277, pci_dev_list_1277}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1278, pci_vendor_1278, pci_dev_list_1278}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1279, pci_vendor_1279, pci_dev_list_1279}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127a, pci_vendor_127a, pci_dev_list_127a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127b, pci_vendor_127b, pci_dev_list_127b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127c, pci_vendor_127c, pci_dev_list_127c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127d, pci_vendor_127d, pci_dev_list_127d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127e, pci_vendor_127e, pci_dev_list_127e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127f, pci_vendor_127f, pci_dev_list_127f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1280, pci_vendor_1280, pci_dev_list_1280}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1281, pci_vendor_1281, pci_dev_list_1281}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1282, pci_vendor_1282, pci_dev_list_1282}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1283, pci_vendor_1283, pci_dev_list_1283}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1284, pci_vendor_1284, pci_dev_list_1284}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1285, pci_vendor_1285, pci_dev_list_1285}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1286, pci_vendor_1286, pci_dev_list_1286}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1287, pci_vendor_1287, pci_dev_list_1287}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1288, pci_vendor_1288, pci_dev_list_1288}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1289, pci_vendor_1289, pci_dev_list_1289}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128a, pci_vendor_128a, pci_dev_list_128a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128b, pci_vendor_128b, pci_dev_list_128b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128c, pci_vendor_128c, pci_dev_list_128c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128d, pci_vendor_128d, pci_dev_list_128d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128e, pci_vendor_128e, pci_dev_list_128e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128f, pci_vendor_128f, pci_dev_list_128f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1290, pci_vendor_1290, pci_dev_list_1290}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1291, pci_vendor_1291, pci_dev_list_1291}, +#endif + {0x1292, pci_vendor_1292, pci_dev_list_1292}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1293, pci_vendor_1293, pci_dev_list_1293}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1294, pci_vendor_1294, pci_dev_list_1294}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1295, pci_vendor_1295, pci_dev_list_1295}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1296, pci_vendor_1296, pci_dev_list_1296}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1297, pci_vendor_1297, pci_dev_list_1297}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1298, pci_vendor_1298, pci_dev_list_1298}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1299, pci_vendor_1299, pci_dev_list_1299}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129a, pci_vendor_129a, pci_dev_list_129a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129b, pci_vendor_129b, pci_dev_list_129b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129c, pci_vendor_129c, pci_dev_list_129c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129d, pci_vendor_129d, pci_dev_list_129d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129e, pci_vendor_129e, pci_dev_list_129e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129f, pci_vendor_129f, pci_dev_list_129f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a0, pci_vendor_12a0, pci_dev_list_12a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a1, pci_vendor_12a1, pci_dev_list_12a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a2, pci_vendor_12a2, pci_dev_list_12a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a3, pci_vendor_12a3, pci_dev_list_12a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a4, pci_vendor_12a4, pci_dev_list_12a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a5, pci_vendor_12a5, pci_dev_list_12a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a6, pci_vendor_12a6, pci_dev_list_12a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a7, pci_vendor_12a7, pci_dev_list_12a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a8, pci_vendor_12a8, pci_dev_list_12a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a9, pci_vendor_12a9, pci_dev_list_12a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12aa, pci_vendor_12aa, pci_dev_list_12aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ab, pci_vendor_12ab, pci_dev_list_12ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ac, pci_vendor_12ac, pci_dev_list_12ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ad, pci_vendor_12ad, pci_dev_list_12ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ae, pci_vendor_12ae, pci_dev_list_12ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12af, pci_vendor_12af, pci_dev_list_12af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b0, pci_vendor_12b0, pci_dev_list_12b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b1, pci_vendor_12b1, pci_dev_list_12b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b2, pci_vendor_12b2, pci_dev_list_12b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b3, pci_vendor_12b3, pci_dev_list_12b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b4, pci_vendor_12b4, pci_dev_list_12b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b5, pci_vendor_12b5, pci_dev_list_12b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b6, pci_vendor_12b6, pci_dev_list_12b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b7, pci_vendor_12b7, pci_dev_list_12b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b8, pci_vendor_12b8, pci_dev_list_12b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b9, pci_vendor_12b9, pci_dev_list_12b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ba, pci_vendor_12ba, pci_dev_list_12ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bb, pci_vendor_12bb, pci_dev_list_12bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bc, pci_vendor_12bc, pci_dev_list_12bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bd, pci_vendor_12bd, pci_dev_list_12bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12be, pci_vendor_12be, pci_dev_list_12be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bf, pci_vendor_12bf, pci_dev_list_12bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c0, pci_vendor_12c0, pci_dev_list_12c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c1, pci_vendor_12c1, pci_dev_list_12c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c2, pci_vendor_12c2, pci_dev_list_12c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c3, pci_vendor_12c3, pci_dev_list_12c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c4, pci_vendor_12c4, pci_dev_list_12c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c5, pci_vendor_12c5, pci_dev_list_12c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c6, pci_vendor_12c6, pci_dev_list_12c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c7, pci_vendor_12c7, pci_dev_list_12c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c8, pci_vendor_12c8, pci_dev_list_12c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c9, pci_vendor_12c9, pci_dev_list_12c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ca, pci_vendor_12ca, pci_dev_list_12ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cb, pci_vendor_12cb, pci_dev_list_12cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cc, pci_vendor_12cc, pci_dev_list_12cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cd, pci_vendor_12cd, pci_dev_list_12cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ce, pci_vendor_12ce, pci_dev_list_12ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cf, pci_vendor_12cf, pci_dev_list_12cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d0, pci_vendor_12d0, pci_dev_list_12d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d1, pci_vendor_12d1, pci_dev_list_12d1}, +#endif + {0x12d2, pci_vendor_12d2, pci_dev_list_12d2}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d3, pci_vendor_12d3, pci_dev_list_12d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d4, pci_vendor_12d4, pci_dev_list_12d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d5, pci_vendor_12d5, pci_dev_list_12d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d6, pci_vendor_12d6, pci_dev_list_12d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d7, pci_vendor_12d7, pci_dev_list_12d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d8, pci_vendor_12d8, pci_dev_list_12d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d9, pci_vendor_12d9, pci_dev_list_12d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12da, pci_vendor_12da, pci_dev_list_12da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12db, pci_vendor_12db, pci_dev_list_12db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12dc, pci_vendor_12dc, pci_dev_list_12dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12dd, pci_vendor_12dd, pci_dev_list_12dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12de, pci_vendor_12de, pci_dev_list_12de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12df, pci_vendor_12df, pci_dev_list_12df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e0, pci_vendor_12e0, pci_dev_list_12e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e1, pci_vendor_12e1, pci_dev_list_12e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e2, pci_vendor_12e2, pci_dev_list_12e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e3, pci_vendor_12e3, pci_dev_list_12e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e4, pci_vendor_12e4, pci_dev_list_12e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e5, pci_vendor_12e5, pci_dev_list_12e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e6, pci_vendor_12e6, pci_dev_list_12e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e7, pci_vendor_12e7, pci_dev_list_12e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e8, pci_vendor_12e8, pci_dev_list_12e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e9, pci_vendor_12e9, pci_dev_list_12e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ea, pci_vendor_12ea, pci_dev_list_12ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12eb, pci_vendor_12eb, pci_dev_list_12eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ec, pci_vendor_12ec, pci_dev_list_12ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ed, pci_vendor_12ed, pci_dev_list_12ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ee, pci_vendor_12ee, pci_dev_list_12ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ef, pci_vendor_12ef, pci_dev_list_12ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f0, pci_vendor_12f0, pci_dev_list_12f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f1, pci_vendor_12f1, pci_dev_list_12f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f2, pci_vendor_12f2, pci_dev_list_12f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f3, pci_vendor_12f3, pci_dev_list_12f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f4, pci_vendor_12f4, pci_dev_list_12f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f5, pci_vendor_12f5, pci_dev_list_12f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f6, pci_vendor_12f6, pci_dev_list_12f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f7, pci_vendor_12f7, pci_dev_list_12f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f8, pci_vendor_12f8, pci_dev_list_12f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f9, pci_vendor_12f9, pci_dev_list_12f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fb, pci_vendor_12fb, pci_dev_list_12fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fc, pci_vendor_12fc, pci_dev_list_12fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fd, pci_vendor_12fd, pci_dev_list_12fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fe, pci_vendor_12fe, pci_dev_list_12fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ff, pci_vendor_12ff, pci_dev_list_12ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1300, pci_vendor_1300, pci_dev_list_1300}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1302, pci_vendor_1302, pci_dev_list_1302}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1303, pci_vendor_1303, pci_dev_list_1303}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1304, pci_vendor_1304, pci_dev_list_1304}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1305, pci_vendor_1305, pci_dev_list_1305}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1306, pci_vendor_1306, pci_dev_list_1306}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1307, pci_vendor_1307, pci_dev_list_1307}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1308, pci_vendor_1308, pci_dev_list_1308}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1309, pci_vendor_1309, pci_dev_list_1309}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130a, pci_vendor_130a, pci_dev_list_130a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130b, pci_vendor_130b, pci_dev_list_130b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130c, pci_vendor_130c, pci_dev_list_130c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130d, pci_vendor_130d, pci_dev_list_130d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130e, pci_vendor_130e, pci_dev_list_130e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130f, pci_vendor_130f, pci_dev_list_130f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1310, pci_vendor_1310, pci_dev_list_1310}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1311, pci_vendor_1311, pci_dev_list_1311}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1312, pci_vendor_1312, pci_dev_list_1312}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1313, pci_vendor_1313, pci_dev_list_1313}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1316, pci_vendor_1316, pci_dev_list_1316}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1317, pci_vendor_1317, pci_dev_list_1317}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1318, pci_vendor_1318, pci_dev_list_1318}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1319, pci_vendor_1319, pci_dev_list_1319}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131a, pci_vendor_131a, pci_dev_list_131a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131c, pci_vendor_131c, pci_dev_list_131c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131d, pci_vendor_131d, pci_dev_list_131d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131e, pci_vendor_131e, pci_dev_list_131e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131f, pci_vendor_131f, pci_dev_list_131f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1320, pci_vendor_1320, pci_dev_list_1320}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1321, pci_vendor_1321, pci_dev_list_1321}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1322, pci_vendor_1322, pci_dev_list_1322}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1323, pci_vendor_1323, pci_dev_list_1323}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1324, pci_vendor_1324, pci_dev_list_1324}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1325, pci_vendor_1325, pci_dev_list_1325}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1326, pci_vendor_1326, pci_dev_list_1326}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1327, pci_vendor_1327, pci_dev_list_1327}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1328, pci_vendor_1328, pci_dev_list_1328}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1329, pci_vendor_1329, pci_dev_list_1329}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132a, pci_vendor_132a, pci_dev_list_132a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132b, pci_vendor_132b, pci_dev_list_132b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132c, pci_vendor_132c, pci_dev_list_132c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132d, pci_vendor_132d, pci_dev_list_132d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1330, pci_vendor_1330, pci_dev_list_1330}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1331, pci_vendor_1331, pci_dev_list_1331}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1332, pci_vendor_1332, pci_dev_list_1332}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1334, pci_vendor_1334, pci_dev_list_1334}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1335, pci_vendor_1335, pci_dev_list_1335}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1337, pci_vendor_1337, pci_dev_list_1337}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1338, pci_vendor_1338, pci_dev_list_1338}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133a, pci_vendor_133a, pci_dev_list_133a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133b, pci_vendor_133b, pci_dev_list_133b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133c, pci_vendor_133c, pci_dev_list_133c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133d, pci_vendor_133d, pci_dev_list_133d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133e, pci_vendor_133e, pci_dev_list_133e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133f, pci_vendor_133f, pci_dev_list_133f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1340, pci_vendor_1340, pci_dev_list_1340}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1341, pci_vendor_1341, pci_dev_list_1341}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1342, pci_vendor_1342, pci_dev_list_1342}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1343, pci_vendor_1343, pci_dev_list_1343}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1344, pci_vendor_1344, pci_dev_list_1344}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1345, pci_vendor_1345, pci_dev_list_1345}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1347, pci_vendor_1347, pci_dev_list_1347}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1349, pci_vendor_1349, pci_dev_list_1349}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134a, pci_vendor_134a, pci_dev_list_134a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134b, pci_vendor_134b, pci_dev_list_134b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134c, pci_vendor_134c, pci_dev_list_134c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134d, pci_vendor_134d, pci_dev_list_134d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134e, pci_vendor_134e, pci_dev_list_134e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134f, pci_vendor_134f, pci_dev_list_134f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1350, pci_vendor_1350, pci_dev_list_1350}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1351, pci_vendor_1351, pci_dev_list_1351}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1353, pci_vendor_1353, pci_dev_list_1353}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1354, pci_vendor_1354, pci_dev_list_1354}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1355, pci_vendor_1355, pci_dev_list_1355}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1356, pci_vendor_1356, pci_dev_list_1356}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1359, pci_vendor_1359, pci_dev_list_1359}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135a, pci_vendor_135a, pci_dev_list_135a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135b, pci_vendor_135b, pci_dev_list_135b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135c, pci_vendor_135c, pci_dev_list_135c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135d, pci_vendor_135d, pci_dev_list_135d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135e, pci_vendor_135e, pci_dev_list_135e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135f, pci_vendor_135f, pci_dev_list_135f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1360, pci_vendor_1360, pci_dev_list_1360}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1361, pci_vendor_1361, pci_dev_list_1361}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1362, pci_vendor_1362, pci_dev_list_1362}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1363, pci_vendor_1363, pci_dev_list_1363}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1364, pci_vendor_1364, pci_dev_list_1364}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1365, pci_vendor_1365, pci_dev_list_1365}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1366, pci_vendor_1366, pci_dev_list_1366}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1367, pci_vendor_1367, pci_dev_list_1367}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1368, pci_vendor_1368, pci_dev_list_1368}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1369, pci_vendor_1369, pci_dev_list_1369}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136a, pci_vendor_136a, pci_dev_list_136a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136b, pci_vendor_136b, pci_dev_list_136b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136c, pci_vendor_136c, pci_dev_list_136c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136d, pci_vendor_136d, pci_dev_list_136d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136f, pci_vendor_136f, pci_dev_list_136f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1370, pci_vendor_1370, pci_dev_list_1370}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1371, pci_vendor_1371, pci_dev_list_1371}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1373, pci_vendor_1373, pci_dev_list_1373}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1374, pci_vendor_1374, pci_dev_list_1374}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1375, pci_vendor_1375, pci_dev_list_1375}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1376, pci_vendor_1376, pci_dev_list_1376}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1377, pci_vendor_1377, pci_dev_list_1377}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1378, pci_vendor_1378, pci_dev_list_1378}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1379, pci_vendor_1379, pci_dev_list_1379}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137a, pci_vendor_137a, pci_dev_list_137a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137b, pci_vendor_137b, pci_dev_list_137b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137c, pci_vendor_137c, pci_dev_list_137c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137d, pci_vendor_137d, pci_dev_list_137d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137e, pci_vendor_137e, pci_dev_list_137e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137f, pci_vendor_137f, pci_dev_list_137f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1380, pci_vendor_1380, pci_dev_list_1380}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1381, pci_vendor_1381, pci_dev_list_1381}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1382, pci_vendor_1382, pci_dev_list_1382}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1383, pci_vendor_1383, pci_dev_list_1383}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1384, pci_vendor_1384, pci_dev_list_1384}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1385, pci_vendor_1385, pci_dev_list_1385}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1386, pci_vendor_1386, pci_dev_list_1386}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1387, pci_vendor_1387, pci_dev_list_1387}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1388, pci_vendor_1388, pci_dev_list_1388}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1389, pci_vendor_1389, pci_dev_list_1389}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138a, pci_vendor_138a, pci_dev_list_138a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138b, pci_vendor_138b, pci_dev_list_138b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138c, pci_vendor_138c, pci_dev_list_138c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138d, pci_vendor_138d, pci_dev_list_138d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138e, pci_vendor_138e, pci_dev_list_138e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138f, pci_vendor_138f, pci_dev_list_138f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1390, pci_vendor_1390, pci_dev_list_1390}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1391, pci_vendor_1391, pci_dev_list_1391}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1392, pci_vendor_1392, pci_dev_list_1392}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1393, pci_vendor_1393, pci_dev_list_1393}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1394, pci_vendor_1394, pci_dev_list_1394}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1395, pci_vendor_1395, pci_dev_list_1395}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1396, pci_vendor_1396, pci_dev_list_1396}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1397, pci_vendor_1397, pci_dev_list_1397}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1398, pci_vendor_1398, pci_dev_list_1398}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1399, pci_vendor_1399, pci_dev_list_1399}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139a, pci_vendor_139a, pci_dev_list_139a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139b, pci_vendor_139b, pci_dev_list_139b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139c, pci_vendor_139c, pci_dev_list_139c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139d, pci_vendor_139d, pci_dev_list_139d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139e, pci_vendor_139e, pci_dev_list_139e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139f, pci_vendor_139f, pci_dev_list_139f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a0, pci_vendor_13a0, pci_dev_list_13a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a1, pci_vendor_13a1, pci_dev_list_13a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a2, pci_vendor_13a2, pci_dev_list_13a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a3, pci_vendor_13a3, pci_dev_list_13a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a4, pci_vendor_13a4, pci_dev_list_13a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a5, pci_vendor_13a5, pci_dev_list_13a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a6, pci_vendor_13a6, pci_dev_list_13a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a7, pci_vendor_13a7, pci_dev_list_13a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a8, pci_vendor_13a8, pci_dev_list_13a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a9, pci_vendor_13a9, pci_dev_list_13a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13aa, pci_vendor_13aa, pci_dev_list_13aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ab, pci_vendor_13ab, pci_dev_list_13ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ac, pci_vendor_13ac, pci_dev_list_13ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ad, pci_vendor_13ad, pci_dev_list_13ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ae, pci_vendor_13ae, pci_dev_list_13ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13af, pci_vendor_13af, pci_dev_list_13af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b0, pci_vendor_13b0, pci_dev_list_13b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b1, pci_vendor_13b1, pci_dev_list_13b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b2, pci_vendor_13b2, pci_dev_list_13b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b3, pci_vendor_13b3, pci_dev_list_13b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b4, pci_vendor_13b4, pci_dev_list_13b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b5, pci_vendor_13b5, pci_dev_list_13b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b6, pci_vendor_13b6, pci_dev_list_13b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b7, pci_vendor_13b7, pci_dev_list_13b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b8, pci_vendor_13b8, pci_dev_list_13b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b9, pci_vendor_13b9, pci_dev_list_13b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ba, pci_vendor_13ba, pci_dev_list_13ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bb, pci_vendor_13bb, pci_dev_list_13bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bc, pci_vendor_13bc, pci_dev_list_13bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bd, pci_vendor_13bd, pci_dev_list_13bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13be, pci_vendor_13be, pci_dev_list_13be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bf, pci_vendor_13bf, pci_dev_list_13bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c0, pci_vendor_13c0, pci_dev_list_13c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c1, pci_vendor_13c1, pci_dev_list_13c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c2, pci_vendor_13c2, pci_dev_list_13c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c3, pci_vendor_13c3, pci_dev_list_13c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c4, pci_vendor_13c4, pci_dev_list_13c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c5, pci_vendor_13c5, pci_dev_list_13c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c6, pci_vendor_13c6, pci_dev_list_13c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c7, pci_vendor_13c7, pci_dev_list_13c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c8, pci_vendor_13c8, pci_dev_list_13c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c9, pci_vendor_13c9, pci_dev_list_13c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ca, pci_vendor_13ca, pci_dev_list_13ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cb, pci_vendor_13cb, pci_dev_list_13cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cc, pci_vendor_13cc, pci_dev_list_13cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cd, pci_vendor_13cd, pci_dev_list_13cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ce, pci_vendor_13ce, pci_dev_list_13ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cf, pci_vendor_13cf, pci_dev_list_13cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d0, pci_vendor_13d0, pci_dev_list_13d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d1, pci_vendor_13d1, pci_dev_list_13d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d2, pci_vendor_13d2, pci_dev_list_13d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d3, pci_vendor_13d3, pci_dev_list_13d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d4, pci_vendor_13d4, pci_dev_list_13d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d5, pci_vendor_13d5, pci_dev_list_13d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d6, pci_vendor_13d6, pci_dev_list_13d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d7, pci_vendor_13d7, pci_dev_list_13d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d8, pci_vendor_13d8, pci_dev_list_13d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d9, pci_vendor_13d9, pci_dev_list_13d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13da, pci_vendor_13da, pci_dev_list_13da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13db, pci_vendor_13db, pci_dev_list_13db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13dc, pci_vendor_13dc, pci_dev_list_13dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13dd, pci_vendor_13dd, pci_dev_list_13dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13de, pci_vendor_13de, pci_dev_list_13de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13df, pci_vendor_13df, pci_dev_list_13df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e0, pci_vendor_13e0, pci_dev_list_13e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e1, pci_vendor_13e1, pci_dev_list_13e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e2, pci_vendor_13e2, pci_dev_list_13e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e3, pci_vendor_13e3, pci_dev_list_13e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e4, pci_vendor_13e4, pci_dev_list_13e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e5, pci_vendor_13e5, pci_dev_list_13e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e6, pci_vendor_13e6, pci_dev_list_13e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e7, pci_vendor_13e7, pci_dev_list_13e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e8, pci_vendor_13e8, pci_dev_list_13e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e9, pci_vendor_13e9, pci_dev_list_13e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ea, pci_vendor_13ea, pci_dev_list_13ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13eb, pci_vendor_13eb, pci_dev_list_13eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ec, pci_vendor_13ec, pci_dev_list_13ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ed, pci_vendor_13ed, pci_dev_list_13ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ee, pci_vendor_13ee, pci_dev_list_13ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ef, pci_vendor_13ef, pci_dev_list_13ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f0, pci_vendor_13f0, pci_dev_list_13f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f1, pci_vendor_13f1, pci_dev_list_13f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f2, pci_vendor_13f2, pci_dev_list_13f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f3, pci_vendor_13f3, pci_dev_list_13f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f4, pci_vendor_13f4, pci_dev_list_13f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f5, pci_vendor_13f5, pci_dev_list_13f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f6, pci_vendor_13f6, pci_dev_list_13f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f7, pci_vendor_13f7, pci_dev_list_13f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f8, pci_vendor_13f8, pci_dev_list_13f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f9, pci_vendor_13f9, pci_dev_list_13f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fa, pci_vendor_13fa, pci_dev_list_13fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fb, pci_vendor_13fb, pci_dev_list_13fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fc, pci_vendor_13fc, pci_dev_list_13fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fd, pci_vendor_13fd, pci_dev_list_13fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fe, pci_vendor_13fe, pci_dev_list_13fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ff, pci_vendor_13ff, pci_dev_list_13ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1400, pci_vendor_1400, pci_dev_list_1400}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1401, pci_vendor_1401, pci_dev_list_1401}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1402, pci_vendor_1402, pci_dev_list_1402}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1403, pci_vendor_1403, pci_dev_list_1403}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1404, pci_vendor_1404, pci_dev_list_1404}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1405, pci_vendor_1405, pci_dev_list_1405}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1406, pci_vendor_1406, pci_dev_list_1406}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1407, pci_vendor_1407, pci_dev_list_1407}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1408, pci_vendor_1408, pci_dev_list_1408}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1409, pci_vendor_1409, pci_dev_list_1409}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140a, pci_vendor_140a, pci_dev_list_140a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140b, pci_vendor_140b, pci_dev_list_140b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140c, pci_vendor_140c, pci_dev_list_140c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140d, pci_vendor_140d, pci_dev_list_140d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140e, pci_vendor_140e, pci_dev_list_140e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140f, pci_vendor_140f, pci_dev_list_140f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1410, pci_vendor_1410, pci_dev_list_1410}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1411, pci_vendor_1411, pci_dev_list_1411}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1412, pci_vendor_1412, pci_dev_list_1412}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1413, pci_vendor_1413, pci_dev_list_1413}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1414, pci_vendor_1414, pci_dev_list_1414}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1415, pci_vendor_1415, pci_dev_list_1415}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1416, pci_vendor_1416, pci_dev_list_1416}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1417, pci_vendor_1417, pci_dev_list_1417}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1418, pci_vendor_1418, pci_dev_list_1418}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1419, pci_vendor_1419, pci_dev_list_1419}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141a, pci_vendor_141a, pci_dev_list_141a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141b, pci_vendor_141b, pci_dev_list_141b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141d, pci_vendor_141d, pci_dev_list_141d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141e, pci_vendor_141e, pci_dev_list_141e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141f, pci_vendor_141f, pci_dev_list_141f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1420, pci_vendor_1420, pci_dev_list_1420}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1421, pci_vendor_1421, pci_dev_list_1421}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1422, pci_vendor_1422, pci_dev_list_1422}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1423, pci_vendor_1423, pci_dev_list_1423}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1424, pci_vendor_1424, pci_dev_list_1424}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1425, pci_vendor_1425, pci_dev_list_1425}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1426, pci_vendor_1426, pci_dev_list_1426}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1427, pci_vendor_1427, pci_dev_list_1427}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1428, pci_vendor_1428, pci_dev_list_1428}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1429, pci_vendor_1429, pci_dev_list_1429}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142a, pci_vendor_142a, pci_dev_list_142a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142b, pci_vendor_142b, pci_dev_list_142b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142c, pci_vendor_142c, pci_dev_list_142c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142d, pci_vendor_142d, pci_dev_list_142d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142e, pci_vendor_142e, pci_dev_list_142e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142f, pci_vendor_142f, pci_dev_list_142f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1430, pci_vendor_1430, pci_dev_list_1430}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1431, pci_vendor_1431, pci_dev_list_1431}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1432, pci_vendor_1432, pci_dev_list_1432}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1433, pci_vendor_1433, pci_dev_list_1433}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1435, pci_vendor_1435, pci_dev_list_1435}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1436, pci_vendor_1436, pci_dev_list_1436}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1437, pci_vendor_1437, pci_dev_list_1437}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1438, pci_vendor_1438, pci_dev_list_1438}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1439, pci_vendor_1439, pci_dev_list_1439}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143a, pci_vendor_143a, pci_dev_list_143a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143b, pci_vendor_143b, pci_dev_list_143b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143c, pci_vendor_143c, pci_dev_list_143c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143d, pci_vendor_143d, pci_dev_list_143d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143e, pci_vendor_143e, pci_dev_list_143e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143f, pci_vendor_143f, pci_dev_list_143f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1440, pci_vendor_1440, pci_dev_list_1440}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1441, pci_vendor_1441, pci_dev_list_1441}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1442, pci_vendor_1442, pci_dev_list_1442}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1443, pci_vendor_1443, pci_dev_list_1443}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1444, pci_vendor_1444, pci_dev_list_1444}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1445, pci_vendor_1445, pci_dev_list_1445}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1446, pci_vendor_1446, pci_dev_list_1446}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1447, pci_vendor_1447, pci_dev_list_1447}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1448, pci_vendor_1448, pci_dev_list_1448}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1449, pci_vendor_1449, pci_dev_list_1449}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144a, pci_vendor_144a, pci_dev_list_144a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144b, pci_vendor_144b, pci_dev_list_144b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144c, pci_vendor_144c, pci_dev_list_144c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144d, pci_vendor_144d, pci_dev_list_144d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144e, pci_vendor_144e, pci_dev_list_144e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144f, pci_vendor_144f, pci_dev_list_144f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1450, pci_vendor_1450, pci_dev_list_1450}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1451, pci_vendor_1451, pci_dev_list_1451}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1453, pci_vendor_1453, pci_dev_list_1453}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1454, pci_vendor_1454, pci_dev_list_1454}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1455, pci_vendor_1455, pci_dev_list_1455}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1456, pci_vendor_1456, pci_dev_list_1456}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1457, pci_vendor_1457, pci_dev_list_1457}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1458, pci_vendor_1458, pci_dev_list_1458}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1459, pci_vendor_1459, pci_dev_list_1459}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145a, pci_vendor_145a, pci_dev_list_145a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145b, pci_vendor_145b, pci_dev_list_145b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145c, pci_vendor_145c, pci_dev_list_145c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145d, pci_vendor_145d, pci_dev_list_145d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145e, pci_vendor_145e, pci_dev_list_145e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145f, pci_vendor_145f, pci_dev_list_145f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1460, pci_vendor_1460, pci_dev_list_1460}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1461, pci_vendor_1461, pci_dev_list_1461}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1462, pci_vendor_1462, pci_dev_list_1462}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1463, pci_vendor_1463, pci_dev_list_1463}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1464, pci_vendor_1464, pci_dev_list_1464}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1465, pci_vendor_1465, pci_dev_list_1465}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1466, pci_vendor_1466, pci_dev_list_1466}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1467, pci_vendor_1467, pci_dev_list_1467}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1468, pci_vendor_1468, pci_dev_list_1468}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1469, pci_vendor_1469, pci_dev_list_1469}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146a, pci_vendor_146a, pci_dev_list_146a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146b, pci_vendor_146b, pci_dev_list_146b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146c, pci_vendor_146c, pci_dev_list_146c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146d, pci_vendor_146d, pci_dev_list_146d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146e, pci_vendor_146e, pci_dev_list_146e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146f, pci_vendor_146f, pci_dev_list_146f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1470, pci_vendor_1470, pci_dev_list_1470}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1471, pci_vendor_1471, pci_dev_list_1471}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1472, pci_vendor_1472, pci_dev_list_1472}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1473, pci_vendor_1473, pci_dev_list_1473}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1474, pci_vendor_1474, pci_dev_list_1474}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1475, pci_vendor_1475, pci_dev_list_1475}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1476, pci_vendor_1476, pci_dev_list_1476}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1477, pci_vendor_1477, pci_dev_list_1477}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1478, pci_vendor_1478, pci_dev_list_1478}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1479, pci_vendor_1479, pci_dev_list_1479}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147a, pci_vendor_147a, pci_dev_list_147a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147b, pci_vendor_147b, pci_dev_list_147b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147c, pci_vendor_147c, pci_dev_list_147c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147d, pci_vendor_147d, pci_dev_list_147d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147e, pci_vendor_147e, pci_dev_list_147e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147f, pci_vendor_147f, pci_dev_list_147f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1480, pci_vendor_1480, pci_dev_list_1480}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1481, pci_vendor_1481, pci_dev_list_1481}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1482, pci_vendor_1482, pci_dev_list_1482}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1483, pci_vendor_1483, pci_dev_list_1483}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1484, pci_vendor_1484, pci_dev_list_1484}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1485, pci_vendor_1485, pci_dev_list_1485}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1486, pci_vendor_1486, pci_dev_list_1486}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1487, pci_vendor_1487, pci_dev_list_1487}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1488, pci_vendor_1488, pci_dev_list_1488}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1489, pci_vendor_1489, pci_dev_list_1489}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148a, pci_vendor_148a, pci_dev_list_148a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148b, pci_vendor_148b, pci_dev_list_148b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148c, pci_vendor_148c, pci_dev_list_148c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148d, pci_vendor_148d, pci_dev_list_148d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148e, pci_vendor_148e, pci_dev_list_148e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148f, pci_vendor_148f, pci_dev_list_148f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1490, pci_vendor_1490, pci_dev_list_1490}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1491, pci_vendor_1491, pci_dev_list_1491}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1492, pci_vendor_1492, pci_dev_list_1492}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1493, pci_vendor_1493, pci_dev_list_1493}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1494, pci_vendor_1494, pci_dev_list_1494}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1495, pci_vendor_1495, pci_dev_list_1495}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1496, pci_vendor_1496, pci_dev_list_1496}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1497, pci_vendor_1497, pci_dev_list_1497}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1498, pci_vendor_1498, pci_dev_list_1498}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1499, pci_vendor_1499, pci_dev_list_1499}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149a, pci_vendor_149a, pci_dev_list_149a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149b, pci_vendor_149b, pci_dev_list_149b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149c, pci_vendor_149c, pci_dev_list_149c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149d, pci_vendor_149d, pci_dev_list_149d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149e, pci_vendor_149e, pci_dev_list_149e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149f, pci_vendor_149f, pci_dev_list_149f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a0, pci_vendor_14a0, pci_dev_list_14a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a1, pci_vendor_14a1, pci_dev_list_14a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a2, pci_vendor_14a2, pci_dev_list_14a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a3, pci_vendor_14a3, pci_dev_list_14a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a4, pci_vendor_14a4, pci_dev_list_14a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a5, pci_vendor_14a5, pci_dev_list_14a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a6, pci_vendor_14a6, pci_dev_list_14a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a7, pci_vendor_14a7, pci_dev_list_14a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a8, pci_vendor_14a8, pci_dev_list_14a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a9, pci_vendor_14a9, pci_dev_list_14a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14aa, pci_vendor_14aa, pci_dev_list_14aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ab, pci_vendor_14ab, pci_dev_list_14ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ac, pci_vendor_14ac, pci_dev_list_14ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ad, pci_vendor_14ad, pci_dev_list_14ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ae, pci_vendor_14ae, pci_dev_list_14ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14af, pci_vendor_14af, pci_dev_list_14af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b0, pci_vendor_14b0, pci_dev_list_14b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b1, pci_vendor_14b1, pci_dev_list_14b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b2, pci_vendor_14b2, pci_dev_list_14b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b3, pci_vendor_14b3, pci_dev_list_14b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b4, pci_vendor_14b4, pci_dev_list_14b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b5, pci_vendor_14b5, pci_dev_list_14b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b6, pci_vendor_14b6, pci_dev_list_14b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b7, pci_vendor_14b7, pci_dev_list_14b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b8, pci_vendor_14b8, pci_dev_list_14b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b9, pci_vendor_14b9, pci_dev_list_14b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ba, pci_vendor_14ba, pci_dev_list_14ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bb, pci_vendor_14bb, pci_dev_list_14bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bc, pci_vendor_14bc, pci_dev_list_14bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bd, pci_vendor_14bd, pci_dev_list_14bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14be, pci_vendor_14be, pci_dev_list_14be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bf, pci_vendor_14bf, pci_dev_list_14bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c0, pci_vendor_14c0, pci_dev_list_14c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c1, pci_vendor_14c1, pci_dev_list_14c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c2, pci_vendor_14c2, pci_dev_list_14c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c3, pci_vendor_14c3, pci_dev_list_14c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c4, pci_vendor_14c4, pci_dev_list_14c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c5, pci_vendor_14c5, pci_dev_list_14c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c6, pci_vendor_14c6, pci_dev_list_14c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c7, pci_vendor_14c7, pci_dev_list_14c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c8, pci_vendor_14c8, pci_dev_list_14c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c9, pci_vendor_14c9, pci_dev_list_14c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ca, pci_vendor_14ca, pci_dev_list_14ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cb, pci_vendor_14cb, pci_dev_list_14cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cc, pci_vendor_14cc, pci_dev_list_14cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cd, pci_vendor_14cd, pci_dev_list_14cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ce, pci_vendor_14ce, pci_dev_list_14ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cf, pci_vendor_14cf, pci_dev_list_14cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d0, pci_vendor_14d0, pci_dev_list_14d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d1, pci_vendor_14d1, pci_dev_list_14d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d2, pci_vendor_14d2, pci_dev_list_14d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d3, pci_vendor_14d3, pci_dev_list_14d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d4, pci_vendor_14d4, pci_dev_list_14d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d5, pci_vendor_14d5, pci_dev_list_14d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d6, pci_vendor_14d6, pci_dev_list_14d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d7, pci_vendor_14d7, pci_dev_list_14d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d8, pci_vendor_14d8, pci_dev_list_14d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d9, pci_vendor_14d9, pci_dev_list_14d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14da, pci_vendor_14da, pci_dev_list_14da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14db, pci_vendor_14db, pci_dev_list_14db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14dc, pci_vendor_14dc, pci_dev_list_14dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14dd, pci_vendor_14dd, pci_dev_list_14dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14de, pci_vendor_14de, pci_dev_list_14de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14df, pci_vendor_14df, pci_dev_list_14df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e1, pci_vendor_14e1, pci_dev_list_14e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e2, pci_vendor_14e2, pci_dev_list_14e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e3, pci_vendor_14e3, pci_dev_list_14e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e4, pci_vendor_14e4, pci_dev_list_14e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e5, pci_vendor_14e5, pci_dev_list_14e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e6, pci_vendor_14e6, pci_dev_list_14e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e7, pci_vendor_14e7, pci_dev_list_14e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e8, pci_vendor_14e8, pci_dev_list_14e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e9, pci_vendor_14e9, pci_dev_list_14e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ea, pci_vendor_14ea, pci_dev_list_14ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14eb, pci_vendor_14eb, pci_dev_list_14eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ec, pci_vendor_14ec, pci_dev_list_14ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ed, pci_vendor_14ed, pci_dev_list_14ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ee, pci_vendor_14ee, pci_dev_list_14ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ef, pci_vendor_14ef, pci_dev_list_14ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f0, pci_vendor_14f0, pci_dev_list_14f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f1, pci_vendor_14f1, pci_dev_list_14f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f2, pci_vendor_14f2, pci_dev_list_14f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f3, pci_vendor_14f3, pci_dev_list_14f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f4, pci_vendor_14f4, pci_dev_list_14f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f5, pci_vendor_14f5, pci_dev_list_14f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f6, pci_vendor_14f6, pci_dev_list_14f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f7, pci_vendor_14f7, pci_dev_list_14f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f8, pci_vendor_14f8, pci_dev_list_14f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f9, pci_vendor_14f9, pci_dev_list_14f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fa, pci_vendor_14fa, pci_dev_list_14fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fb, pci_vendor_14fb, pci_dev_list_14fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fc, pci_vendor_14fc, pci_dev_list_14fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fd, pci_vendor_14fd, pci_dev_list_14fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fe, pci_vendor_14fe, pci_dev_list_14fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ff, pci_vendor_14ff, pci_dev_list_14ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1500, pci_vendor_1500, pci_dev_list_1500}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1501, pci_vendor_1501, pci_dev_list_1501}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1502, pci_vendor_1502, pci_dev_list_1502}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1503, pci_vendor_1503, pci_dev_list_1503}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1504, pci_vendor_1504, pci_dev_list_1504}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1505, pci_vendor_1505, pci_dev_list_1505}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1506, pci_vendor_1506, pci_dev_list_1506}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1507, pci_vendor_1507, pci_dev_list_1507}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1508, pci_vendor_1508, pci_dev_list_1508}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1509, pci_vendor_1509, pci_dev_list_1509}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150a, pci_vendor_150a, pci_dev_list_150a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150b, pci_vendor_150b, pci_dev_list_150b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150c, pci_vendor_150c, pci_dev_list_150c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150d, pci_vendor_150d, pci_dev_list_150d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150e, pci_vendor_150e, pci_dev_list_150e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150f, pci_vendor_150f, pci_dev_list_150f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1510, pci_vendor_1510, pci_dev_list_1510}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1511, pci_vendor_1511, pci_dev_list_1511}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1512, pci_vendor_1512, pci_dev_list_1512}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1513, pci_vendor_1513, pci_dev_list_1513}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1514, pci_vendor_1514, pci_dev_list_1514}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1515, pci_vendor_1515, pci_dev_list_1515}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1516, pci_vendor_1516, pci_dev_list_1516}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1517, pci_vendor_1517, pci_dev_list_1517}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1518, pci_vendor_1518, pci_dev_list_1518}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1519, pci_vendor_1519, pci_dev_list_1519}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151a, pci_vendor_151a, pci_dev_list_151a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151b, pci_vendor_151b, pci_dev_list_151b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151c, pci_vendor_151c, pci_dev_list_151c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151d, pci_vendor_151d, pci_dev_list_151d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151e, pci_vendor_151e, pci_dev_list_151e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151f, pci_vendor_151f, pci_dev_list_151f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1520, pci_vendor_1520, pci_dev_list_1520}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1521, pci_vendor_1521, pci_dev_list_1521}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1522, pci_vendor_1522, pci_dev_list_1522}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1523, pci_vendor_1523, pci_dev_list_1523}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1524, pci_vendor_1524, pci_dev_list_1524}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1525, pci_vendor_1525, pci_dev_list_1525}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1526, pci_vendor_1526, pci_dev_list_1526}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1527, pci_vendor_1527, pci_dev_list_1527}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1528, pci_vendor_1528, pci_dev_list_1528}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1529, pci_vendor_1529, pci_dev_list_1529}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152a, pci_vendor_152a, pci_dev_list_152a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152b, pci_vendor_152b, pci_dev_list_152b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152c, pci_vendor_152c, pci_dev_list_152c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152d, pci_vendor_152d, pci_dev_list_152d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152e, pci_vendor_152e, pci_dev_list_152e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152f, pci_vendor_152f, pci_dev_list_152f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1530, pci_vendor_1530, pci_dev_list_1530}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1531, pci_vendor_1531, pci_dev_list_1531}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1532, pci_vendor_1532, pci_dev_list_1532}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1533, pci_vendor_1533, pci_dev_list_1533}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1534, pci_vendor_1534, pci_dev_list_1534}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1535, pci_vendor_1535, pci_dev_list_1535}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1537, pci_vendor_1537, pci_dev_list_1537}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1538, pci_vendor_1538, pci_dev_list_1538}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1539, pci_vendor_1539, pci_dev_list_1539}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153a, pci_vendor_153a, pci_dev_list_153a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153b, pci_vendor_153b, pci_dev_list_153b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153c, pci_vendor_153c, pci_dev_list_153c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153d, pci_vendor_153d, pci_dev_list_153d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153e, pci_vendor_153e, pci_dev_list_153e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153f, pci_vendor_153f, pci_dev_list_153f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1540, pci_vendor_1540, pci_dev_list_1540}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1541, pci_vendor_1541, pci_dev_list_1541}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1542, pci_vendor_1542, pci_dev_list_1542}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1543, pci_vendor_1543, pci_dev_list_1543}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1544, pci_vendor_1544, pci_dev_list_1544}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1545, pci_vendor_1545, pci_dev_list_1545}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1546, pci_vendor_1546, pci_dev_list_1546}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1547, pci_vendor_1547, pci_dev_list_1547}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1548, pci_vendor_1548, pci_dev_list_1548}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1549, pci_vendor_1549, pci_dev_list_1549}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154a, pci_vendor_154a, pci_dev_list_154a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154b, pci_vendor_154b, pci_dev_list_154b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154c, pci_vendor_154c, pci_dev_list_154c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154d, pci_vendor_154d, pci_dev_list_154d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154e, pci_vendor_154e, pci_dev_list_154e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154f, pci_vendor_154f, pci_dev_list_154f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1550, pci_vendor_1550, pci_dev_list_1550}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1551, pci_vendor_1551, pci_dev_list_1551}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1552, pci_vendor_1552, pci_dev_list_1552}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1553, pci_vendor_1553, pci_dev_list_1553}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1554, pci_vendor_1554, pci_dev_list_1554}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1555, pci_vendor_1555, pci_dev_list_1555}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1556, pci_vendor_1556, pci_dev_list_1556}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1557, pci_vendor_1557, pci_dev_list_1557}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1558, pci_vendor_1558, pci_dev_list_1558}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1559, pci_vendor_1559, pci_dev_list_1559}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155a, pci_vendor_155a, pci_dev_list_155a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155b, pci_vendor_155b, pci_dev_list_155b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155c, pci_vendor_155c, pci_dev_list_155c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155d, pci_vendor_155d, pci_dev_list_155d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155e, pci_vendor_155e, pci_dev_list_155e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155f, pci_vendor_155f, pci_dev_list_155f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1560, pci_vendor_1560, pci_dev_list_1560}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1561, pci_vendor_1561, pci_dev_list_1561}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1562, pci_vendor_1562, pci_dev_list_1562}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1563, pci_vendor_1563, pci_dev_list_1563}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1564, pci_vendor_1564, pci_dev_list_1564}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1565, pci_vendor_1565, pci_dev_list_1565}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1566, pci_vendor_1566, pci_dev_list_1566}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1567, pci_vendor_1567, pci_dev_list_1567}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1568, pci_vendor_1568, pci_dev_list_1568}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1569, pci_vendor_1569, pci_dev_list_1569}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156a, pci_vendor_156a, pci_dev_list_156a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156b, pci_vendor_156b, pci_dev_list_156b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156c, pci_vendor_156c, pci_dev_list_156c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156d, pci_vendor_156d, pci_dev_list_156d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156e, pci_vendor_156e, pci_dev_list_156e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156f, pci_vendor_156f, pci_dev_list_156f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1570, pci_vendor_1570, pci_dev_list_1570}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1571, pci_vendor_1571, pci_dev_list_1571}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1572, pci_vendor_1572, pci_dev_list_1572}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1573, pci_vendor_1573, pci_dev_list_1573}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1574, pci_vendor_1574, pci_dev_list_1574}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1575, pci_vendor_1575, pci_dev_list_1575}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1576, pci_vendor_1576, pci_dev_list_1576}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1578, pci_vendor_1578, pci_dev_list_1578}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1579, pci_vendor_1579, pci_dev_list_1579}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157a, pci_vendor_157a, pci_dev_list_157a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157b, pci_vendor_157b, pci_dev_list_157b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157c, pci_vendor_157c, pci_dev_list_157c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157d, pci_vendor_157d, pci_dev_list_157d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157e, pci_vendor_157e, pci_dev_list_157e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157f, pci_vendor_157f, pci_dev_list_157f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1580, pci_vendor_1580, pci_dev_list_1580}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1581, pci_vendor_1581, pci_dev_list_1581}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1582, pci_vendor_1582, pci_dev_list_1582}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1583, pci_vendor_1583, pci_dev_list_1583}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1584, pci_vendor_1584, pci_dev_list_1584}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1585, pci_vendor_1585, pci_dev_list_1585}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1586, pci_vendor_1586, pci_dev_list_1586}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1587, pci_vendor_1587, pci_dev_list_1587}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1588, pci_vendor_1588, pci_dev_list_1588}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1589, pci_vendor_1589, pci_dev_list_1589}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158a, pci_vendor_158a, pci_dev_list_158a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158b, pci_vendor_158b, pci_dev_list_158b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158c, pci_vendor_158c, pci_dev_list_158c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158d, pci_vendor_158d, pci_dev_list_158d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158e, pci_vendor_158e, pci_dev_list_158e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158f, pci_vendor_158f, pci_dev_list_158f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1590, pci_vendor_1590, pci_dev_list_1590}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1591, pci_vendor_1591, pci_dev_list_1591}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1592, pci_vendor_1592, pci_dev_list_1592}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1593, pci_vendor_1593, pci_dev_list_1593}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1594, pci_vendor_1594, pci_dev_list_1594}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1595, pci_vendor_1595, pci_dev_list_1595}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1596, pci_vendor_1596, pci_dev_list_1596}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1597, pci_vendor_1597, pci_dev_list_1597}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1598, pci_vendor_1598, pci_dev_list_1598}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1599, pci_vendor_1599, pci_dev_list_1599}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159a, pci_vendor_159a, pci_dev_list_159a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159b, pci_vendor_159b, pci_dev_list_159b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159c, pci_vendor_159c, pci_dev_list_159c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159d, pci_vendor_159d, pci_dev_list_159d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159e, pci_vendor_159e, pci_dev_list_159e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159f, pci_vendor_159f, pci_dev_list_159f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a0, pci_vendor_15a0, pci_dev_list_15a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a1, pci_vendor_15a1, pci_dev_list_15a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a2, pci_vendor_15a2, pci_dev_list_15a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a3, pci_vendor_15a3, pci_dev_list_15a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a4, pci_vendor_15a4, pci_dev_list_15a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a5, pci_vendor_15a5, pci_dev_list_15a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a6, pci_vendor_15a6, pci_dev_list_15a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a7, pci_vendor_15a7, pci_dev_list_15a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a8, pci_vendor_15a8, pci_dev_list_15a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15aa, pci_vendor_15aa, pci_dev_list_15aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ab, pci_vendor_15ab, pci_dev_list_15ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ac, pci_vendor_15ac, pci_dev_list_15ac}, +#endif + {0x15ad, pci_vendor_15ad, pci_dev_list_15ad}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ae, pci_vendor_15ae, pci_dev_list_15ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b0, pci_vendor_15b0, pci_dev_list_15b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b1, pci_vendor_15b1, pci_dev_list_15b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b2, pci_vendor_15b2, pci_dev_list_15b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b3, pci_vendor_15b3, pci_dev_list_15b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b4, pci_vendor_15b4, pci_dev_list_15b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b5, pci_vendor_15b5, pci_dev_list_15b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b6, pci_vendor_15b6, pci_dev_list_15b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b7, pci_vendor_15b7, pci_dev_list_15b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b8, pci_vendor_15b8, pci_dev_list_15b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b9, pci_vendor_15b9, pci_dev_list_15b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ba, pci_vendor_15ba, pci_dev_list_15ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bb, pci_vendor_15bb, pci_dev_list_15bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bc, pci_vendor_15bc, pci_dev_list_15bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bd, pci_vendor_15bd, pci_dev_list_15bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15be, pci_vendor_15be, pci_dev_list_15be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bf, pci_vendor_15bf, pci_dev_list_15bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c0, pci_vendor_15c0, pci_dev_list_15c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c1, pci_vendor_15c1, pci_dev_list_15c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c2, pci_vendor_15c2, pci_dev_list_15c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c3, pci_vendor_15c3, pci_dev_list_15c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c4, pci_vendor_15c4, pci_dev_list_15c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c5, pci_vendor_15c5, pci_dev_list_15c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c6, pci_vendor_15c6, pci_dev_list_15c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c7, pci_vendor_15c7, pci_dev_list_15c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c8, pci_vendor_15c8, pci_dev_list_15c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c9, pci_vendor_15c9, pci_dev_list_15c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ca, pci_vendor_15ca, pci_dev_list_15ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cb, pci_vendor_15cb, pci_dev_list_15cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cc, pci_vendor_15cc, pci_dev_list_15cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cd, pci_vendor_15cd, pci_dev_list_15cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ce, pci_vendor_15ce, pci_dev_list_15ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cf, pci_vendor_15cf, pci_dev_list_15cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d1, pci_vendor_15d1, pci_dev_list_15d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d2, pci_vendor_15d2, pci_dev_list_15d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d3, pci_vendor_15d3, pci_dev_list_15d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d4, pci_vendor_15d4, pci_dev_list_15d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d5, pci_vendor_15d5, pci_dev_list_15d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d6, pci_vendor_15d6, pci_dev_list_15d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d7, pci_vendor_15d7, pci_dev_list_15d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d8, pci_vendor_15d8, pci_dev_list_15d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d9, pci_vendor_15d9, pci_dev_list_15d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15da, pci_vendor_15da, pci_dev_list_15da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15db, pci_vendor_15db, pci_dev_list_15db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15dc, pci_vendor_15dc, pci_dev_list_15dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15dd, pci_vendor_15dd, pci_dev_list_15dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15de, pci_vendor_15de, pci_dev_list_15de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15df, pci_vendor_15df, pci_dev_list_15df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e0, pci_vendor_15e0, pci_dev_list_15e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e1, pci_vendor_15e1, pci_dev_list_15e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e2, pci_vendor_15e2, pci_dev_list_15e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e3, pci_vendor_15e3, pci_dev_list_15e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e4, pci_vendor_15e4, pci_dev_list_15e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e5, pci_vendor_15e5, pci_dev_list_15e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e6, pci_vendor_15e6, pci_dev_list_15e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e7, pci_vendor_15e7, pci_dev_list_15e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e8, pci_vendor_15e8, pci_dev_list_15e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e9, pci_vendor_15e9, pci_dev_list_15e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ea, pci_vendor_15ea, pci_dev_list_15ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15eb, pci_vendor_15eb, pci_dev_list_15eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ec, pci_vendor_15ec, pci_dev_list_15ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ed, pci_vendor_15ed, pci_dev_list_15ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ee, pci_vendor_15ee, pci_dev_list_15ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ef, pci_vendor_15ef, pci_dev_list_15ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f0, pci_vendor_15f0, pci_dev_list_15f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f1, pci_vendor_15f1, pci_dev_list_15f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f2, pci_vendor_15f2, pci_dev_list_15f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f3, pci_vendor_15f3, pci_dev_list_15f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f4, pci_vendor_15f4, pci_dev_list_15f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f5, pci_vendor_15f5, pci_dev_list_15f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f6, pci_vendor_15f6, pci_dev_list_15f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f7, pci_vendor_15f7, pci_dev_list_15f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f8, pci_vendor_15f8, pci_dev_list_15f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f9, pci_vendor_15f9, pci_dev_list_15f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fa, pci_vendor_15fa, pci_dev_list_15fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fb, pci_vendor_15fb, pci_dev_list_15fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fc, pci_vendor_15fc, pci_dev_list_15fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fd, pci_vendor_15fd, pci_dev_list_15fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fe, pci_vendor_15fe, pci_dev_list_15fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ff, pci_vendor_15ff, pci_dev_list_15ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1600, pci_vendor_1600, pci_dev_list_1600}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1601, pci_vendor_1601, pci_dev_list_1601}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1602, pci_vendor_1602, pci_dev_list_1602}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1603, pci_vendor_1603, pci_dev_list_1603}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1604, pci_vendor_1604, pci_dev_list_1604}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1605, pci_vendor_1605, pci_dev_list_1605}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1606, pci_vendor_1606, pci_dev_list_1606}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1607, pci_vendor_1607, pci_dev_list_1607}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1608, pci_vendor_1608, pci_dev_list_1608}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1609, pci_vendor_1609, pci_dev_list_1609}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1612, pci_vendor_1612, pci_dev_list_1612}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1619, pci_vendor_1619, pci_dev_list_1619}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1629, pci_vendor_1629, pci_dev_list_1629}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1638, pci_vendor_1638, pci_dev_list_1638}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x163c, pci_vendor_163c, pci_dev_list_163c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1657, pci_vendor_1657, pci_dev_list_1657}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165a, pci_vendor_165a, pci_dev_list_165a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165d, pci_vendor_165d, pci_dev_list_165d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1661, pci_vendor_1661, pci_dev_list_1661}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1668, pci_vendor_1668, pci_dev_list_1668}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1681, pci_vendor_1681, pci_dev_list_1681}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ab, pci_vendor_16ab, pci_dev_list_16ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16be, pci_vendor_16be, pci_dev_list_16be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ec, pci_vendor_16ec, pci_dev_list_16ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f6, pci_vendor_16f6, pci_dev_list_16f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1705, pci_vendor_1705, pci_dev_list_1705}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x170b, pci_vendor_170b, pci_dev_list_170b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x170c, pci_vendor_170c, pci_dev_list_170c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x172a, pci_vendor_172a, pci_dev_list_172a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1737, pci_vendor_1737, pci_dev_list_1737}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x173b, pci_vendor_173b, pci_dev_list_173b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1743, pci_vendor_1743, pci_dev_list_1743}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x174b, pci_vendor_174b, pci_dev_list_174b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x175e, pci_vendor_175e, pci_dev_list_175e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1787, pci_vendor_1787, pci_dev_list_1787}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1796, pci_vendor_1796, pci_dev_list_1796}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1799, pci_vendor_1799, pci_dev_list_1799}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17af, pci_vendor_17af, pci_dev_list_17af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cc, pci_vendor_17cc, pci_dev_list_17cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1813, pci_vendor_1813, pci_dev_list_1813}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1851, pci_vendor_1851, pci_dev_list_1851}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1852, pci_vendor_1852, pci_dev_list_1852}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1888, pci_vendor_1888, pci_dev_list_1888}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1a08, pci_vendor_1a08, pci_dev_list_1a08}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1b13, pci_vendor_1b13, pci_dev_list_1b13}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1c1c, pci_vendor_1c1c, pci_dev_list_1c1c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1d44, pci_vendor_1d44, pci_dev_list_1d44}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1de1, pci_vendor_1de1, pci_dev_list_1de1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2000, pci_vendor_2000, pci_dev_list_2000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2001, pci_vendor_2001, pci_dev_list_2001}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2003, pci_vendor_2003, pci_dev_list_2003}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2004, pci_vendor_2004, pci_dev_list_2004}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x21c3, pci_vendor_21c3, pci_dev_list_21c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2348, pci_vendor_2348, pci_dev_list_2348}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2646, pci_vendor_2646, pci_dev_list_2646}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x270b, pci_vendor_270b, pci_dev_list_270b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x270f, pci_vendor_270f, pci_dev_list_270f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2711, pci_vendor_2711, pci_dev_list_2711}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2a15, pci_vendor_2a15, pci_dev_list_2a15}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3000, pci_vendor_3000, pci_dev_list_3000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3142, pci_vendor_3142, pci_dev_list_3142}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3388, pci_vendor_3388, pci_dev_list_3388}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3411, pci_vendor_3411, pci_dev_list_3411}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3513, pci_vendor_3513, pci_dev_list_3513}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x38ef, pci_vendor_38ef, pci_dev_list_38ef}, +#endif + {0x3d3d, pci_vendor_3d3d, pci_dev_list_3d3d}, + {0x4005, pci_vendor_4005, pci_dev_list_4005}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4033, pci_vendor_4033, pci_dev_list_4033}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4143, pci_vendor_4143, pci_dev_list_4143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x416c, pci_vendor_416c, pci_dev_list_416c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4444, pci_vendor_4444, pci_dev_list_4444}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4468, pci_vendor_4468, pci_dev_list_4468}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4594, pci_vendor_4594, pci_dev_list_4594}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x45fb, pci_vendor_45fb, pci_dev_list_45fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4680, pci_vendor_4680, pci_dev_list_4680}, +#endif + {0x4843, pci_vendor_4843, pci_dev_list_4843}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4916, pci_vendor_4916, pci_dev_list_4916}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4943, pci_vendor_4943, pci_dev_list_4943}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4978, pci_vendor_4978, pci_dev_list_4978}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4a14, pci_vendor_4a14, pci_dev_list_4a14}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4b10, pci_vendor_4b10, pci_dev_list_4b10}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4c48, pci_vendor_4c48, pci_dev_list_4c48}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4c53, pci_vendor_4c53, pci_dev_list_4c53}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4ca1, pci_vendor_4ca1, pci_dev_list_4ca1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4d51, pci_vendor_4d51, pci_dev_list_4d51}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4d54, pci_vendor_4d54, pci_dev_list_4d54}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4ddc, pci_vendor_4ddc, pci_dev_list_4ddc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5046, pci_vendor_5046, pci_dev_list_5046}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5053, pci_vendor_5053, pci_dev_list_5053}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5136, pci_vendor_5136, pci_dev_list_5136}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5143, pci_vendor_5143, pci_dev_list_5143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5145, pci_vendor_5145, pci_dev_list_5145}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5168, pci_vendor_5168, pci_dev_list_5168}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5301, pci_vendor_5301, pci_dev_list_5301}, +#endif + {0x5333, pci_vendor_5333, pci_dev_list_5333}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x544c, pci_vendor_544c, pci_dev_list_544c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5455, pci_vendor_5455, pci_dev_list_5455}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5519, pci_vendor_5519, pci_dev_list_5519}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5544, pci_vendor_5544, pci_dev_list_5544}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5555, pci_vendor_5555, pci_dev_list_5555}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5654, pci_vendor_5654, pci_dev_list_5654}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5700, pci_vendor_5700, pci_dev_list_5700}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6356, pci_vendor_6356, pci_dev_list_6356}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6374, pci_vendor_6374, pci_dev_list_6374}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6409, pci_vendor_6409, pci_dev_list_6409}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6666, pci_vendor_6666, pci_dev_list_6666}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7604, pci_vendor_7604, pci_dev_list_7604}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7bde, pci_vendor_7bde, pci_dev_list_7bde}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7fed, pci_vendor_7fed, pci_dev_list_7fed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8008, pci_vendor_8008, pci_dev_list_8008}, +#endif + {0x8086, pci_vendor_8086, pci_dev_list_8086}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8800, pci_vendor_8800, pci_dev_list_8800}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8866, pci_vendor_8866, pci_dev_list_8866}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8888, pci_vendor_8888, pci_dev_list_8888}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8e0e, pci_vendor_8e0e, pci_dev_list_8e0e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8e2e, pci_vendor_8e2e, pci_dev_list_8e2e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9004, pci_vendor_9004, pci_dev_list_9004}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9005, pci_vendor_9005, pci_dev_list_9005}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x907f, pci_vendor_907f, pci_dev_list_907f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x919a, pci_vendor_919a, pci_dev_list_919a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9412, pci_vendor_9412, pci_dev_list_9412}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9699, pci_vendor_9699, pci_dev_list_9699}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9710, pci_vendor_9710, pci_dev_list_9710}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa0a0, pci_vendor_a0a0, pci_dev_list_a0a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa0f1, pci_vendor_a0f1, pci_dev_list_a0f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa200, pci_vendor_a200, pci_dev_list_a200}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa259, pci_vendor_a259, pci_dev_list_a259}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa25b, pci_vendor_a25b, pci_dev_list_a25b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa304, pci_vendor_a304, pci_dev_list_a304}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa727, pci_vendor_a727, pci_dev_list_a727}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xaa42, pci_vendor_aa42, pci_dev_list_aa42}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xac1e, pci_vendor_ac1e, pci_dev_list_ac1e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xb1b3, pci_vendor_b1b3, pci_dev_list_b1b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xbd11, pci_vendor_bd11, pci_dev_list_bd11}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc001, pci_vendor_c001, pci_dev_list_c001}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc0a9, pci_vendor_c0a9, pci_dev_list_c0a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc0de, pci_vendor_c0de, pci_dev_list_c0de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc0fe, pci_vendor_c0fe, pci_dev_list_c0fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xca50, pci_vendor_ca50, pci_dev_list_ca50}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xcafe, pci_vendor_cafe, pci_dev_list_cafe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xcccc, pci_vendor_cccc, pci_dev_list_cccc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xcddd, pci_vendor_cddd, pci_dev_list_cddd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd4d4, pci_vendor_d4d4, pci_dev_list_d4d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd531, pci_vendor_d531, pci_dev_list_d531}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd84d, pci_vendor_d84d, pci_dev_list_d84d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xdead, pci_vendor_dead, pci_dev_list_dead}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe000, pci_vendor_e000, pci_dev_list_e000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe159, pci_vendor_e159, pci_dev_list_e159}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe4bf, pci_vendor_e4bf, pci_dev_list_e4bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xea01, pci_vendor_ea01, pci_dev_list_ea01}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xea60, pci_vendor_ea60, pci_dev_list_ea60}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xeabb, pci_vendor_eabb, pci_dev_list_eabb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xeace, pci_vendor_eace, pci_dev_list_eace}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xec80, pci_vendor_ec80, pci_dev_list_ec80}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xecc0, pci_vendor_ecc0, pci_dev_list_ecc0}, +#endif + {0xedd8, pci_vendor_edd8, pci_dev_list_edd8}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xf1d0, pci_vendor_f1d0, pci_dev_list_f1d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfa57, pci_vendor_fa57, pci_dev_list_fa57}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfebd, pci_vendor_febd, pci_dev_list_febd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfeda, pci_vendor_feda, pci_dev_list_feda}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfffe, pci_vendor_fffe, pci_dev_list_fffe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xffff, pci_vendor_ffff, pci_dev_list_ffff}, +#endif + {0x0000, NULL, NULL} +}; + +#if defined(INIT_VENDOR_SUBSYS_INFO) && defined(INIT_SUBSYS_INFO) +static const pciVendorSubsysInfo pciVendorSubsysInfoList[] = { +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0000, pci_vendor_0000, pci_ss_list_0000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x001a, pci_vendor_001a, pci_ss_list_001a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0033, pci_vendor_0033, pci_ss_list_0033}, +#endif + {0x003d, pci_vendor_003d, pci_ss_list_003d}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0059, pci_vendor_0059, pci_ss_list_0059}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0070, pci_vendor_0070, pci_ss_list_0070}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0100, pci_vendor_0100, pci_ss_list_0100}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0675, pci_vendor_0675, pci_ss_list_0675}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0925, pci_vendor_0925, pci_ss_list_0925}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x09c1, pci_vendor_09c1, pci_ss_list_09c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0a89, pci_vendor_0a89, pci_ss_list_0a89}, +#endif + {0x0e11, pci_vendor_0e11, pci_ss_list_0e11}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0e55, pci_vendor_0e55, pci_ss_list_0e55}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1000, pci_vendor_1000, pci_ss_list_1000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1001, pci_vendor_1001, pci_ss_list_1001}, +#endif + {0x1002, pci_vendor_1002, pci_ss_list_1002}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1003, pci_vendor_1003, pci_ss_list_1003}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1004, pci_vendor_1004, pci_ss_list_1004}, +#endif + {0x1005, pci_vendor_1005, pci_ss_list_1005}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1006, pci_vendor_1006, pci_ss_list_1006}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1007, pci_vendor_1007, pci_ss_list_1007}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1008, pci_vendor_1008, pci_ss_list_1008}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x100a, pci_vendor_100a, pci_ss_list_100a}, +#endif + {0x100b, pci_vendor_100b, pci_ss_list_100b}, + {0x100c, pci_vendor_100c, pci_ss_list_100c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x100d, pci_vendor_100d, pci_ss_list_100d}, +#endif + {0x100e, pci_vendor_100e, pci_ss_list_100e}, + {0x1010, pci_vendor_1010, pci_ss_list_1010}, + {0x1011, pci_vendor_1011, pci_ss_list_1011}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1012, pci_vendor_1012, pci_ss_list_1012}, +#endif + {0x1013, pci_vendor_1013, pci_ss_list_1013}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1014, pci_vendor_1014, pci_ss_list_1014}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1015, pci_vendor_1015, pci_ss_list_1015}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1016, pci_vendor_1016, pci_ss_list_1016}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1017, pci_vendor_1017, pci_ss_list_1017}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1018, pci_vendor_1018, pci_ss_list_1018}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1019, pci_vendor_1019, pci_ss_list_1019}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101a, pci_vendor_101a, pci_ss_list_101a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101b, pci_vendor_101b, pci_ss_list_101b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101c, pci_vendor_101c, pci_ss_list_101c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101e, pci_vendor_101e, pci_ss_list_101e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101f, pci_vendor_101f, pci_ss_list_101f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1020, pci_vendor_1020, pci_ss_list_1020}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1021, pci_vendor_1021, pci_ss_list_1021}, +#endif + {0x1022, pci_vendor_1022, pci_ss_list_1022}, + {0x1023, pci_vendor_1023, pci_ss_list_1023}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1024, pci_vendor_1024, pci_ss_list_1024}, +#endif + {0x1025, pci_vendor_1025, pci_ss_list_1025}, + {0x1028, pci_vendor_1028, pci_ss_list_1028}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1029, pci_vendor_1029, pci_ss_list_1029}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102a, pci_vendor_102a, pci_ss_list_102a}, +#endif + {0x102b, pci_vendor_102b, pci_ss_list_102b}, + {0x102c, pci_vendor_102c, pci_ss_list_102c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102d, pci_vendor_102d, pci_ss_list_102d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102e, pci_vendor_102e, pci_ss_list_102e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102f, pci_vendor_102f, pci_ss_list_102f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1030, pci_vendor_1030, pci_ss_list_1030}, +#endif + {0x1031, pci_vendor_1031, pci_ss_list_1031}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1032, pci_vendor_1032, pci_ss_list_1032}, +#endif + {0x1033, pci_vendor_1033, pci_ss_list_1033}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1034, pci_vendor_1034, pci_ss_list_1034}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1035, pci_vendor_1035, pci_ss_list_1035}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1036, pci_vendor_1036, pci_ss_list_1036}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1037, pci_vendor_1037, pci_ss_list_1037}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1038, pci_vendor_1038, pci_ss_list_1038}, +#endif + {0x1039, pci_vendor_1039, pci_ss_list_1039}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103a, pci_vendor_103a, pci_ss_list_103a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103b, pci_vendor_103b, pci_ss_list_103b}, +#endif + {0x103c, pci_vendor_103c, pci_ss_list_103c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103e, pci_vendor_103e, pci_ss_list_103e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103f, pci_vendor_103f, pci_ss_list_103f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1040, pci_vendor_1040, pci_ss_list_1040}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1041, pci_vendor_1041, pci_ss_list_1041}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1042, pci_vendor_1042, pci_ss_list_1042}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1043, pci_vendor_1043, pci_ss_list_1043}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1044, pci_vendor_1044, pci_ss_list_1044}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1045, pci_vendor_1045, pci_ss_list_1045}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1046, pci_vendor_1046, pci_ss_list_1046}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1047, pci_vendor_1047, pci_ss_list_1047}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1048, pci_vendor_1048, pci_ss_list_1048}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1049, pci_vendor_1049, pci_ss_list_1049}, +#endif + {0x104a, pci_vendor_104a, pci_ss_list_104a}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x104b, pci_vendor_104b, pci_ss_list_104b}, +#endif + {0x104c, pci_vendor_104c, pci_ss_list_104c}, + {0x104d, pci_vendor_104d, pci_ss_list_104d}, + {0x104e, pci_vendor_104e, pci_ss_list_104e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x104f, pci_vendor_104f, pci_ss_list_104f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1050, pci_vendor_1050, pci_ss_list_1050}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1051, pci_vendor_1051, pci_ss_list_1051}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1052, pci_vendor_1052, pci_ss_list_1052}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1053, pci_vendor_1053, pci_ss_list_1053}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1054, pci_vendor_1054, pci_ss_list_1054}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1055, pci_vendor_1055, pci_ss_list_1055}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1056, pci_vendor_1056, pci_ss_list_1056}, +#endif + {0x1057, pci_vendor_1057, pci_ss_list_1057}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1058, pci_vendor_1058, pci_ss_list_1058}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1059, pci_vendor_1059, pci_ss_list_1059}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105a, pci_vendor_105a, pci_ss_list_105a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105b, pci_vendor_105b, pci_ss_list_105b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105c, pci_vendor_105c, pci_ss_list_105c}, +#endif + {0x105d, pci_vendor_105d, pci_ss_list_105d}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105e, pci_vendor_105e, pci_ss_list_105e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105f, pci_vendor_105f, pci_ss_list_105f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1060, pci_vendor_1060, pci_ss_list_1060}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1061, pci_vendor_1061, pci_ss_list_1061}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1062, pci_vendor_1062, pci_ss_list_1062}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1063, pci_vendor_1063, pci_ss_list_1063}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1064, pci_vendor_1064, pci_ss_list_1064}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1065, pci_vendor_1065, pci_ss_list_1065}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1066, pci_vendor_1066, pci_ss_list_1066}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1067, pci_vendor_1067, pci_ss_list_1067}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1068, pci_vendor_1068, pci_ss_list_1068}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1069, pci_vendor_1069, pci_ss_list_1069}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106a, pci_vendor_106a, pci_ss_list_106a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106b, pci_vendor_106b, pci_ss_list_106b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106c, pci_vendor_106c, pci_ss_list_106c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106d, pci_vendor_106d, pci_ss_list_106d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106e, pci_vendor_106e, pci_ss_list_106e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106f, pci_vendor_106f, pci_ss_list_106f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1070, pci_vendor_1070, pci_ss_list_1070}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1071, pci_vendor_1071, pci_ss_list_1071}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1072, pci_vendor_1072, pci_ss_list_1072}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1073, pci_vendor_1073, pci_ss_list_1073}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1074, pci_vendor_1074, pci_ss_list_1074}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1075, pci_vendor_1075, pci_ss_list_1075}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1076, pci_vendor_1076, pci_ss_list_1076}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1077, pci_vendor_1077, pci_ss_list_1077}, +#endif + {0x1078, pci_vendor_1078, pci_ss_list_1078}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1079, pci_vendor_1079, pci_ss_list_1079}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107a, pci_vendor_107a, pci_ss_list_107a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107b, pci_vendor_107b, pci_ss_list_107b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107c, pci_vendor_107c, pci_ss_list_107c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107d, pci_vendor_107d, pci_ss_list_107d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107e, pci_vendor_107e, pci_ss_list_107e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107f, pci_vendor_107f, pci_ss_list_107f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1080, pci_vendor_1080, pci_ss_list_1080}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1081, pci_vendor_1081, pci_ss_list_1081}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1082, pci_vendor_1082, pci_ss_list_1082}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1083, pci_vendor_1083, pci_ss_list_1083}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1084, pci_vendor_1084, pci_ss_list_1084}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1085, pci_vendor_1085, pci_ss_list_1085}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1086, pci_vendor_1086, pci_ss_list_1086}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1087, pci_vendor_1087, pci_ss_list_1087}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1088, pci_vendor_1088, pci_ss_list_1088}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1089, pci_vendor_1089, pci_ss_list_1089}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108a, pci_vendor_108a, pci_ss_list_108a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108c, pci_vendor_108c, pci_ss_list_108c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108d, pci_vendor_108d, pci_ss_list_108d}, +#endif + {0x108e, pci_vendor_108e, pci_ss_list_108e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108f, pci_vendor_108f, pci_ss_list_108f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1090, pci_vendor_1090, pci_ss_list_1090}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1091, pci_vendor_1091, pci_ss_list_1091}, +#endif + {0x1092, pci_vendor_1092, pci_ss_list_1092}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1093, pci_vendor_1093, pci_ss_list_1093}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1094, pci_vendor_1094, pci_ss_list_1094}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1095, pci_vendor_1095, pci_ss_list_1095}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1096, pci_vendor_1096, pci_ss_list_1096}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1097, pci_vendor_1097, pci_ss_list_1097}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1098, pci_vendor_1098, pci_ss_list_1098}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1099, pci_vendor_1099, pci_ss_list_1099}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109a, pci_vendor_109a, pci_ss_list_109a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109b, pci_vendor_109b, pci_ss_list_109b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109c, pci_vendor_109c, pci_ss_list_109c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109d, pci_vendor_109d, pci_ss_list_109d}, +#endif + {0x109e, pci_vendor_109e, pci_ss_list_109e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109f, pci_vendor_109f, pci_ss_list_109f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a0, pci_vendor_10a0, pci_ss_list_10a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a1, pci_vendor_10a1, pci_ss_list_10a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a2, pci_vendor_10a2, pci_ss_list_10a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a3, pci_vendor_10a3, pci_ss_list_10a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a4, pci_vendor_10a4, pci_ss_list_10a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a5, pci_vendor_10a5, pci_ss_list_10a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a6, pci_vendor_10a6, pci_ss_list_10a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a7, pci_vendor_10a7, pci_ss_list_10a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a8, pci_vendor_10a8, pci_ss_list_10a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a9, pci_vendor_10a9, pci_ss_list_10a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10aa, pci_vendor_10aa, pci_ss_list_10aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ab, pci_vendor_10ab, pci_ss_list_10ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ac, pci_vendor_10ac, pci_ss_list_10ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ad, pci_vendor_10ad, pci_ss_list_10ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ae, pci_vendor_10ae, pci_ss_list_10ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10af, pci_vendor_10af, pci_ss_list_10af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b0, pci_vendor_10b0, pci_ss_list_10b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b1, pci_vendor_10b1, pci_ss_list_10b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b2, pci_vendor_10b2, pci_ss_list_10b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b3, pci_vendor_10b3, pci_ss_list_10b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b4, pci_vendor_10b4, pci_ss_list_10b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b5, pci_vendor_10b5, pci_ss_list_10b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b6, pci_vendor_10b6, pci_ss_list_10b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b7, pci_vendor_10b7, pci_ss_list_10b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b8, pci_vendor_10b8, pci_ss_list_10b8}, +#endif + {0x10b9, pci_vendor_10b9, pci_ss_list_10b9}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ba, pci_vendor_10ba, pci_ss_list_10ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bb, pci_vendor_10bb, pci_ss_list_10bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bc, pci_vendor_10bc, pci_ss_list_10bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bd, pci_vendor_10bd, pci_ss_list_10bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10be, pci_vendor_10be, pci_ss_list_10be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bf, pci_vendor_10bf, pci_ss_list_10bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c0, pci_vendor_10c0, pci_ss_list_10c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c1, pci_vendor_10c1, pci_ss_list_10c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c2, pci_vendor_10c2, pci_ss_list_10c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c3, pci_vendor_10c3, pci_ss_list_10c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c4, pci_vendor_10c4, pci_ss_list_10c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c5, pci_vendor_10c5, pci_ss_list_10c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c6, pci_vendor_10c6, pci_ss_list_10c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c7, pci_vendor_10c7, pci_ss_list_10c7}, +#endif + {0x10c8, pci_vendor_10c8, pci_ss_list_10c8}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c9, pci_vendor_10c9, pci_ss_list_10c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ca, pci_vendor_10ca, pci_ss_list_10ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cb, pci_vendor_10cb, pci_ss_list_10cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cc, pci_vendor_10cc, pci_ss_list_10cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cd, pci_vendor_10cd, pci_ss_list_10cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ce, pci_vendor_10ce, pci_ss_list_10ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cf, pci_vendor_10cf, pci_ss_list_10cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d0, pci_vendor_10d0, pci_ss_list_10d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d1, pci_vendor_10d1, pci_ss_list_10d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d2, pci_vendor_10d2, pci_ss_list_10d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d3, pci_vendor_10d3, pci_ss_list_10d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d4, pci_vendor_10d4, pci_ss_list_10d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d5, pci_vendor_10d5, pci_ss_list_10d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d6, pci_vendor_10d6, pci_ss_list_10d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d7, pci_vendor_10d7, pci_ss_list_10d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d8, pci_vendor_10d8, pci_ss_list_10d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d9, pci_vendor_10d9, pci_ss_list_10d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10da, pci_vendor_10da, pci_ss_list_10da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10db, pci_vendor_10db, pci_ss_list_10db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10dc, pci_vendor_10dc, pci_ss_list_10dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10dd, pci_vendor_10dd, pci_ss_list_10dd}, +#endif + {0x10de, pci_vendor_10de, pci_ss_list_10de}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10df, pci_vendor_10df, pci_ss_list_10df}, +#endif + {0x10e0, pci_vendor_10e0, pci_ss_list_10e0}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e1, pci_vendor_10e1, pci_ss_list_10e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e2, pci_vendor_10e2, pci_ss_list_10e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e3, pci_vendor_10e3, pci_ss_list_10e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e4, pci_vendor_10e4, pci_ss_list_10e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e5, pci_vendor_10e5, pci_ss_list_10e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e6, pci_vendor_10e6, pci_ss_list_10e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e7, pci_vendor_10e7, pci_ss_list_10e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e8, pci_vendor_10e8, pci_ss_list_10e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e9, pci_vendor_10e9, pci_ss_list_10e9}, +#endif + {0x10ea, pci_vendor_10ea, pci_ss_list_10ea}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10eb, pci_vendor_10eb, pci_ss_list_10eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ec, pci_vendor_10ec, pci_ss_list_10ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ed, pci_vendor_10ed, pci_ss_list_10ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ee, pci_vendor_10ee, pci_ss_list_10ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ef, pci_vendor_10ef, pci_ss_list_10ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f0, pci_vendor_10f0, pci_ss_list_10f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f1, pci_vendor_10f1, pci_ss_list_10f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f2, pci_vendor_10f2, pci_ss_list_10f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f3, pci_vendor_10f3, pci_ss_list_10f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f4, pci_vendor_10f4, pci_ss_list_10f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f5, pci_vendor_10f5, pci_ss_list_10f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f6, pci_vendor_10f6, pci_ss_list_10f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f7, pci_vendor_10f7, pci_ss_list_10f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f8, pci_vendor_10f8, pci_ss_list_10f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f9, pci_vendor_10f9, pci_ss_list_10f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fa, pci_vendor_10fa, pci_ss_list_10fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fb, pci_vendor_10fb, pci_ss_list_10fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fc, pci_vendor_10fc, pci_ss_list_10fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fd, pci_vendor_10fd, pci_ss_list_10fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fe, pci_vendor_10fe, pci_ss_list_10fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ff, pci_vendor_10ff, pci_ss_list_10ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1100, pci_vendor_1100, pci_ss_list_1100}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1101, pci_vendor_1101, pci_ss_list_1101}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1102, pci_vendor_1102, pci_ss_list_1102}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1103, pci_vendor_1103, pci_ss_list_1103}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1104, pci_vendor_1104, pci_ss_list_1104}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1105, pci_vendor_1105, pci_ss_list_1105}, +#endif + {0x1106, pci_vendor_1106, pci_ss_list_1106}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1107, pci_vendor_1107, pci_ss_list_1107}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1108, pci_vendor_1108, pci_ss_list_1108}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1109, pci_vendor_1109, pci_ss_list_1109}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110a, pci_vendor_110a, pci_ss_list_110a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110b, pci_vendor_110b, pci_ss_list_110b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110c, pci_vendor_110c, pci_ss_list_110c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110d, pci_vendor_110d, pci_ss_list_110d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110e, pci_vendor_110e, pci_ss_list_110e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110f, pci_vendor_110f, pci_ss_list_110f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1110, pci_vendor_1110, pci_ss_list_1110}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1111, pci_vendor_1111, pci_ss_list_1111}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1112, pci_vendor_1112, pci_ss_list_1112}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1113, pci_vendor_1113, pci_ss_list_1113}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1114, pci_vendor_1114, pci_ss_list_1114}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1115, pci_vendor_1115, pci_ss_list_1115}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1116, pci_vendor_1116, pci_ss_list_1116}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1117, pci_vendor_1117, pci_ss_list_1117}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1118, pci_vendor_1118, pci_ss_list_1118}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1119, pci_vendor_1119, pci_ss_list_1119}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111a, pci_vendor_111a, pci_ss_list_111a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111b, pci_vendor_111b, pci_ss_list_111b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111c, pci_vendor_111c, pci_ss_list_111c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111d, pci_vendor_111d, pci_ss_list_111d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111e, pci_vendor_111e, pci_ss_list_111e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111f, pci_vendor_111f, pci_ss_list_111f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1120, pci_vendor_1120, pci_ss_list_1120}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1121, pci_vendor_1121, pci_ss_list_1121}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1122, pci_vendor_1122, pci_ss_list_1122}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1123, pci_vendor_1123, pci_ss_list_1123}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1124, pci_vendor_1124, pci_ss_list_1124}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1125, pci_vendor_1125, pci_ss_list_1125}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1126, pci_vendor_1126, pci_ss_list_1126}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1127, pci_vendor_1127, pci_ss_list_1127}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1129, pci_vendor_1129, pci_ss_list_1129}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112a, pci_vendor_112a, pci_ss_list_112a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112b, pci_vendor_112b, pci_ss_list_112b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112c, pci_vendor_112c, pci_ss_list_112c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112d, pci_vendor_112d, pci_ss_list_112d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112e, pci_vendor_112e, pci_ss_list_112e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112f, pci_vendor_112f, pci_ss_list_112f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1130, pci_vendor_1130, pci_ss_list_1130}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1131, pci_vendor_1131, pci_ss_list_1131}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1132, pci_vendor_1132, pci_ss_list_1132}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1133, pci_vendor_1133, pci_ss_list_1133}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1134, pci_vendor_1134, pci_ss_list_1134}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1135, pci_vendor_1135, pci_ss_list_1135}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1136, pci_vendor_1136, pci_ss_list_1136}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1137, pci_vendor_1137, pci_ss_list_1137}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1138, pci_vendor_1138, pci_ss_list_1138}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1139, pci_vendor_1139, pci_ss_list_1139}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113a, pci_vendor_113a, pci_ss_list_113a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113b, pci_vendor_113b, pci_ss_list_113b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113c, pci_vendor_113c, pci_ss_list_113c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113d, pci_vendor_113d, pci_ss_list_113d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113e, pci_vendor_113e, pci_ss_list_113e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113f, pci_vendor_113f, pci_ss_list_113f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1140, pci_vendor_1140, pci_ss_list_1140}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1141, pci_vendor_1141, pci_ss_list_1141}, +#endif + {0x1142, pci_vendor_1142, pci_ss_list_1142}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1143, pci_vendor_1143, pci_ss_list_1143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1144, pci_vendor_1144, pci_ss_list_1144}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1145, pci_vendor_1145, pci_ss_list_1145}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1146, pci_vendor_1146, pci_ss_list_1146}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1147, pci_vendor_1147, pci_ss_list_1147}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1148, pci_vendor_1148, pci_ss_list_1148}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1149, pci_vendor_1149, pci_ss_list_1149}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114a, pci_vendor_114a, pci_ss_list_114a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114b, pci_vendor_114b, pci_ss_list_114b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114c, pci_vendor_114c, pci_ss_list_114c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114d, pci_vendor_114d, pci_ss_list_114d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114e, pci_vendor_114e, pci_ss_list_114e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114f, pci_vendor_114f, pci_ss_list_114f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1150, pci_vendor_1150, pci_ss_list_1150}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1151, pci_vendor_1151, pci_ss_list_1151}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1152, pci_vendor_1152, pci_ss_list_1152}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1153, pci_vendor_1153, pci_ss_list_1153}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1154, pci_vendor_1154, pci_ss_list_1154}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1155, pci_vendor_1155, pci_ss_list_1155}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1156, pci_vendor_1156, pci_ss_list_1156}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1157, pci_vendor_1157, pci_ss_list_1157}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1158, pci_vendor_1158, pci_ss_list_1158}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1159, pci_vendor_1159, pci_ss_list_1159}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115a, pci_vendor_115a, pci_ss_list_115a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115b, pci_vendor_115b, pci_ss_list_115b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115c, pci_vendor_115c, pci_ss_list_115c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115d, pci_vendor_115d, pci_ss_list_115d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115e, pci_vendor_115e, pci_ss_list_115e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115f, pci_vendor_115f, pci_ss_list_115f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1160, pci_vendor_1160, pci_ss_list_1160}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1161, pci_vendor_1161, pci_ss_list_1161}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1162, pci_vendor_1162, pci_ss_list_1162}, +#endif + {0x1163, pci_vendor_1163, pci_ss_list_1163}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1164, pci_vendor_1164, pci_ss_list_1164}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1165, pci_vendor_1165, pci_ss_list_1165}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1166, pci_vendor_1166, pci_ss_list_1166}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1167, pci_vendor_1167, pci_ss_list_1167}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1168, pci_vendor_1168, pci_ss_list_1168}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1169, pci_vendor_1169, pci_ss_list_1169}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116a, pci_vendor_116a, pci_ss_list_116a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116b, pci_vendor_116b, pci_ss_list_116b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116c, pci_vendor_116c, pci_ss_list_116c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116d, pci_vendor_116d, pci_ss_list_116d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116e, pci_vendor_116e, pci_ss_list_116e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116f, pci_vendor_116f, pci_ss_list_116f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1170, pci_vendor_1170, pci_ss_list_1170}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1171, pci_vendor_1171, pci_ss_list_1171}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1172, pci_vendor_1172, pci_ss_list_1172}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1173, pci_vendor_1173, pci_ss_list_1173}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1174, pci_vendor_1174, pci_ss_list_1174}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1175, pci_vendor_1175, pci_ss_list_1175}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1176, pci_vendor_1176, pci_ss_list_1176}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1177, pci_vendor_1177, pci_ss_list_1177}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1178, pci_vendor_1178, pci_ss_list_1178}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1179, pci_vendor_1179, pci_ss_list_1179}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117a, pci_vendor_117a, pci_ss_list_117a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117b, pci_vendor_117b, pci_ss_list_117b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117c, pci_vendor_117c, pci_ss_list_117c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117d, pci_vendor_117d, pci_ss_list_117d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117e, pci_vendor_117e, pci_ss_list_117e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117f, pci_vendor_117f, pci_ss_list_117f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1180, pci_vendor_1180, pci_ss_list_1180}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1181, pci_vendor_1181, pci_ss_list_1181}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1183, pci_vendor_1183, pci_ss_list_1183}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1184, pci_vendor_1184, pci_ss_list_1184}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1185, pci_vendor_1185, pci_ss_list_1185}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1186, pci_vendor_1186, pci_ss_list_1186}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1187, pci_vendor_1187, pci_ss_list_1187}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1188, pci_vendor_1188, pci_ss_list_1188}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1189, pci_vendor_1189, pci_ss_list_1189}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118a, pci_vendor_118a, pci_ss_list_118a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118b, pci_vendor_118b, pci_ss_list_118b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118c, pci_vendor_118c, pci_ss_list_118c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118d, pci_vendor_118d, pci_ss_list_118d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118e, pci_vendor_118e, pci_ss_list_118e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118f, pci_vendor_118f, pci_ss_list_118f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1190, pci_vendor_1190, pci_ss_list_1190}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1191, pci_vendor_1191, pci_ss_list_1191}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1192, pci_vendor_1192, pci_ss_list_1192}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1193, pci_vendor_1193, pci_ss_list_1193}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1194, pci_vendor_1194, pci_ss_list_1194}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1195, pci_vendor_1195, pci_ss_list_1195}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1196, pci_vendor_1196, pci_ss_list_1196}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1197, pci_vendor_1197, pci_ss_list_1197}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1198, pci_vendor_1198, pci_ss_list_1198}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1199, pci_vendor_1199, pci_ss_list_1199}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119a, pci_vendor_119a, pci_ss_list_119a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119b, pci_vendor_119b, pci_ss_list_119b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119c, pci_vendor_119c, pci_ss_list_119c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119d, pci_vendor_119d, pci_ss_list_119d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119e, pci_vendor_119e, pci_ss_list_119e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119f, pci_vendor_119f, pci_ss_list_119f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a0, pci_vendor_11a0, pci_ss_list_11a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a1, pci_vendor_11a1, pci_ss_list_11a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a2, pci_vendor_11a2, pci_ss_list_11a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a3, pci_vendor_11a3, pci_ss_list_11a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a4, pci_vendor_11a4, pci_ss_list_11a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a5, pci_vendor_11a5, pci_ss_list_11a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a6, pci_vendor_11a6, pci_ss_list_11a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a7, pci_vendor_11a7, pci_ss_list_11a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a8, pci_vendor_11a8, pci_ss_list_11a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a9, pci_vendor_11a9, pci_ss_list_11a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11aa, pci_vendor_11aa, pci_ss_list_11aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ab, pci_vendor_11ab, pci_ss_list_11ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ac, pci_vendor_11ac, pci_ss_list_11ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ad, pci_vendor_11ad, pci_ss_list_11ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ae, pci_vendor_11ae, pci_ss_list_11ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11af, pci_vendor_11af, pci_ss_list_11af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b0, pci_vendor_11b0, pci_ss_list_11b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b1, pci_vendor_11b1, pci_ss_list_11b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b2, pci_vendor_11b2, pci_ss_list_11b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b3, pci_vendor_11b3, pci_ss_list_11b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b4, pci_vendor_11b4, pci_ss_list_11b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b5, pci_vendor_11b5, pci_ss_list_11b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b6, pci_vendor_11b6, pci_ss_list_11b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b7, pci_vendor_11b7, pci_ss_list_11b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b8, pci_vendor_11b8, pci_ss_list_11b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b9, pci_vendor_11b9, pci_ss_list_11b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ba, pci_vendor_11ba, pci_ss_list_11ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bb, pci_vendor_11bb, pci_ss_list_11bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bc, pci_vendor_11bc, pci_ss_list_11bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bd, pci_vendor_11bd, pci_ss_list_11bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11be, pci_vendor_11be, pci_ss_list_11be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bf, pci_vendor_11bf, pci_ss_list_11bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c0, pci_vendor_11c0, pci_ss_list_11c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c1, pci_vendor_11c1, pci_ss_list_11c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c2, pci_vendor_11c2, pci_ss_list_11c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c3, pci_vendor_11c3, pci_ss_list_11c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c4, pci_vendor_11c4, pci_ss_list_11c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c5, pci_vendor_11c5, pci_ss_list_11c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c6, pci_vendor_11c6, pci_ss_list_11c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c7, pci_vendor_11c7, pci_ss_list_11c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c8, pci_vendor_11c8, pci_ss_list_11c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c9, pci_vendor_11c9, pci_ss_list_11c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ca, pci_vendor_11ca, pci_ss_list_11ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cb, pci_vendor_11cb, pci_ss_list_11cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cc, pci_vendor_11cc, pci_ss_list_11cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cd, pci_vendor_11cd, pci_ss_list_11cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ce, pci_vendor_11ce, pci_ss_list_11ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cf, pci_vendor_11cf, pci_ss_list_11cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d0, pci_vendor_11d0, pci_ss_list_11d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d1, pci_vendor_11d1, pci_ss_list_11d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d2, pci_vendor_11d2, pci_ss_list_11d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d3, pci_vendor_11d3, pci_ss_list_11d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d4, pci_vendor_11d4, pci_ss_list_11d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d5, pci_vendor_11d5, pci_ss_list_11d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d6, pci_vendor_11d6, pci_ss_list_11d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d7, pci_vendor_11d7, pci_ss_list_11d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d8, pci_vendor_11d8, pci_ss_list_11d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d9, pci_vendor_11d9, pci_ss_list_11d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11da, pci_vendor_11da, pci_ss_list_11da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11db, pci_vendor_11db, pci_ss_list_11db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11dc, pci_vendor_11dc, pci_ss_list_11dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11dd, pci_vendor_11dd, pci_ss_list_11dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11de, pci_vendor_11de, pci_ss_list_11de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11df, pci_vendor_11df, pci_ss_list_11df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e0, pci_vendor_11e0, pci_ss_list_11e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e1, pci_vendor_11e1, pci_ss_list_11e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e2, pci_vendor_11e2, pci_ss_list_11e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e3, pci_vendor_11e3, pci_ss_list_11e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e4, pci_vendor_11e4, pci_ss_list_11e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e5, pci_vendor_11e5, pci_ss_list_11e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e6, pci_vendor_11e6, pci_ss_list_11e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e7, pci_vendor_11e7, pci_ss_list_11e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e8, pci_vendor_11e8, pci_ss_list_11e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e9, pci_vendor_11e9, pci_ss_list_11e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ea, pci_vendor_11ea, pci_ss_list_11ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11eb, pci_vendor_11eb, pci_ss_list_11eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ec, pci_vendor_11ec, pci_ss_list_11ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ed, pci_vendor_11ed, pci_ss_list_11ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ee, pci_vendor_11ee, pci_ss_list_11ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ef, pci_vendor_11ef, pci_ss_list_11ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f0, pci_vendor_11f0, pci_ss_list_11f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f1, pci_vendor_11f1, pci_ss_list_11f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f2, pci_vendor_11f2, pci_ss_list_11f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f3, pci_vendor_11f3, pci_ss_list_11f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f4, pci_vendor_11f4, pci_ss_list_11f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f5, pci_vendor_11f5, pci_ss_list_11f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f6, pci_vendor_11f6, pci_ss_list_11f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f7, pci_vendor_11f7, pci_ss_list_11f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f8, pci_vendor_11f8, pci_ss_list_11f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f9, pci_vendor_11f9, pci_ss_list_11f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fa, pci_vendor_11fa, pci_ss_list_11fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fb, pci_vendor_11fb, pci_ss_list_11fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fc, pci_vendor_11fc, pci_ss_list_11fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fd, pci_vendor_11fd, pci_ss_list_11fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fe, pci_vendor_11fe, pci_ss_list_11fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ff, pci_vendor_11ff, pci_ss_list_11ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1200, pci_vendor_1200, pci_ss_list_1200}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1201, pci_vendor_1201, pci_ss_list_1201}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1202, pci_vendor_1202, pci_ss_list_1202}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1203, pci_vendor_1203, pci_ss_list_1203}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1204, pci_vendor_1204, pci_ss_list_1204}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1205, pci_vendor_1205, pci_ss_list_1205}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1206, pci_vendor_1206, pci_ss_list_1206}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1208, pci_vendor_1208, pci_ss_list_1208}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1209, pci_vendor_1209, pci_ss_list_1209}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120a, pci_vendor_120a, pci_ss_list_120a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120b, pci_vendor_120b, pci_ss_list_120b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120c, pci_vendor_120c, pci_ss_list_120c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120d, pci_vendor_120d, pci_ss_list_120d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120e, pci_vendor_120e, pci_ss_list_120e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120f, pci_vendor_120f, pci_ss_list_120f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1210, pci_vendor_1210, pci_ss_list_1210}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1211, pci_vendor_1211, pci_ss_list_1211}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1212, pci_vendor_1212, pci_ss_list_1212}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1213, pci_vendor_1213, pci_ss_list_1213}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1214, pci_vendor_1214, pci_ss_list_1214}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1215, pci_vendor_1215, pci_ss_list_1215}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1216, pci_vendor_1216, pci_ss_list_1216}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1217, pci_vendor_1217, pci_ss_list_1217}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1218, pci_vendor_1218, pci_ss_list_1218}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1219, pci_vendor_1219, pci_ss_list_1219}, +#endif + {0x121a, pci_vendor_121a, pci_ss_list_121a}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121b, pci_vendor_121b, pci_ss_list_121b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121c, pci_vendor_121c, pci_ss_list_121c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121d, pci_vendor_121d, pci_ss_list_121d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121e, pci_vendor_121e, pci_ss_list_121e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121f, pci_vendor_121f, pci_ss_list_121f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1220, pci_vendor_1220, pci_ss_list_1220}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1221, pci_vendor_1221, pci_ss_list_1221}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1222, pci_vendor_1222, pci_ss_list_1222}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1223, pci_vendor_1223, pci_ss_list_1223}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1224, pci_vendor_1224, pci_ss_list_1224}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1225, pci_vendor_1225, pci_ss_list_1225}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1227, pci_vendor_1227, pci_ss_list_1227}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1228, pci_vendor_1228, pci_ss_list_1228}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1229, pci_vendor_1229, pci_ss_list_1229}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122a, pci_vendor_122a, pci_ss_list_122a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122b, pci_vendor_122b, pci_ss_list_122b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122c, pci_vendor_122c, pci_ss_list_122c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122d, pci_vendor_122d, pci_ss_list_122d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122e, pci_vendor_122e, pci_ss_list_122e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122f, pci_vendor_122f, pci_ss_list_122f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1230, pci_vendor_1230, pci_ss_list_1230}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1231, pci_vendor_1231, pci_ss_list_1231}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1232, pci_vendor_1232, pci_ss_list_1232}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1233, pci_vendor_1233, pci_ss_list_1233}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1234, pci_vendor_1234, pci_ss_list_1234}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1235, pci_vendor_1235, pci_ss_list_1235}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1236, pci_vendor_1236, pci_ss_list_1236}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1237, pci_vendor_1237, pci_ss_list_1237}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1238, pci_vendor_1238, pci_ss_list_1238}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1239, pci_vendor_1239, pci_ss_list_1239}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123a, pci_vendor_123a, pci_ss_list_123a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123b, pci_vendor_123b, pci_ss_list_123b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123c, pci_vendor_123c, pci_ss_list_123c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123d, pci_vendor_123d, pci_ss_list_123d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123e, pci_vendor_123e, pci_ss_list_123e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123f, pci_vendor_123f, pci_ss_list_123f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1240, pci_vendor_1240, pci_ss_list_1240}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1241, pci_vendor_1241, pci_ss_list_1241}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1242, pci_vendor_1242, pci_ss_list_1242}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1243, pci_vendor_1243, pci_ss_list_1243}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1244, pci_vendor_1244, pci_ss_list_1244}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1245, pci_vendor_1245, pci_ss_list_1245}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1246, pci_vendor_1246, pci_ss_list_1246}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1247, pci_vendor_1247, pci_ss_list_1247}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1248, pci_vendor_1248, pci_ss_list_1248}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1249, pci_vendor_1249, pci_ss_list_1249}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124a, pci_vendor_124a, pci_ss_list_124a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124b, pci_vendor_124b, pci_ss_list_124b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124c, pci_vendor_124c, pci_ss_list_124c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124d, pci_vendor_124d, pci_ss_list_124d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124e, pci_vendor_124e, pci_ss_list_124e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124f, pci_vendor_124f, pci_ss_list_124f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1250, pci_vendor_1250, pci_ss_list_1250}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1251, pci_vendor_1251, pci_ss_list_1251}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1253, pci_vendor_1253, pci_ss_list_1253}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1254, pci_vendor_1254, pci_ss_list_1254}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1255, pci_vendor_1255, pci_ss_list_1255}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1256, pci_vendor_1256, pci_ss_list_1256}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1257, pci_vendor_1257, pci_ss_list_1257}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1258, pci_vendor_1258, pci_ss_list_1258}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1259, pci_vendor_1259, pci_ss_list_1259}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125a, pci_vendor_125a, pci_ss_list_125a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125b, pci_vendor_125b, pci_ss_list_125b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125c, pci_vendor_125c, pci_ss_list_125c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125d, pci_vendor_125d, pci_ss_list_125d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125e, pci_vendor_125e, pci_ss_list_125e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125f, pci_vendor_125f, pci_ss_list_125f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1260, pci_vendor_1260, pci_ss_list_1260}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1261, pci_vendor_1261, pci_ss_list_1261}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1262, pci_vendor_1262, pci_ss_list_1262}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1263, pci_vendor_1263, pci_ss_list_1263}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1264, pci_vendor_1264, pci_ss_list_1264}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1265, pci_vendor_1265, pci_ss_list_1265}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1266, pci_vendor_1266, pci_ss_list_1266}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1267, pci_vendor_1267, pci_ss_list_1267}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1268, pci_vendor_1268, pci_ss_list_1268}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1269, pci_vendor_1269, pci_ss_list_1269}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126a, pci_vendor_126a, pci_ss_list_126a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126b, pci_vendor_126b, pci_ss_list_126b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126c, pci_vendor_126c, pci_ss_list_126c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126d, pci_vendor_126d, pci_ss_list_126d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126e, pci_vendor_126e, pci_ss_list_126e}, +#endif + {0x126f, pci_vendor_126f, pci_ss_list_126f}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1270, pci_vendor_1270, pci_ss_list_1270}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1271, pci_vendor_1271, pci_ss_list_1271}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1272, pci_vendor_1272, pci_ss_list_1272}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1273, pci_vendor_1273, pci_ss_list_1273}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1274, pci_vendor_1274, pci_ss_list_1274}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1275, pci_vendor_1275, pci_ss_list_1275}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1276, pci_vendor_1276, pci_ss_list_1276}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1277, pci_vendor_1277, pci_ss_list_1277}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1278, pci_vendor_1278, pci_ss_list_1278}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1279, pci_vendor_1279, pci_ss_list_1279}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127a, pci_vendor_127a, pci_ss_list_127a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127b, pci_vendor_127b, pci_ss_list_127b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127c, pci_vendor_127c, pci_ss_list_127c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127d, pci_vendor_127d, pci_ss_list_127d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127e, pci_vendor_127e, pci_ss_list_127e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127f, pci_vendor_127f, pci_ss_list_127f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1280, pci_vendor_1280, pci_ss_list_1280}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1281, pci_vendor_1281, pci_ss_list_1281}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1282, pci_vendor_1282, pci_ss_list_1282}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1283, pci_vendor_1283, pci_ss_list_1283}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1284, pci_vendor_1284, pci_ss_list_1284}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1285, pci_vendor_1285, pci_ss_list_1285}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1286, pci_vendor_1286, pci_ss_list_1286}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1287, pci_vendor_1287, pci_ss_list_1287}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1288, pci_vendor_1288, pci_ss_list_1288}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1289, pci_vendor_1289, pci_ss_list_1289}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128a, pci_vendor_128a, pci_ss_list_128a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128b, pci_vendor_128b, pci_ss_list_128b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128c, pci_vendor_128c, pci_ss_list_128c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128d, pci_vendor_128d, pci_ss_list_128d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128e, pci_vendor_128e, pci_ss_list_128e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128f, pci_vendor_128f, pci_ss_list_128f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1290, pci_vendor_1290, pci_ss_list_1290}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1291, pci_vendor_1291, pci_ss_list_1291}, +#endif + {0x1292, pci_vendor_1292, pci_ss_list_1292}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1293, pci_vendor_1293, pci_ss_list_1293}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1294, pci_vendor_1294, pci_ss_list_1294}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1295, pci_vendor_1295, pci_ss_list_1295}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1296, pci_vendor_1296, pci_ss_list_1296}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1297, pci_vendor_1297, pci_ss_list_1297}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1298, pci_vendor_1298, pci_ss_list_1298}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1299, pci_vendor_1299, pci_ss_list_1299}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129a, pci_vendor_129a, pci_ss_list_129a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129b, pci_vendor_129b, pci_ss_list_129b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129c, pci_vendor_129c, pci_ss_list_129c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129d, pci_vendor_129d, pci_ss_list_129d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129e, pci_vendor_129e, pci_ss_list_129e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129f, pci_vendor_129f, pci_ss_list_129f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a0, pci_vendor_12a0, pci_ss_list_12a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a1, pci_vendor_12a1, pci_ss_list_12a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a2, pci_vendor_12a2, pci_ss_list_12a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a3, pci_vendor_12a3, pci_ss_list_12a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a4, pci_vendor_12a4, pci_ss_list_12a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a5, pci_vendor_12a5, pci_ss_list_12a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a6, pci_vendor_12a6, pci_ss_list_12a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a7, pci_vendor_12a7, pci_ss_list_12a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a8, pci_vendor_12a8, pci_ss_list_12a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a9, pci_vendor_12a9, pci_ss_list_12a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12aa, pci_vendor_12aa, pci_ss_list_12aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ab, pci_vendor_12ab, pci_ss_list_12ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ac, pci_vendor_12ac, pci_ss_list_12ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ad, pci_vendor_12ad, pci_ss_list_12ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ae, pci_vendor_12ae, pci_ss_list_12ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12af, pci_vendor_12af, pci_ss_list_12af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b0, pci_vendor_12b0, pci_ss_list_12b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b1, pci_vendor_12b1, pci_ss_list_12b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b2, pci_vendor_12b2, pci_ss_list_12b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b3, pci_vendor_12b3, pci_ss_list_12b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b4, pci_vendor_12b4, pci_ss_list_12b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b5, pci_vendor_12b5, pci_ss_list_12b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b6, pci_vendor_12b6, pci_ss_list_12b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b7, pci_vendor_12b7, pci_ss_list_12b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b8, pci_vendor_12b8, pci_ss_list_12b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b9, pci_vendor_12b9, pci_ss_list_12b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ba, pci_vendor_12ba, pci_ss_list_12ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bb, pci_vendor_12bb, pci_ss_list_12bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bc, pci_vendor_12bc, pci_ss_list_12bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bd, pci_vendor_12bd, pci_ss_list_12bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12be, pci_vendor_12be, pci_ss_list_12be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bf, pci_vendor_12bf, pci_ss_list_12bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c0, pci_vendor_12c0, pci_ss_list_12c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c1, pci_vendor_12c1, pci_ss_list_12c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c2, pci_vendor_12c2, pci_ss_list_12c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c3, pci_vendor_12c3, pci_ss_list_12c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c4, pci_vendor_12c4, pci_ss_list_12c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c5, pci_vendor_12c5, pci_ss_list_12c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c6, pci_vendor_12c6, pci_ss_list_12c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c7, pci_vendor_12c7, pci_ss_list_12c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c8, pci_vendor_12c8, pci_ss_list_12c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c9, pci_vendor_12c9, pci_ss_list_12c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ca, pci_vendor_12ca, pci_ss_list_12ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cb, pci_vendor_12cb, pci_ss_list_12cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cc, pci_vendor_12cc, pci_ss_list_12cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cd, pci_vendor_12cd, pci_ss_list_12cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ce, pci_vendor_12ce, pci_ss_list_12ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cf, pci_vendor_12cf, pci_ss_list_12cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d0, pci_vendor_12d0, pci_ss_list_12d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d1, pci_vendor_12d1, pci_ss_list_12d1}, +#endif + {0x12d2, pci_vendor_12d2, pci_ss_list_12d2}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d3, pci_vendor_12d3, pci_ss_list_12d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d4, pci_vendor_12d4, pci_ss_list_12d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d5, pci_vendor_12d5, pci_ss_list_12d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d6, pci_vendor_12d6, pci_ss_list_12d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d7, pci_vendor_12d7, pci_ss_list_12d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d8, pci_vendor_12d8, pci_ss_list_12d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d9, pci_vendor_12d9, pci_ss_list_12d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12da, pci_vendor_12da, pci_ss_list_12da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12db, pci_vendor_12db, pci_ss_list_12db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12dc, pci_vendor_12dc, pci_ss_list_12dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12dd, pci_vendor_12dd, pci_ss_list_12dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12de, pci_vendor_12de, pci_ss_list_12de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12df, pci_vendor_12df, pci_ss_list_12df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e0, pci_vendor_12e0, pci_ss_list_12e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e1, pci_vendor_12e1, pci_ss_list_12e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e2, pci_vendor_12e2, pci_ss_list_12e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e3, pci_vendor_12e3, pci_ss_list_12e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e4, pci_vendor_12e4, pci_ss_list_12e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e5, pci_vendor_12e5, pci_ss_list_12e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e6, pci_vendor_12e6, pci_ss_list_12e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e7, pci_vendor_12e7, pci_ss_list_12e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e8, pci_vendor_12e8, pci_ss_list_12e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e9, pci_vendor_12e9, pci_ss_list_12e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ea, pci_vendor_12ea, pci_ss_list_12ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12eb, pci_vendor_12eb, pci_ss_list_12eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ec, pci_vendor_12ec, pci_ss_list_12ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ed, pci_vendor_12ed, pci_ss_list_12ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ee, pci_vendor_12ee, pci_ss_list_12ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ef, pci_vendor_12ef, pci_ss_list_12ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f0, pci_vendor_12f0, pci_ss_list_12f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f1, pci_vendor_12f1, pci_ss_list_12f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f2, pci_vendor_12f2, pci_ss_list_12f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f3, pci_vendor_12f3, pci_ss_list_12f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f4, pci_vendor_12f4, pci_ss_list_12f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f5, pci_vendor_12f5, pci_ss_list_12f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f6, pci_vendor_12f6, pci_ss_list_12f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f7, pci_vendor_12f7, pci_ss_list_12f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f8, pci_vendor_12f8, pci_ss_list_12f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f9, pci_vendor_12f9, pci_ss_list_12f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fb, pci_vendor_12fb, pci_ss_list_12fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fc, pci_vendor_12fc, pci_ss_list_12fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fd, pci_vendor_12fd, pci_ss_list_12fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fe, pci_vendor_12fe, pci_ss_list_12fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ff, pci_vendor_12ff, pci_ss_list_12ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1300, pci_vendor_1300, pci_ss_list_1300}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1302, pci_vendor_1302, pci_ss_list_1302}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1303, pci_vendor_1303, pci_ss_list_1303}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1304, pci_vendor_1304, pci_ss_list_1304}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1305, pci_vendor_1305, pci_ss_list_1305}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1306, pci_vendor_1306, pci_ss_list_1306}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1307, pci_vendor_1307, pci_ss_list_1307}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1308, pci_vendor_1308, pci_ss_list_1308}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1309, pci_vendor_1309, pci_ss_list_1309}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130a, pci_vendor_130a, pci_ss_list_130a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130b, pci_vendor_130b, pci_ss_list_130b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130c, pci_vendor_130c, pci_ss_list_130c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130d, pci_vendor_130d, pci_ss_list_130d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130e, pci_vendor_130e, pci_ss_list_130e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130f, pci_vendor_130f, pci_ss_list_130f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1310, pci_vendor_1310, pci_ss_list_1310}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1311, pci_vendor_1311, pci_ss_list_1311}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1312, pci_vendor_1312, pci_ss_list_1312}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1313, pci_vendor_1313, pci_ss_list_1313}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1316, pci_vendor_1316, pci_ss_list_1316}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1317, pci_vendor_1317, pci_ss_list_1317}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1318, pci_vendor_1318, pci_ss_list_1318}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1319, pci_vendor_1319, pci_ss_list_1319}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131a, pci_vendor_131a, pci_ss_list_131a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131c, pci_vendor_131c, pci_ss_list_131c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131d, pci_vendor_131d, pci_ss_list_131d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131e, pci_vendor_131e, pci_ss_list_131e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131f, pci_vendor_131f, pci_ss_list_131f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1320, pci_vendor_1320, pci_ss_list_1320}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1321, pci_vendor_1321, pci_ss_list_1321}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1322, pci_vendor_1322, pci_ss_list_1322}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1323, pci_vendor_1323, pci_ss_list_1323}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1324, pci_vendor_1324, pci_ss_list_1324}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1325, pci_vendor_1325, pci_ss_list_1325}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1326, pci_vendor_1326, pci_ss_list_1326}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1327, pci_vendor_1327, pci_ss_list_1327}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1328, pci_vendor_1328, pci_ss_list_1328}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1329, pci_vendor_1329, pci_ss_list_1329}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132a, pci_vendor_132a, pci_ss_list_132a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132b, pci_vendor_132b, pci_ss_list_132b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132c, pci_vendor_132c, pci_ss_list_132c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132d, pci_vendor_132d, pci_ss_list_132d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1330, pci_vendor_1330, pci_ss_list_1330}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1331, pci_vendor_1331, pci_ss_list_1331}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1332, pci_vendor_1332, pci_ss_list_1332}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1334, pci_vendor_1334, pci_ss_list_1334}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1335, pci_vendor_1335, pci_ss_list_1335}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1337, pci_vendor_1337, pci_ss_list_1337}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1338, pci_vendor_1338, pci_ss_list_1338}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133a, pci_vendor_133a, pci_ss_list_133a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133b, pci_vendor_133b, pci_ss_list_133b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133c, pci_vendor_133c, pci_ss_list_133c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133d, pci_vendor_133d, pci_ss_list_133d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133e, pci_vendor_133e, pci_ss_list_133e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133f, pci_vendor_133f, pci_ss_list_133f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1340, pci_vendor_1340, pci_ss_list_1340}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1341, pci_vendor_1341, pci_ss_list_1341}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1342, pci_vendor_1342, pci_ss_list_1342}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1343, pci_vendor_1343, pci_ss_list_1343}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1344, pci_vendor_1344, pci_ss_list_1344}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1345, pci_vendor_1345, pci_ss_list_1345}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1347, pci_vendor_1347, pci_ss_list_1347}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1349, pci_vendor_1349, pci_ss_list_1349}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134a, pci_vendor_134a, pci_ss_list_134a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134b, pci_vendor_134b, pci_ss_list_134b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134c, pci_vendor_134c, pci_ss_list_134c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134d, pci_vendor_134d, pci_ss_list_134d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134e, pci_vendor_134e, pci_ss_list_134e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134f, pci_vendor_134f, pci_ss_list_134f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1350, pci_vendor_1350, pci_ss_list_1350}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1351, pci_vendor_1351, pci_ss_list_1351}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1353, pci_vendor_1353, pci_ss_list_1353}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1354, pci_vendor_1354, pci_ss_list_1354}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1355, pci_vendor_1355, pci_ss_list_1355}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1356, pci_vendor_1356, pci_ss_list_1356}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1359, pci_vendor_1359, pci_ss_list_1359}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135a, pci_vendor_135a, pci_ss_list_135a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135b, pci_vendor_135b, pci_ss_list_135b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135c, pci_vendor_135c, pci_ss_list_135c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135d, pci_vendor_135d, pci_ss_list_135d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135e, pci_vendor_135e, pci_ss_list_135e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135f, pci_vendor_135f, pci_ss_list_135f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1360, pci_vendor_1360, pci_ss_list_1360}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1361, pci_vendor_1361, pci_ss_list_1361}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1362, pci_vendor_1362, pci_ss_list_1362}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1363, pci_vendor_1363, pci_ss_list_1363}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1364, pci_vendor_1364, pci_ss_list_1364}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1365, pci_vendor_1365, pci_ss_list_1365}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1366, pci_vendor_1366, pci_ss_list_1366}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1367, pci_vendor_1367, pci_ss_list_1367}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1368, pci_vendor_1368, pci_ss_list_1368}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1369, pci_vendor_1369, pci_ss_list_1369}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136a, pci_vendor_136a, pci_ss_list_136a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136b, pci_vendor_136b, pci_ss_list_136b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136c, pci_vendor_136c, pci_ss_list_136c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136d, pci_vendor_136d, pci_ss_list_136d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136f, pci_vendor_136f, pci_ss_list_136f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1370, pci_vendor_1370, pci_ss_list_1370}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1371, pci_vendor_1371, pci_ss_list_1371}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1373, pci_vendor_1373, pci_ss_list_1373}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1374, pci_vendor_1374, pci_ss_list_1374}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1375, pci_vendor_1375, pci_ss_list_1375}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1376, pci_vendor_1376, pci_ss_list_1376}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1377, pci_vendor_1377, pci_ss_list_1377}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1378, pci_vendor_1378, pci_ss_list_1378}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1379, pci_vendor_1379, pci_ss_list_1379}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137a, pci_vendor_137a, pci_ss_list_137a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137b, pci_vendor_137b, pci_ss_list_137b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137c, pci_vendor_137c, pci_ss_list_137c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137d, pci_vendor_137d, pci_ss_list_137d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137e, pci_vendor_137e, pci_ss_list_137e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137f, pci_vendor_137f, pci_ss_list_137f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1380, pci_vendor_1380, pci_ss_list_1380}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1381, pci_vendor_1381, pci_ss_list_1381}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1382, pci_vendor_1382, pci_ss_list_1382}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1383, pci_vendor_1383, pci_ss_list_1383}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1384, pci_vendor_1384, pci_ss_list_1384}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1385, pci_vendor_1385, pci_ss_list_1385}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1386, pci_vendor_1386, pci_ss_list_1386}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1387, pci_vendor_1387, pci_ss_list_1387}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1388, pci_vendor_1388, pci_ss_list_1388}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1389, pci_vendor_1389, pci_ss_list_1389}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138a, pci_vendor_138a, pci_ss_list_138a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138b, pci_vendor_138b, pci_ss_list_138b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138c, pci_vendor_138c, pci_ss_list_138c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138d, pci_vendor_138d, pci_ss_list_138d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138e, pci_vendor_138e, pci_ss_list_138e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138f, pci_vendor_138f, pci_ss_list_138f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1390, pci_vendor_1390, pci_ss_list_1390}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1391, pci_vendor_1391, pci_ss_list_1391}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1392, pci_vendor_1392, pci_ss_list_1392}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1393, pci_vendor_1393, pci_ss_list_1393}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1394, pci_vendor_1394, pci_ss_list_1394}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1395, pci_vendor_1395, pci_ss_list_1395}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1396, pci_vendor_1396, pci_ss_list_1396}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1397, pci_vendor_1397, pci_ss_list_1397}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1398, pci_vendor_1398, pci_ss_list_1398}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1399, pci_vendor_1399, pci_ss_list_1399}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139a, pci_vendor_139a, pci_ss_list_139a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139b, pci_vendor_139b, pci_ss_list_139b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139c, pci_vendor_139c, pci_ss_list_139c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139d, pci_vendor_139d, pci_ss_list_139d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139e, pci_vendor_139e, pci_ss_list_139e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139f, pci_vendor_139f, pci_ss_list_139f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a0, pci_vendor_13a0, pci_ss_list_13a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a1, pci_vendor_13a1, pci_ss_list_13a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a2, pci_vendor_13a2, pci_ss_list_13a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a3, pci_vendor_13a3, pci_ss_list_13a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a4, pci_vendor_13a4, pci_ss_list_13a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a5, pci_vendor_13a5, pci_ss_list_13a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a6, pci_vendor_13a6, pci_ss_list_13a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a7, pci_vendor_13a7, pci_ss_list_13a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a8, pci_vendor_13a8, pci_ss_list_13a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a9, pci_vendor_13a9, pci_ss_list_13a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13aa, pci_vendor_13aa, pci_ss_list_13aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ab, pci_vendor_13ab, pci_ss_list_13ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ac, pci_vendor_13ac, pci_ss_list_13ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ad, pci_vendor_13ad, pci_ss_list_13ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ae, pci_vendor_13ae, pci_ss_list_13ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13af, pci_vendor_13af, pci_ss_list_13af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b0, pci_vendor_13b0, pci_ss_list_13b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b1, pci_vendor_13b1, pci_ss_list_13b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b2, pci_vendor_13b2, pci_ss_list_13b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b3, pci_vendor_13b3, pci_ss_list_13b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b4, pci_vendor_13b4, pci_ss_list_13b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b5, pci_vendor_13b5, pci_ss_list_13b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b6, pci_vendor_13b6, pci_ss_list_13b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b7, pci_vendor_13b7, pci_ss_list_13b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b8, pci_vendor_13b8, pci_ss_list_13b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b9, pci_vendor_13b9, pci_ss_list_13b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ba, pci_vendor_13ba, pci_ss_list_13ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bb, pci_vendor_13bb, pci_ss_list_13bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bc, pci_vendor_13bc, pci_ss_list_13bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bd, pci_vendor_13bd, pci_ss_list_13bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13be, pci_vendor_13be, pci_ss_list_13be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bf, pci_vendor_13bf, pci_ss_list_13bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c0, pci_vendor_13c0, pci_ss_list_13c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c1, pci_vendor_13c1, pci_ss_list_13c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c2, pci_vendor_13c2, pci_ss_list_13c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c3, pci_vendor_13c3, pci_ss_list_13c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c4, pci_vendor_13c4, pci_ss_list_13c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c5, pci_vendor_13c5, pci_ss_list_13c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c6, pci_vendor_13c6, pci_ss_list_13c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c7, pci_vendor_13c7, pci_ss_list_13c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c8, pci_vendor_13c8, pci_ss_list_13c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c9, pci_vendor_13c9, pci_ss_list_13c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ca, pci_vendor_13ca, pci_ss_list_13ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cb, pci_vendor_13cb, pci_ss_list_13cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cc, pci_vendor_13cc, pci_ss_list_13cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cd, pci_vendor_13cd, pci_ss_list_13cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ce, pci_vendor_13ce, pci_ss_list_13ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cf, pci_vendor_13cf, pci_ss_list_13cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d0, pci_vendor_13d0, pci_ss_list_13d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d1, pci_vendor_13d1, pci_ss_list_13d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d2, pci_vendor_13d2, pci_ss_list_13d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d3, pci_vendor_13d3, pci_ss_list_13d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d4, pci_vendor_13d4, pci_ss_list_13d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d5, pci_vendor_13d5, pci_ss_list_13d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d6, pci_vendor_13d6, pci_ss_list_13d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d7, pci_vendor_13d7, pci_ss_list_13d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d8, pci_vendor_13d8, pci_ss_list_13d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d9, pci_vendor_13d9, pci_ss_list_13d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13da, pci_vendor_13da, pci_ss_list_13da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13db, pci_vendor_13db, pci_ss_list_13db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13dc, pci_vendor_13dc, pci_ss_list_13dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13dd, pci_vendor_13dd, pci_ss_list_13dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13de, pci_vendor_13de, pci_ss_list_13de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13df, pci_vendor_13df, pci_ss_list_13df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e0, pci_vendor_13e0, pci_ss_list_13e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e1, pci_vendor_13e1, pci_ss_list_13e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e2, pci_vendor_13e2, pci_ss_list_13e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e3, pci_vendor_13e3, pci_ss_list_13e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e4, pci_vendor_13e4, pci_ss_list_13e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e5, pci_vendor_13e5, pci_ss_list_13e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e6, pci_vendor_13e6, pci_ss_list_13e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e7, pci_vendor_13e7, pci_ss_list_13e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e8, pci_vendor_13e8, pci_ss_list_13e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e9, pci_vendor_13e9, pci_ss_list_13e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ea, pci_vendor_13ea, pci_ss_list_13ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13eb, pci_vendor_13eb, pci_ss_list_13eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ec, pci_vendor_13ec, pci_ss_list_13ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ed, pci_vendor_13ed, pci_ss_list_13ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ee, pci_vendor_13ee, pci_ss_list_13ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ef, pci_vendor_13ef, pci_ss_list_13ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f0, pci_vendor_13f0, pci_ss_list_13f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f1, pci_vendor_13f1, pci_ss_list_13f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f2, pci_vendor_13f2, pci_ss_list_13f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f3, pci_vendor_13f3, pci_ss_list_13f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f4, pci_vendor_13f4, pci_ss_list_13f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f5, pci_vendor_13f5, pci_ss_list_13f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f6, pci_vendor_13f6, pci_ss_list_13f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f7, pci_vendor_13f7, pci_ss_list_13f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f8, pci_vendor_13f8, pci_ss_list_13f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f9, pci_vendor_13f9, pci_ss_list_13f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fa, pci_vendor_13fa, pci_ss_list_13fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fb, pci_vendor_13fb, pci_ss_list_13fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fc, pci_vendor_13fc, pci_ss_list_13fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fd, pci_vendor_13fd, pci_ss_list_13fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fe, pci_vendor_13fe, pci_ss_list_13fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ff, pci_vendor_13ff, pci_ss_list_13ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1400, pci_vendor_1400, pci_ss_list_1400}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1401, pci_vendor_1401, pci_ss_list_1401}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1402, pci_vendor_1402, pci_ss_list_1402}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1403, pci_vendor_1403, pci_ss_list_1403}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1404, pci_vendor_1404, pci_ss_list_1404}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1405, pci_vendor_1405, pci_ss_list_1405}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1406, pci_vendor_1406, pci_ss_list_1406}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1407, pci_vendor_1407, pci_ss_list_1407}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1408, pci_vendor_1408, pci_ss_list_1408}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1409, pci_vendor_1409, pci_ss_list_1409}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140a, pci_vendor_140a, pci_ss_list_140a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140b, pci_vendor_140b, pci_ss_list_140b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140c, pci_vendor_140c, pci_ss_list_140c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140d, pci_vendor_140d, pci_ss_list_140d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140e, pci_vendor_140e, pci_ss_list_140e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140f, pci_vendor_140f, pci_ss_list_140f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1410, pci_vendor_1410, pci_ss_list_1410}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1411, pci_vendor_1411, pci_ss_list_1411}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1412, pci_vendor_1412, pci_ss_list_1412}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1413, pci_vendor_1413, pci_ss_list_1413}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1414, pci_vendor_1414, pci_ss_list_1414}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1415, pci_vendor_1415, pci_ss_list_1415}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1416, pci_vendor_1416, pci_ss_list_1416}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1417, pci_vendor_1417, pci_ss_list_1417}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1418, pci_vendor_1418, pci_ss_list_1418}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1419, pci_vendor_1419, pci_ss_list_1419}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141a, pci_vendor_141a, pci_ss_list_141a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141b, pci_vendor_141b, pci_ss_list_141b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141d, pci_vendor_141d, pci_ss_list_141d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141e, pci_vendor_141e, pci_ss_list_141e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141f, pci_vendor_141f, pci_ss_list_141f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1420, pci_vendor_1420, pci_ss_list_1420}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1421, pci_vendor_1421, pci_ss_list_1421}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1422, pci_vendor_1422, pci_ss_list_1422}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1423, pci_vendor_1423, pci_ss_list_1423}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1424, pci_vendor_1424, pci_ss_list_1424}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1425, pci_vendor_1425, pci_ss_list_1425}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1426, pci_vendor_1426, pci_ss_list_1426}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1427, pci_vendor_1427, pci_ss_list_1427}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1428, pci_vendor_1428, pci_ss_list_1428}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1429, pci_vendor_1429, pci_ss_list_1429}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142a, pci_vendor_142a, pci_ss_list_142a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142b, pci_vendor_142b, pci_ss_list_142b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142c, pci_vendor_142c, pci_ss_list_142c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142d, pci_vendor_142d, pci_ss_list_142d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142e, pci_vendor_142e, pci_ss_list_142e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142f, pci_vendor_142f, pci_ss_list_142f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1430, pci_vendor_1430, pci_ss_list_1430}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1431, pci_vendor_1431, pci_ss_list_1431}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1432, pci_vendor_1432, pci_ss_list_1432}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1433, pci_vendor_1433, pci_ss_list_1433}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1435, pci_vendor_1435, pci_ss_list_1435}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1436, pci_vendor_1436, pci_ss_list_1436}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1437, pci_vendor_1437, pci_ss_list_1437}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1438, pci_vendor_1438, pci_ss_list_1438}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1439, pci_vendor_1439, pci_ss_list_1439}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143a, pci_vendor_143a, pci_ss_list_143a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143b, pci_vendor_143b, pci_ss_list_143b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143c, pci_vendor_143c, pci_ss_list_143c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143d, pci_vendor_143d, pci_ss_list_143d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143e, pci_vendor_143e, pci_ss_list_143e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143f, pci_vendor_143f, pci_ss_list_143f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1440, pci_vendor_1440, pci_ss_list_1440}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1441, pci_vendor_1441, pci_ss_list_1441}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1442, pci_vendor_1442, pci_ss_list_1442}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1443, pci_vendor_1443, pci_ss_list_1443}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1444, pci_vendor_1444, pci_ss_list_1444}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1445, pci_vendor_1445, pci_ss_list_1445}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1446, pci_vendor_1446, pci_ss_list_1446}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1447, pci_vendor_1447, pci_ss_list_1447}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1448, pci_vendor_1448, pci_ss_list_1448}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1449, pci_vendor_1449, pci_ss_list_1449}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144a, pci_vendor_144a, pci_ss_list_144a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144b, pci_vendor_144b, pci_ss_list_144b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144c, pci_vendor_144c, pci_ss_list_144c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144d, pci_vendor_144d, pci_ss_list_144d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144e, pci_vendor_144e, pci_ss_list_144e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144f, pci_vendor_144f, pci_ss_list_144f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1450, pci_vendor_1450, pci_ss_list_1450}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1451, pci_vendor_1451, pci_ss_list_1451}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1453, pci_vendor_1453, pci_ss_list_1453}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1454, pci_vendor_1454, pci_ss_list_1454}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1455, pci_vendor_1455, pci_ss_list_1455}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1456, pci_vendor_1456, pci_ss_list_1456}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1457, pci_vendor_1457, pci_ss_list_1457}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1458, pci_vendor_1458, pci_ss_list_1458}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1459, pci_vendor_1459, pci_ss_list_1459}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145a, pci_vendor_145a, pci_ss_list_145a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145b, pci_vendor_145b, pci_ss_list_145b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145c, pci_vendor_145c, pci_ss_list_145c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145d, pci_vendor_145d, pci_ss_list_145d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145e, pci_vendor_145e, pci_ss_list_145e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145f, pci_vendor_145f, pci_ss_list_145f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1460, pci_vendor_1460, pci_ss_list_1460}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1461, pci_vendor_1461, pci_ss_list_1461}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1462, pci_vendor_1462, pci_ss_list_1462}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1463, pci_vendor_1463, pci_ss_list_1463}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1464, pci_vendor_1464, pci_ss_list_1464}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1465, pci_vendor_1465, pci_ss_list_1465}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1466, pci_vendor_1466, pci_ss_list_1466}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1467, pci_vendor_1467, pci_ss_list_1467}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1468, pci_vendor_1468, pci_ss_list_1468}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1469, pci_vendor_1469, pci_ss_list_1469}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146a, pci_vendor_146a, pci_ss_list_146a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146b, pci_vendor_146b, pci_ss_list_146b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146c, pci_vendor_146c, pci_ss_list_146c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146d, pci_vendor_146d, pci_ss_list_146d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146e, pci_vendor_146e, pci_ss_list_146e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146f, pci_vendor_146f, pci_ss_list_146f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1470, pci_vendor_1470, pci_ss_list_1470}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1471, pci_vendor_1471, pci_ss_list_1471}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1472, pci_vendor_1472, pci_ss_list_1472}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1473, pci_vendor_1473, pci_ss_list_1473}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1474, pci_vendor_1474, pci_ss_list_1474}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1475, pci_vendor_1475, pci_ss_list_1475}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1476, pci_vendor_1476, pci_ss_list_1476}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1477, pci_vendor_1477, pci_ss_list_1477}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1478, pci_vendor_1478, pci_ss_list_1478}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1479, pci_vendor_1479, pci_ss_list_1479}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147a, pci_vendor_147a, pci_ss_list_147a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147b, pci_vendor_147b, pci_ss_list_147b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147c, pci_vendor_147c, pci_ss_list_147c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147d, pci_vendor_147d, pci_ss_list_147d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147e, pci_vendor_147e, pci_ss_list_147e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147f, pci_vendor_147f, pci_ss_list_147f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1480, pci_vendor_1480, pci_ss_list_1480}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1481, pci_vendor_1481, pci_ss_list_1481}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1482, pci_vendor_1482, pci_ss_list_1482}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1483, pci_vendor_1483, pci_ss_list_1483}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1484, pci_vendor_1484, pci_ss_list_1484}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1485, pci_vendor_1485, pci_ss_list_1485}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1486, pci_vendor_1486, pci_ss_list_1486}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1487, pci_vendor_1487, pci_ss_list_1487}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1488, pci_vendor_1488, pci_ss_list_1488}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1489, pci_vendor_1489, pci_ss_list_1489}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148a, pci_vendor_148a, pci_ss_list_148a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148b, pci_vendor_148b, pci_ss_list_148b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148c, pci_vendor_148c, pci_ss_list_148c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148d, pci_vendor_148d, pci_ss_list_148d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148e, pci_vendor_148e, pci_ss_list_148e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148f, pci_vendor_148f, pci_ss_list_148f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1490, pci_vendor_1490, pci_ss_list_1490}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1491, pci_vendor_1491, pci_ss_list_1491}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1492, pci_vendor_1492, pci_ss_list_1492}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1493, pci_vendor_1493, pci_ss_list_1493}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1494, pci_vendor_1494, pci_ss_list_1494}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1495, pci_vendor_1495, pci_ss_list_1495}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1496, pci_vendor_1496, pci_ss_list_1496}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1497, pci_vendor_1497, pci_ss_list_1497}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1498, pci_vendor_1498, pci_ss_list_1498}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1499, pci_vendor_1499, pci_ss_list_1499}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149a, pci_vendor_149a, pci_ss_list_149a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149b, pci_vendor_149b, pci_ss_list_149b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149c, pci_vendor_149c, pci_ss_list_149c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149d, pci_vendor_149d, pci_ss_list_149d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149e, pci_vendor_149e, pci_ss_list_149e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149f, pci_vendor_149f, pci_ss_list_149f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a0, pci_vendor_14a0, pci_ss_list_14a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a1, pci_vendor_14a1, pci_ss_list_14a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a2, pci_vendor_14a2, pci_ss_list_14a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a3, pci_vendor_14a3, pci_ss_list_14a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a4, pci_vendor_14a4, pci_ss_list_14a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a5, pci_vendor_14a5, pci_ss_list_14a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a6, pci_vendor_14a6, pci_ss_list_14a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a7, pci_vendor_14a7, pci_ss_list_14a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a8, pci_vendor_14a8, pci_ss_list_14a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a9, pci_vendor_14a9, pci_ss_list_14a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14aa, pci_vendor_14aa, pci_ss_list_14aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ab, pci_vendor_14ab, pci_ss_list_14ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ac, pci_vendor_14ac, pci_ss_list_14ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ad, pci_vendor_14ad, pci_ss_list_14ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ae, pci_vendor_14ae, pci_ss_list_14ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14af, pci_vendor_14af, pci_ss_list_14af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b0, pci_vendor_14b0, pci_ss_list_14b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b1, pci_vendor_14b1, pci_ss_list_14b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b2, pci_vendor_14b2, pci_ss_list_14b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b3, pci_vendor_14b3, pci_ss_list_14b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b4, pci_vendor_14b4, pci_ss_list_14b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b5, pci_vendor_14b5, pci_ss_list_14b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b6, pci_vendor_14b6, pci_ss_list_14b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b7, pci_vendor_14b7, pci_ss_list_14b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b8, pci_vendor_14b8, pci_ss_list_14b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b9, pci_vendor_14b9, pci_ss_list_14b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ba, pci_vendor_14ba, pci_ss_list_14ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bb, pci_vendor_14bb, pci_ss_list_14bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bc, pci_vendor_14bc, pci_ss_list_14bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bd, pci_vendor_14bd, pci_ss_list_14bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14be, pci_vendor_14be, pci_ss_list_14be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bf, pci_vendor_14bf, pci_ss_list_14bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c0, pci_vendor_14c0, pci_ss_list_14c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c1, pci_vendor_14c1, pci_ss_list_14c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c2, pci_vendor_14c2, pci_ss_list_14c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c3, pci_vendor_14c3, pci_ss_list_14c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c4, pci_vendor_14c4, pci_ss_list_14c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c5, pci_vendor_14c5, pci_ss_list_14c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c6, pci_vendor_14c6, pci_ss_list_14c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c7, pci_vendor_14c7, pci_ss_list_14c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c8, pci_vendor_14c8, pci_ss_list_14c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c9, pci_vendor_14c9, pci_ss_list_14c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ca, pci_vendor_14ca, pci_ss_list_14ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cb, pci_vendor_14cb, pci_ss_list_14cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cc, pci_vendor_14cc, pci_ss_list_14cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cd, pci_vendor_14cd, pci_ss_list_14cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ce, pci_vendor_14ce, pci_ss_list_14ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cf, pci_vendor_14cf, pci_ss_list_14cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d0, pci_vendor_14d0, pci_ss_list_14d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d1, pci_vendor_14d1, pci_ss_list_14d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d2, pci_vendor_14d2, pci_ss_list_14d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d3, pci_vendor_14d3, pci_ss_list_14d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d4, pci_vendor_14d4, pci_ss_list_14d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d5, pci_vendor_14d5, pci_ss_list_14d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d6, pci_vendor_14d6, pci_ss_list_14d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d7, pci_vendor_14d7, pci_ss_list_14d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d8, pci_vendor_14d8, pci_ss_list_14d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d9, pci_vendor_14d9, pci_ss_list_14d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14da, pci_vendor_14da, pci_ss_list_14da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14db, pci_vendor_14db, pci_ss_list_14db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14dc, pci_vendor_14dc, pci_ss_list_14dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14dd, pci_vendor_14dd, pci_ss_list_14dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14de, pci_vendor_14de, pci_ss_list_14de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14df, pci_vendor_14df, pci_ss_list_14df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e1, pci_vendor_14e1, pci_ss_list_14e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e2, pci_vendor_14e2, pci_ss_list_14e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e3, pci_vendor_14e3, pci_ss_list_14e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e4, pci_vendor_14e4, pci_ss_list_14e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e5, pci_vendor_14e5, pci_ss_list_14e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e6, pci_vendor_14e6, pci_ss_list_14e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e7, pci_vendor_14e7, pci_ss_list_14e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e8, pci_vendor_14e8, pci_ss_list_14e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e9, pci_vendor_14e9, pci_ss_list_14e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ea, pci_vendor_14ea, pci_ss_list_14ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14eb, pci_vendor_14eb, pci_ss_list_14eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ec, pci_vendor_14ec, pci_ss_list_14ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ed, pci_vendor_14ed, pci_ss_list_14ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ee, pci_vendor_14ee, pci_ss_list_14ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ef, pci_vendor_14ef, pci_ss_list_14ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f0, pci_vendor_14f0, pci_ss_list_14f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f1, pci_vendor_14f1, pci_ss_list_14f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f2, pci_vendor_14f2, pci_ss_list_14f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f3, pci_vendor_14f3, pci_ss_list_14f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f4, pci_vendor_14f4, pci_ss_list_14f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f5, pci_vendor_14f5, pci_ss_list_14f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f6, pci_vendor_14f6, pci_ss_list_14f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f7, pci_vendor_14f7, pci_ss_list_14f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f8, pci_vendor_14f8, pci_ss_list_14f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f9, pci_vendor_14f9, pci_ss_list_14f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fa, pci_vendor_14fa, pci_ss_list_14fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fb, pci_vendor_14fb, pci_ss_list_14fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fc, pci_vendor_14fc, pci_ss_list_14fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fd, pci_vendor_14fd, pci_ss_list_14fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fe, pci_vendor_14fe, pci_ss_list_14fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ff, pci_vendor_14ff, pci_ss_list_14ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1500, pci_vendor_1500, pci_ss_list_1500}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1501, pci_vendor_1501, pci_ss_list_1501}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1502, pci_vendor_1502, pci_ss_list_1502}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1503, pci_vendor_1503, pci_ss_list_1503}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1504, pci_vendor_1504, pci_ss_list_1504}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1505, pci_vendor_1505, pci_ss_list_1505}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1506, pci_vendor_1506, pci_ss_list_1506}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1507, pci_vendor_1507, pci_ss_list_1507}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1508, pci_vendor_1508, pci_ss_list_1508}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1509, pci_vendor_1509, pci_ss_list_1509}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150a, pci_vendor_150a, pci_ss_list_150a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150b, pci_vendor_150b, pci_ss_list_150b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150c, pci_vendor_150c, pci_ss_list_150c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150d, pci_vendor_150d, pci_ss_list_150d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150e, pci_vendor_150e, pci_ss_list_150e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150f, pci_vendor_150f, pci_ss_list_150f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1510, pci_vendor_1510, pci_ss_list_1510}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1511, pci_vendor_1511, pci_ss_list_1511}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1512, pci_vendor_1512, pci_ss_list_1512}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1513, pci_vendor_1513, pci_ss_list_1513}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1514, pci_vendor_1514, pci_ss_list_1514}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1515, pci_vendor_1515, pci_ss_list_1515}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1516, pci_vendor_1516, pci_ss_list_1516}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1517, pci_vendor_1517, pci_ss_list_1517}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1518, pci_vendor_1518, pci_ss_list_1518}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1519, pci_vendor_1519, pci_ss_list_1519}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151a, pci_vendor_151a, pci_ss_list_151a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151b, pci_vendor_151b, pci_ss_list_151b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151c, pci_vendor_151c, pci_ss_list_151c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151d, pci_vendor_151d, pci_ss_list_151d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151e, pci_vendor_151e, pci_ss_list_151e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151f, pci_vendor_151f, pci_ss_list_151f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1520, pci_vendor_1520, pci_ss_list_1520}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1521, pci_vendor_1521, pci_ss_list_1521}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1522, pci_vendor_1522, pci_ss_list_1522}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1523, pci_vendor_1523, pci_ss_list_1523}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1524, pci_vendor_1524, pci_ss_list_1524}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1525, pci_vendor_1525, pci_ss_list_1525}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1526, pci_vendor_1526, pci_ss_list_1526}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1527, pci_vendor_1527, pci_ss_list_1527}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1528, pci_vendor_1528, pci_ss_list_1528}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1529, pci_vendor_1529, pci_ss_list_1529}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152a, pci_vendor_152a, pci_ss_list_152a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152b, pci_vendor_152b, pci_ss_list_152b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152c, pci_vendor_152c, pci_ss_list_152c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152d, pci_vendor_152d, pci_ss_list_152d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152e, pci_vendor_152e, pci_ss_list_152e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152f, pci_vendor_152f, pci_ss_list_152f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1530, pci_vendor_1530, pci_ss_list_1530}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1531, pci_vendor_1531, pci_ss_list_1531}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1532, pci_vendor_1532, pci_ss_list_1532}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1533, pci_vendor_1533, pci_ss_list_1533}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1534, pci_vendor_1534, pci_ss_list_1534}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1535, pci_vendor_1535, pci_ss_list_1535}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1537, pci_vendor_1537, pci_ss_list_1537}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1538, pci_vendor_1538, pci_ss_list_1538}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1539, pci_vendor_1539, pci_ss_list_1539}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153a, pci_vendor_153a, pci_ss_list_153a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153b, pci_vendor_153b, pci_ss_list_153b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153c, pci_vendor_153c, pci_ss_list_153c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153d, pci_vendor_153d, pci_ss_list_153d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153e, pci_vendor_153e, pci_ss_list_153e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153f, pci_vendor_153f, pci_ss_list_153f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1540, pci_vendor_1540, pci_ss_list_1540}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1541, pci_vendor_1541, pci_ss_list_1541}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1542, pci_vendor_1542, pci_ss_list_1542}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1543, pci_vendor_1543, pci_ss_list_1543}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1544, pci_vendor_1544, pci_ss_list_1544}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1545, pci_vendor_1545, pci_ss_list_1545}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1546, pci_vendor_1546, pci_ss_list_1546}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1547, pci_vendor_1547, pci_ss_list_1547}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1548, pci_vendor_1548, pci_ss_list_1548}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1549, pci_vendor_1549, pci_ss_list_1549}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154a, pci_vendor_154a, pci_ss_list_154a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154b, pci_vendor_154b, pci_ss_list_154b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154c, pci_vendor_154c, pci_ss_list_154c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154d, pci_vendor_154d, pci_ss_list_154d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154e, pci_vendor_154e, pci_ss_list_154e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154f, pci_vendor_154f, pci_ss_list_154f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1550, pci_vendor_1550, pci_ss_list_1550}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1551, pci_vendor_1551, pci_ss_list_1551}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1552, pci_vendor_1552, pci_ss_list_1552}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1553, pci_vendor_1553, pci_ss_list_1553}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1554, pci_vendor_1554, pci_ss_list_1554}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1555, pci_vendor_1555, pci_ss_list_1555}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1556, pci_vendor_1556, pci_ss_list_1556}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1557, pci_vendor_1557, pci_ss_list_1557}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1558, pci_vendor_1558, pci_ss_list_1558}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1559, pci_vendor_1559, pci_ss_list_1559}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155a, pci_vendor_155a, pci_ss_list_155a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155b, pci_vendor_155b, pci_ss_list_155b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155c, pci_vendor_155c, pci_ss_list_155c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155d, pci_vendor_155d, pci_ss_list_155d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155e, pci_vendor_155e, pci_ss_list_155e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155f, pci_vendor_155f, pci_ss_list_155f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1560, pci_vendor_1560, pci_ss_list_1560}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1561, pci_vendor_1561, pci_ss_list_1561}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1562, pci_vendor_1562, pci_ss_list_1562}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1563, pci_vendor_1563, pci_ss_list_1563}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1564, pci_vendor_1564, pci_ss_list_1564}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1565, pci_vendor_1565, pci_ss_list_1565}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1566, pci_vendor_1566, pci_ss_list_1566}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1567, pci_vendor_1567, pci_ss_list_1567}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1568, pci_vendor_1568, pci_ss_list_1568}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1569, pci_vendor_1569, pci_ss_list_1569}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156a, pci_vendor_156a, pci_ss_list_156a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156b, pci_vendor_156b, pci_ss_list_156b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156c, pci_vendor_156c, pci_ss_list_156c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156d, pci_vendor_156d, pci_ss_list_156d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156e, pci_vendor_156e, pci_ss_list_156e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156f, pci_vendor_156f, pci_ss_list_156f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1570, pci_vendor_1570, pci_ss_list_1570}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1571, pci_vendor_1571, pci_ss_list_1571}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1572, pci_vendor_1572, pci_ss_list_1572}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1573, pci_vendor_1573, pci_ss_list_1573}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1574, pci_vendor_1574, pci_ss_list_1574}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1575, pci_vendor_1575, pci_ss_list_1575}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1576, pci_vendor_1576, pci_ss_list_1576}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1578, pci_vendor_1578, pci_ss_list_1578}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1579, pci_vendor_1579, pci_ss_list_1579}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157a, pci_vendor_157a, pci_ss_list_157a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157b, pci_vendor_157b, pci_ss_list_157b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157c, pci_vendor_157c, pci_ss_list_157c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157d, pci_vendor_157d, pci_ss_list_157d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157e, pci_vendor_157e, pci_ss_list_157e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157f, pci_vendor_157f, pci_ss_list_157f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1580, pci_vendor_1580, pci_ss_list_1580}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1581, pci_vendor_1581, pci_ss_list_1581}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1582, pci_vendor_1582, pci_ss_list_1582}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1583, pci_vendor_1583, pci_ss_list_1583}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1584, pci_vendor_1584, pci_ss_list_1584}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1585, pci_vendor_1585, pci_ss_list_1585}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1586, pci_vendor_1586, pci_ss_list_1586}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1587, pci_vendor_1587, pci_ss_list_1587}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1588, pci_vendor_1588, pci_ss_list_1588}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1589, pci_vendor_1589, pci_ss_list_1589}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158a, pci_vendor_158a, pci_ss_list_158a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158b, pci_vendor_158b, pci_ss_list_158b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158c, pci_vendor_158c, pci_ss_list_158c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158d, pci_vendor_158d, pci_ss_list_158d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158e, pci_vendor_158e, pci_ss_list_158e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158f, pci_vendor_158f, pci_ss_list_158f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1590, pci_vendor_1590, pci_ss_list_1590}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1591, pci_vendor_1591, pci_ss_list_1591}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1592, pci_vendor_1592, pci_ss_list_1592}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1593, pci_vendor_1593, pci_ss_list_1593}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1594, pci_vendor_1594, pci_ss_list_1594}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1595, pci_vendor_1595, pci_ss_list_1595}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1596, pci_vendor_1596, pci_ss_list_1596}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1597, pci_vendor_1597, pci_ss_list_1597}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1598, pci_vendor_1598, pci_ss_list_1598}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1599, pci_vendor_1599, pci_ss_list_1599}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159a, pci_vendor_159a, pci_ss_list_159a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159b, pci_vendor_159b, pci_ss_list_159b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159c, pci_vendor_159c, pci_ss_list_159c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159d, pci_vendor_159d, pci_ss_list_159d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159e, pci_vendor_159e, pci_ss_list_159e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159f, pci_vendor_159f, pci_ss_list_159f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a0, pci_vendor_15a0, pci_ss_list_15a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a1, pci_vendor_15a1, pci_ss_list_15a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a2, pci_vendor_15a2, pci_ss_list_15a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a3, pci_vendor_15a3, pci_ss_list_15a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a4, pci_vendor_15a4, pci_ss_list_15a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a5, pci_vendor_15a5, pci_ss_list_15a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a6, pci_vendor_15a6, pci_ss_list_15a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a7, pci_vendor_15a7, pci_ss_list_15a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a8, pci_vendor_15a8, pci_ss_list_15a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15aa, pci_vendor_15aa, pci_ss_list_15aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ab, pci_vendor_15ab, pci_ss_list_15ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ac, pci_vendor_15ac, pci_ss_list_15ac}, +#endif + {0x15ad, pci_vendor_15ad, pci_ss_list_15ad}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ae, pci_vendor_15ae, pci_ss_list_15ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b0, pci_vendor_15b0, pci_ss_list_15b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b1, pci_vendor_15b1, pci_ss_list_15b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b2, pci_vendor_15b2, pci_ss_list_15b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b3, pci_vendor_15b3, pci_ss_list_15b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b4, pci_vendor_15b4, pci_ss_list_15b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b5, pci_vendor_15b5, pci_ss_list_15b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b6, pci_vendor_15b6, pci_ss_list_15b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b7, pci_vendor_15b7, pci_ss_list_15b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b8, pci_vendor_15b8, pci_ss_list_15b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b9, pci_vendor_15b9, pci_ss_list_15b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ba, pci_vendor_15ba, pci_ss_list_15ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bb, pci_vendor_15bb, pci_ss_list_15bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bc, pci_vendor_15bc, pci_ss_list_15bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bd, pci_vendor_15bd, pci_ss_list_15bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15be, pci_vendor_15be, pci_ss_list_15be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bf, pci_vendor_15bf, pci_ss_list_15bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c0, pci_vendor_15c0, pci_ss_list_15c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c1, pci_vendor_15c1, pci_ss_list_15c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c2, pci_vendor_15c2, pci_ss_list_15c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c3, pci_vendor_15c3, pci_ss_list_15c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c4, pci_vendor_15c4, pci_ss_list_15c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c5, pci_vendor_15c5, pci_ss_list_15c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c6, pci_vendor_15c6, pci_ss_list_15c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c7, pci_vendor_15c7, pci_ss_list_15c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c8, pci_vendor_15c8, pci_ss_list_15c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c9, pci_vendor_15c9, pci_ss_list_15c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ca, pci_vendor_15ca, pci_ss_list_15ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cb, pci_vendor_15cb, pci_ss_list_15cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cc, pci_vendor_15cc, pci_ss_list_15cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cd, pci_vendor_15cd, pci_ss_list_15cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ce, pci_vendor_15ce, pci_ss_list_15ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cf, pci_vendor_15cf, pci_ss_list_15cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d1, pci_vendor_15d1, pci_ss_list_15d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d2, pci_vendor_15d2, pci_ss_list_15d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d3, pci_vendor_15d3, pci_ss_list_15d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d4, pci_vendor_15d4, pci_ss_list_15d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d5, pci_vendor_15d5, pci_ss_list_15d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d6, pci_vendor_15d6, pci_ss_list_15d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d7, pci_vendor_15d7, pci_ss_list_15d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d8, pci_vendor_15d8, pci_ss_list_15d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d9, pci_vendor_15d9, pci_ss_list_15d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15da, pci_vendor_15da, pci_ss_list_15da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15db, pci_vendor_15db, pci_ss_list_15db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15dc, pci_vendor_15dc, pci_ss_list_15dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15dd, pci_vendor_15dd, pci_ss_list_15dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15de, pci_vendor_15de, pci_ss_list_15de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15df, pci_vendor_15df, pci_ss_list_15df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e0, pci_vendor_15e0, pci_ss_list_15e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e1, pci_vendor_15e1, pci_ss_list_15e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e2, pci_vendor_15e2, pci_ss_list_15e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e3, pci_vendor_15e3, pci_ss_list_15e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e4, pci_vendor_15e4, pci_ss_list_15e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e5, pci_vendor_15e5, pci_ss_list_15e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e6, pci_vendor_15e6, pci_ss_list_15e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e7, pci_vendor_15e7, pci_ss_list_15e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e8, pci_vendor_15e8, pci_ss_list_15e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e9, pci_vendor_15e9, pci_ss_list_15e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ea, pci_vendor_15ea, pci_ss_list_15ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15eb, pci_vendor_15eb, pci_ss_list_15eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ec, pci_vendor_15ec, pci_ss_list_15ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ed, pci_vendor_15ed, pci_ss_list_15ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ee, pci_vendor_15ee, pci_ss_list_15ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ef, pci_vendor_15ef, pci_ss_list_15ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f0, pci_vendor_15f0, pci_ss_list_15f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f1, pci_vendor_15f1, pci_ss_list_15f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f2, pci_vendor_15f2, pci_ss_list_15f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f3, pci_vendor_15f3, pci_ss_list_15f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f4, pci_vendor_15f4, pci_ss_list_15f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f5, pci_vendor_15f5, pci_ss_list_15f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f6, pci_vendor_15f6, pci_ss_list_15f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f7, pci_vendor_15f7, pci_ss_list_15f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f8, pci_vendor_15f8, pci_ss_list_15f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f9, pci_vendor_15f9, pci_ss_list_15f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fa, pci_vendor_15fa, pci_ss_list_15fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fb, pci_vendor_15fb, pci_ss_list_15fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fc, pci_vendor_15fc, pci_ss_list_15fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fd, pci_vendor_15fd, pci_ss_list_15fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fe, pci_vendor_15fe, pci_ss_list_15fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ff, pci_vendor_15ff, pci_ss_list_15ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1600, pci_vendor_1600, pci_ss_list_1600}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1601, pci_vendor_1601, pci_ss_list_1601}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1602, pci_vendor_1602, pci_ss_list_1602}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1603, pci_vendor_1603, pci_ss_list_1603}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1604, pci_vendor_1604, pci_ss_list_1604}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1605, pci_vendor_1605, pci_ss_list_1605}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1606, pci_vendor_1606, pci_ss_list_1606}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1607, pci_vendor_1607, pci_ss_list_1607}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1608, pci_vendor_1608, pci_ss_list_1608}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1609, pci_vendor_1609, pci_ss_list_1609}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1612, pci_vendor_1612, pci_ss_list_1612}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1619, pci_vendor_1619, pci_ss_list_1619}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1629, pci_vendor_1629, pci_ss_list_1629}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1638, pci_vendor_1638, pci_ss_list_1638}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x163c, pci_vendor_163c, pci_ss_list_163c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1657, pci_vendor_1657, pci_ss_list_1657}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165a, pci_vendor_165a, pci_ss_list_165a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165d, pci_vendor_165d, pci_ss_list_165d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1661, pci_vendor_1661, pci_ss_list_1661}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1668, pci_vendor_1668, pci_ss_list_1668}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1681, pci_vendor_1681, pci_ss_list_1681}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ab, pci_vendor_16ab, pci_ss_list_16ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16be, pci_vendor_16be, pci_ss_list_16be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ec, pci_vendor_16ec, pci_ss_list_16ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f6, pci_vendor_16f6, pci_ss_list_16f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1705, pci_vendor_1705, pci_ss_list_1705}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x170b, pci_vendor_170b, pci_ss_list_170b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x170c, pci_vendor_170c, pci_ss_list_170c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x172a, pci_vendor_172a, pci_ss_list_172a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1737, pci_vendor_1737, pci_ss_list_1737}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x173b, pci_vendor_173b, pci_ss_list_173b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1743, pci_vendor_1743, pci_ss_list_1743}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x174b, pci_vendor_174b, pci_ss_list_174b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x175e, pci_vendor_175e, pci_ss_list_175e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1787, pci_vendor_1787, pci_ss_list_1787}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1796, pci_vendor_1796, pci_ss_list_1796}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1799, pci_vendor_1799, pci_ss_list_1799}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17af, pci_vendor_17af, pci_ss_list_17af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cc, pci_vendor_17cc, pci_ss_list_17cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1813, pci_vendor_1813, pci_ss_list_1813}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1851, pci_vendor_1851, pci_ss_list_1851}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1852, pci_vendor_1852, pci_ss_list_1852}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1888, pci_vendor_1888, pci_ss_list_1888}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1a08, pci_vendor_1a08, pci_ss_list_1a08}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1b13, pci_vendor_1b13, pci_ss_list_1b13}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1c1c, pci_vendor_1c1c, pci_ss_list_1c1c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1d44, pci_vendor_1d44, pci_ss_list_1d44}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1de1, pci_vendor_1de1, pci_ss_list_1de1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2000, pci_vendor_2000, pci_ss_list_2000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2001, pci_vendor_2001, pci_ss_list_2001}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2003, pci_vendor_2003, pci_ss_list_2003}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2004, pci_vendor_2004, pci_ss_list_2004}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x21c3, pci_vendor_21c3, pci_ss_list_21c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2348, pci_vendor_2348, pci_ss_list_2348}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2646, pci_vendor_2646, pci_ss_list_2646}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x270b, pci_vendor_270b, pci_ss_list_270b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x270f, pci_vendor_270f, pci_ss_list_270f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2711, pci_vendor_2711, pci_ss_list_2711}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2a15, pci_vendor_2a15, pci_ss_list_2a15}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3000, pci_vendor_3000, pci_ss_list_3000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3142, pci_vendor_3142, pci_ss_list_3142}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3388, pci_vendor_3388, pci_ss_list_3388}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3411, pci_vendor_3411, pci_ss_list_3411}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3513, pci_vendor_3513, pci_ss_list_3513}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x38ef, pci_vendor_38ef, pci_ss_list_38ef}, +#endif + {0x3d3d, pci_vendor_3d3d, pci_ss_list_3d3d}, + {0x4005, pci_vendor_4005, pci_ss_list_4005}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4033, pci_vendor_4033, pci_ss_list_4033}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4143, pci_vendor_4143, pci_ss_list_4143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x416c, pci_vendor_416c, pci_ss_list_416c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4444, pci_vendor_4444, pci_ss_list_4444}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4468, pci_vendor_4468, pci_ss_list_4468}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4594, pci_vendor_4594, pci_ss_list_4594}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x45fb, pci_vendor_45fb, pci_ss_list_45fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4680, pci_vendor_4680, pci_ss_list_4680}, +#endif + {0x4843, pci_vendor_4843, pci_ss_list_4843}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4916, pci_vendor_4916, pci_ss_list_4916}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4943, pci_vendor_4943, pci_ss_list_4943}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4978, pci_vendor_4978, pci_ss_list_4978}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4a14, pci_vendor_4a14, pci_ss_list_4a14}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4b10, pci_vendor_4b10, pci_ss_list_4b10}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4c48, pci_vendor_4c48, pci_ss_list_4c48}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4c53, pci_vendor_4c53, pci_ss_list_4c53}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4ca1, pci_vendor_4ca1, pci_ss_list_4ca1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4d51, pci_vendor_4d51, pci_ss_list_4d51}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4d54, pci_vendor_4d54, pci_ss_list_4d54}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4ddc, pci_vendor_4ddc, pci_ss_list_4ddc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5046, pci_vendor_5046, pci_ss_list_5046}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5053, pci_vendor_5053, pci_ss_list_5053}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5136, pci_vendor_5136, pci_ss_list_5136}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5143, pci_vendor_5143, pci_ss_list_5143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5145, pci_vendor_5145, pci_ss_list_5145}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5168, pci_vendor_5168, pci_ss_list_5168}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5301, pci_vendor_5301, pci_ss_list_5301}, +#endif + {0x5333, pci_vendor_5333, pci_ss_list_5333}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x544c, pci_vendor_544c, pci_ss_list_544c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5455, pci_vendor_5455, pci_ss_list_5455}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5519, pci_vendor_5519, pci_ss_list_5519}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5544, pci_vendor_5544, pci_ss_list_5544}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5555, pci_vendor_5555, pci_ss_list_5555}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5654, pci_vendor_5654, pci_ss_list_5654}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5700, pci_vendor_5700, pci_ss_list_5700}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6356, pci_vendor_6356, pci_ss_list_6356}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6374, pci_vendor_6374, pci_ss_list_6374}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6409, pci_vendor_6409, pci_ss_list_6409}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6666, pci_vendor_6666, pci_ss_list_6666}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7604, pci_vendor_7604, pci_ss_list_7604}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7bde, pci_vendor_7bde, pci_ss_list_7bde}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7fed, pci_vendor_7fed, pci_ss_list_7fed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8008, pci_vendor_8008, pci_ss_list_8008}, +#endif + {0x8086, pci_vendor_8086, pci_ss_list_8086}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8800, pci_vendor_8800, pci_ss_list_8800}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8866, pci_vendor_8866, pci_ss_list_8866}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8888, pci_vendor_8888, pci_ss_list_8888}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8e0e, pci_vendor_8e0e, pci_ss_list_8e0e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8e2e, pci_vendor_8e2e, pci_ss_list_8e2e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9004, pci_vendor_9004, pci_ss_list_9004}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9005, pci_vendor_9005, pci_ss_list_9005}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x907f, pci_vendor_907f, pci_ss_list_907f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x919a, pci_vendor_919a, pci_ss_list_919a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9412, pci_vendor_9412, pci_ss_list_9412}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9699, pci_vendor_9699, pci_ss_list_9699}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9710, pci_vendor_9710, pci_ss_list_9710}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa0a0, pci_vendor_a0a0, pci_ss_list_a0a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa0f1, pci_vendor_a0f1, pci_ss_list_a0f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa200, pci_vendor_a200, pci_ss_list_a200}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa259, pci_vendor_a259, pci_ss_list_a259}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa25b, pci_vendor_a25b, pci_ss_list_a25b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa304, pci_vendor_a304, pci_ss_list_a304}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa727, pci_vendor_a727, pci_ss_list_a727}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xaa42, pci_vendor_aa42, pci_ss_list_aa42}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xac1e, pci_vendor_ac1e, pci_ss_list_ac1e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xb1b3, pci_vendor_b1b3, pci_ss_list_b1b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xbd11, pci_vendor_bd11, pci_ss_list_bd11}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc001, pci_vendor_c001, pci_ss_list_c001}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc0a9, pci_vendor_c0a9, pci_ss_list_c0a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc0de, pci_vendor_c0de, pci_ss_list_c0de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc0fe, pci_vendor_c0fe, pci_ss_list_c0fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xca50, pci_vendor_ca50, pci_ss_list_ca50}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xcafe, pci_vendor_cafe, pci_ss_list_cafe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xcccc, pci_vendor_cccc, pci_ss_list_cccc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xcddd, pci_vendor_cddd, pci_ss_list_cddd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd4d4, pci_vendor_d4d4, pci_ss_list_d4d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd531, pci_vendor_d531, pci_ss_list_d531}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd84d, pci_vendor_d84d, pci_ss_list_d84d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xdead, pci_vendor_dead, pci_ss_list_dead}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe000, pci_vendor_e000, pci_ss_list_e000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe159, pci_vendor_e159, pci_ss_list_e159}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe4bf, pci_vendor_e4bf, pci_ss_list_e4bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xea01, pci_vendor_ea01, pci_ss_list_ea01}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xea60, pci_vendor_ea60, pci_ss_list_ea60}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xeabb, pci_vendor_eabb, pci_ss_list_eabb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xeace, pci_vendor_eace, pci_ss_list_eace}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xec80, pci_vendor_ec80, pci_ss_list_ec80}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xecc0, pci_vendor_ecc0, pci_ss_list_ecc0}, +#endif + {0xedd8, pci_vendor_edd8, pci_ss_list_edd8}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xf1d0, pci_vendor_f1d0, pci_ss_list_f1d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfa57, pci_vendor_fa57, pci_ss_list_fa57}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfebd, pci_vendor_febd, pci_ss_list_febd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfeda, pci_vendor_feda, pci_ss_list_feda}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfffe, pci_vendor_fffe, pci_ss_list_fffe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xffff, pci_vendor_ffff, pci_ss_list_ffff}, +#endif + {0x0000, NULL, NULL} +}; +#endif |