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Diffstat (limited to 'hw/xfree86/ramdac/TI.c')
-rw-r--r--hw/xfree86/ramdac/TI.c838
1 files changed, 423 insertions, 415 deletions
diff --git a/hw/xfree86/ramdac/TI.c b/hw/xfree86/ramdac/TI.c
index eee5d45cf..393b774d4 100644
--- a/hw/xfree86/ramdac/TI.c
+++ b/hw/xfree86/ramdac/TI.c
@@ -43,28 +43,27 @@
#define TI_MAX_VCO_FREQ 220000
unsigned long
-TIramdacCalculateMNPForClock(
- unsigned long RefClock, /* In 100Hz units */
- unsigned long ReqClock, /* In 100Hz units */
- char IsPixClock, /* boolean, is this the pixel or the sys clock */
- unsigned long MinClock, /* Min VCO rating */
- unsigned long MaxClock, /* Max VCO rating */
- unsigned long *rM, /* M Out */
- unsigned long *rN, /* N Out */
- unsigned long *rP /* Min P In, P Out */
-)
+TIramdacCalculateMNPForClock(unsigned long RefClock, /* In 100Hz units */
+ unsigned long ReqClock, /* In 100Hz units */
+ char IsPixClock, /* boolean, is this the pixel or the sys clock */
+ unsigned long MinClock, /* Min VCO rating */
+ unsigned long MaxClock, /* Max VCO rating */
+ unsigned long *rM, /* M Out */
+ unsigned long *rN, /* N Out */
+ unsigned long *rP /* Min P In, P Out */
+ )
{
- unsigned long n, p;
- unsigned long best_m = 0, best_n = 0;
- double VCO, IntRef = (double)RefClock;
- double m_err, inc_m, calc_m;
- unsigned long ActualClock;
+ unsigned long n, p;
+ unsigned long best_m = 0, best_n = 0;
+ double VCO, IntRef = (double) RefClock;
+ double m_err, inc_m, calc_m;
+ unsigned long ActualClock;
/* Make sure that MinClock <= ReqClock <= MaxClock */
- if ( ReqClock < MinClock)
- ReqClock = MinClock;
- if ( ReqClock > MaxClock )
- ReqClock = MaxClock;
+ if (ReqClock < MinClock)
+ ReqClock = MinClock;
+ if (ReqClock > MaxClock)
+ ReqClock = MaxClock;
/*
* ActualClock = VCO / 2 ^ p
@@ -72,15 +71,15 @@ TIramdacCalculateMNPForClock(
* Note that since TI_MAX_VCO_FREQ = 2 * TI_MIN_VCO_FREQ
* we don't have to bother checking for this maximum limit.
*/
- VCO = (double)ReqClock;
- for ( p = 0; p < 3 && VCO < TI_MIN_VCO_FREQ; ( p )++ )
- VCO *= 2.0;
+ VCO = (double) ReqClock;
+ for (p = 0; p < 3 && VCO < TI_MIN_VCO_FREQ; (p)++)
+ VCO *= 2.0;
/*
* We avoid doing multiplications by ( 65 - n ),
* and add an increment instead - this keeps any error small.
*/
- inc_m = VCO / ( IntRef * 8.0 );
+ inc_m = VCO / (IntRef * 8.0);
/* Initial value of calc_m for the loop */
calc_m = inc_m + inc_m + inc_m;
@@ -89,21 +88,21 @@ TIramdacCalculateMNPForClock(
m_err = 2.0;
/* Search for the closest INTEGER value of ( 65 - m ) */
- for ( n = 3; n <= 25; ( n )++, calc_m += inc_m ) {
-
- /* Ignore values of ( 65 - m ) which we can't use */
- if ( calc_m < 3.0 || calc_m > 64.0 )
- continue;
-
- /*
- * Pick the closest INTEGER (has smallest fractional part).
- * The optimizer should clean this up for us.
- */
- if (( calc_m - ( int ) calc_m ) < m_err ) {
- m_err = calc_m - ( int ) calc_m;
- best_m = ( int ) calc_m;
- best_n = n;
- }
+ for (n = 3; n <= 25; (n)++, calc_m += inc_m) {
+
+ /* Ignore values of ( 65 - m ) which we can't use */
+ if (calc_m < 3.0 || calc_m > 64.0)
+ continue;
+
+ /*
+ * Pick the closest INTEGER (has smallest fractional part).
+ * The optimizer should clean this up for us.
+ */
+ if ((calc_m - (int) calc_m) < m_err) {
+ m_err = calc_m - (int) calc_m;
+ best_m = (int) calc_m;
+ best_n = n;
+ }
}
/* 65 - ( 65 - x ) = x */
@@ -113,17 +112,17 @@ TIramdacCalculateMNPForClock(
/* Now all the calculations can be completed */
VCO = 8.0 * IntRef * best_m / best_n;
- ActualClock = VCO / ( 1 << p );
+ ActualClock = VCO / (1 << p);
- DebugF( "f_out=%ld f_vco=%.1f n=%d m=%d p=%d\n",
- ActualClock, VCO, *rN, *rM, *rP);
+ DebugF("f_out=%ld f_vco=%.1f n=%d m=%d p=%d\n",
+ ActualClock, VCO, *rN, *rM, *rP);
return ActualClock;
}
void
TIramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr ramdacPtr,
- RamDacRegRecPtr ramdacReg)
+ RamDacRegRecPtr ramdacReg)
{
int i;
unsigned long status;
@@ -139,7 +138,7 @@ TIramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr ramdacPtr,
TIRESTORE(TIDAC_palette_page);
TIRESTORE(TIDAC_general_ctrl);
TIRESTORE(TIDAC_misc_ctrl);
- /* 0x2A & 0x2B are reserved */
+ /* 0x2A & 0x2B are reserved */
TIRESTORE(TIDAC_key_over_low);
TIRESTORE(TIDAC_key_over_high);
TIRESTORE(TIDAC_key_red_low);
@@ -149,8 +148,8 @@ TIramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr ramdacPtr,
TIRESTORE(TIDAC_key_blue_low);
TIRESTORE(TIDAC_key_blue_high);
TIRESTORE(TIDAC_key_ctrl);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_clock_ctrl, 0, 0x30);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_clock_ctrl, 0, 0x38);
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_clock_ctrl, 0, 0x30);
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_clock_ctrl, 0, 0x38);
TIRESTORE(TIDAC_clock_ctrl);
TIRESTORE(TIDAC_sense_test);
TIRESTORE(TIDAC_ind_curs_ctrl);
@@ -158,102 +157,102 @@ TIramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr ramdacPtr,
/* only restore clocks if they were valid to begin with */
if (ramdacReg->DacRegs[TIDAC_PIXEL_VALID]) {
- /* Reset pixel clock */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x22);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_pixel_data, 0, 0x3c);
-
- /* Restore N, M & P values for pixel clocks */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_pixel_data, 0,
- ramdacReg->DacRegs[TIDAC_PIXEL_N]);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_pixel_data, 0,
- ramdacReg->DacRegs[TIDAC_PIXEL_M]);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_pixel_data, 0,
- ramdacReg->DacRegs[TIDAC_PIXEL_P]);
-
- /* wait for pixel clock to lock */
- i = 1000000;
- do {
- status = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_pixel_data);
- } while ((!(status & 0x40)) && (--i));
- if (!(status & 0x40)) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Pixel clock setup timed out\n");
- return;
- }
+ /* Reset pixel clock */
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0x22);
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_pixel_data, 0, 0x3c);
+
+ /* Restore N, M & P values for pixel clocks */
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0);
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_pixel_data, 0,
+ ramdacReg->DacRegs[TIDAC_PIXEL_N]);
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_pixel_data, 0,
+ ramdacReg->DacRegs[TIDAC_PIXEL_M]);
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_pixel_data, 0,
+ ramdacReg->DacRegs[TIDAC_PIXEL_P]);
+
+ /* wait for pixel clock to lock */
+ i = 1000000;
+ do {
+ status = (*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_pixel_data);
+ } while ((!(status & 0x40)) && (--i));
+ if (!(status & 0x40)) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Pixel clock setup timed out\n");
+ return;
+ }
}
if (ramdacReg->DacRegs[TIDAC_LOOP_VALID]) {
- /* Reset loop clock */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x22);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_loop_data, 0, 0x70);
-
- /* Restore N, M & P values for pixel clocks */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_loop_data, 0,
- ramdacReg->DacRegs[TIDAC_LOOP_N]);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_loop_data, 0,
- ramdacReg->DacRegs[TIDAC_LOOP_M]);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_loop_data, 0,
- ramdacReg->DacRegs[TIDAC_LOOP_P]);
-
- /* wait for loop clock to lock */
- i = 1000000;
- do {
- status = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_loop_data);
- } while ((!(status & 0x40)) && (--i));
- if (!(status & 0x40)) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Loop clock setup timed out\n");
- return;
- }
+ /* Reset loop clock */
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0x22);
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_loop_data, 0, 0x70);
+
+ /* Restore N, M & P values for pixel clocks */
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0);
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_loop_data, 0,
+ ramdacReg->DacRegs[TIDAC_LOOP_N]);
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_loop_data, 0,
+ ramdacReg->DacRegs[TIDAC_LOOP_M]);
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_loop_data, 0,
+ ramdacReg->DacRegs[TIDAC_LOOP_P]);
+
+ /* wait for loop clock to lock */
+ i = 1000000;
+ do {
+ status = (*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_loop_data);
+ } while ((!(status & 0x40)) && (--i));
+ if (!(status & 0x40)) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Loop clock setup timed out\n");
+ return;
+ }
}
/* restore palette */
- (*ramdacPtr->WriteAddress)(pScrn, 0);
+ (*ramdacPtr->WriteAddress) (pScrn, 0);
#ifndef NOT_DONE
- for (i=0;i<768;i++)
- (*ramdacPtr->WriteData)(pScrn, ramdacReg->DAC[i]);
+ for (i = 0; i < 768; i++)
+ (*ramdacPtr->WriteData) (pScrn, ramdacReg->DAC[i]);
#else
- (*ramdacPtr->WriteData)(pScrn, 0);
- (*ramdacPtr->WriteData)(pScrn, 0);
- (*ramdacPtr->WriteData)(pScrn, 0);
- for (i=0;i<765;i++)
- (*ramdacPtr->WriteData)(pScrn, 0xff);
+ (*ramdacPtr->WriteData) (pScrn, 0);
+ (*ramdacPtr->WriteData) (pScrn, 0);
+ (*ramdacPtr->WriteData) (pScrn, 0);
+ for (i = 0; i < 765; i++)
+ (*ramdacPtr->WriteData) (pScrn, 0xff);
#endif
}
void
-TIramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr ramdacPtr,
- RamDacRegRecPtr ramdacReg)
+TIramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr ramdacPtr,
+ RamDacRegRecPtr ramdacReg)
{
int i;
- (*ramdacPtr->ReadAddress)(pScrn, 0);
- for (i=0;i<768;i++)
- ramdacReg->DAC[i] = (*ramdacPtr->ReadData)(pScrn);
+ (*ramdacPtr->ReadAddress) (pScrn, 0);
+ for (i = 0; i < 768; i++)
+ ramdacReg->DAC[i] = (*ramdacPtr->ReadData) (pScrn);
/* Read back N,M and P values for pixel clock */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0);
- ramdacReg->DacRegs[TIDAC_PIXEL_N] =
- (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_pixel_data);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x11);
- ramdacReg->DacRegs[TIDAC_PIXEL_M] =
- (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_pixel_data);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x22);
- ramdacReg->DacRegs[TIDAC_PIXEL_P] =
- (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_pixel_data);
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0);
+ ramdacReg->DacRegs[TIDAC_PIXEL_N] =
+ (*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_pixel_data);
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0x11);
+ ramdacReg->DacRegs[TIDAC_PIXEL_M] =
+ (*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_pixel_data);
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0x22);
+ ramdacReg->DacRegs[TIDAC_PIXEL_P] =
+ (*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_pixel_data);
/* Read back N,M and P values for loop clock */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0);
- ramdacReg->DacRegs[TIDAC_LOOP_N] =
- (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_loop_data);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x11);
- ramdacReg->DacRegs[TIDAC_LOOP_M] =
- (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_loop_data);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x22);
- ramdacReg->DacRegs[TIDAC_LOOP_P] =
- (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_loop_data);
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0);
+ ramdacReg->DacRegs[TIDAC_LOOP_N] =
+ (*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_loop_data);
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0x11);
+ ramdacReg->DacRegs[TIDAC_LOOP_M] =
+ (*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_loop_data);
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0x22);
+ ramdacReg->DacRegs[TIDAC_LOOP_P] =
+ (*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_loop_data);
/* Order is important */
TISAVE(TIDAC_latch_ctrl);
@@ -263,7 +262,7 @@ TIramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr ramdacPtr,
TISAVE(TIDAC_palette_page);
TISAVE(TIDAC_general_ctrl);
TISAVE(TIDAC_misc_ctrl);
- /* 0x2A & 0x2B are reserved */
+ /* 0x2A & 0x2B are reserved */
TISAVE(TIDAC_key_over_low);
TISAVE(TIDAC_key_over_high);
TISAVE(TIDAC_key_red_low);
@@ -289,59 +288,61 @@ TIramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs)
unsigned char id, rev, rev2, id2;
/* read ID and revision */
- rev = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_rev);
- id = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_id);
+ rev = (*ramdacPtr->ReadDAC) (pScrn, TIDAC_rev);
+ id = (*ramdacPtr->ReadDAC) (pScrn, TIDAC_id);
/* check if ID and revision are read only */
- (*ramdacPtr->WriteDAC)(pScrn, ~rev, 0, TIDAC_rev);
- (*ramdacPtr->WriteDAC)(pScrn, ~id, 0, TIDAC_id);
- rev2 = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_rev);
- id2 = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_id);
+ (*ramdacPtr->WriteDAC) (pScrn, ~rev, 0, TIDAC_rev);
+ (*ramdacPtr->WriteDAC) (pScrn, ~id, 0, TIDAC_id);
+ rev2 = (*ramdacPtr->ReadDAC) (pScrn, TIDAC_rev);
+ id2 = (*ramdacPtr->ReadDAC) (pScrn, TIDAC_id);
switch (id) {
- case TIDAC_TVP_3030_ID:
- if (id == id2 && rev == rev2) /* check for READ ONLY */
- TIramdac_ID = TI3030_RAMDAC;
- break;
- case TIDAC_TVP_3026_ID:
- if (id == id2 && rev == rev2) /* check for READ ONLY */
- TIramdac_ID = TI3026_RAMDAC;
- break;
+ case TIDAC_TVP_3030_ID:
+ if (id == id2 && rev == rev2) /* check for READ ONLY */
+ TIramdac_ID = TI3030_RAMDAC;
+ break;
+ case TIDAC_TVP_3026_ID:
+ if (id == id2 && rev == rev2) /* check for READ ONLY */
+ TIramdac_ID = TI3026_RAMDAC;
+ break;
}
- (*ramdacPtr->WriteDAC)(pScrn, rev, 0, TIDAC_rev);
- (*ramdacPtr->WriteDAC)(pScrn, id, 0, TIDAC_id);
+ (*ramdacPtr->WriteDAC) (pScrn, rev, 0, TIDAC_rev);
+ (*ramdacPtr->WriteDAC) (pScrn, id, 0, TIDAC_id);
if (TIramdac_ID == -1) {
- xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
- "Cannot determine TI RAMDAC type, aborting\n");
- return NULL;
- } else {
- xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
- "Attached RAMDAC is %s\n", TIramdacDeviceInfo[TIramdac_ID&0xFFFF].DeviceName);
+ xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
+ "Cannot determine TI RAMDAC type, aborting\n");
+ return NULL;
+ }
+ else {
+ xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
+ "Attached RAMDAC is %s\n",
+ TIramdacDeviceInfo[TIramdac_ID & 0xFFFF].DeviceName);
}
- for (i=0;ramdacs[i].token != -1;i++) {
- if (ramdacs[i].token == TIramdac_ID)
- RamDacIsSupported = TRUE;
+ for (i = 0; ramdacs[i].token != -1; i++) {
+ if (ramdacs[i].token == TIramdac_ID)
+ RamDacIsSupported = TRUE;
}
if (!RamDacIsSupported) {
- xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
- "This TI RAMDAC is NOT supported by this driver, aborting\n");
- return NULL;
+ xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
+ "This TI RAMDAC is NOT supported by this driver, aborting\n");
+ return NULL;
}
ramdacHelperPtr = RamDacHelperCreateInfoRec();
switch (TIramdac_ID) {
- case TI3030_RAMDAC:
- ramdacHelperPtr->SetBpp = TIramdac3030SetBpp;
- ramdacHelperPtr->HWCursorInit = TIramdacHWCursorInit;
- break;
- case TI3026_RAMDAC:
- ramdacHelperPtr->SetBpp = TIramdac3026SetBpp;
- ramdacHelperPtr->HWCursorInit = TIramdacHWCursorInit;
- break;
+ case TI3030_RAMDAC:
+ ramdacHelperPtr->SetBpp = TIramdac3030SetBpp;
+ ramdacHelperPtr->HWCursorInit = TIramdacHWCursorInit;
+ break;
+ case TI3026_RAMDAC:
+ ramdacHelperPtr->SetBpp = TIramdac3026SetBpp;
+ ramdacHelperPtr->HWCursorInit = TIramdacHWCursorInit;
+ break;
}
ramdacPtr->RamDacType = TIramdac_ID;
ramdacHelperPtr->RamDacType = TIramdac_ID;
@@ -356,115 +357,116 @@ TIramdac3026SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr ramdacReg)
{
switch (pScrn->bitsPerPixel) {
case 32:
- /* order is important */
- ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
- ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x46;
- ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x5c;
- ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
- ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
- ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
- ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
- /* 0x2A & 0x2B are reserved */
- ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
- ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
- ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
- if (pScrn->overlayFlags & OVERLAY_8_32_PLANAR) {
- ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x06;
- ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
- ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x01;
- }
- ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
- break;
+ /* order is important */
+ ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x46;
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x5c;
+ ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
+ ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
+ ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
+ /* 0x2A & 0x2B are reserved */
+ ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
+ ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
+ if (pScrn->overlayFlags & OVERLAY_8_32_PLANAR) {
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x06;
+ ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
+ ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x01;
+ }
+ ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
+ break;
case 24:
- /* order is important */
- ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
- ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x56;
- ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x58;
- ramdacReg->DacRegs[TIDAC_clock_select] = 0x25;
- ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
- ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
- ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
- /* 0x2A & 0x2B are reserved */
- ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
- ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
- ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
- ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
- break;
+ /* order is important */
+ ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x56;
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x58;
+ ramdacReg->DacRegs[TIDAC_clock_select] = 0x25;
+ ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
+ ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
+ ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
+ /* 0x2A & 0x2B are reserved */
+ ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
+ ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
+ ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
+ break;
case 16:
- /* order is important */
+ /* order is important */
#if 0
- /* Matrox driver uses this */
- ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x07;
+ /* Matrox driver uses this */
+ ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x07;
#else
- ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
+ ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
#endif
- if (pScrn->depth == 16) {
- ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x45;
- } else {
- ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x44;
- }
+ if (pScrn->depth == 16) {
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x45;
+ }
+ else {
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x44;
+ }
#if 0
- /* Matrox driver uses this */
- ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x50;
- ramdacReg->DacRegs[TIDAC_clock_select] = 0x15;
- ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
- ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
+ /* Matrox driver uses this */
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x50;
+ ramdacReg->DacRegs[TIDAC_clock_select] = 0x15;
+ ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
+ ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
#else
- ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x54;
- ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
- ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
- ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x54;
+ ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
+ ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
+ ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
#endif
- ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
- /* 0x2A & 0x2B are reserved */
- ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
- ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
- ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
- ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
- break;
+ ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
+ /* 0x2A & 0x2B are reserved */
+ ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
+ ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
+ ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
+ break;
case 8:
- /* order is important */
- ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
- ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x80;
- ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x4c;
- ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
- ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
- ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
- ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x1C;
- /* 0x2A & 0x2B are reserved */
- ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_low] = 0x00;
- ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
- ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x00;
- ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
- ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
- break;
+ /* order is important */
+ ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x80;
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x4c;
+ ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
+ ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
+ ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x1C;
+ /* 0x2A & 0x2B are reserved */
+ ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_low] = 0x00;
+ ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
+ ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x00;
+ ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
+ ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
+ break;
}
}
@@ -473,125 +475,126 @@ TIramdac3030SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr ramdacReg)
{
switch (pScrn->bitsPerPixel) {
case 32:
- /* order is important */
- ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
- ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x46;
- ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x5D;
- ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
- ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
- ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
- ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
- /* 0x2A & 0x2B are reserved */
- ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
- ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
- ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
- if (pScrn->overlayFlags & OVERLAY_8_32_PLANAR) {
- ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x06;
- ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
- ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x01;
- }
- ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
- break;
+ /* order is important */
+ ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x46;
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x5D;
+ ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
+ ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
+ ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
+ /* 0x2A & 0x2B are reserved */
+ ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
+ ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
+ if (pScrn->overlayFlags & OVERLAY_8_32_PLANAR) {
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x06;
+ ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
+ ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x01;
+ }
+ ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
+ break;
case 24:
- /* order is important */
- ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
- ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x56;
- ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x58;
- ramdacReg->DacRegs[TIDAC_clock_select] = 0x25;
- ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
- ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
- ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
- /* 0x2A & 0x2B are reserved */
- ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
- ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
- ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
- ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
- break;
+ /* order is important */
+ ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x56;
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x58;
+ ramdacReg->DacRegs[TIDAC_clock_select] = 0x25;
+ ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
+ ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
+ ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
+ /* 0x2A & 0x2B are reserved */
+ ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
+ ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
+ ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
+ break;
case 16:
- /* order is important */
+ /* order is important */
#if 0
- /* Matrox driver uses this */
- ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x07;
+ /* Matrox driver uses this */
+ ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x07;
#else
- ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
+ ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
#endif
- if (pScrn->depth == 16) {
- ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x45;
- } else {
- ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x44;
- }
+ if (pScrn->depth == 16) {
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x45;
+ }
+ else {
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x44;
+ }
#if 0
- /* Matrox driver uses this */
- ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x50;
- ramdacReg->DacRegs[TIDAC_clock_select] = 0x15;
- ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
- ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
+ /* Matrox driver uses this */
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x50;
+ ramdacReg->DacRegs[TIDAC_clock_select] = 0x15;
+ ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
+ ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
#else
- ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x55;
- ramdacReg->DacRegs[TIDAC_clock_select] = 0x85;
- ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
- ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x55;
+ ramdacReg->DacRegs[TIDAC_clock_select] = 0x85;
+ ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
+ ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
#endif
- ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
- /* 0x2A & 0x2B are reserved */
- ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
- ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
- ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
- ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
- break;
+ ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
+ /* 0x2A & 0x2B are reserved */
+ ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
+ ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
+ ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
+ break;
case 8:
- /* order is important */
- ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
- ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x80;
- ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x4d;
- ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
- ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
- ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
- ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x1C;
- /* 0x2A & 0x2B are reserved */
- ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_low] = 0x00;
- ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
- ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x00;
- ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
- ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
- break;
+ /* order is important */
+ ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x80;
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x4d;
+ ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
+ ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
+ ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x1C;
+ /* 0x2A & 0x2B are reserved */
+ ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_low] = 0x00;
+ ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
+ ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x00;
+ ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
+ ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
+ break;
}
}
-static void
+static void
TIramdacShowCursor(ScrnInfoPtr pScrn)
{
RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
/* Enable cursor - X11 mode */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_ind_curs_ctrl, 0, 0x03);
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_ind_curs_ctrl, 0, 0x03);
}
static void
@@ -600,7 +603,7 @@ TIramdacHideCursor(ScrnInfoPtr pScrn)
RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
/* Disable cursor - X11 mode */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_ind_curs_ctrl, 0, 0x00);
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_ind_curs_ctrl, 0, 0x00);
}
static void
@@ -611,10 +614,10 @@ TIramdacSetCursorPosition(ScrnInfoPtr pScrn, int x, int y)
x += 64;
y += 64;
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_XLOW, 0, x & 0xff);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_XHIGH, 0, (x >> 8) & 0x0f);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_YLOW, 0, y & 0xff);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_YHIGH, 0, (y >> 8) & 0x0f);
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_XLOW, 0, x & 0xff);
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_XHIGH, 0, (x >> 8) & 0x0f);
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_YLOW, 0, y & 0xff);
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_YHIGH, 0, (y >> 8) & 0x0f);
}
static void
@@ -623,36 +626,40 @@ TIramdacSetCursorColors(ScrnInfoPtr pScrn, int bg, int fg)
RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
/* Background color */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_WRITE_ADDR, 0, 1);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_COLOR, 0, ((bg&0x00ff0000) >> 16));
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_COLOR, 0, ((bg&0x0000ff00) >> 8));
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_COLOR, 0, (bg&0x000000ff) );
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_WRITE_ADDR, 0, 1);
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_COLOR, 0,
+ ((bg & 0x00ff0000) >> 16));
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_COLOR, 0,
+ ((bg & 0x0000ff00) >> 8));
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_COLOR, 0, (bg & 0x000000ff));
/* Foreground color */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_WRITE_ADDR, 0, 2);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_COLOR, 0, ((fg&0x00ff0000) >> 16));
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_COLOR, 0, ((fg&0x0000ff00) >> 8));
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_COLOR, 0, (fg&0x000000ff) );
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_WRITE_ADDR, 0, 2);
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_COLOR, 0,
+ ((fg & 0x00ff0000) >> 16));
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_COLOR, 0,
+ ((fg & 0x0000ff00) >> 8));
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_COLOR, 0, (fg & 0x000000ff));
}
-static void
+static void
TIramdacLoadCursorImage(ScrnInfoPtr pScrn, unsigned char *src)
{
RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
int i = 1024;
/* reset A9,A8 */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_ind_curs_ctrl, 0, 0x00);
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_ind_curs_ctrl, 0, 0x00);
/* reset cursor RAM load address A7..A0 */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_INDEX, 0x00, 0x00);
-
- while(i--) {
- /* NOT_DONE: might need a delay here */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_RAM_DATA, 0, *(src++));
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_INDEX, 0x00, 0x00);
+
+ while (i--) {
+ /* NOT_DONE: might need a delay here */
+ (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_RAM_DATA, 0, *(src++));
}
}
-static Bool
+static Bool
TIramdacUseHWCursor(ScreenPtr pScr, CursorPtr pCurs)
{
return TRUE;
@@ -664,8 +671,8 @@ TIramdacHWCursorInit(xf86CursorInfoPtr infoPtr)
infoPtr->MaxWidth = 64;
infoPtr->MaxHeight = 64;
infoPtr->Flags = HARDWARE_CURSOR_BIT_ORDER_MSBFIRST |
- HARDWARE_CURSOR_TRUECOLOR_AT_8BPP |
- HARDWARE_CURSOR_SOURCE_MASK_NOT_INTERLEAVED;
+ HARDWARE_CURSOR_TRUECOLOR_AT_8BPP |
+ HARDWARE_CURSOR_SOURCE_MASK_NOT_INTERLEAVED;
infoPtr->SetCursorColors = TIramdacSetCursorColors;
infoPtr->SetCursorPosition = TIramdacSetCursorPosition;
infoPtr->LoadCursorImage = TIramdacLoadCursorImage;
@@ -674,44 +681,45 @@ TIramdacHWCursorInit(xf86CursorInfoPtr infoPtr)
infoPtr->UseHWCursor = TIramdacUseHWCursor;
}
-void TIramdacLoadPalette(
- ScrnInfoPtr pScrn,
- int numColors,
- int *indices,
- LOCO *colors,
- VisualPtr pVisual
-){
+void
+TIramdacLoadPalette(ScrnInfoPtr pScrn,
+ int numColors,
+ int *indices, LOCO * colors, VisualPtr pVisual)
+{
RamDacRecPtr hwp = RAMDACSCRPTR(pScrn);
int i, index, shift;
if (pScrn->depth == 16) {
- for(i = 0; i < numColors; i++) {
- index = indices[i];
- (*hwp->WriteAddress)(pScrn, index << 2);
- (*hwp->WriteData)(pScrn, colors[index >> 1].red);
- (*hwp->WriteData)(pScrn, colors[index].green);
- (*hwp->WriteData)(pScrn, colors[index >> 1].blue);
-
- if(index <= 31) {
- (*hwp->WriteAddress)(pScrn, index << 3);
- (*hwp->WriteData)(pScrn, colors[index].red);
- (*hwp->WriteData)(pScrn, colors[(index << 1) + 1].green);
- (*hwp->WriteData)(pScrn, colors[index].blue);
- }
+ for (i = 0; i < numColors; i++) {
+ index = indices[i];
+ (*hwp->WriteAddress) (pScrn, index << 2);
+ (*hwp->WriteData) (pScrn, colors[index >> 1].red);
+ (*hwp->WriteData) (pScrn, colors[index].green);
+ (*hwp->WriteData) (pScrn, colors[index >> 1].blue);
+
+ if (index <= 31) {
+ (*hwp->WriteAddress) (pScrn, index << 3);
+ (*hwp->WriteData) (pScrn, colors[index].red);
+ (*hwp->WriteData) (pScrn, colors[(index << 1) + 1].green);
+ (*hwp->WriteData) (pScrn, colors[index].blue);
+ }
+ }
}
-} else {
- shift = (pScrn->depth == 15) ? 3 : 0;
-
- for(i = 0; i < numColors; i++) {
- index = indices[i];
- (*hwp->WriteAddress)(pScrn, index << shift);
- (*hwp->WriteData)(pScrn, colors[index].red);
- (*hwp->WriteData)(pScrn, colors[index].green);
- (*hwp->WriteData)(pScrn, colors[index].blue);
+ else {
+ shift = (pScrn->depth == 15) ? 3 : 0;
+
+ for (i = 0; i < numColors; i++) {
+ index = indices[i];
+ (*hwp->WriteAddress) (pScrn, index << shift);
+ (*hwp->WriteData) (pScrn, colors[index].red);
+ (*hwp->WriteData) (pScrn, colors[index].green);
+ (*hwp->WriteData) (pScrn, colors[index].blue);
+ }
}
}
-}
-TIramdacLoadPaletteProc *TIramdacLoadPaletteWeak(void) {
+TIramdacLoadPaletteProc *
+TIramdacLoadPaletteWeak(void)
+{
return TIramdacLoadPalette;
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-19 07:34:02 +0000