1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
|
/*
* Copyright 2011 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Authors: Alex Deucher <alexander.deucher@amd.com>
*
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "xf86.h"
#include <errno.h>
#include "radeon.h"
#include "radeon_reg.h"
#include "cayman_reg.h"
#include "evergreen_state.h"
#include "radeon_vbo.h"
#include "radeon_exa_shared.h"
/*
* Setup of default state
*/
void
cayman_set_default_state(ScrnInfoPtr pScrn)
{
tex_resource_t tex_res;
shader_config_t fs_conf;
int i;
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
if (accel_state->XInited3D)
return;
memset(&tex_res, 0, sizeof(tex_resource_t));
memset(&fs_conf, 0, sizeof(shader_config_t));
accel_state->XInited3D = TRUE;
evergreen_start_3d(pScrn);
BEGIN_BATCH(21);
EREG(SQ_LDS_ALLOC_PS, 0);
PACK0(SQ_ESGS_RING_ITEMSIZE, 6);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
PACK0(SQ_GS_VERT_ITEMSIZE, 4);
E32(0);
E32(0);
E32(0);
E32(0);
PACK0(SQ_VTX_BASE_VTX_LOC, 2);
E32(0);
E32(0);
END_BATCH();
/* DB */
BEGIN_BATCH(3 + 2);
EREG(DB_Z_INFO, 0);
RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
BEGIN_BATCH(3 + 2);
EREG(DB_STENCIL_INFO, 0);
RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
BEGIN_BATCH(3 + 2);
EREG(DB_HTILE_DATA_BASE, 0);
RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
BEGIN_BATCH(52);
EREG(DB_DEPTH_INFO, 0);
EREG(DB_DEPTH_CONTROL, 0);
PACK0(PA_SC_VPORT_ZMIN_0, 2);
EFLOAT(0.0); // PA_SC_VPORT_ZMIN_0
EFLOAT(1.0); // PA_SC_VPORT_ZMAX_0
PACK0(DB_RENDER_CONTROL, 5);
E32(STENCIL_COMPRESS_DISABLE_bit | DEPTH_COMPRESS_DISABLE_bit); // DB_RENDER_CONTROL
E32(0); // DB_COUNT_CONTROL
E32(0); // DB_DEPTH_VIEW
E32(0x2a); // DB_RENDER_OVERRIDE
E32(0); // DB_RENDER_OVERRIDE2
PACK0(DB_STENCIL_CLEAR, 2);
E32(0); // DB_STENCIL_CLEAR
E32(0); // DB_DEPTH_CLEAR
EREG(DB_ALPHA_TO_MASK, ((2 << ALPHA_TO_MASK_OFFSET0_shift) |
(2 << ALPHA_TO_MASK_OFFSET1_shift) |
(2 << ALPHA_TO_MASK_OFFSET2_shift) |
(2 << ALPHA_TO_MASK_OFFSET3_shift)));
EREG(DB_SHADER_CONTROL, ((EARLY_Z_THEN_LATE_Z << Z_ORDER_shift) |
DUAL_EXPORT_ENABLE_bit)); /* Only useful if no depth export */
// SX
EREG(SX_MISC, 0);
// CB
PACK0(SX_ALPHA_TEST_CONTROL, 5);
E32(0); // SX_ALPHA_TEST_CONTROL
E32(0x00000000); //CB_BLEND_RED
E32(0x00000000); //CB_BLEND_GREEN
E32(0x00000000); //CB_BLEND_BLUE
E32(0x00000000); //CB_BLEND_ALPHA
EREG(CB_SHADER_MASK, OUTPUT0_ENABLE_mask);
// SC
EREG(PA_SC_WINDOW_OFFSET, ((0 << WINDOW_X_OFFSET_shift) |
(0 << WINDOW_Y_OFFSET_shift)));
EREG(PA_SC_CLIPRECT_RULE, CLIP_RULE_mask);
EREG(PA_SC_EDGERULE, 0xAAAAAAAA);
EREG(PA_SU_HARDWARE_SCREEN_OFFSET, 0);
END_BATCH();
/* clip boolean is set to always visible -> doesn't matter */
for (i = 0; i < PA_SC_CLIPRECT_0_TL_num; i++)
evergreen_set_clip_rect (pScrn, i, 0, 0, 8192, 8192);
for (i = 0; i < PA_SC_VPORT_SCISSOR_0_TL_num; i++)
evergreen_set_vport_scissor (pScrn, i, 0, 0, 8192, 8192);
BEGIN_BATCH(73);
PACK0(PA_SC_MODE_CNTL_0, 2);
E32(0); // PA_SC_MODE_CNTL_0
E32(0); // PA_SC_MODE_CNTL_1
PACK0(PA_SC_CENTROID_PRIORITY_0, 27);
E32((0 << DISTANCE_0_shift) |
(1 << DISTANCE_1_shift) |
(2 << DISTANCE_2_shift) |
(3 << DISTANCE_3_shift) |
(4 << DISTANCE_4_shift) |
(5 << DISTANCE_5_shift) |
(6 << DISTANCE_6_shift) |
(7 << DISTANCE_7_shift)); // PA_SC_CENTROID_PRIORITY_0
E32((8 << DISTANCE_8_shift) |
(9 << DISTANCE_9_shift) |
(10 << DISTANCE_10_shift) |
(11 << DISTANCE_11_shift) |
(12 << DISTANCE_12_shift) |
(13 << DISTANCE_13_shift) |
(14 << DISTANCE_14_shift) |
(15 << DISTANCE_15_shift)); // PA_SC_CENTROID_PRIORITY_1
E32(0); // PA_SC_LINE_CNTL
E32(0); // PA_SC_AA_CONFIG
E32(((X_ROUND_TO_EVEN << PA_SU_VTX_CNTL__ROUND_MODE_shift) |
PIX_CENTER_bit)); // PA_SU_VTX_CNTL
EFLOAT(1.0); // PA_CL_GB_VERT_CLIP_ADJ
EFLOAT(1.0); // PA_CL_GB_VERT_DISC_ADJ
EFLOAT(1.0); // PA_CL_GB_HORZ_CLIP_ADJ
EFLOAT(1.0); // PA_CL_GB_HORZ_DISC_ADJ
E32(0); // PA_SC_AA_SAMPLE_LOCS_PIXEL_*
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0); // PA_SC_AA_SAMPLE_LOCS__PIXEL_*
E32(0xFFFFFFFF); // PA_SC_AA_MASK_*
E32(0xFFFFFFFF); // PA_SC_AA_MASK_*
// CL
PACK0(PA_CL_CLIP_CNTL, 8);
E32(CLIP_DISABLE_bit); // PA_CL_CLIP_CNTL
E32(FACE_bit); // PA_SU_SC_MODE_CNTL
E32(VTX_XY_FMT_bit); // PA_CL_VTE_CNTL
E32(0); // PA_CL_VS_OUT_CNTL
E32(0); // PA_CL_NANINF_CNTL
E32(0); // PA_SU_LINE_STIPPLE_CNTL
E32(0); // PA_SU_LINE_STIPPLE_SCALE
E32(0); // PA_SU_PRIM_FILTER_CNTL
// SU
PACK0(PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
/* src = semantic id 0; mask = semantic id 1 */
EREG(SPI_VS_OUT_ID_0, ((0 << SEMANTIC_0_shift) |
(1 << SEMANTIC_1_shift)));
PACK0(SPI_PS_INPUT_CNTL_0 + (0 << 2), 2);
/* SPI_PS_INPUT_CNTL_0 maps to GPR[0] - load with semantic id 0 */
E32(((0 << SEMANTIC_shift) |
(0x01 << DEFAULT_VAL_shift)));
/* SPI_PS_INPUT_CNTL_1 maps to GPR[1] - load with semantic id 1 */
E32(((1 << SEMANTIC_shift) |
(0x01 << DEFAULT_VAL_shift)));
PACK0(SPI_INPUT_Z, 13);
E32(0); // SPI_INPUT_Z
E32(0); // SPI_FOG_CNTL
E32(LINEAR_CENTROID_ENA__X_ON_AT_CENTROID << LINEAR_CENTROID_ENA_shift); // SPI_BARYC_CNTL
E32(0); // SPI_PS_IN_CONTROL_2
E32(0);
E32(0);
E32(0);
E32(0);
E32(0); // SPI_GPR_MGMT
E32(0); // SPI_LDS_MGMT
E32(0); // SPI_STACK_MGMT
E32(0); // SPI_WAVE_MGMT_1
E32(0); // SPI_WAVE_MGMT_2
END_BATCH();
// clear FS
fs_conf.bo = accel_state->shaders_bo;
evergreen_fs_setup(pScrn, &fs_conf, RADEON_GEM_DOMAIN_VRAM);
// VGT
BEGIN_BATCH(46);
PACK0(VGT_MAX_VTX_INDX, 4);
E32(0xffffff);
E32(0);
E32(0);
E32(0);
PACK0(VGT_INSTANCE_STEP_RATE_0, 2);
E32(0);
E32(0);
PACK0(VGT_REUSE_OFF, 2);
E32(0);
E32(0);
PACK0(PA_SU_POINT_SIZE, 17);
E32(0); // PA_SU_POINT_SIZE
E32(0); // PA_SU_POINT_MINMAX
E32((8 << PA_SU_LINE_CNTL__WIDTH_shift)); /* Line width 1 pixel */ // PA_SU_LINE_CNTL
E32(0); // PA_SC_LINE_STIPPLE
E32(0); // VGT_OUTPUT_PATH_CNTL
E32(0); // VGT_HOS_CNTL
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0); // VGT_GS_MODE
EREG(VGT_PRIMITIVEID_EN, 0);
EREG(VGT_MULTI_PRIM_IB_RESET_EN, 0);
EREG(VGT_SHADER_STAGES_EN, 0);
PACK0(VGT_STRMOUT_CONFIG, 2);
E32(0);
E32(0);
END_BATCH();
}
|
