diff options
| author | Qiang Yu <Qiang.Yu@amd.com> | 2016-09-14 16:01:16 +0900 |
|---|---|---|
| committer | Michel Dänzer <michel.daenzer@amd.com> | 2016-09-14 16:01:16 +0900 |
| commit | 804dd4be71733f5f5078e5b4824abe9a9bb1228d (patch) | |
| tree | a5a19ac23a0b64c7baa779ead3f01553a2a50feb /src | |
| parent | a04f4015d6afef20c2b79e2779f6555836ee2b07 (diff) | |
Remove RR_Capability_SinkOutput for GPU without CRTC.
Signed-off-by: Qiang Yu <Qiang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
(Cherry picked from commit a0bbb373f902e0ffc14570c85faec7e44134f62e)
Diffstat (limited to 'src')
| -rw-r--r-- | src/amdgpu_kms.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/src/amdgpu_kms.c b/src/amdgpu_kms.c index ae98cf1..125cb77 100644 --- a/src/amdgpu_kms.c +++ b/src/amdgpu_kms.c @@ -758,8 +758,11 @@ static void AMDGPUSetupCapabilities(ScrnInfoPtr pScrn) if (ret == 0) { if (value & DRM_PRIME_CAP_EXPORT) pScrn->capabilities |= RR_Capability_SourceOutput | RR_Capability_SinkOffload; - if (value & DRM_PRIME_CAP_IMPORT) - pScrn->capabilities |= RR_Capability_SinkOutput | RR_Capability_SourceOffload; + if (value & DRM_PRIME_CAP_IMPORT) { + pScrn->capabilities |= RR_Capability_SourceOffload; + if (info->drmmode.count_crtcs) + pScrn->capabilities |= RR_Capability_SinkOutput; + } } #endif } @@ -873,8 +876,6 @@ Bool AMDGPUPreInit_KMS(ScrnInfoPtr pScrn, int flags) amdgpu_drm_queue_init(); - AMDGPUSetupCapabilities(pScrn); - /* don't enable tiling if accel is not enabled */ if (info->use_glamor) { /* set default group bytes, overridden by kernel info below */ @@ -928,6 +929,8 @@ Bool AMDGPUPreInit_KMS(ScrnInfoPtr pScrn, int flags) goto fail; } + AMDGPUSetupCapabilities(pScrn); + if (info->drmmode.count_crtcs == 1) pAMDGPUEnt->HasCRTC2 = FALSE; else |