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authorMichel Dänzer <michel.daenzer@amd.com>2016-02-15 18:28:13 +0900
committerMichel Dänzer <michel@daenzer.net>2016-02-19 11:49:12 +0900
commit7729b29b0a76c3e2eacfcb02abcbe115948b2937 (patch)
tree689bcb2041e227ca4118568afaef6133f87f4f1c
parent65ee496c0567ea6aaf947a6098fbf925d2f6b14b (diff)
Don't advertise any PRIME offloading capabilities without acceleration
Acceleration is required even for display offloading. Trying to enable display offloading without acceleration resulted in a crash. (ported from radeon commit b19417e2fddf4df725951aea5ad5e9558338f59e) Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 59c0a6807110eca829c6708e16585a38f39a5c17)
-rw-r--r--src/amdgpu_kms.c22
1 files changed, 10 insertions, 12 deletions
diff --git a/src/amdgpu_kms.c b/src/amdgpu_kms.c
index 75d35c1..c257941 100644
--- a/src/amdgpu_kms.c
+++ b/src/amdgpu_kms.c
@@ -663,25 +663,23 @@ static Bool amdgpu_get_tile_config(ScrnInfoPtr pScrn)
static void AMDGPUSetupCapabilities(ScrnInfoPtr pScrn)
{
#ifdef AMDGPU_PIXMAP_SHARING
+ AMDGPUInfoPtr info = AMDGPUPTR(pScrn);
AMDGPUEntPtr pAMDGPUEnt = AMDGPUEntPriv(pScrn);
uint64_t value;
int ret;
pScrn->capabilities = 0;
+
+ /* PRIME offloading requires acceleration */
+ if (!info->use_glamor)
+ return;
+
ret = drmGetCap(pAMDGPUEnt->fd, DRM_CAP_PRIME, &value);
if (ret == 0) {
- AMDGPUInfoPtr info = AMDGPUPTR(pScrn);
-
- if (value & DRM_PRIME_CAP_EXPORT) {
- pScrn->capabilities |= RR_Capability_SourceOutput;
- if (info->use_glamor && info->dri2.available)
- pScrn->capabilities |= RR_Capability_SinkOffload;
- }
- if (value & DRM_PRIME_CAP_IMPORT) {
- pScrn->capabilities |= RR_Capability_SinkOutput;
- if (info->use_glamor && info->dri2.available)
- pScrn->capabilities |= RR_Capability_SourceOffload;
- }
+ if (value & DRM_PRIME_CAP_EXPORT)
+ pScrn->capabilities |= RR_Capability_SourceOutput | RR_Capability_SinkOffload;
+ if (value & DRM_PRIME_CAP_IMPORT)
+ pScrn->capabilities |= RR_Capability_SinkOutput | RR_Capability_SourceOffload;
}
#endif
}