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# IntelRegisters
This is an attempt to explain the i8xx registers. It was started for the i830, and bits of information about the other models was unsystematically added. Please extend as appropriate, and mark the differences.
## Architecture overview
The i830 emulates two PCI cards. The register of the PCI cards seem to shadow each other, and the X driver only uses the first card.
There are several parts used for graphic output:
Display planes A,B,C --> Pipes A,B --> Analog/Digital Ports I2C control for TV encoder.
Some registers may be double buffered, and may need a write to another register to commit.
Here are some definitions from the i845G data sheet:
* A PLANE consists of a rectangular shaped image that has characteristics such as source, size, position, method, and format. These planes get attached to source surfaces that are rectangular memory surfaces with a similar set of characteristics. They are also associated with a destination pipe.
* A PIPE consists of a set of combined planes and a timing generator.
## I2C control
[[!table header="no" class="mointable" data="""
Chipset | I2C lines | Known TV
i810 | DDC; LTV | GPIOB = LTV
i830 | DDC1, I2C, DDC2; M_DDC, M_I2C | GPIOC = M_I2C
i845 | DDC_A; MI2C, MDVI, MDDC | GPIOE
i865 | DDC_A; MI2C, MDVI, MDDC | GPIOE = M_I2C
"""]]
On the i830, DVO port A uses DDC2 or I2C, DVO ports B/C use M_I2C or M_DDC. The DDC ports are used for EDID display information transfer from the monitor (typically at address 0xA0) or flat panel. On the I2C port a device at 0x04 has been observed, possibly a flat panel controller.
[[!table header="no" class="mointable" data="""
0x05010 | GPIOA General purpose I/O A, one of the DDC ports.
0x05014 | GPIOB General purpose I/O B, I2C port.
0x05018 | GPIOC General purpose I/O C, M_I2C port.
0x05020 | GPIOE General purpose I/O E (for i845)
0x05024 | GPIOF General purpose I/O F (for i???)
31:13 | reserved
12 | GPIO1 data in
11 | GPIO1 data value
10 | GPIO1 data mask (1=write data)
9 | GPIO1 direction value (0=input, 1=output)
8 | GPIO1 direction mask (1=write direction)
7: 5 | reserved
4 | GPIO0 data in
3 | GPIO0 data value
2 | GPIO0 data mask
1 | GPIO0 direction value
0 | GPIO0 direction mask
"""]]
GPIO1 is the data pin, GPIO0 is the clock pin. Maybe there are even more GPIO registers?
The i865 implements a hardware GMBus controller that can be used to control these signals. This allows higher speed transactions (up to 400 kHz) on theses lines than was allowed with previous software centric `bit-bashing' techniques.
It is not completely clear how the GMBus controller registers work.
[[!table header="no" class="mointable" data="""
0x05100 | GMBUS CLK_PORT_SEL
0x05104 | GMBUS CMD
?:16 | DATA_COUNT
?: 8 | SLAVE_REG
0x05108 | GMBUS_STATUS
0x0510C | GMBUS_DATA
"""]]
## Display planes
There are (at least) 3 display planes:
* A: primary display plane
* B: 'sprite' plane (for specific laptop display information?)
* C: overlay plane (can also be directly sent in YUV format to DVO)
The datasheet diagram shows overlay, sprite, two cursor, and primary and secondary display units. Maybe those correspond to the planes. The datasheet also meantions a popup plane for mobile applications. The single overlay plane can only displayed on "single-pipe simultanious displays" for multi-monitors. (For the i810, 0x70008 PIXCONF has some of the functions used here.) For the i865, these registers seem to be somewhere else.
[[!table header="no" class="mointable" data="""
0x70180 | DSPACTRL Display plane A control
0x71180 | DSPBCTRL Display plane B control
31 | plane enable (1=enabled)
30 | gamma correction enable (0=bypass, 1=enabled)
29:26 | pixformat (2=8BPP, 4=15_16BPP, 5=16BPP, 6=32BPP_NO_ALPHA, 7=32BPP)
25 | stereo enable (1=enabled)
24 | select pipe (0=A, 1=B)
23 | reserved
22 | source key enable (1=enabled)
21:20 | pixel multiplicity (0=normal, 1=doubleline, 2=3=reserved)
19 | reserved
18 | stereo polarity (0=first, 1=second)
17-16 | reserved
15 | alpha transfer mode (1=enabled) ; B only
14- 1 | reserved
0 | sprite_above (0=display A, 1=overlay) ; B only
"""]]
Note: 8BPP is indexed, 15_16BPP is 5-5-5, 16BPP is 5-6-5, 32BPP_NO_ALPHA is X:8:8:8, and 32BPP is 8:8:8:8.
Note: Stereo requires two start (base) addresses, at least for plane B.
It is not clear why a display plane has to connect to a pipe, instead of the other way round, unless the plane block also contains the counters.
|| 0x70184 || DSPABASE Display plane A base address || 0x71184 || DSPBBASE Display plane B base address
|| 0x70188 || DSPASTRIDE Display plane A stride (= pitch) || 0x71188 || DSPBSTRIDE Display plane B stride (= pitch) ||<)>31-16 || UNKNOWN, 15CF/0001 ||<)> ?- 0 || stride
## Pipes
There are two pipes, which control the timing.
[[!table header="no" class="mointable" data="""
0x60000 | HTOTAL_A
0x60004 | HBLANK_A
0x60008 | HSYNC_A
0x6000c | VTOTAL_A
0x60010 | VBLANK_A
0x60014 | VSYNC_A
0x6001c | PIPEASRC
26:16 | horizontal (= HTOTAL displayed)
10: 0 | vertical (= VTOTAL displayed)
0x60020 | BCLRPAT border color pattern
"""]]
Identical registers for pipe B are at 0x61000-0x61020.
On the i810, there also was the LCDTV_C register, which is probably not any longer supported.
[[!table header="no" class="mointable" data="""
0x60018 | LCDTV_C LCD/TV-Out control register
"""]]
[[!table header="no" class="mointable" data="""
0x70008 | PIPEACONF (PIXCONF for i810)
31 | enable (1=enabled)
30 | width (1=double, 0=single)
29:27 | reserved
25 | lock (1=locked) ; unclear
24 | (0=palette, 1=gamma)
23: 0 | reserved
0x71008 | PIPEBCONF
31 | enable (1=enabled)
30:25 | reserved
24 | (0=palette, 1=gamma)
23: 0 | reserved
"""]]
[[!table header="no" class="mointable" data="""
0x71400 | UNKNOWN (= 0020008e)
"""]]
## Analog/Digital Ports
There are three dedicated Digital Video Ports and one Analog Port. DVOB and C are multixplexed with the AGP pins. The local flat panel (LFP) is normally connected to DVOA. DVOB and DVOC may be combined into one 24bit wide port. DVO port signals are:
[[!table header="no" class="mointable" data="""
CLK/CLK# | differental clock output up to 165 MHz
D[11:0] | 12bit data
HSYNC | outgoing HSync with programmable polarity
VSYNC | outgoing VSync with programmable polarity
BLANK# | outgoing blank period or border period signal
INTR | incoming interrupt (DVOA and DVOBC)
CLKINT | incoming clock or second interrupt (DVOA and DVOBC)
FLD/STL | incoming TV field (to synchronize overlay) or FP stall signal
"""]]
The DPLL registers control the phase locked loops that convert the incoming to the outgoing clock, or possibly some internal clock to the outgoing clock. They are associated to the corresponding pipe.
[[!table header="no" class="mointable" data="""
0x06014 | DPLL_A
0x06018 | DPLL_B
31 | VCO enable (=1 for TFT, TV, mon)
30 | 2X clock enable (=1 for TFT, TV; =0 for mon)
29 | synclock enable (=0)
28 | VGA mode disable (=1 for TFT, TV, mon; =0 mon)
27:24 | reserved
24 | [i???] PLL divisor select
23 | P2 post divisor (loop divide flag?)
22 | reserved
21 | P1 force DIV2
20:16 | P1 post divisor
15 | reserved
14:13 | reference select (=0 for LCD/mon, =2 for TV ?)
12: 0 | reserved
1 | [i???] rate select mask (0=fp0, 1=fp1)
"""]]
There seems to be additional PLLs for the flat panel. (FIXME: Dave, please add a detailed explanation).
[[!table header="no" class="mointable" data="""
0x06040 | FPA0 flat panel PLL A0
0x06044 | FPA1 flat panel PLL A1
0x06048 | FPB0 flat panel PLL B0
0x0604C | FPB1 flat panel PLL B1
21:16 | N
13: 8 | M1
5: 0 | M2
"""]]
where M = 5*(M1+2) + (M2+2), and Clk = RefCLK * M / (N+2) / P
The ADPA register controls the analog output (monitor).
[[!table header="no" class="mointable" data="""
0x61100 | ADPA
31 | DAC enable (1=enabled) (=monitor enabled)
30 | Pipe select (0=A, 1=B) [maybe doesn't work]
29:16 | reserved
15 | Use_VGA_HVPolarity (0=Sets HVPolarity)
14:12 | UNKNOWN
11 | VSync control disable (1=disabled)
10 | HSync control disable (1=disabled)
9: 5 | reserved
4 | VSync active (0=low, 1=high)
3 | HSync active (0=low, 1=high)
2: 0 | reserved
"""]]
For the 3 DVO ports, only the enable bit is known. Other bits may include interrupt handling, polarity control for blank and sync signals, configuration of clock vs. second interrupt and field vs. stall.
[[!table header="no" class="mointable" data="""
0x61120 | DVOA
0x61140 | DVOB
0x61160 | DVOC
31 | DVO enable (1=enabled)
30 | Pipe select (guess!) (0=A, 1=B)
29 | UNKNOWN
15: 0 | UNKNOWN
14 | UNKNOWN
8 | UNKNOWN
7 | UNKNOWN
6 | UNKNOWN
4 | UNKNOWN
3 | UNKNOWN
2 | UNKNOWN
"""]]
This is used in i855 instead of DVO.
[[!table header="no" class="mointable" data="""
0x61180 | LVDS meaning unknown
"""]]
[[!table header="no" class="mointable" data="""
0x61124 | DVOA_SRCDIM
0x61144 | DVOB_SRCDIM
0x61164 | DVOC_SRCDIM
23:12 | (not needed ?)
11: 0 | (not needed ?)
"""]]
FIXME: What about 0x61104 ADPA_SRCDIM? and 0x61184 LVDS_SRCDIM? Maybe used for centering?
## Other registers
[[!table header="no" class="mointable" data="""
0x020cc | UNKNOWN = 000c000c / 0000004c
"""]]
There are now two watermark registers, with a format different from the I810 FW_BLC register.
[[!table header="no" class="mointable" data="""
0x020d8 | Watermark/Burst = 01080108
0x020dc | Watermark/Burst = 00000108
31:27 | reserved
26:24 | Burst B
23:21 | reserved
20:16 | Watermark B
15:12 | reserved
11: 8 | Burst A
7: 6 | reserved
5: 0 | Watermark A
"""]]
Software Flags (= scratch registers):
[[!table header="no" class="mointable" data="""
0x71410 | SWF0
0x71414 | SWF1 (amount of video memory available)
0x71418 | SWF2
0x7141c | SWF3
0x71420 | SWF4
0x71424 | SWF5
0x71428 | SWF6
"""]]
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