Age | Commit message (Collapse) | Author | Files | Lines |
|
I verified AVC VDEnc on KBL with the HuC loading patch from
https://patchwork.freedesktop.org/api/1.0/series/16584/revisions/1/mbox/
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Kelley, Sean V <sean.v.kelley@intel.com>
Tested-by: Tang, FuweiX <fuweix.tang@intel.com>
|
|
I verified AVC VDEnc with the HuC loading patch from
https://patchwork.freedesktop.org/api/1.0/series/16584/revisions/1/mbox/
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Tested-by: Tang, FuweiX <fuweix.tang@intel.com>
|
|
Not all profiles for vp9 are supported by the encoder and user needs
to know about it
Signed-off-by: Daniel Charles <daniel.charles@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
|
|
CBR and VBR for low power encode depend on the fully loaded HuC firmware.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
|
|
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
|
|
Signed-off-by: Pengfei Qu <Pengfei.Qu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
|
|
When sharing the YUY2/UYVY buffer with other driver, the current alignment is too
strict, which causes that it is not handled correctly by other driver.(The current
alignment is considered based on I420/YV12)
https://bugs.freedesktop.org/show_bug.cgi?id=96689
Tested-by: Cheah, Vincent Beng Keat<vincent.beng.keat.cheah@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
|
|
Allow up to 8K * 8K resolution for JPEG encode and decode on
gen9 HW (SKL,BXT,KBL).
Signed-off-by: U. Artie Eoff <ullysses.a.eoff@intel.com>
|
|
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Sean V Kelley <sean.v.kelley@intel.com>
|
|
Only CQP mode is supported by now
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-By: Sean V Kelley <sean.v.kelley@intel.com>
|
|
In addition, add IS_SKL() and IS_BXT() for later usage
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-By: Sean V Kelley <sean.v.kelley@intel.com>
|
|
With the commit 'CSC: Remove average logic when saving NV12 surface on IVB+',
This fixes https://bugs.freedesktop.org/show_bug.cgi?id=94845 on BXT/KBL
Reviewed-by: Kelley, Sean V <sean.v.kelley@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
|
|
v2:
ignore bit_depth for profile0,1
add the support of enum VAProfileVP9Profile2
v1:
initial
Signed-off-by: peng.chen <peng.c.chen@intel.com>
|
|
v2:
remove the file mode change
v1:
initial
Signed-off-by: peng.chen <peng.c.chen@intel.com>
|
|
v2:
1, remove VPP P016 related code
2, optimize NV12->P010
3, enable IECP if all DI&DN are disabled
v1:
initial
Signed-off-by: peng.chen <peng.c.chen@intel.com>
|
|
Signed-off-by: Sirisha Muppavarapu <sirisha.muppavarapu@intel.com>
Signed-off-by: peng.chen <peng.c.chen@intel.com>
|
|
v2: code cleanup
v3: store shift in an int to make it more readable (Emil)
Signed-off-by: Peng Chen <peng.c.chen@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Cc: Emil Velikov <emil.l.velikov@gmail.com>
|
|
Added PCIIDs, Device info and the relevant code.
Signed-off-by: Sirisha Muppavarapu <sirisha.muppavarapu@intel.com>
[Peng: disable MPEG-2 encoding on BXT]
Signed-off-by: peng.chen <peng.c.chen@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
|
|
Otherwise the buffer access is incorrect.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Xiang haihao <haihao.xiang@intel.com>
|
|
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
|
|
We can re-use SKL HEVC decode pipeline
Signed-off-by: Sean V Kelley <seanvk@posteo.de>
Cc: haihao.xiang@intel.com
Cc: focus.luo@intel.com
(cherry picked from commit 78171ec3b8e73071405d9ff6ecbddc05a6787001)
|
|
Signed-off-by: Qu,Pengfei <Pengfei.Qu@intel.com>
(cherry picked from commit 22439f1fcebbd2c1d563503720b1123a4bb97160)
|
|
Signed-off-by: Qu,Pengfei <Pengfei.Qu@intel.com>
(cherry picked from commit d4f1087a0606c7c8d2d5fd65d9f46990f41ce93a)
|
|
Add BSW vp8 encoding support, and let SKL and BDW use the same PAK pipeline.
Signed-off-by: Zhong Li <zhong.li@intel.com>
(cherry picked from commit c2be56ae6f3628ea246a1dd02e5cac18da84df56)
|
|
Signed-off-by: Zhong Li <zhong.li@intel.com>
(cherry picked from commit d8588862d85414ef412fd5e7ae1fb9ca78b69e84)
Conflicts:
src/i965_device_info.c
|
|
Signed-off-by: Sirisha Muppavarapu <sirisha.muppavarapu@intel.com>
(cherry picked from commit 2eb9a2037a05d742ee63638f3400b772f9a311e1)
|
|
v2: Only support HEVC Main Profile
v3: Check profile against VAProfileHEVCMain in i965_BeginPicture()
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit f623373aab09ff1477532dd25bd0ffe5bdd5e7e2)
|
|
The hcp (HEVC codec pipeline) for decoding will be built later
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit f5de561ddbf6f70efbbd9a2663327cce4ba5f0fb)
|
|
We can re-use CHV JPEG encoding pipeline
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit 85fe60453c674d1927c9e05df2d896c53cb0e401)
|
|
There are only a few changes on media pipeline between BDW
and SKL, so we can reuse most BDW VPP code. I will follow the DOCs
to fix media pipeline states for SKL and add shaders for each
processing
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit 31f09369d4f934e19909616b2a2e94bc54ef3e64)
Conflicts:
src/gen8_post_processing.c
|
|
The separated file are added for the media encoding on SKL, which is copied
from that on Gen8 and the function name is changed from gen8_xxx to gen9_xxx.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit f6da8bbc29d7449a3bc9e586906496eab4011c25)
Cleanup packed header insertion for MVC encoding
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit dde2a653519f757a167d4a1a55c516b1ec8d716e)
|
|
The seperated file of gen9_render.c is added for the rendering, which
is copied from gen8_render.c and the function name is changed from
gen8_XXX to gen9_XXX.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit 9f9e5d144bd4131876371df0dfc00085a39049e8)
|
|
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit 7d3be309fed0330097426ffd5a055cb2db473236)
Conflicts:
src/intel_driver.h
|
|
(cherry picked from commit 14efb88b0f421c543b56cd73ab425a943e46f88f)
|
|
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Daniel Charles <daniel.charles@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Ram Mohan Satyanarayana <ram.mohanx.satyanarayana@intel.com>
(cherry picked from commit 71a431b04ea04b93ba8f32e95fa545b30726bf59)
|
|
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Daniel Charles <daniel.charles@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Ram Mohan Satyanarayana <ram.mohanx.satyanarayana@intel.com>
(cherry picked from commit 080784f57f48c517d7a672b23b6d07278b232660)
|
|
Pending branding and differentiation by stepping. CHV is used generically
to match libdrm and mesa identification.
Signed-off-by: Sean V Kelley <sean.v.kelley@intel.com>
(cherry picked from commit 1121cb1f87228005a2b15b5ead95701a7fbe7519)
Conflicts:
src/i965_device_info.c
|
|
On some systems there is no access to /proc/cpuinfo. So the inline assembly
is used directly to detect the CPUID string.
V2->V3: Follow the suggestion from Google engineer to remove the unused code
of "if 0". And the "unsigned int" data type is updated to "uint32_t".
V1->V2: Based on the Matt Turner's suggestion the __cpuid defined in GCC
cpuid.h is called directly, which is helpful to handle the PIC issue on
32-bit.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit 3e8cce4e7292651af10c9f375a6ad2e9fa494021)
|
|
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit 021149c50ffd5c55d45acbda6bb950c7206b7255)
|
|
At the same time the extra string arrary is removed.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit 05ece0c3698f4f48c4141e8bd0608b9869d8ad0c)
|
|
Haswell
Some Haswell machine doesn't support the encoding. So it should be disabled.
Otherwise the driver can't report the supported capability correctly.
V1->V2: Minor update based on comment from Gwenole Beauchesne. For example:
use the bool tye and remove the hardcoded value
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit 23ae0f76ee5b3c097e6ae34182219cf44b09b82e)
|
|
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit 065db8289d3f38a923959f87d1b75767a0633e61)
|
|
H.264 MVC decoding support is defined as follows:
- Stereo High profile on Sandybridge and newer ;
- Multiview High profile on Haswell and newer.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
(cherry picked from commit 1f244834dedb7b46863b315a898d8649d01c5f58)
Conflicts:
src/i965_device_info.c
src/i965_drv_video.c
src/va_backend_compat.h
|
|
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
(cherry picked from commit 7d1ddfd3646f35f306f38bfabef6af9b2ebb19f4)
Conflicts:
src/i965_drv_video.c
|
|
Set the right surface states for reference, STMM and output surface,
fix the shader as well
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Tested-By: Simon Farnsworth <simon.farnsworth@onelan.co.uk>
(cherry picked from commit 1d1b8da1284f7f918733db79428f09af38d7e14a)
Conflicts:
src/i965_post_processing.c
|
|
Optimize support for grayscale surfaces in two aspects: (i) space
by only allocating the luminance component ; (ii) speed by avoiding
initialization of the (now inexistent) chrominance planes.
Keep backward compatibility with older codec layers that only
supported YUV 4:2:0 and not grayscale formats properly.
v2: fix check for extra H.264 chroma formats [Haihao]
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
|
|
If the hardware supports JPEG decoding, then we have to expose the
right set of chroma formats for the output (decoded) VA surface. In
particular, we could support YUV 4:0:0, 4:1:0, 4:2:2 and 4:4:4.
v2: export support for YUV 4:0:0 (grayscale) too [Haihao]
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
|
|
pitch must be 64 at least for linear surface for most functions on IVB/HSW/BDW
such VEBOX, Data port media read/write
https://bugs.freedesktop.org/show_bug.cgi?id=72522
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit 57db5c2524f4e3cb6ae2301bddfdf1c40cdbb626)
|
|
It is to reduce the usage of IS_GENxxx() as well.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit 77b6a72504d917af9335ab94f6ecbefb8b087206)
|
|
It is to reduce the usage of IS_GENxxx()
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit f150fbf444ca63b5e9c3e8f7e17aa3386f7061fa)
|