diff options
| author | Qu, PengFei <pengfei.qu@intel.com> | 2016-05-30 09:56:00 -0400 |
|---|---|---|
| committer | Xiang, Haihao <haihao.xiang@intel.com> | 2016-06-13 20:59:47 +0800 |
| commit | dd9a0fb7a885f79f6413df0bd1afd5556c919a03 (patch) | |
| tree | bc26f37a728fd0e880dcb03dac3767be2fe497f4 /src/i965_gpe_utils.c | |
| parent | 7b823b8fe7d3d4b166852b8714abe52d4344d0fc (diff) | |
Follow the HW spec to set the surface cache attribute for Gen9+
Currently it will use the unoptimized cache attribute for the surface on Gen9+.
This is to follow the HW spec to optimize the cache attribute of the surface
for gen9+.
Signed-off-by: Qu, Pengfei <pengfei.qu@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Diffstat (limited to 'src/i965_gpe_utils.c')
| -rw-r--r-- | src/i965_gpe_utils.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/i965_gpe_utils.c b/src/i965_gpe_utils.c index 91d1192..d911196 100644 --- a/src/i965_gpe_utils.c +++ b/src/i965_gpe_utils.c @@ -721,6 +721,7 @@ gen8_gpe_set_surface2_state(VADriverContextP ctx, struct object_surface *obj_surface, struct gen8_surface_state2 *ss) { + struct i965_driver_data *i965 = i965_driver_data(ctx); int w, h, w_pitch; unsigned int tiling, swizzle; @@ -734,6 +735,9 @@ gen8_gpe_set_surface2_state(VADriverContextP ctx, memset(ss, 0, sizeof(*ss)); /* ss0 */ + if (IS_GEN9(i965->intel.device_info)) + ss->ss5.surface_object_mocs = GEN9_CACHE_PTE; + ss->ss6.base_addr = (uint32_t)obj_surface->bo->offset64; ss->ss7.base_addr_high = (uint32_t)(obj_surface->bo->offset64 >> 32); /* ss1 */ @@ -782,6 +786,7 @@ gen8_gpe_set_media_rw_surface_state(VADriverContextP ctx, struct object_surface *obj_surface, struct gen8_surface_state *ss) { + struct i965_driver_data *i965 = i965_driver_data(ctx); int w, h, w_pitch; unsigned int tiling, swizzle; @@ -792,6 +797,9 @@ gen8_gpe_set_media_rw_surface_state(VADriverContextP ctx, memset(ss, 0, sizeof(*ss)); /* ss0 */ + if (IS_GEN9(i965->intel.device_info)) + ss->ss1.surface_mocs = GEN9_CACHE_PTE; + ss->ss0.surface_type = I965_SURFACE_2D; ss->ss0.surface_format = I965_SURFACEFORMAT_R8_UNORM; /* ss1 */ @@ -810,6 +818,7 @@ gen8_gpe_set_media_chroma_surface_state(VADriverContextP ctx, struct object_surface *obj_surface, struct gen8_surface_state *ss) { + struct i965_driver_data *i965 = i965_driver_data(ctx); int w, w_pitch; unsigned int tiling, swizzle; int cbcr_offset; @@ -822,6 +831,9 @@ gen8_gpe_set_media_chroma_surface_state(VADriverContextP ctx, cbcr_offset = obj_surface->height * obj_surface->width; memset(ss, 0, sizeof(*ss)); /* ss0 */ + if (IS_GEN9(i965->intel.device_info)) + ss->ss1.surface_mocs = GEN9_CACHE_PTE; + ss->ss0.surface_type = I965_SURFACE_2D; ss->ss0.surface_format = I965_SURFACEFORMAT_R8_UNORM; /* ss1 */ @@ -897,6 +909,7 @@ gen8_gpe_set_buffer_surface_state(VADriverContextP ctx, struct i965_buffer_surface *buffer_surface, struct gen8_surface_state *ss) { + struct i965_driver_data *i965 = i965_driver_data(ctx); int num_entries; assert(buffer_surface->bo); @@ -905,6 +918,9 @@ gen8_gpe_set_buffer_surface_state(VADriverContextP ctx, memset(ss, 0, sizeof(*ss)); /* ss0 */ ss->ss0.surface_type = I965_SURFACE_BUFFER; + if (IS_GEN9(i965->intel.device_info)) + ss->ss1.surface_mocs = GEN9_CACHE_PTE; + /* ss1 */ ss->ss8.base_addr = (uint32_t)buffer_surface->bo->offset64; ss->ss9.base_addr_high = (uint32_t)(buffer_surface->bo->offset64 >> 32); |