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authorZhao Yakui <yakui.zhao@intel.com>2017-01-17 08:40:18 +0800
committerSean V Kelley <seanvk@posteo.de>2017-01-17 15:03:29 -0800
commitfce75e3a7fe6d61fad0411359406ab291dd3f2c7 (patch)
tree73a2654b43c4919ae5f22d1c319d57b1030138f9 /src/gen9_mfc_hevc.c
parentee9261e895a5b86a2532595629cd9c31fff51747 (diff)
Follow the HW spec to configure the buffer cache on Gen9+
The MOCS field is used to define the cache type for the given buffer. From the SKL+, the MOCS field is interpreted as the index that is used to find the corresponding cache type in kernel driver. The current MOCS setting causes that buffer uses the wrong cache type. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Reviewed-by: Sean V Kelley <sean.v.kelley@intel.com>
Diffstat (limited to 'src/gen9_mfc_hevc.c')
-rw-r--r--src/gen9_mfc_hevc.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/gen9_mfc_hevc.c b/src/gen9_mfc_hevc.c
index 8a84c1c..4234cf7 100644
--- a/src/gen9_mfc_hevc.c
+++ b/src/gen9_mfc_hevc.c
@@ -93,7 +93,7 @@ typedef enum _gen6_brc_status {
} \
OUT_BCS_BATCH(batch, 0); \
if (ma) \
- OUT_BCS_BATCH(batch, 0); \
+ OUT_BCS_BATCH(batch, i965->intel.mocs_state); \
} while (0)
#define OUT_BUFFER_MA_TARGET(buf_bo) OUT_BUFFER_X(buf_bo, 1, 1)
@@ -318,6 +318,7 @@ static void
gen9_hcpe_ind_obj_base_addr_state(VADriverContextP ctx,
struct intel_encoder_context *encoder_context)
{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
struct intel_batchbuffer *batch = encoder_context->base.batch;
struct gen9_hcpe_context *mfc_context = encoder_context->mfc_context;
@@ -334,7 +335,7 @@ gen9_hcpe_ind_obj_base_addr_state(VADriverContextP ctx,
I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
mfc_context->hcp_indirect_pak_bse_object.offset);
OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, i965->intel.mocs_state);
OUT_BCS_RELOC(batch,
mfc_context->hcp_indirect_pak_bse_object.bo,
I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,