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authorZhao Yakui <yakui.zhao@intel.com>2017-01-17 08:40:18 +0800
committerSean V Kelley <seanvk@posteo.de>2017-01-17 15:03:29 -0800
commitfce75e3a7fe6d61fad0411359406ab291dd3f2c7 (patch)
tree73a2654b43c4919ae5f22d1c319d57b1030138f9 /src/gen8_mfd.c
parentee9261e895a5b86a2532595629cd9c31fff51747 (diff)
Follow the HW spec to configure the buffer cache on Gen9+
The MOCS field is used to define the cache type for the given buffer. From the SKL+, the MOCS field is interpreted as the index that is used to find the corresponding cache type in kernel driver. The current MOCS setting causes that buffer uses the wrong cache type. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Reviewed-by: Sean V Kelley <sean.v.kelley@intel.com>
Diffstat (limited to 'src/gen8_mfd.c')
-rw-r--r--src/gen8_mfd.c50
1 files changed, 30 insertions, 20 deletions
diff --git a/src/gen8_mfd.c b/src/gen8_mfd.c
index 9852664..61999b3 100644
--- a/src/gen8_mfd.c
+++ b/src/gen8_mfd.c
@@ -179,6 +179,7 @@ gen8_mfd_pipe_buf_addr_state(VADriverContextP ctx,
int standard_select,
struct gen7_mfd_context *gen7_mfd_context)
{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
int i;
@@ -193,7 +194,8 @@ gen8_mfd_pipe_buf_addr_state(VADriverContextP ctx,
OUT_BCS_BATCH(batch, 0);
OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, i965->intel.mocs_state);
+
/* Post-debloing 4-6 */
if (gen7_mfd_context->post_deblocking_output.valid)
OUT_BCS_RELOC(batch, gen7_mfd_context->post_deblocking_output.bo,
@@ -203,7 +205,7 @@ gen8_mfd_pipe_buf_addr_state(VADriverContextP ctx,
OUT_BCS_BATCH(batch, 0);
OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, i965->intel.mocs_state);
/* uncompressed-video & stream out 7-12 */
OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
@@ -222,7 +224,8 @@ gen8_mfd_pipe_buf_addr_state(VADriverContextP ctx,
OUT_BCS_BATCH(batch, 0);
OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, i965->intel.mocs_state);
+
/* deblocking-filter-row-store 16-18 */
if (gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
OUT_BCS_RELOC(batch, gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
@@ -231,7 +234,8 @@ gen8_mfd_pipe_buf_addr_state(VADriverContextP ctx,
else
OUT_BCS_BATCH(batch, 0);
OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
+
+ OUT_BCS_BATCH(batch, i965->intel.mocs_state);
/* DW 19..50 */
for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
@@ -253,7 +257,7 @@ gen8_mfd_pipe_buf_addr_state(VADriverContextP ctx,
}
/* reference property 51 */
- OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, i965->intel.mocs_state);
/* Macroblock status & ILDB 52-57 */
OUT_BCS_BATCH(batch, 0);
@@ -278,13 +282,14 @@ gen8_mfd_ind_obj_base_addr_state(VADriverContextP ctx,
struct gen7_mfd_context *gen7_mfd_context)
{
struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
BEGIN_BCS_BATCH(batch, 26);
OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (26 - 2));
/* MFX In BS 1-5 */
OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, i965->intel.mocs_state);
/* Upper bound 4-5 */
OUT_BCS_BATCH(batch, 0);
OUT_BCS_BATCH(batch, 0);
@@ -327,6 +332,7 @@ gen8_mfd_bsp_buf_base_addr_state(VADriverContextP ctx,
struct gen7_mfd_context *gen7_mfd_context)
{
struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
BEGIN_BCS_BATCH(batch, 10);
OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2));
@@ -339,7 +345,7 @@ gen8_mfd_bsp_buf_base_addr_state(VADriverContextP ctx,
OUT_BCS_BATCH(batch, 0);
OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, i965->intel.mocs_state);
/* MPR Row Store Scratch buffer 4-6 */
if (gen7_mfd_context->mpr_row_store_scratch_buffer.valid)
OUT_BCS_RELOC(batch, gen7_mfd_context->mpr_row_store_scratch_buffer.bo,
@@ -349,7 +355,7 @@ gen8_mfd_bsp_buf_base_addr_state(VADriverContextP ctx,
OUT_BCS_BATCH(batch, 0);
OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, i965->intel.mocs_state);
/* Bitplane 7-9 */
if (gen7_mfd_context->bitplane_read_buffer.valid)
@@ -359,7 +365,7 @@ gen8_mfd_bsp_buf_base_addr_state(VADriverContextP ctx,
else
OUT_BCS_BATCH(batch, 0);
OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, i965->intel.mocs_state);
ADVANCE_BCS_BATCH(batch);
}
@@ -510,6 +516,7 @@ gen8_mfd_avc_directmode_state(VADriverContextP ctx,
VASliceParameterBufferH264 *slice_param,
struct gen7_mfd_context *gen7_mfd_context)
{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
struct object_surface *obj_surface;
GenAvcSurface *gen7_avc_surface;
@@ -538,7 +545,7 @@ gen8_mfd_avc_directmode_state(VADriverContextP ctx,
}
}
- OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, i965->intel.mocs_state);
/* the current decoding frame/field */
va_pic = &pic_param->CurrPic;
@@ -551,7 +558,7 @@ gen8_mfd_avc_directmode_state(VADriverContextP ctx,
0);
OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, i965->intel.mocs_state);
/* POC List */
for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
@@ -1712,6 +1719,7 @@ gen8_mfd_vc1_directmode_state(VADriverContextP ctx,
struct decode_state *decode_state,
struct gen7_mfd_context *gen7_mfd_context)
{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
struct object_surface *obj_surface;
dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
@@ -1739,7 +1747,7 @@ gen8_mfd_vc1_directmode_state(VADriverContextP ctx,
OUT_BCS_BATCH(batch, 0);
OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, i965->intel.mocs_state);
if (dmv_read_buffer)
OUT_BCS_RELOC(batch, dmv_read_buffer,
@@ -1749,7 +1757,7 @@ gen8_mfd_vc1_directmode_state(VADriverContextP ctx,
OUT_BCS_BATCH(batch, 0);
OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, i965->intel.mocs_state);
ADVANCE_BCS_BATCH(batch);
}
@@ -2308,7 +2316,7 @@ gen8_jpeg_wa_pipe_buf_addr_state(VADriverContextP ctx,
I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
0);
OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, i965->intel.mocs_state);
OUT_BCS_BATCH(batch, 0); /* post deblocking */
@@ -2329,7 +2337,8 @@ gen8_jpeg_wa_pipe_buf_addr_state(VADriverContextP ctx,
I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
0);
OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
+
+ OUT_BCS_BATCH(batch, i965->intel.mocs_state);
/* the DW 16-18 is for deblocking filter */
OUT_BCS_BATCH(batch, 0);
@@ -2387,14 +2396,14 @@ gen8_jpeg_wa_bsp_buf_base_addr_state(VADriverContextP ctx,
0);
OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, i965->intel.mocs_state);
OUT_BCS_RELOC(batch,
mpr_bo,
I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
0);
OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, i965->intel.mocs_state);
OUT_BCS_BATCH(batch, 0);
OUT_BCS_BATCH(batch, 0);
@@ -2509,7 +2518,7 @@ gen8_jpeg_wa_ind_obj_base_addr_state(VADriverContextP ctx,
I915_GEM_DOMAIN_INSTRUCTION, 0,
0);
OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
+ OUT_BCS_BATCH(batch, i965->intel.mocs_state);
OUT_BCS_BATCH(batch, 0);
OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
OUT_BCS_BATCH(batch, 0);
@@ -2816,6 +2825,7 @@ gen8_mfd_vp8_pic_state(VADriverContextP ctx,
struct decode_state *decode_state,
struct gen7_mfd_context *gen7_mfd_context)
{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
VAPictureParameterBufferVP8 *pic_param = (VAPictureParameterBufferVP8 *)decode_state->pic_param->buffer;
VAIQMatrixBufferVP8 *iq_matrix = (VAIQMatrixBufferVP8 *)decode_state->iq_matrix->buffer;
@@ -2893,7 +2903,7 @@ gen8_mfd_vp8_pic_state(VADriverContextP ctx,
0, I915_GEM_DOMAIN_INSTRUCTION,
0);
OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, i965->intel.mocs_state);
} else {
OUT_BCS_BATCH(batch, 0);
OUT_BCS_BATCH(batch, 0);
@@ -2951,7 +2961,7 @@ gen8_mfd_vp8_pic_state(VADriverContextP ctx,
0, I915_GEM_DOMAIN_INSTRUCTION,
0);
OUT_BCS_BATCH(batch, 0);
- OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, i965->intel.mocs_state);
}
else {
OUT_BCS_BATCH(batch, 0);