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authorKevin Brace <kevinbrace@gmx.com>2018-06-19 16:18:31 -0700
committerKevin Brace <kevinbrace@gmx.com>2018-06-19 16:32:10 -0700
commit752311098a96f46b54385165a41da5f3663ababc (patch)
treebef18bc24685c2e07f23ee400afe280aa32a95fd
parent640217271a4cfb3a6c84f8160b8dfe384584d6f7 (diff)
Turn off CR45[0] when VX900 chipset is in use
Officially, CR45[0] is a reserved bit for VX900 chipset, but this bit set to 1 causes the display connected to VGA output of ECS VX900-I and VIA VE-900 mainboards to indicate receiving out of range signals and nothing will be displayed on the screen. Tested-by: P Touchman <ptouchman@gmail.com> Signed-off-by: Kevin Brace <kevinbrace@gmx.com>
-rw-r--r--src/via_display.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/via_display.c b/src/via_display.c
index 9607dcd..f18796b 100644
--- a/src/via_display.c
+++ b/src/via_display.c
@@ -744,6 +744,13 @@ viaIGAInitCommon(ScrnInfoPtr pScrn)
temp = hwp->readCrtc(hwp, 0x3F);
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"CR3F: 0x%02X\n", temp));
+
+ if (pVia->Chipset == VIA_VX900) {
+ temp = hwp->readCrtc(hwp, 0x45);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "CR45: 0x%02X\n", temp));
+ }
+
temp = hwp->readCrtc(hwp, 0x47);
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"CR47: 0x%02X\n", temp));
@@ -927,6 +934,10 @@ viaIGAInitCommon(ScrnInfoPtr pScrn)
* 1: Enable */
ViaCrtcMask(hwp, 0x36, 0x01, 0x01);
+ if (pVia->Chipset == VIA_VX900) {
+ ViaCrtcMask(hwp, 0x45, 0x00, 0x01);
+ }
+
/* 3X5.3B through 3X5.3F are scratch pad registers. */
ViaCrtcMask(hwp, 0x3B, pVIADisplay->originalCR3B, 0xFF);
ViaCrtcMask(hwp, 0x3C, pVIADisplay->originalCR3C, 0xFF);