diff options
| author | Kevin Brace <kevinbrace@gmx.com> | 2018-11-15 15:53:12 -0800 |
|---|---|---|
| committer | Kevin Brace <kevinbrace@gmx.com> | 2018-11-15 15:53:12 -0800 |
| commit | 37603513258896c4015f402b6d3b9cd0ba38a948 (patch) | |
| tree | 2e0d9871ebf293ff491ac97a77ac75c7a549852c | |
| parent | 355e19b95bf8858b2d8b9f5c4c4b2819d83961b2 (diff) | |
Fix for garbled display on VIA EPIA-M830 mainboard after resume
It appears that if the new memory map registers added since VX800
chipset are not restored after exiting standby resume, the display on
certain models will become garbled. This bugs was observed on VIA
Embedded EPIA-M830 mainboard with VX800 chipset.
Signed-off-by: Kevin Brace <kevinbrace@gmx.com>
| -rw-r--r-- | src/via_display.c | 20 | ||||
| -rw-r--r-- | src/via_ums.c | 14 |
2 files changed, 34 insertions, 0 deletions
diff --git a/src/via_display.c b/src/via_display.c index 7b46dad..a6773f5 100644 --- a/src/via_display.c +++ b/src/via_display.c @@ -595,6 +595,7 @@ viaIGAInitCommon(ScrnInfoPtr pScrn) vgaHWPtr hwp = VGAHWPTR(pScrn); VIAPtr pVia = VIAPTR(pScrn); VIADisplayPtr pVIADisplay = pVia->pVIADisplay; + VIARegPtr Regs = &pVIADisplay->SavedReg; CARD8 i; #ifdef HAVE_DEBUG CARD8 temp; @@ -918,6 +919,25 @@ viaIGAInitCommon(ScrnInfoPtr pScrn) * 11: Clock on/off according to each engine IDLE status */ ViaSeqMask(hwp, 0x3F, 0xFF, 0xFF); + /* + * Initialize frame buffer size and GTI for VX800, VX855, and + * VX900 chipsets. This code is really necessary for standby + * resume to work properly on VIA Embedded EPIA-M830 mainboard. + */ + if ((pVia->Chipset == VIA_VX800) || + (pVia->Chipset == VIA_VX855) || + (pVia->Chipset == VIA_VX900)) { + hwp->writeSeq(hwp, 0x14, Regs->SR[0x14]); + hwp->writeSeq(hwp, 0x68, Regs->SR[0x68]); + hwp->writeSeq(hwp, 0x69, Regs->SR[0x69]); + hwp->writeSeq(hwp, 0x6A, Regs->SR[0x6A]); + hwp->writeSeq(hwp, 0x6B, Regs->SR[0x6B]); + hwp->writeSeq(hwp, 0x6C, Regs->SR[0x6C]); + hwp->writeSeq(hwp, 0x6D, Regs->SR[0x6D]); + hwp->writeSeq(hwp, 0x6E, Regs->SR[0x6E]); + hwp->writeSeq(hwp, 0x6F, Regs->SR[0x6F]); + } + /* 3X5.36[7] - DPMS VSYNC Output * 3X5.36[6] - DPMS HSYNC Output * 3X5.36[5:4] - DPMS Control diff --git a/src/via_ums.c b/src/via_ums.c index 2e590d1..b0c3aa3 100644 --- a/src/via_ums.c +++ b/src/via_ums.c @@ -1148,6 +1148,20 @@ umsCrtcInit(ScrnInfoPtr pScrn) break; } + if ((pVia->Chipset == VIA_VX800) || + (pVia->Chipset == VIA_VX855) || + (pVia->Chipset == VIA_VX900)) { + Regs->SR[0x14] = hwp->readSeq(hwp, 0x14); + Regs->SR[0x68] = hwp->readSeq(hwp, 0x68); + Regs->SR[0x69] = hwp->readSeq(hwp, 0x69); + Regs->SR[0x6A] = hwp->readSeq(hwp, 0x6A); + Regs->SR[0x6B] = hwp->readSeq(hwp, 0x6B); + Regs->SR[0x6C] = hwp->readSeq(hwp, 0x6C); + Regs->SR[0x6D] = hwp->readSeq(hwp, 0x6D); + Regs->SR[0x6E] = hwp->readSeq(hwp, 0x6E); + Regs->SR[0x6F] = hwp->readSeq(hwp, 0x6F); + } + Regs->CR[0x0C] = hwp->readCrtc(hwp, 0x0C); Regs->CR[0x0D] = hwp->readCrtc(hwp, 0x0D); |