summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/openchrome/openchrome_drv.h
blob: 71a04a9e863383a6df4ac0e053be650ed0d933db (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
/*
 * Copyright © 2019 Kevin Brace
 * Copyright 2012 James Simmons <jsimmons@infradead.org>. All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person
 * obtaining a copy of this software and associated documentation
 * files (the "Software"), to deal in the Software without
 * restriction, including without limitation the rights to use, copy,
 * modify, merge, publish, distribute, sublicense, and/or sell copies
 * of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including
 * the next paragraph) shall be included in all copies or substantial
 * portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */
/*
 * Author(s):
 *
 * Kevin Brace <kevinbrace@gmx.com>
 * James Simmons <jsimmons@infradead.org>
 */

#ifndef _OPENCHROME_DRV_H
#define _OPENCHROME_DRV_H


#include <linux/module.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>

#include <video/vga.h>

#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_encoder.h>
#include <drm/drm_fb_helper.h>
#include <drm/drm_framebuffer.h>
#include <drm/drm_gem.h>
#include <drm/drm_ioctl.h>
#include <drm/drm_plane.h>

#include <drm/ttm/ttm_bo_api.h>
#include <drm/ttm/ttm_bo_driver.h>
#include <drm/ttm/ttm_placement.h>

#include <drm/openchrome_drm.h>

#include "openchrome_crtc_hw.h"
#include "openchrome_regs.h"


#define DRIVER_MAJOR		3
#define DRIVER_MINOR		4
#define DRIVER_PATCHLEVEL	8
#define DRIVER_NAME		"openchrome"
#define DRIVER_DESC		"OpenChrome DRM for VIA Technologies Chrome IGP"
#define DRIVER_DATE		"20210403"
#define DRIVER_AUTHOR		"OpenChrome Project"


#define OPENCHROME_TTM_PL_NUM	2

#define OPENCHROME_MAX_CRTC	2

#define OPENCHROME_CURSOR_SIZE	64

#define VIA_MM_ALIGN_SIZE	16


#define CLE266_REVISION_AX	0x0A
#define CLE266_REVISION_CX	0x0C

#define CX700_REVISION_700	0x0
#define CX700_REVISION_700M	0x1
#define CX700_REVISION_700M2	0x2

#define VIA_MEM_NONE		0x00
#define VIA_MEM_SDR66		0x01
#define VIA_MEM_SDR100		0x02
#define VIA_MEM_SDR133		0x03
#define VIA_MEM_DDR_200		0x04
#define VIA_MEM_DDR_266		0x05
#define VIA_MEM_DDR_333		0x06
#define VIA_MEM_DDR_400		0x07
#define VIA_MEM_DDR2_400	0x08
#define VIA_MEM_DDR2_533	0x09
#define VIA_MEM_DDR2_667	0x0A
#define VIA_MEM_DDR2_800	0x0B
#define VIA_MEM_DDR2_1066	0x0C
#define VIA_MEM_DDR3_533	0x0D
#define VIA_MEM_DDR3_667	0x0E
#define VIA_MEM_DDR3_800	0x0F
#define VIA_MEM_DDR3_1066	0x10
#define VIA_MEM_DDR3_1333	0x11
#define VIA_MEM_DDR3_1600	0x12

/* IGA Scaling disable */
#define VIA_NO_SCALING	0

/* IGA Scaling down */
#define VIA_HOR_SHRINK	BIT(0)
#define VIA_VER_SHRINK	BIT(1)
#define VIA_SHRINK	(BIT(0) | BIT(1))

/* IGA Scaling up */
#define VIA_HOR_EXPAND	BIT(2)
#define VIA_VER_EXPAND	BIT(3)
#define VIA_EXPAND	(BIT(2) | BIT(3))

/* Define IGA Scaling up/down status :  Horizontal or Vertical  */
/* Is IGA Hor scaling up/down status */
#define	HOR_SCALE	BIT(0)
/* Is IGA Ver scaling up/down status */
#define	VER_SCALE	BIT(1)
/* Is IGA Hor and Ver scaling up/down status */
#define	HOR_VER_SCALE	(BIT(0) | BIT(1))

#define	VIA_I2C_NONE	0x0
#define	VIA_I2C_BUS1	BIT(0)
#define	VIA_I2C_BUS2	BIT(1)
#define	VIA_I2C_BUS3	BIT(2)
#define	VIA_I2C_BUS4	BIT(3)
#define	VIA_I2C_BUS5	BIT(4)

#define VIA_DI_PORT_NONE	0x0
#define VIA_DI_PORT_DIP0	BIT(0)
#define VIA_DI_PORT_DIP1	BIT(1)
#define VIA_DI_PORT_DVP0	BIT(2)
#define VIA_DI_PORT_DVP1	BIT(3)
#define VIA_DI_PORT_DFPL	BIT(4)
#define VIA_DI_PORT_FPDPLOW	BIT(4)
#define VIA_DI_PORT_DFPH	BIT(5)
#define VIA_DI_PORT_FPDPHIGH	BIT(5)
#define VIA_DI_PORT_DFP		BIT(6)
#define VIA_DI_PORT_LVDS1	BIT(7)
#define VIA_DI_PORT_TMDS	BIT(7)
#define VIA_DI_PORT_LVDS2	BIT(8)

/* External TMDS (DVI) Transmitter Type */
#define	VIA_TMDS_NONE	0x0
#define	VIA_TMDS_VT1632	BIT(0)
#define	VIA_TMDS_SII164	BIT(1)


typedef struct _via_fp_info {
	u32 x;
	u32 y;
} via_fp_info;

struct via_crtc {
	struct drm_crtc base;
	struct crtc_timings pixel_timings;
	struct crtc_timings timings;
	struct vga_registers display_queue;
	struct vga_registers high_threshold;
	struct vga_registers threshold;
	struct vga_registers fifo_depth;
	struct vga_registers offset;
	struct vga_registers fetch;
	int scaling_mode;
	uint32_t index;
};

struct via_connector {
	struct drm_connector base;
	u32 i2c_bus;
	struct list_head props;
	uint32_t flags;
};

struct via_encoder {
	struct drm_encoder base;
	u32 i2c_bus;
	u32 di_port;
	struct via_connector cons[];
};

struct via_state {
	struct vga_regset crt_regs[256];
	struct vga_regset seq_regs[256];
};

struct openchrome_bo {
	struct ttm_buffer_object	ttm_bo;
	struct ttm_bo_kmap_obj		kmap;
	struct ttm_placement		placement;
	struct ttm_place		placements[OPENCHROME_TTM_PL_NUM];
	struct drm_gem_object		gem;
};

struct openchrome_framebuffer {
	struct drm_fb_helper		helper;
	struct openchrome_bo		*bo;
};

enum via_engine {
	VIA_ENG_H1 = 0,
	VIA_ENG_H2,
	VIA_ENG_H5S1,
	VIA_ENG_H5S2VP1,
	VIA_ENG_H6S2
};

struct openchrome_drm_private {
	struct drm_device *dev;

	struct ttm_device		bdev;

	/* Set this flag for ttm_bo_device_init. */
	bool need_dma32;

	int revision;

	struct openchrome_framebuffer *openchrome_fb;
	u8 vram_type;
	resource_size_t vram_start;
	resource_size_t vram_size;
	int vram_mtrr;

	resource_size_t mmio_base;
	resource_size_t mmio_size;
	void __iomem		*mmio;

	struct via_state pm_cache;

	bool spread_spectrum;

	/*
	 * Frame Buffer Size Control register (SR14) needs to be saved and
	 * restored upon standby resume or can lead to a display corruption
	 * issue. These registers are only available on VX800, VX855, and
	 * VX900 chipsets. This bug was observed on VIA EPIA-M830 mainboard.
	 */
	uint8_t saved_sr14;

	/*
	 * GTI registers (SR66 through SR6F) need to be saved and restored
	 * upon standby resume or can lead to a display corruption issue.
	 * These registers are only available on VX800, VX855, and VX900
	 * chipsets. This bug was observed on VIA EPIA-M830 mainboard.
	 */
	uint8_t saved_sr66;
	uint8_t saved_sr67;
	uint8_t saved_sr68;
	uint8_t saved_sr69;
	uint8_t saved_sr6a;
	uint8_t saved_sr6b;
	uint8_t saved_sr6c;
	uint8_t saved_sr6d;
	uint8_t saved_sr6e;
	uint8_t saved_sr6f;

	/* 3X5.3B through 3X5.3F are scratch pad registers.
	 * They are important for FP detection. */
	uint8_t saved_cr3b;
	uint8_t saved_cr3c;
	uint8_t saved_cr3d;
	uint8_t saved_cr3e;
	uint8_t saved_cr3f;

	/*
	 * Due to the way VIA NanoBook reference design implemented
	 * the pin strapping settings, DRM needs to ignore them for
	 * FP and DVI to be properly detected.
	 */
	bool is_via_nanobook;

	/*
	 * Quanta IL1 netbook has its FP connected to DVP1
	 * rather than LVDS, hence, a special flag register
	 * is needed for properly controlling its FP.
	 */
	bool is_quanta_il1;

	/*
	 * Samsung NC20 netbook has its FP connected to LVDS2
	 * rather than the more logical LVDS1, hence, a special
	 * flag register is needed for properly controlling its
	 * FP.
	 */
	bool is_samsung_nc20;

	bool analog_presence;
	u32 analog_i2c_bus;

	bool int_tmds_presence;
	u32 int_tmds_di_port;
	u32 int_tmds_i2c_bus;

	bool ext_tmds_presence;
	u32 ext_tmds_di_port;
	u32 ext_tmds_i2c_bus;
	u32 ext_tmds_transmitter;

	bool int_fp1_presence;
	u32 int_fp1_di_port;
	u32 int_fp1_i2c_bus;

	bool int_fp2_presence;
	u32 int_fp2_di_port;
	u32 int_fp2_i2c_bus;

	/* Keeping track of the number of DVI connectors. */
	u32 number_dvi;

	/* Keeping track of the number of FP (Flat Panel) connectors. */
	u32 number_fp;

	u32 mapped_i2c_bus;
};


/* VIA MMIO register access */
#define VIA_BASE ((dev_private->mmio))

#define VIA_READ(reg)		ioread32(VIA_BASE + reg)
#define VIA_WRITE(reg, val)	iowrite32(val, VIA_BASE + reg)
#define VIA_READ8(reg)		ioread8(VIA_BASE + reg)
#define VIA_WRITE8(reg, val)	iowrite8(val, VIA_BASE + reg)

#define VIA_WRITE_MASK(reg, data, mask) \
	VIA_WRITE(reg, (data & mask) | (VIA_READ(reg) & ~mask)) \

#define VGABASE (VIA_BASE+VIA_MMIO_VGABASE)


static inline void
via_lock_crtc(void __iomem *regs)
{
	svga_wcrt_mask(regs, 0x11, BIT(7), BIT(7));
}

static inline void
via_unlock_crtc(void __iomem *regs, int pci_id)
{
	u8 mask = BIT(0);

	svga_wcrt_mask(regs, 0x11, 0, BIT(7));
	if ((pci_id == PCI_DEVICE_ID_VIA_VX875) ||
	    (pci_id == PCI_DEVICE_ID_VIA_VX900_VGA))
		mask = BIT(4);
	svga_wcrt_mask(regs, 0x47, 0, mask);
}

static inline void
enable_second_display_channel(void __iomem *regs)
{
	svga_wcrt_mask(regs, 0x6A, BIT(7), BIT(7));
}

static inline void
disable_second_display_channel(void __iomem *regs)
{
	svga_wcrt_mask(regs, 0x6A, 0x00, BIT(7));
}


extern const struct drm_ioctl_desc openchrome_driver_ioctls[];
extern int openchrome_driver_num_ioctls;

extern struct ttm_device_funcs openchrome_bo_driver;

int openchrome_vram_detect(struct openchrome_drm_private *dev_private);
extern int openchrome_vram_init(
			struct openchrome_drm_private *dev_private);
extern void openchrome_vram_fini(
			struct openchrome_drm_private *dev_private);
int openchrome_mmio_init(struct openchrome_drm_private *dev_private);
void openchrome_mmio_fini(struct openchrome_drm_private *dev_private);
void openchrome_graphics_unlock(
			struct openchrome_drm_private *dev_private);
void chip_revision_info(struct openchrome_drm_private *dev_private);
int openchrome_device_init(struct openchrome_drm_private *dev_private);
void openchrome_device_fini(struct openchrome_drm_private *dev_private);
int openchrome_drm_init(struct drm_device *dev);
void openchrome_drm_fini(struct drm_device *dev);

int openchrome_dev_pm_ops_suspend(struct device *dev);
int openchrome_dev_pm_ops_resume(struct device *dev);

int openchrome_ttm_mmap(struct file *filp, struct vm_area_struct *vma);
void openchrome_ttm_domain_to_placement(struct openchrome_bo *bo,
					uint32_t ttm_domain);
void openchrome_ttm_bo_destroy(struct ttm_buffer_object *tbo);
int openchrome_bo_pin(struct openchrome_bo *bo, uint32_t ttm_domain);
void openchrome_bo_unpin(struct openchrome_bo *bo);
int openchrome_bo_create(struct drm_device *dev,
				struct ttm_device *bdev,
				uint64_t size,
				enum ttm_bo_type type,
				uint32_t ttm_domain,
				bool kmap,
				struct openchrome_bo **bo_ptr);
void openchrome_bo_destroy(struct openchrome_bo *bo, bool kmap);
int openchrome_mm_init(struct openchrome_drm_private *dev_private);
void openchrome_mm_fini(struct openchrome_drm_private *dev_private);

void openchrome_transmitter_io_pad_state(
			struct openchrome_drm_private *dev_private,
			uint32_t di_port, bool io_pad_on);
void openchrome_transmitter_clock_drive_strength(
			struct openchrome_drm_private *dev_private,
			u32 di_port, u8 drive_strength);
void openchrome_transmitter_data_drive_strength(
			struct openchrome_drm_private *dev_private,
			u32 di_port, u8 drive_strength);
void openchrome_transmitter_display_source(
			struct openchrome_drm_private *dev_private,
			u32 di_port, int index);

extern const struct drm_plane_helper_funcs
openchrome_cursor_drm_plane_helper_funcs;
extern const struct drm_plane_funcs openchrome_cursor_drm_plane_funcs;
extern const uint32_t openchrome_cursor_formats[];
extern const unsigned int openchrome_cursor_formats_size;

/* display */
extern int via_modeset_init(struct drm_device *dev);
extern void via_modeset_fini(struct drm_device *dev);

/* i2c */
extern struct i2c_adapter *via_find_ddc_bus(int port);
extern void via_i2c_readbytes(struct i2c_adapter *adapter,
				u8 slave_addr, char offset,
				u8 *buffer, unsigned int size);
extern void via_i2c_writebytes(struct i2c_adapter *adapter,
				u8 slave_addr, char offset,
				u8 *data, unsigned int size);
extern int via_i2c_init(struct drm_device *dev);
extern void via_i2c_exit(void);

/* clock */
extern u32 via_get_clk_value(struct drm_device *dev, u32 clk);
extern void via_set_vclock(struct drm_crtc *crtc, u32 clk);

/* framebuffers */
void openchrome_mode_config_init(
			struct openchrome_drm_private *dev_private);
extern int openchrome_fb_init(struct drm_device *dev);
extern void openchrome_fb_fini(struct drm_device *dev);

/* crtc */
extern void via_load_crtc_pixel_timing(struct drm_crtc *crtc,
					struct drm_display_mode *mode);
int openchrome_crtc_init(struct openchrome_drm_private *dev_private,
				uint32_t index);

/* encoders */
extern void via_set_sync_polarity(struct drm_encoder *encoder,
				struct drm_display_mode *mode,
				struct drm_display_mode *adjusted_mode);
extern void via_encoder_cleanup(struct drm_encoder *encoder);
extern void via_encoder_prepare(struct drm_encoder *encoder);
extern void via_encoder_disable(struct drm_encoder *encoder);
extern void via_encoder_commit(struct drm_encoder *encoder);

/* connectors */
extern int via_connector_set_property(struct drm_connector *connector,
					struct drm_property *property,
					uint64_t value);
extern int via_connector_mode_valid(struct drm_connector *connector,
					struct drm_display_mode *mode);
extern void via_connector_destroy(struct drm_connector *connector);

extern void via_analog_probe(struct drm_device *dev);
extern bool openchrome_vt1632_probe(struct i2c_adapter *i2c_bus);
extern bool openchrome_sii164_probe(struct i2c_adapter *i2c_bus);
extern void openchrome_ext_dvi_probe(struct drm_device *dev);
extern void via_tmds_probe(struct drm_device *dev);
extern void via_fp_probe(struct drm_device *dev);

extern void via_hdmi_init(struct drm_device *dev, u32 di_port);
extern void via_analog_init(struct drm_device *dev);
extern void openchrome_vt1632_init(struct drm_device *dev);
extern void openchrome_sii164_init(struct drm_device *dev);
extern void openchrome_ext_dvi_init(struct drm_device *dev);
extern void via_tmds_init(struct drm_device *dev);
extern void via_fp_init(struct drm_device *dev);

#endif /* _OPENCHROME_DRV_H */