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authorKevin Brace <kevinbrace@gmx.com>2018-02-09 19:37:57 -0800
committerKevin Brace <kevinbrace@gmx.com>2018-02-09 19:37:57 -0800
commit1b90e1d4cdcc82c12f85e94ac0abaf9f4ce489c8 (patch)
treef37bba2b901d369c203a4ed45930f36dac4af076
parentf02828f64918f545d149854da3cc191a73451510 (diff)
drm/openchrome: Fix for chip_revision_info
Starting with the newer PCIe generation Chrome IGP found in VX800, VX855, and VX900 chipsets, the PCI bus location of the device was changed from the earlier AGP generation Chrome IGP. There are situations where the device's PCI subvendor ID and subsystem ID need to be available to DRM, and this fix corrects the problem for the newer PCIe generation Chrome IGP. Signed-off-by: Kevin Brace <kevinbrace@gmx.com>
-rw-r--r--drivers/gpu/drm/openchrome/via_drv.c59
1 files changed, 43 insertions, 16 deletions
diff --git a/drivers/gpu/drm/openchrome/via_drv.c b/drivers/gpu/drm/openchrome/via_drv.c
index b515c11440d6..2e5f0fb4bb6c 100644
--- a/drivers/gpu/drm/openchrome/via_drv.c
+++ b/drivers/gpu/drm/openchrome/via_drv.c
@@ -163,53 +163,78 @@ static void via_mmio_setup(struct via_device *dev_priv)
static void chip_revision_info(struct drm_device *dev)
{
struct via_device *dev_priv = dev->dev_private;
- struct pci_bus *bus;
- struct pci_dev *device;
+ struct pci_bus *bus = NULL;
u16 device_id, subsystem_vendor_id, subsystem_device_id;
u8 tmp;
+ int pci_bus;
+ u8 pci_device, pci_function;
int ret;
DRM_DEBUG_KMS("Entered %s.\n", __func__);
- bus = pci_find_bus(0, 1);
- if (!bus) {
- goto pci_error;
+ /*
+ * VX800, VX855, and VX900 chipsets have Chrome IGP
+ * connected as Bus 0, Device 1 PCI device.
+ */
+ if ((dev->pdev->device == PCI_DEVICE_ID_VIA_VT1122) ||
+ (dev->pdev->device == PCI_DEVICE_ID_VIA_VX875) ||
+ (dev->pdev->device == PCI_DEVICE_ID_VIA_VX900_VGA)) {
+
+ pci_bus = 0;
+ pci_device = 1;
+ pci_function = 0;
+
+ /*
+ * For all other devices, Chrome IGP is connected as
+ * Bus 1, Device 0 PCI Device.
+ */
+ } else {
+ pci_bus = 1;
+ pci_device = 0;
+ pci_function = 0;
}
- device = pci_get_slot(bus, PCI_DEVFN(0, 0));
- if (!device) {
+ bus = pci_find_bus(0, pci_bus);
+ if (!bus) {
goto pci_error;
}
- ret = pci_read_config_word(device, 0x02, &device_id);
+ ret = pci_bus_read_config_word(bus, PCI_DEVFN(pci_device,
+ pci_function),
+ PCI_DEVICE_ID,
+ &device_id);
if (ret) {
goto pci_error;
}
- ret = pci_read_config_word(device, 0x2c,
+ ret = pci_bus_read_config_word(bus, PCI_DEVFN(pci_device,
+ pci_function),
+ PCI_SUBSYSTEM_VENDOR_ID,
&subsystem_vendor_id);
if (ret) {
goto pci_error;
}
- ret = pci_read_config_word(device, 0x2e,
+ ret = pci_bus_read_config_word(bus, PCI_DEVFN(pci_device,
+ pci_function),
+ PCI_SUBSYSTEM_ID,
&subsystem_device_id);
if (ret) {
goto pci_error;
}
+ DRM_DEBUG_KMS("DRM Device ID: "
+ "0x%04x\n", dev->pdev->device);
DRM_DEBUG_KMS("Chrome IGP Device ID: "
- "0x%04X\n", device_id);
+ "0x%04x\n", device_id);
DRM_DEBUG_KMS("Chrome IGP Subsystem Vendor ID: "
- "0x%04X\n", subsystem_vendor_id);
+ "0x%04x\n", subsystem_vendor_id);
DRM_DEBUG_KMS("Chrome IGP Subsystem Device ID: "
- "0x%04X\n", subsystem_device_id);
+ "0x%04x\n", subsystem_device_id);
switch (dev->pdev->device) {
-
- /* Check the revision of CLE266 chipset. */
+ /* CLE266 Chipset */
case PCI_DEVICE_ID_VIA_CLE266:
-
/* CR4F only defined in CLE266.CX chipset. */
tmp = vga_rcrt(VGABASE, 0x4F);
vga_wcrt(VGABASE, 0x4F, 0x55);
@@ -259,7 +284,9 @@ static void chip_revision_info(struct drm_device *dev)
}
break;
+ /* VX855 / VX875 Chipset */
case PCI_DEVICE_ID_VIA_VX875:
+ /* VX900 Chipset */
case PCI_DEVICE_ID_VIA_VX900_VGA:
dev_priv->revision = vga_rseq(VGABASE, 0x3B);
break;