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authorKevin Brace <kevinbrace@gmx.com>2018-01-27 23:43:22 -0800
committerKevin Brace <kevinbrace@gmx.com>2018-01-27 23:46:39 -0800
commitba307601f98b0c59c9380325a6c0a7d8a5173251 (patch)
tree9e6c4c21a5c0f8d3611843ab63883c9b131ac182
parent1255bbf97102519aeb5aaf56ee9ae9721e9d926b (diff)
drm/openchrome: Fix for CLE266 IGA1 display regression
The new CLE266 chipset IGA1 display FIFO parameters were severely disrupting IGA1 display. This commit fixes this bug. Also, with this fix, mode setting of IGA1 with analog (VGA) output after standby resumeis now fully working. This fix was validated on VIA EPIA-M mainboard. Signed-off-by: Kevin Brace <kevinbrace@gmx.com>
-rw-r--r--drivers/gpu/drm/openchrome/via_crtc.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/openchrome/via_crtc.c b/drivers/gpu/drm/openchrome/via_crtc.c
index b5b667c9732a..20c4dca5f34f 100644
--- a/drivers/gpu/drm/openchrome/via_crtc.c
+++ b/drivers/gpu/drm/openchrome/via_crtc.c
@@ -505,7 +505,7 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
if (dev_priv->revision == CLE266_REVISION_AX) {
if (mode->hdisplay > 1024) {
/* SR17[6:0] */
- fifo_max_depth = 192;
+ fifo_max_depth = 96;
/* SR16[5:0] */
fifo_threshold = 92;
@@ -516,7 +516,7 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
enable_extended_display_fifo = true;
} else {
/* SR17[6:0] */
- fifo_max_depth = 128;
+ fifo_max_depth = 64;
/* SR16[5:0] */
fifo_threshold = 32;
@@ -572,7 +572,7 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
} else {
if (mode->hdisplay >= 1024) {
/* SR17[6:0] */
- fifo_max_depth = 256;
+ fifo_max_depth = 128;
/* SR16[5:0] */
fifo_threshold = 112;
@@ -583,7 +583,7 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
enable_extended_display_fifo = false;
} else {
/* SR17[6:0] */
- fifo_max_depth = 128;
+ fifo_max_depth = 64;
/* SR16[5:0] */
fifo_threshold = 32;