summaryrefslogtreecommitdiff
path: root/src/intel/common/intel_batch_decoder.c
blob: f9655c7c474ee77af005fe8b1cf344449a39de0e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
/*
 * Copyright © 2017 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 */

#include "common/intel_decoder.h"
#include "intel_disasm.h"
#include "util/macros.h"
#include "main/macros.h" /* Needed for ROUND_DOWN_TO */

#include <string.h>

void
intel_batch_decode_ctx_init(struct intel_batch_decode_ctx *ctx,
                            const struct intel_device_info *devinfo,
                            FILE *fp, enum intel_batch_decode_flags flags,
                            const char *xml_path,
                            struct intel_batch_decode_bo (*get_bo)(void *,
                                                                   bool,
                                                                   uint64_t),
                            unsigned (*get_state_size)(void *, uint64_t,
                                                       uint64_t),
                            void *user_data)
{
   memset(ctx, 0, sizeof(*ctx));

   ctx->devinfo = *devinfo;
   ctx->get_bo = get_bo;
   ctx->get_state_size = get_state_size;
   ctx->user_data = user_data;
   ctx->fp = fp;
   ctx->flags = flags;
   ctx->max_vbo_decoded_lines = -1; /* No limit! */
   ctx->engine = I915_ENGINE_CLASS_RENDER;

   if (xml_path == NULL)
      ctx->spec = intel_spec_load(devinfo);
   else
      ctx->spec = intel_spec_load_from_path(devinfo, xml_path);
}

void
intel_batch_decode_ctx_finish(struct intel_batch_decode_ctx *ctx)
{
   intel_spec_destroy(ctx->spec);
}

#define CSI "\e["
#define RED_COLOR    CSI "31m"
#define BLUE_HEADER  CSI "0;44m" CSI "1;37m"
#define GREEN_HEADER CSI "1;42m"
#define NORMAL       CSI "0m"

static void
ctx_print_group(struct intel_batch_decode_ctx *ctx,
                struct intel_group *group,
                uint64_t address, const void *map)
{
   intel_print_group(ctx->fp, group, address, map, 0,
                   (ctx->flags & INTEL_BATCH_DECODE_IN_COLOR) != 0);
}

static struct intel_batch_decode_bo
ctx_get_bo(struct intel_batch_decode_ctx *ctx, bool ppgtt, uint64_t addr)
{
   if (intel_spec_get_gen(ctx->spec) >= intel_make_gen(8,0)) {
      /* On Broadwell and above, we have 48-bit addresses which consume two
       * dwords.  Some packets require that these get stored in a "canonical
       * form" which means that bit 47 is sign-extended through the upper
       * bits. In order to correctly handle those aub dumps, we need to mask
       * off the top 16 bits.
       */
      addr &= (~0ull >> 16);
   }

   struct intel_batch_decode_bo bo = ctx->get_bo(ctx->user_data, ppgtt, addr);

   if (intel_spec_get_gen(ctx->spec) >= intel_make_gen(8,0))
      bo.addr &= (~0ull >> 16);

   /* We may actually have an offset into the bo */
   if (bo.map != NULL) {
      assert(bo.addr <= addr);
      uint64_t offset = addr - bo.addr;
      bo.map += offset;
      bo.addr += offset;
      bo.size -= offset;
   }

   return bo;
}

static int
update_count(struct intel_batch_decode_ctx *ctx,
             uint64_t address,
             uint64_t base_address,
             unsigned element_dwords,
             unsigned guess)
{
   unsigned size = 0;

   if (ctx->get_state_size)
      size = ctx->get_state_size(ctx->user_data, address, base_address);

   if (size > 0)
      return size / (sizeof(uint32_t) * element_dwords);

   /* In the absence of any information, just guess arbitrarily. */
   return guess;
}

static void
ctx_disassemble_program(struct intel_batch_decode_ctx *ctx,
                        uint32_t ksp, const char *type)
{
   uint64_t addr = ctx->instruction_base + ksp;
   struct intel_batch_decode_bo bo = ctx_get_bo(ctx, true, addr);
   if (!bo.map)
      return;

   fprintf(ctx->fp, "\nReferenced %s:\n", type);
   intel_disassemble(&ctx->devinfo, bo.map, 0, ctx->fp);
}

/* Heuristic to determine whether a uint32_t is probably actually a float
 * (http://stackoverflow.com/a/2953466)
 */

static bool
probably_float(uint32_t bits)
{
   int exp = ((bits & 0x7f800000U) >> 23) - 127;
   uint32_t mant = bits & 0x007fffff;

   /* +- 0.0 */
   if (exp == -127 && mant == 0)
      return true;

   /* +- 1 billionth to 1 billion */
   if (-30 <= exp && exp <= 30)
      return true;

   /* some value with only a few binary digits */
   if ((mant & 0x0000ffff) == 0)
      return true;

   return false;
}

static void
ctx_print_buffer(struct intel_batch_decode_ctx *ctx,
                 struct intel_batch_decode_bo bo,
                 uint32_t read_length,
                 uint32_t pitch,
                 int max_lines)
{
   const uint32_t *dw_end =
         bo.map + ROUND_DOWN_TO(MIN2(bo.size, read_length), 4);

   int column_count = 0, pitch_col_count = 0, line_count = -1;
   for (const uint32_t *dw = bo.map; dw < dw_end; dw++) {
      if (pitch_col_count * 4 == pitch || column_count == 8) {
         fprintf(ctx->fp, "\n");
         column_count = 0;
         if (pitch_col_count * 4 == pitch)
            pitch_col_count = 0;
         line_count++;

         if (max_lines >= 0 && line_count >= max_lines)
            break;
      }
      fprintf(ctx->fp, column_count == 0 ? "  " : " ");

      if ((ctx->flags & INTEL_BATCH_DECODE_FLOATS) && probably_float(*dw))
         fprintf(ctx->fp, "  %8.2f", *(float *) dw);
      else
         fprintf(ctx->fp, "  0x%08x", *dw);

      column_count++;
      pitch_col_count++;
   }
   fprintf(ctx->fp, "\n");
}

static struct intel_group *
intel_ctx_find_instruction(struct intel_batch_decode_ctx *ctx, const uint32_t *p)
{
   return intel_spec_find_instruction(ctx->spec, ctx->engine, p);
}

static void
handle_state_base_address(struct intel_batch_decode_ctx *ctx, const uint32_t *p)
{
   struct intel_group *inst = intel_ctx_find_instruction(ctx, p);

   struct intel_field_iterator iter;
   intel_field_iterator_init(&iter, inst, p, 0, false);

   uint64_t surface_base = 0, dynamic_base = 0, instruction_base = 0;
   bool surface_modify = 0, dynamic_modify = 0, instruction_modify = 0;

   while (intel_field_iterator_next(&iter)) {
      if (strcmp(iter.name, "Surface State Base Address") == 0) {
         surface_base = iter.raw_value;
      } else if (strcmp(iter.name, "Dynamic State Base Address") == 0) {
         dynamic_base = iter.raw_value;
      } else if (strcmp(iter.name, "Instruction Base Address") == 0) {
         instruction_base = iter.raw_value;
      } else if (strcmp(iter.name, "Surface State Base Address Modify Enable") == 0) {
         surface_modify = iter.raw_value;
      } else if (strcmp(iter.name, "Dynamic State Base Address Modify Enable") == 0) {
         dynamic_modify = iter.raw_value;
      } else if (strcmp(iter.name, "Instruction Base Address Modify Enable") == 0) {
         instruction_modify = iter.raw_value;
      }
   }

   if (dynamic_modify)
      ctx->dynamic_base = dynamic_base;

   if (surface_modify)
      ctx->surface_base = surface_base;

   if (instruction_modify)
      ctx->instruction_base = instruction_base;
}

static void
handle_binding_table_pool_alloc(struct intel_batch_decode_ctx *ctx,
                                const uint32_t *p)
{
   struct intel_group *inst = intel_ctx_find_instruction(ctx, p);

   struct intel_field_iterator iter;
   intel_field_iterator_init(&iter, inst, p, 0, false);

   uint64_t bt_pool_base = 0;
   bool bt_pool_enable = false;

   while (intel_field_iterator_next(&iter)) {
      if (strcmp(iter.name, "Binding Table Pool Base Address") == 0) {
         bt_pool_base = iter.raw_value;
      } else if (strcmp(iter.name, "Binding Table Pool Enable") == 0) {
         bt_pool_enable = iter.raw_value;
      }
   }

   if (bt_pool_enable) {
      ctx->bt_pool_base = bt_pool_base;
   } else {
      ctx->bt_pool_base = 0;
   }
}

static void
dump_binding_table(struct intel_batch_decode_ctx *ctx,
                   uint32_t offset, int count)
{
   struct intel_group *strct =
      intel_spec_find_struct(ctx->spec, "RENDER_SURFACE_STATE");
   if (strct == NULL) {
      fprintf(ctx->fp, "did not find RENDER_SURFACE_STATE info\n");
      return;
   }

   /* When 256B binding tables are enabled, we have to shift the offset */
   if (ctx->use_256B_binding_tables)
      offset <<= 3;

   const uint64_t bt_pool_base = ctx->bt_pool_base ? ctx->bt_pool_base :
                                                     ctx->surface_base;

   if (count < 0) {
      count = update_count(ctx, bt_pool_base + offset,
                           bt_pool_base, 1, 8);
   }

   if (offset % 32 != 0 || offset >= UINT16_MAX) {
      fprintf(ctx->fp, "  invalid binding table pointer\n");
      return;
   }

   struct intel_batch_decode_bo bind_bo =
      ctx_get_bo(ctx, true, bt_pool_base + offset);

   if (bind_bo.map == NULL) {
      fprintf(ctx->fp, "  binding table unavailable\n");
      return;
   }

   const uint32_t *pointers = bind_bo.map;
   for (int i = 0; i < count; i++) {
      if (pointers[i] == 0)
         continue;

      uint64_t addr = ctx->surface_base + pointers[i];
      struct intel_batch_decode_bo bo = ctx_get_bo(ctx, true, addr);
      uint32_t size = strct->dw_length * 4;

      if (pointers[i] % 32 != 0 ||
          addr < bo.addr || addr + size >= bo.addr + bo.size) {
         fprintf(ctx->fp, "pointer %u: 0x%08x <not valid>\n", i, pointers[i]);
         continue;
      }

      fprintf(ctx->fp, "pointer %u: 0x%08x\n", i, pointers[i]);
      ctx_print_group(ctx, strct, addr, bo.map + (addr - bo.addr));
   }
}

static void
dump_samplers(struct intel_batch_decode_ctx *ctx, uint32_t offset, int count)
{
   struct intel_group *strct = intel_spec_find_struct(ctx->spec, "SAMPLER_STATE");
   uint64_t state_addr = ctx->dynamic_base + offset;

   assert(count > 0);

   struct intel_batch_decode_bo bo = ctx_get_bo(ctx, true, state_addr);
   const void *state_map = bo.map;

   if (state_map == NULL) {
      fprintf(ctx->fp, "  samplers unavailable\n");
      return;
   }

   if (offset % 32 != 0) {
      fprintf(ctx->fp, "  invalid sampler state pointer\n");
      return;
   }

   const unsigned sampler_state_size = strct->dw_length * 4;

   if (count * sampler_state_size >= bo.size) {
      fprintf(ctx->fp, "  sampler state ends after bo ends\n");
      assert(!"sampler state ends after bo ends");
      return;
   }

   for (int i = 0; i < count; i++) {
      fprintf(ctx->fp, "sampler state %d\n", i);
      ctx_print_group(ctx, strct, state_addr, state_map);
      state_addr += sampler_state_size;
      state_map += sampler_state_size;
   }
}

static void
handle_interface_descriptor_data(struct intel_batch_decode_ctx *ctx,
                                 struct intel_group *desc, const uint32_t *p)
{
   uint64_t ksp = 0;
   uint32_t sampler_offset = 0, sampler_count = 0;
   uint32_t binding_table_offset = 0, binding_entry_count = 0;

   struct intel_field_iterator iter;
   intel_field_iterator_init(&iter, desc, p, 0, false);
   while (intel_field_iterator_next(&iter)) {
      if (strcmp(iter.name, "Kernel Start Pointer") == 0) {
         ksp = strtoll(iter.value, NULL, 16);
      } else if (strcmp(iter.name, "Sampler State Pointer") == 0) {
         sampler_offset = strtol(iter.value, NULL, 16);
      } else if (strcmp(iter.name, "Sampler Count") == 0) {
         sampler_count = strtol(iter.value, NULL, 10);
      } else if (strcmp(iter.name, "Binding Table Pointer") == 0) {
         binding_table_offset = strtol(iter.value, NULL, 16);
      } else if (strcmp(iter.name, "Binding Table Entry Count") == 0) {
         binding_entry_count = strtol(iter.value, NULL, 10);
      }
   }

   ctx_disassemble_program(ctx, ksp, "compute shader");
   fprintf(ctx->fp, "\n");

   if (sampler_count)
      dump_samplers(ctx, sampler_offset, sampler_count);
   if (binding_entry_count)
      dump_binding_table(ctx, binding_table_offset, binding_entry_count);
}

static void
handle_media_interface_descriptor_load(struct intel_batch_decode_ctx *ctx,
                                       const uint32_t *p)
{
   struct intel_group *inst = intel_ctx_find_instruction(ctx, p);
   struct intel_group *desc =
      intel_spec_find_struct(ctx->spec, "INTERFACE_DESCRIPTOR_DATA");

   struct intel_field_iterator iter;
   intel_field_iterator_init(&iter, inst, p, 0, false);
   uint32_t descriptor_offset = 0;
   int descriptor_count = 0;
   while (intel_field_iterator_next(&iter)) {
      if (strcmp(iter.name, "Interface Descriptor Data Start Address") == 0) {
         descriptor_offset = strtol(iter.value, NULL, 16);
      } else if (strcmp(iter.name, "Interface Descriptor Total Length") == 0) {
         descriptor_count =
            strtol(iter.value, NULL, 16) / (desc->dw_length * 4);
      }
   }

   uint64_t desc_addr = ctx->dynamic_base + descriptor_offset;
   struct intel_batch_decode_bo bo = ctx_get_bo(ctx, true, desc_addr);
   const void *desc_map = bo.map;

   if (desc_map == NULL) {
      fprintf(ctx->fp, "  interface descriptors unavailable\n");
      return;
   }

   for (int i = 0; i < descriptor_count; i++) {
      fprintf(ctx->fp, "descriptor %d: %08x\n", i, descriptor_offset);

      ctx_print_group(ctx, desc, desc_addr, desc_map);

      handle_interface_descriptor_data(ctx, desc, desc_map);

      desc_map += desc->dw_length;
      desc_addr += desc->dw_length * 4;
   }
}

static void
handle_compute_walker(struct intel_batch_decode_ctx *ctx,
                      const uint32_t *p)
{
   struct intel_group *inst = intel_ctx_find_instruction(ctx, p);

   struct intel_field_iterator iter;
   intel_field_iterator_init(&iter, inst, p, 0, false);
   while (intel_field_iterator_next(&iter)) {
      if (strcmp(iter.name, "Interface Descriptor") == 0) {
         handle_interface_descriptor_data(ctx, iter.struct_desc,
                                          &iter.p[iter.start_bit / 32]);
      }
   }
}

static void
handle_3dstate_vertex_buffers(struct intel_batch_decode_ctx *ctx,
                              const uint32_t *p)
{
   struct intel_group *inst = intel_ctx_find_instruction(ctx, p);
   struct intel_group *vbs = intel_spec_find_struct(ctx->spec, "VERTEX_BUFFER_STATE");

   struct intel_batch_decode_bo vb = {};
   uint32_t vb_size = 0;
   int index = -1;
   int pitch = -1;
   bool ready = false;

   struct intel_field_iterator iter;
   intel_field_iterator_init(&iter, inst, p, 0, false);
   while (intel_field_iterator_next(&iter)) {
      if (iter.struct_desc != vbs)
         continue;

      struct intel_field_iterator vbs_iter;
      intel_field_iterator_init(&vbs_iter, vbs, &iter.p[iter.start_bit / 32], 0, false);
      while (intel_field_iterator_next(&vbs_iter)) {
         if (strcmp(vbs_iter.name, "Vertex Buffer Index") == 0) {
            index = vbs_iter.raw_value;
         } else if (strcmp(vbs_iter.name, "Buffer Pitch") == 0) {
            pitch = vbs_iter.raw_value;
         } else if (strcmp(vbs_iter.name, "Buffer Starting Address") == 0) {
            vb = ctx_get_bo(ctx, true, vbs_iter.raw_value);
         } else if (strcmp(vbs_iter.name, "Buffer Size") == 0) {
            vb_size = vbs_iter.raw_value;
            ready = true;
         } else if (strcmp(vbs_iter.name, "End Address") == 0) {
            if (vb.map && vbs_iter.raw_value >= vb.addr)
               vb_size = (vbs_iter.raw_value + 1) - vb.addr;
            else
               vb_size = 0;
            ready = true;
         }

         if (!ready)
            continue;

         fprintf(ctx->fp, "vertex buffer %d, size %d\n", index, vb_size);

         if (vb.map == NULL) {
            fprintf(ctx->fp, "  buffer contents unavailable\n");
            continue;
         }

         if (vb.map == 0 || vb_size == 0)
            continue;

         ctx_print_buffer(ctx, vb, vb_size, pitch, ctx->max_vbo_decoded_lines);

         vb.map = NULL;
         vb_size = 0;
         index = -1;
         pitch = -1;
         ready = false;
      }
   }
}

static void
handle_3dstate_index_buffer(struct intel_batch_decode_ctx *ctx,
                            const uint32_t *p)
{
   struct intel_group *inst = intel_ctx_find_instruction(ctx, p);

   struct intel_batch_decode_bo ib = {};
   uint32_t ib_size = 0;
   uint32_t format = 0;

   struct intel_field_iterator iter;
   intel_field_iterator_init(&iter, inst, p, 0, false);
   while (intel_field_iterator_next(&iter)) {
      if (strcmp(iter.name, "Index Format") == 0) {
         format = iter.raw_value;
      } else if (strcmp(iter.name, "Buffer Starting Address") == 0) {
         ib = ctx_get_bo(ctx, true, iter.raw_value);
      } else if (strcmp(iter.name, "Buffer Size") == 0) {
         ib_size = iter.raw_value;
      }
   }

   if (ib.map == NULL) {
      fprintf(ctx->fp, "  buffer contents unavailable\n");
      return;
   }

   const void *m = ib.map;
   const void *ib_end = ib.map + MIN2(ib.size, ib_size);
   for (int i = 0; m < ib_end && i < 10; i++) {
      switch (format) {
      case 0:
         fprintf(ctx->fp, "%3d ", *(uint8_t *)m);
         m += 1;
         break;
      case 1:
         fprintf(ctx->fp, "%3d ", *(uint16_t *)m);
         m += 2;
         break;
      case 2:
         fprintf(ctx->fp, "%3d ", *(uint32_t *)m);
         m += 4;
         break;
      }
   }

   if (m < ib_end)
      fprintf(ctx->fp, "...");
   fprintf(ctx->fp, "\n");
}

static void
decode_single_ksp(struct intel_batch_decode_ctx *ctx, const uint32_t *p)
{
   struct intel_group *inst = intel_ctx_find_instruction(ctx, p);

   uint64_t ksp = 0;
   bool is_simd8 = ctx->devinfo.ver >= 11; /* vertex shaders on Gfx8+ only */
   bool is_enabled = true;

   struct intel_field_iterator iter;
   intel_field_iterator_init(&iter, inst, p, 0, false);
   while (intel_field_iterator_next(&iter)) {
      if (strcmp(iter.name, "Kernel Start Pointer") == 0) {
         ksp = iter.raw_value;
      } else if (strcmp(iter.name, "SIMD8 Dispatch Enable") == 0) {
         is_simd8 = iter.raw_value;
      } else if (strcmp(iter.name, "Dispatch Mode") == 0) {
         is_simd8 = strcmp(iter.value, "SIMD8") == 0;
      } else if (strcmp(iter.name, "Dispatch Enable") == 0) {
         is_simd8 = strcmp(iter.value, "SIMD8") == 0;
      } else if (strcmp(iter.name, "Enable") == 0) {
         is_enabled = iter.raw_value;
      }
   }

   const char *type =
      strcmp(inst->name,   "VS_STATE") == 0 ? "vertex shader" :
      strcmp(inst->name,   "GS_STATE") == 0 ? "geometry shader" :
      strcmp(inst->name,   "SF_STATE") == 0 ? "strips and fans shader" :
      strcmp(inst->name, "CLIP_STATE") == 0 ? "clip shader" :
      strcmp(inst->name, "3DSTATE_DS") == 0 ? "tessellation evaluation shader" :
      strcmp(inst->name, "3DSTATE_HS") == 0 ? "tessellation control shader" :
      strcmp(inst->name, "3DSTATE_VS") == 0 ? (is_simd8 ? "SIMD8 vertex shader" : "vec4 vertex shader") :
      strcmp(inst->name, "3DSTATE_GS") == 0 ? (is_simd8 ? "SIMD8 geometry shader" : "vec4 geometry shader") :
      NULL;

   if (is_enabled) {
      ctx_disassemble_program(ctx, ksp, type);
      fprintf(ctx->fp, "\n");
   }
}

static void
decode_ps_kernels(struct intel_batch_decode_ctx *ctx, const uint32_t *p)
{
   struct intel_group *inst = intel_ctx_find_instruction(ctx, p);

   uint64_t ksp[3] = {0, 0, 0};
   bool enabled[3] = {false, false, false};

   struct intel_field_iterator iter;
   intel_field_iterator_init(&iter, inst, p, 0, false);
   while (intel_field_iterator_next(&iter)) {
      if (strncmp(iter.name, "Kernel Start Pointer ",
                  strlen("Kernel Start Pointer ")) == 0) {
         int idx = iter.name[strlen("Kernel Start Pointer ")] - '0';
         ksp[idx] = strtol(iter.value, NULL, 16);
      } else if (strcmp(iter.name, "8 Pixel Dispatch Enable") == 0) {
         enabled[0] = strcmp(iter.value, "true") == 0;
      } else if (strcmp(iter.name, "16 Pixel Dispatch Enable") == 0) {
         enabled[1] = strcmp(iter.value, "true") == 0;
      } else if (strcmp(iter.name, "32 Pixel Dispatch Enable") == 0) {
         enabled[2] = strcmp(iter.value, "true") == 0;
      }
   }

   /* Reorder KSPs to be [8, 16, 32] instead of the hardware order. */
   if (enabled[0] + enabled[1] + enabled[2] == 1) {
      if (enabled[1]) {
         ksp[1] = ksp[0];
         ksp[0] = 0;
      } else if (enabled[2]) {
         ksp[2] = ksp[0];
         ksp[0] = 0;
      }
   } else {
      uint64_t tmp = ksp[1];
      ksp[1] = ksp[2];
      ksp[2] = tmp;
   }

   if (enabled[0])
      ctx_disassemble_program(ctx, ksp[0], "SIMD8 fragment shader");
   if (enabled[1])
      ctx_disassemble_program(ctx, ksp[1], "SIMD16 fragment shader");
   if (enabled[2])
      ctx_disassemble_program(ctx, ksp[2], "SIMD32 fragment shader");

   if (enabled[0] || enabled[1] || enabled[2])
      fprintf(ctx->fp, "\n");
}

static void
decode_3dstate_constant_all(struct intel_batch_decode_ctx *ctx, const uint32_t *p)
{
   struct intel_group *inst =
      intel_spec_find_instruction(ctx->spec, ctx->engine, p);
   struct intel_group *body =
      intel_spec_find_struct(ctx->spec, "3DSTATE_CONSTANT_ALL_DATA");

   uint32_t read_length[4];
   struct intel_batch_decode_bo buffer[4];
   memset(buffer, 0, sizeof(buffer));

   struct intel_field_iterator outer;
   intel_field_iterator_init(&outer, inst, p, 0, false);
   int idx = 0;
   while (intel_field_iterator_next(&outer)) {
      if (outer.struct_desc != body)
         continue;

      struct intel_field_iterator iter;
      intel_field_iterator_init(&iter, body, &outer.p[outer.start_bit / 32],
                              0, false);
      while (intel_field_iterator_next(&iter)) {
         if (!strcmp(iter.name, "Pointer To Constant Buffer")) {
            buffer[idx] = ctx_get_bo(ctx, true, iter.raw_value);
         } else if (!strcmp(iter.name, "Constant Buffer Read Length")) {
            read_length[idx] = iter.raw_value;
         }
      }
      idx++;
   }

   for (int i = 0; i < 4; i++) {
      if (read_length[i] == 0 || buffer[i].map == NULL)
         continue;

      unsigned size = read_length[i] * 32;
      fprintf(ctx->fp, "constant buffer %d, size %u\n", i, size);

      ctx_print_buffer(ctx, buffer[i], size, 0, -1);
   }
}

static void
decode_3dstate_constant(struct intel_batch_decode_ctx *ctx, const uint32_t *p)
{
   struct intel_group *inst = intel_ctx_find_instruction(ctx, p);
   struct intel_group *body =
      intel_spec_find_struct(ctx->spec, "3DSTATE_CONSTANT_BODY");

   uint32_t read_length[4] = {0};
   uint64_t read_addr[4];

   struct intel_field_iterator outer;
   intel_field_iterator_init(&outer, inst, p, 0, false);
   while (intel_field_iterator_next(&outer)) {
      if (outer.struct_desc != body)
         continue;

      struct intel_field_iterator iter;
      intel_field_iterator_init(&iter, body, &outer.p[outer.start_bit / 32],
                              0, false);

      while (intel_field_iterator_next(&iter)) {
         int idx;
         if (sscanf(iter.name, "Read Length[%d]", &idx) == 1) {
            read_length[idx] = iter.raw_value;
         } else if (sscanf(iter.name, "Buffer[%d]", &idx) == 1) {
            read_addr[idx] = iter.raw_value;
         }
      }

      for (int i = 0; i < 4; i++) {
         if (read_length[i] == 0)
            continue;

         struct intel_batch_decode_bo buffer = ctx_get_bo(ctx, true, read_addr[i]);
         if (!buffer.map) {
            fprintf(ctx->fp, "constant buffer %d unavailable\n", i);
            continue;
         }

         unsigned size = read_length[i] * 32;
         fprintf(ctx->fp, "constant buffer %d, size %u\n", i, size);

         ctx_print_buffer(ctx, buffer, size, 0, -1);
      }
   }
}

static void
decode_gfx4_3dstate_binding_table_pointers(struct intel_batch_decode_ctx *ctx,
                                           const uint32_t *p)
{
   fprintf(ctx->fp, "VS Binding Table:\n");
   dump_binding_table(ctx, p[1], -1);

   fprintf(ctx->fp, "GS Binding Table:\n");
   dump_binding_table(ctx, p[2], -1);

   if (ctx->devinfo.ver < 6) {
      fprintf(ctx->fp, "CLIP Binding Table:\n");
      dump_binding_table(ctx, p[3], -1);
      fprintf(ctx->fp, "SF Binding Table:\n");
      dump_binding_table(ctx, p[4], -1);
      fprintf(ctx->fp, "PS Binding Table:\n");
      dump_binding_table(ctx, p[5], -1);
   } else {
      fprintf(ctx->fp, "PS Binding Table:\n");
      dump_binding_table(ctx, p[3], -1);
   }
}

static void
decode_3dstate_binding_table_pointers(struct intel_batch_decode_ctx *ctx,
                                      const uint32_t *p)
{
   dump_binding_table(ctx, p[1], -1);
}

static void
decode_3dstate_sampler_state_pointers(struct intel_batch_decode_ctx *ctx,
                                      const uint32_t *p)
{
   dump_samplers(ctx, p[1], 1);
}

static void
decode_3dstate_sampler_state_pointers_gfx6(struct intel_batch_decode_ctx *ctx,
                                           const uint32_t *p)
{
   dump_samplers(ctx, p[1], 1);
   dump_samplers(ctx, p[2], 1);
   dump_samplers(ctx, p[3], 1);
}

static bool
str_ends_with(const char *str, const char *end)
{
   int offset = strlen(str) - strlen(end);
   if (offset < 0)
      return false;

   return strcmp(str + offset, end) == 0;
}

static void
decode_dynamic_state_pointers(struct intel_batch_decode_ctx *ctx,
                              const char *struct_type, const uint32_t *p,
                              int count)
{
   struct intel_group *inst = intel_ctx_find_instruction(ctx, p);

   uint32_t state_offset = 0;

   struct intel_field_iterator iter;
   intel_field_iterator_init(&iter, inst, p, 0, false);
   while (intel_field_iterator_next(&iter)) {
      if (str_ends_with(iter.name, "Pointer")) {
         state_offset = iter.raw_value;
         break;
      }
   }

   uint64_t state_addr = ctx->dynamic_base + state_offset;
   struct intel_batch_decode_bo bo = ctx_get_bo(ctx, true, state_addr);
   const void *state_map = bo.map;

   if (state_map == NULL) {
      fprintf(ctx->fp, "  dynamic %s state unavailable\n", struct_type);
      return;
   }

   struct intel_group *state = intel_spec_find_struct(ctx->spec, struct_type);
   if (strcmp(struct_type, "BLEND_STATE") == 0) {
      /* Blend states are different from the others because they have a header
       * struct called BLEND_STATE which is followed by a variable number of
       * BLEND_STATE_ENTRY structs.
       */
      fprintf(ctx->fp, "%s\n", struct_type);
      ctx_print_group(ctx, state, state_addr, state_map);

      state_addr += state->dw_length * 4;
      state_map += state->dw_length * 4;

      struct_type = "BLEND_STATE_ENTRY";
      state = intel_spec_find_struct(ctx->spec, struct_type);
   }

   count = update_count(ctx, ctx->dynamic_base + state_offset,
                        ctx->dynamic_base, state->dw_length, count);

   for (int i = 0; i < count; i++) {
      fprintf(ctx->fp, "%s %d\n", struct_type, i);
      ctx_print_group(ctx, state, state_addr, state_map);

      state_addr += state->dw_length * 4;
      state_map += state->dw_length * 4;
   }
}

static void
decode_3dstate_viewport_state_pointers_cc(struct intel_batch_decode_ctx *ctx,
                                          const uint32_t *p)
{
   decode_dynamic_state_pointers(ctx, "CC_VIEWPORT", p, 4);
}

static void
decode_3dstate_viewport_state_pointers_sf_clip(struct intel_batch_decode_ctx *ctx,
                                               const uint32_t *p)
{
   decode_dynamic_state_pointers(ctx, "SF_CLIP_VIEWPORT", p, 4);
}

static void
decode_3dstate_blend_state_pointers(struct intel_batch_decode_ctx *ctx,
                                    const uint32_t *p)
{
   decode_dynamic_state_pointers(ctx, "BLEND_STATE", p, 1);
}

static void
decode_3dstate_cc_state_pointers(struct intel_batch_decode_ctx *ctx,
                                 const uint32_t *p)
{
   decode_dynamic_state_pointers(ctx, "COLOR_CALC_STATE", p, 1);
}

static void
decode_3dstate_scissor_state_pointers(struct intel_batch_decode_ctx *ctx,
                                      const uint32_t *p)
{
   decode_dynamic_state_pointers(ctx, "SCISSOR_RECT", p, 1);
}

static void
decode_3dstate_slice_table_state_pointers(struct intel_batch_decode_ctx *ctx,
                                          const uint32_t *p)
{
   decode_dynamic_state_pointers(ctx, "SLICE_HASH_TABLE", p, 1);
}

static void
handle_gt_mode(struct intel_batch_decode_ctx *ctx,
               uint32_t reg_addr, uint32_t val)
{
   struct intel_group *reg = intel_spec_find_register(ctx->spec, reg_addr);

   struct intel_field_iterator iter;
   intel_field_iterator_init(&iter, reg, &val, 0, false);

   uint32_t bt_alignment;
   bool bt_alignment_mask = 0;

   while (intel_field_iterator_next(&iter)) {
      if (strcmp(iter.name, "Binding Table Alignment") == 0) {
         bt_alignment = iter.raw_value;
      } else if (strcmp(iter.name, "Binding Table Alignment Mask") == 0) {
         bt_alignment_mask = iter.raw_value;
      }
   }

   if (bt_alignment_mask)
      ctx->use_256B_binding_tables = bt_alignment;
}

struct reg_handler {
   const char *name;
   void (*handler)(struct intel_batch_decode_ctx *ctx,
                   uint32_t reg_addr, uint32_t val);
} reg_handlers[] = {
   { "GT_MODE", handle_gt_mode }
};

static void
decode_load_register_imm(struct intel_batch_decode_ctx *ctx, const uint32_t *p)
{
   struct intel_group *inst = intel_ctx_find_instruction(ctx, p);
   const unsigned length = intel_group_get_length(inst, p);
   assert(length & 1);
   const unsigned nr_regs = (length - 1) / 2;

   for (unsigned i = 0; i < nr_regs; i++) {
      struct intel_group *reg = intel_spec_find_register(ctx->spec, p[i * 2 + 1]);
      if (reg != NULL) {
         fprintf(ctx->fp, "register %s (0x%x): 0x%x\n",
                 reg->name, reg->register_offset, p[2]);
         ctx_print_group(ctx, reg, reg->register_offset, &p[2]);

         for (unsigned i = 0; i < ARRAY_SIZE(reg_handlers); i++) {
            if (strcmp(reg->name, reg_handlers[i].name) == 0)
               reg_handlers[i].handler(ctx, p[1], p[2]);
         }
      }
   }
}

static void
decode_vs_state(struct intel_batch_decode_ctx *ctx, uint32_t offset)
{
   struct intel_group *strct =
      intel_spec_find_struct(ctx->spec, "VS_STATE");
   if (strct == NULL) {
      fprintf(ctx->fp, "did not find VS_STATE info\n");
      return;
   }

   struct intel_batch_decode_bo bind_bo =
      ctx_get_bo(ctx, true, offset);

   if (bind_bo.map == NULL) {
      fprintf(ctx->fp, " vs state unavailable\n");
      return;
   }

   ctx_print_group(ctx, strct, offset, bind_bo.map);
}

static void
decode_gs_state(struct intel_batch_decode_ctx *ctx, uint32_t offset)
{
   struct intel_group *strct =
      intel_spec_find_struct(ctx->spec, "GS_STATE");
   if (strct == NULL) {
      fprintf(ctx->fp, "did not find GS_STATE info\n");
      return;
   }

   struct intel_batch_decode_bo bind_bo =
      ctx_get_bo(ctx, true, offset);

   if (bind_bo.map == NULL) {
      fprintf(ctx->fp, " gs state unavailable\n");
      return;
   }

   ctx_print_group(ctx, strct, offset, bind_bo.map);
}

static void
decode_clip_state(struct intel_batch_decode_ctx *ctx, uint32_t offset)
{
   struct intel_group *strct =
      intel_spec_find_struct(ctx->spec, "CLIP_STATE");
   if (strct == NULL) {
      fprintf(ctx->fp, "did not find CLIP_STATE info\n");
      return;
   }

   struct intel_batch_decode_bo bind_bo =
      ctx_get_bo(ctx, true, offset);

   if (bind_bo.map == NULL) {
      fprintf(ctx->fp, " clip state unavailable\n");
      return;
   }

   ctx_print_group(ctx, strct, offset, bind_bo.map);

   struct intel_group *vp_strct =
      intel_spec_find_struct(ctx->spec, "CLIP_VIEWPORT");
   if (vp_strct == NULL) {
      fprintf(ctx->fp, "did not find CLIP_VIEWPORT info\n");
      return;
   }
   uint32_t clip_vp_offset = ((uint32_t *)bind_bo.map)[6] & ~0x3;
   struct intel_batch_decode_bo vp_bo =
      ctx_get_bo(ctx, true, clip_vp_offset);
   if (vp_bo.map == NULL) {
      fprintf(ctx->fp, " clip vp state unavailable\n");
      return;
   }
   ctx_print_group(ctx, vp_strct, clip_vp_offset, vp_bo.map);
}

static void
decode_sf_state(struct intel_batch_decode_ctx *ctx, uint32_t offset)
{
   struct intel_group *strct =
      intel_spec_find_struct(ctx->spec, "SF_STATE");
   if (strct == NULL) {
      fprintf(ctx->fp, "did not find SF_STATE info\n");
      return;
   }

   struct intel_batch_decode_bo bind_bo =
      ctx_get_bo(ctx, true, offset);

   if (bind_bo.map == NULL) {
      fprintf(ctx->fp, " sf state unavailable\n");
      return;
   }

   ctx_print_group(ctx, strct, offset, bind_bo.map);

   struct intel_group *vp_strct =
      intel_spec_find_struct(ctx->spec, "SF_VIEWPORT");
   if (vp_strct == NULL) {
      fprintf(ctx->fp, "did not find SF_VIEWPORT info\n");
      return;
   }

   uint32_t sf_vp_offset = ((uint32_t *)bind_bo.map)[5] & ~0x3;
   struct intel_batch_decode_bo vp_bo =
      ctx_get_bo(ctx, true, sf_vp_offset);
   if (vp_bo.map == NULL) {
      fprintf(ctx->fp, " sf vp state unavailable\n");
      return;
   }
   ctx_print_group(ctx, vp_strct, sf_vp_offset, vp_bo.map);
}

static void
decode_wm_state(struct intel_batch_decode_ctx *ctx, uint32_t offset)
{
   struct intel_group *strct =
      intel_spec_find_struct(ctx->spec, "WM_STATE");
   if (strct == NULL) {
      fprintf(ctx->fp, "did not find WM_STATE info\n");
      return;
   }

   struct intel_batch_decode_bo bind_bo =
      ctx_get_bo(ctx, true, offset);

   if (bind_bo.map == NULL) {
      fprintf(ctx->fp, " wm state unavailable\n");
      return;
   }

   ctx_print_group(ctx, strct, offset, bind_bo.map);
}

static void
decode_cc_state(struct intel_batch_decode_ctx *ctx, uint32_t offset)
{
   struct intel_group *strct =
      intel_spec_find_struct(ctx->spec, "COLOR_CALC_STATE");
   if (strct == NULL) {
      fprintf(ctx->fp, "did not find COLOR_CALC_STATE info\n");
      return;
   }

   struct intel_batch_decode_bo bind_bo =
      ctx_get_bo(ctx, true, offset);

   if (bind_bo.map == NULL) {
      fprintf(ctx->fp, " cc state unavailable\n");
      return;
   }

   ctx_print_group(ctx, strct, offset, bind_bo.map);

   struct intel_group *vp_strct =
      intel_spec_find_struct(ctx->spec, "CC_VIEWPORT");
   if (vp_strct == NULL) {
      fprintf(ctx->fp, "did not find CC_VIEWPORT info\n");
      return;
   }
   uint32_t cc_vp_offset = ((uint32_t *)bind_bo.map)[4] & ~0x3;
   struct intel_batch_decode_bo vp_bo =
      ctx_get_bo(ctx, true, cc_vp_offset);
   if (vp_bo.map == NULL) {
      fprintf(ctx->fp, " cc vp state unavailable\n");
      return;
   }
   ctx_print_group(ctx, vp_strct, cc_vp_offset, vp_bo.map);
}
static void
decode_pipelined_pointers(struct intel_batch_decode_ctx *ctx, const uint32_t *p)
{
   fprintf(ctx->fp, "VS State Table:\n");
   decode_vs_state(ctx, p[1]);
   if (p[2] & 1) {
      fprintf(ctx->fp, "GS State Table:\n");
      decode_gs_state(ctx, p[2] & ~1);
   }
   fprintf(ctx->fp, "Clip State Table:\n");
   decode_clip_state(ctx, p[3] & ~1);
   fprintf(ctx->fp, "SF State Table:\n");
   decode_sf_state(ctx, p[4]);
   fprintf(ctx->fp, "WM State Table:\n");
   decode_wm_state(ctx, p[5]);
   fprintf(ctx->fp, "CC State Table:\n");
   decode_cc_state(ctx, p[6]);
}

static void
decode_cps_pointers(struct intel_batch_decode_ctx *ctx, const uint32_t *p)
{
   decode_dynamic_state_pointers(ctx, "CPS_STATE", p, 1);
}

struct custom_decoder {
   const char *cmd_name;
   void (*decode)(struct intel_batch_decode_ctx *ctx, const uint32_t *p);
} custom_decoders[] = {
   { "STATE_BASE_ADDRESS", handle_state_base_address },
   { "3DSTATE_BINDING_TABLE_POOL_ALLOC", handle_binding_table_pool_alloc },
   { "MEDIA_INTERFACE_DESCRIPTOR_LOAD", handle_media_interface_descriptor_load },
   { "COMPUTE_WALKER", handle_compute_walker },
   { "3DSTATE_VERTEX_BUFFERS", handle_3dstate_vertex_buffers },
   { "3DSTATE_INDEX_BUFFER", handle_3dstate_index_buffer },
   { "3DSTATE_VS", decode_single_ksp },
   { "3DSTATE_GS", decode_single_ksp },
   { "3DSTATE_DS", decode_single_ksp },
   { "3DSTATE_HS", decode_single_ksp },
   { "3DSTATE_PS", decode_ps_kernels },
   { "3DSTATE_WM", decode_ps_kernels },
   { "3DSTATE_CONSTANT_VS", decode_3dstate_constant },
   { "3DSTATE_CONSTANT_GS", decode_3dstate_constant },
   { "3DSTATE_CONSTANT_PS", decode_3dstate_constant },
   { "3DSTATE_CONSTANT_HS", decode_3dstate_constant },
   { "3DSTATE_CONSTANT_DS", decode_3dstate_constant },
   { "3DSTATE_CONSTANT_ALL", decode_3dstate_constant_all },

   { "3DSTATE_BINDING_TABLE_POINTERS", decode_gfx4_3dstate_binding_table_pointers },
   { "3DSTATE_BINDING_TABLE_POINTERS_VS", decode_3dstate_binding_table_pointers },
   { "3DSTATE_BINDING_TABLE_POINTERS_HS", decode_3dstate_binding_table_pointers },
   { "3DSTATE_BINDING_TABLE_POINTERS_DS", decode_3dstate_binding_table_pointers },
   { "3DSTATE_BINDING_TABLE_POINTERS_GS", decode_3dstate_binding_table_pointers },
   { "3DSTATE_BINDING_TABLE_POINTERS_PS", decode_3dstate_binding_table_pointers },

   { "3DSTATE_SAMPLER_STATE_POINTERS_VS", decode_3dstate_sampler_state_pointers },
   { "3DSTATE_SAMPLER_STATE_POINTERS_HS", decode_3dstate_sampler_state_pointers },
   { "3DSTATE_SAMPLER_STATE_POINTERS_DS", decode_3dstate_sampler_state_pointers },
   { "3DSTATE_SAMPLER_STATE_POINTERS_GS", decode_3dstate_sampler_state_pointers },
   { "3DSTATE_SAMPLER_STATE_POINTERS_PS", decode_3dstate_sampler_state_pointers },
   { "3DSTATE_SAMPLER_STATE_POINTERS", decode_3dstate_sampler_state_pointers_gfx6 },

   { "3DSTATE_VIEWPORT_STATE_POINTERS_CC", decode_3dstate_viewport_state_pointers_cc },
   { "3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP", decode_3dstate_viewport_state_pointers_sf_clip },
   { "3DSTATE_BLEND_STATE_POINTERS", decode_3dstate_blend_state_pointers },
   { "3DSTATE_CC_STATE_POINTERS", decode_3dstate_cc_state_pointers },
   { "3DSTATE_SCISSOR_STATE_POINTERS", decode_3dstate_scissor_state_pointers },
   { "3DSTATE_SLICE_TABLE_STATE_POINTERS", decode_3dstate_slice_table_state_pointers },
   { "MI_LOAD_REGISTER_IMM", decode_load_register_imm },
   { "3DSTATE_PIPELINED_POINTERS", decode_pipelined_pointers },
   { "3DSTATE_CPS_POINTERS", decode_cps_pointers },
};

void
intel_print_batch(struct intel_batch_decode_ctx *ctx,
                  const uint32_t *batch, uint32_t batch_size,
                  uint64_t batch_addr, bool from_ring)
{
   const uint32_t *p, *end = batch + batch_size / sizeof(uint32_t);
   int length;
   struct intel_group *inst;
   const char *reset_color = ctx->flags & INTEL_BATCH_DECODE_IN_COLOR ? NORMAL : "";

   if (ctx->n_batch_buffer_start >= 100) {
      fprintf(ctx->fp, "%s0x%08"PRIx64": Max batch buffer jumps exceeded%s\n",
              (ctx->flags & INTEL_BATCH_DECODE_IN_COLOR) ? RED_COLOR : "",
              (ctx->flags & INTEL_BATCH_DECODE_OFFSETS) ? batch_addr : 0,
              reset_color);
      return;
   }

   ctx->n_batch_buffer_start++;

   for (p = batch; p < end; p += length) {
      inst = intel_ctx_find_instruction(ctx, p);
      length = intel_group_get_length(inst, p);
      assert(inst == NULL || length > 0);
      length = MAX2(1, length);

      uint64_t offset;
      if (ctx->flags & INTEL_BATCH_DECODE_OFFSETS)
         offset = batch_addr + ((char *)p - (char *)batch);
      else
         offset = 0;

      if (inst == NULL) {
         fprintf(ctx->fp, "%s0x%08"PRIx64": unknown instruction %08x%s\n",
                 (ctx->flags & INTEL_BATCH_DECODE_IN_COLOR) ? RED_COLOR : "",
                 offset, p[0], reset_color);

         for (int i=1; i < length; i++) {
            fprintf(ctx->fp, "%s0x%08"PRIx64": -- %08x%s\n",
                 (ctx->flags & INTEL_BATCH_DECODE_IN_COLOR) ? RED_COLOR : "",
                 offset + i * 4, p[i], reset_color);
         }

         continue;
      }

      const char *color;
      const char *inst_name = intel_group_get_name(inst);
      if (ctx->flags & INTEL_BATCH_DECODE_IN_COLOR) {
         reset_color = NORMAL;
         if (ctx->flags & INTEL_BATCH_DECODE_FULL) {
            if (strcmp(inst_name, "MI_BATCH_BUFFER_START") == 0 ||
                strcmp(inst_name, "MI_BATCH_BUFFER_END") == 0)
               color = GREEN_HEADER;
            else
               color = BLUE_HEADER;
         } else {
            color = NORMAL;
         }
      } else {
         color = "";
         reset_color = "";
      }

      fprintf(ctx->fp, "%s0x%08"PRIx64":  0x%08x:  %-80s%s\n",
              color, offset, p[0], inst_name, reset_color);

      if (ctx->flags & INTEL_BATCH_DECODE_FULL) {
         ctx_print_group(ctx, inst, offset, p);

         for (int i = 0; i < ARRAY_SIZE(custom_decoders); i++) {
            if (strcmp(inst_name, custom_decoders[i].cmd_name) == 0) {
               custom_decoders[i].decode(ctx, p);
               break;
            }
         }
      }

      if (strcmp(inst_name, "MI_BATCH_BUFFER_START") == 0) {
         uint64_t next_batch_addr = 0;
         bool ppgtt = false;
         bool second_level = false;
         bool predicate = false;
         struct intel_field_iterator iter;
         intel_field_iterator_init(&iter, inst, p, 0, false);
         while (intel_field_iterator_next(&iter)) {
            if (strcmp(iter.name, "Batch Buffer Start Address") == 0) {
               next_batch_addr = iter.raw_value;
            } else if (strcmp(iter.name, "Second Level Batch Buffer") == 0) {
               second_level = iter.raw_value;
            } else if (strcmp(iter.name, "Address Space Indicator") == 0) {
               ppgtt = iter.raw_value;
            } else if (strcmp(iter.name, "Predication Enable") == 0) {
               predicate = iter.raw_value;
            }
         }

         if (!predicate) {
            struct intel_batch_decode_bo next_batch = ctx_get_bo(ctx, ppgtt, next_batch_addr);

            if (next_batch.map == NULL) {
               fprintf(ctx->fp, "Secondary batch at 0x%08"PRIx64" unavailable\n",
                       next_batch_addr);
            } else {
               intel_print_batch(ctx, next_batch.map, next_batch.size,
                                 next_batch.addr, false);
            }
            if (second_level) {
               /* MI_BATCH_BUFFER_START with "2nd Level Batch Buffer" set acts
                * like a subroutine call.  Commands that come afterwards get
                * processed once the 2nd level batch buffer returns with
                * MI_BATCH_BUFFER_END.
                */
               continue;
            } else if (!from_ring) {
               /* MI_BATCH_BUFFER_START with "2nd Level Batch Buffer" unset acts
                * like a goto.  Nothing after it will ever get processed.  In
                * order to prevent the recursion from growing, we just reset the
                * loop and continue;
                */
               break;
            }
         }
      } else if (strcmp(inst_name, "MI_BATCH_BUFFER_END") == 0) {
         break;
      }
   }

   ctx->n_batch_buffer_start--;
}